drivers/net/ethernet/renesas/rswitch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Renesas Ethernet Switch device driver
   3  *
   4  * Copyright (C) 2022 Renesas Electronics Corporation
   5  */
   6
   7 #ifndef __RSWITCH_H__
   8 #define __RSWITCH_H__
   9
  10 #include <linux/platform_device.h>
  11 #include "rcar_gen4_ptp.h"
  12
  13 #define RSWITCH_MAX_NUM_QUEUES  128
  14
  15 #define RSWITCH_NUM_PORTS       3
  16 #define rswitch_for_each_enabled_port(priv, i)          \
  17         for (i = 0; i < RSWITCH_NUM_PORTS; i++)         \
  18                 if (priv->rdev[i]->disabled)            \
  19                         continue;                       \
  20                 else
  21
  22 #define rswitch_for_each_enabled_port_continue_reverse(priv, i) \
  23         for (i--; i >= 0; i--)                                  \
  24                 if (priv->rdev[i]->disabled)                    \
  25                         continue;                               \
  26                 else
  27
  28 #define TX_RING_SIZE            1024
  29 #define RX_RING_SIZE            1024
  30
  31 #define PKT_BUF_SZ              1584
  32 #define RSWITCH_ALIGN           128
  33 #define RSWITCH_MAX_CTAG_PCP    7
  34
  35 #define RSWITCH_TIMEOUT_US      100000
  36
  37 #define RSWITCH_TOP_OFFSET      0x00008000
  38 #define RSWITCH_COMA_OFFSET     0x00009000
  39 #define RSWITCH_ETHA_OFFSET     0x0000a000      /* with RMAC */
  40 #define RSWITCH_ETHA_SIZE       0x00002000      /* with RMAC */
  41 #define RSWITCH_GWCA0_OFFSET    0x00010000
  42 #define RSWITCH_GWCA1_OFFSET    0x00012000
  43
  44 /* TODO: hardcoded ETHA/GWCA settings for now */
  45 #define GWCA_IRQ_RESOURCE_NAME  "gwca0_rxtx%d"
  46 #define GWCA_IRQ_NAME           "rswitch: gwca0_rxtx%d"
  47 #define GWCA_NUM_IRQS           8
  48 #define GWCA_INDEX              0
  49 #define AGENT_INDEX_GWCA        3
  50 #define GWRO                    RSWITCH_GWCA0_OFFSET
  51
  52 #define FWRO    0
  53 #define TPRO    RSWITCH_TOP_OFFSET
  54 #define CARO    RSWITCH_COMA_OFFSET
  55 #define TARO    0
  56 #define RMRO    0x1000
  57 enum rswitch_reg {
  58         FWGC            = FWRO + 0x0000,
  59         FWTTC0          = FWRO + 0x0010,
  60         FWTTC1          = FWRO + 0x0014,
  61         FWLBMC          = FWRO + 0x0018,
  62         FWCEPTC         = FWRO + 0x0020,
  63         FWCEPRC0        = FWRO + 0x0024,
  64         FWCEPRC1        = FWRO + 0x0028,
  65         FWCEPRC2        = FWRO + 0x002c,
  66         FWCLPTC         = FWRO + 0x0030,
  67         FWCLPRC         = FWRO + 0x0034,
  68         FWCMPTC         = FWRO + 0x0040,
  69         FWEMPTC         = FWRO + 0x0044,
  70         FWSDMPTC        = FWRO + 0x0050,
  71         FWSDMPVC        = FWRO + 0x0054,
  72         FWLBWMC0        = FWRO + 0x0080,
  73         FWPC00          = FWRO + 0x0100,
  74         FWPC10          = FWRO + 0x0104,
  75         FWPC20          = FWRO + 0x0108,
  76         FWCTGC00        = FWRO + 0x0400,
  77         FWCTGC10        = FWRO + 0x0404,
  78         FWCTTC00        = FWRO + 0x0408,
  79         FWCTTC10        = FWRO + 0x040c,
  80         FWCTTC200       = FWRO + 0x0410,
  81         FWCTSC00        = FWRO + 0x0420,
  82         FWCTSC10        = FWRO + 0x0424,
  83         FWCTSC20        = FWRO + 0x0428,
  84         FWCTSC30        = FWRO + 0x042c,
  85         FWCTSC40        = FWRO + 0x0430,
  86         FWTWBFC0        = FWRO + 0x1000,
  87         FWTWBFVC0       = FWRO + 0x1004,
  88         FWTHBFC0        = FWRO + 0x1400,
  89         FWTHBFV0C0      = FWRO + 0x1404,
  90         FWTHBFV1C0      = FWRO + 0x1408,
  91         FWFOBFC0        = FWRO + 0x1800,
  92         FWFOBFV0C0      = FWRO + 0x1804,
  93         FWFOBFV1C0      = FWRO + 0x1808,
  94         FWRFC0          = FWRO + 0x1c00,
  95         FWRFVC0         = FWRO + 0x1c04,
  96         FWCFC0          = FWRO + 0x2000,
  97         FWCFMC00        = FWRO + 0x2004,
  98         FWIP4SC         = FWRO + 0x4008,
  99         FWIP6SC         = FWRO + 0x4018,
 100         FWIP6OC         = FWRO + 0x401c,
 101         FWL2SC          = FWRO + 0x4020,
 102         FWSFHEC         = FWRO + 0x4030,
 103         FWSHCR0         = FWRO + 0x4040,
 104         FWSHCR1         = FWRO + 0x4044,
 105         FWSHCR2         = FWRO + 0x4048,
 106         FWSHCR3         = FWRO + 0x404c,
 107         FWSHCR4         = FWRO + 0x4050,
 108         FWSHCR5         = FWRO + 0x4054,
 109         FWSHCR6         = FWRO + 0x4058,
 110         FWSHCR7         = FWRO + 0x405c,
 111         FWSHCR8         = FWRO + 0x4060,
 112         FWSHCR9         = FWRO + 0x4064,
 113         FWSHCR10        = FWRO + 0x4068,
 114         FWSHCR11        = FWRO + 0x406c,
 115         FWSHCR12        = FWRO + 0x4070,
 116         FWSHCR13        = FWRO + 0x4074,
 117         FWSHCRR         = FWRO + 0x4078,
 118         FWLTHHEC        = FWRO + 0x4090,
 119         FWLTHHC         = FWRO + 0x4094,
 120         FWLTHTL0        = FWRO + 0x40a0,
 121         FWLTHTL1        = FWRO + 0x40a4,
 122         FWLTHTL2        = FWRO + 0x40a8,
 123         FWLTHTL3        = FWRO + 0x40ac,
 124         FWLTHTL4        = FWRO + 0x40b0,
 125         FWLTHTL5        = FWRO + 0x40b4,
 126         FWLTHTL6        = FWRO + 0x40b8,
 127         FWLTHTL7        = FWRO + 0x40bc,
 128         FWLTHTL80       = FWRO + 0x40c0,
 129         FWLTHTL9        = FWRO + 0x40d0,
 130         FWLTHTLR        = FWRO + 0x40d4,
 131         FWLTHTIM        = FWRO + 0x40e0,
 132         FWLTHTEM        = FWRO + 0x40e4,
 133         FWLTHTS0        = FWRO + 0x4100,
 134         FWLTHTS1        = FWRO + 0x4104,
 135         FWLTHTS2        = FWRO + 0x4108,
 136         FWLTHTS3        = FWRO + 0x410c,
 137         FWLTHTS4        = FWRO + 0x4110,
 138         FWLTHTSR0       = FWRO + 0x4120,
 139         FWLTHTSR1       = FWRO + 0x4124,
 140         FWLTHTSR2       = FWRO + 0x4128,
 141         FWLTHTSR3       = FWRO + 0x412c,
 142         FWLTHTSR40      = FWRO + 0x4130,
 143         FWLTHTSR5       = FWRO + 0x4140,
 144         FWLTHTR         = FWRO + 0x4150,
 145         FWLTHTRR0       = FWRO + 0x4154,
 146         FWLTHTRR1       = FWRO + 0x4158,
 147         FWLTHTRR2       = FWRO + 0x415c,
 148         FWLTHTRR3       = FWRO + 0x4160,
 149         FWLTHTRR4       = FWRO + 0x4164,
 150         FWLTHTRR5       = FWRO + 0x4168,
 151         FWLTHTRR6       = FWRO + 0x416c,
 152         FWLTHTRR7       = FWRO + 0x4170,
 153         FWLTHTRR8       = FWRO + 0x4174,
 154         FWLTHTRR9       = FWRO + 0x4180,
 155         FWLTHTRR10      = FWRO + 0x4190,
 156         FWIPHEC         = FWRO + 0x4214,
 157         FWIPHC          = FWRO + 0x4218,
 158         FWIPTL0         = FWRO + 0x4220,
 159         FWIPTL1         = FWRO + 0x4224,
 160         FWIPTL2         = FWRO + 0x4228,
 161         FWIPTL3         = FWRO + 0x422c,
 162         FWIPTL4         = FWRO + 0x4230,
 163         FWIPTL5         = FWRO + 0x4234,
 164         FWIPTL6         = FWRO + 0x4238,
 165         FWIPTL7         = FWRO + 0x4240,
 166         FWIPTL8         = FWRO + 0x4250,
 167         FWIPTLR         = FWRO + 0x4254,
 168         FWIPTIM         = FWRO + 0x4260,
 169         FWIPTEM         = FWRO + 0x4264,
 170         FWIPTS0         = FWRO + 0x4270,
 171         FWIPTS1         = FWRO + 0x4274,
 172         FWIPTS2         = FWRO + 0x4278,
 173         FWIPTS3         = FWRO + 0x427c,
 174         FWIPTS4         = FWRO + 0x4280,
 175         FWIPTSR0        = FWRO + 0x4284,
 176         FWIPTSR1        = FWRO + 0x4288,
 177         FWIPTSR2        = FWRO + 0x428c,
 178         FWIPTSR3        = FWRO + 0x4290,
 179         FWIPTSR4        = FWRO + 0x42a0,
 180         FWIPTR          = FWRO + 0x42b0,
 181         FWIPTRR0        = FWRO + 0x42b4,
 182         FWIPTRR1        = FWRO + 0x42b8,
 183         FWIPTRR2        = FWRO + 0x42bc,
 184         FWIPTRR3        = FWRO + 0x42c0,
 185         FWIPTRR4        = FWRO + 0x42c4,
 186         FWIPTRR5        = FWRO + 0x42c8,
 187         FWIPTRR6        = FWRO + 0x42cc,
 188         FWIPTRR7        = FWRO + 0x42d0,
 189         FWIPTRR8        = FWRO + 0x42e0,
 190         FWIPTRR9        = FWRO + 0x42f0,
 191         FWIPHLEC        = FWRO + 0x4300,
 192         FWIPAGUSPC      = FWRO + 0x4500,
 193         FWIPAGC         = FWRO + 0x4504,
 194         FWIPAGM0        = FWRO + 0x4510,
 195         FWIPAGM1        = FWRO + 0x4514,
 196         FWIPAGM2        = FWRO + 0x4518,
 197         FWIPAGM3        = FWRO + 0x451c,
 198         FWIPAGM4        = FWRO + 0x4520,
 199         FWMACHEC        = FWRO + 0x4620,
 200         FWMACHC         = FWRO + 0x4624,
 201         FWMACTL0        = FWRO + 0x4630,
 202         FWMACTL1        = FWRO + 0x4634,
 203         FWMACTL2        = FWRO + 0x4638,
 204         FWMACTL3        = FWRO + 0x463c,
 205         FWMACTL4        = FWRO + 0x4640,
 206         FWMACTL5        = FWRO + 0x4650,
 207         FWMACTLR        = FWRO + 0x4654,
 208         FWMACTIM        = FWRO + 0x4660,
 209         FWMACTEM        = FWRO + 0x4664,
 210         FWMACTS0        = FWRO + 0x4670,
 211         FWMACTS1        = FWRO + 0x4674,
 212         FWMACTSR0       = FWRO + 0x4678,
 213         FWMACTSR1       = FWRO + 0x467c,
 214         FWMACTSR2       = FWRO + 0x4680,
 215         FWMACTSR3       = FWRO + 0x4690,
 216         FWMACTR         = FWRO + 0x46a0,
 217         FWMACTRR0       = FWRO + 0x46a4,
 218         FWMACTRR1       = FWRO + 0x46a8,
 219         FWMACTRR2       = FWRO + 0x46ac,
 220         FWMACTRR3       = FWRO + 0x46b0,
 221         FWMACTRR4       = FWRO + 0x46b4,
 222         FWMACTRR5       = FWRO + 0x46c0,
 223         FWMACTRR6       = FWRO + 0x46d0,
 224         FWMACHLEC       = FWRO + 0x4700,
 225         FWMACAGUSPC     = FWRO + 0x4880,
 226         FWMACAGC        = FWRO + 0x4884,
 227         FWMACAGM0       = FWRO + 0x4888,
 228         FWMACAGM1       = FWRO + 0x488c,
 229         FWVLANTEC       = FWRO + 0x4900,
 230         FWVLANTL0       = FWRO + 0x4910,
 231         FWVLANTL1       = FWRO + 0x4914,
 232         FWVLANTL2       = FWRO + 0x4918,
 233         FWVLANTL3       = FWRO + 0x4920,
 234         FWVLANTL4       = FWRO + 0x4930,
 235         FWVLANTLR       = FWRO + 0x4934,
 236         FWVLANTIM       = FWRO + 0x4940,
 237         FWVLANTEM       = FWRO + 0x4944,
 238         FWVLANTS        = FWRO + 0x4950,
 239         FWVLANTSR0      = FWRO + 0x4954,
 240         FWVLANTSR1      = FWRO + 0x4958,
 241         FWVLANTSR2      = FWRO + 0x4960,
 242         FWVLANTSR3      = FWRO + 0x4970,
 243         FWPBFC0         = FWRO + 0x4a00,
 244         FWPBFCSDC00     = FWRO + 0x4a04,
 245         FWL23URL0       = FWRO + 0x4e00,
 246         FWL23URL1       = FWRO + 0x4e04,
 247         FWL23URL2       = FWRO + 0x4e08,
 248         FWL23URL3       = FWRO + 0x4e0c,
 249         FWL23URLR       = FWRO + 0x4e10,
 250         FWL23UTIM       = FWRO + 0x4e20,
 251         FWL23URR        = FWRO + 0x4e30,
 252         FWL23URRR0      = FWRO + 0x4e34,
 253         FWL23URRR1      = FWRO + 0x4e38,
 254         FWL23URRR2      = FWRO + 0x4e3c,
 255         FWL23URRR3      = FWRO + 0x4e40,
 256         FWL23URMC0      = FWRO + 0x4f00,
 257         FWPMFGC0        = FWRO + 0x5000,
 258         FWPGFC0         = FWRO + 0x5100,
 259         FWPGFIGSC0      = FWRO + 0x5104,
 260         FWPGFENC0       = FWRO + 0x5108,
 261         FWPGFENM0       = FWRO + 0x510c,
 262         FWPGFCSTC00     = FWRO + 0x5110,
 263         FWPGFCSTC10     = FWRO + 0x5114,
 264         FWPGFCSTM00     = FWRO + 0x5118,
 265         FWPGFCSTM10     = FWRO + 0x511c,
 266         FWPGFCTC0       = FWRO + 0x5120,
 267         FWPGFCTM0       = FWRO + 0x5124,
 268         FWPGFHCC0       = FWRO + 0x5128,
 269         FWPGFSM0        = FWRO + 0x512c,
 270         FWPGFGC0        = FWRO + 0x5130,
 271         FWPGFGL0        = FWRO + 0x5500,
 272         FWPGFGL1        = FWRO + 0x5504,
 273         FWPGFGLR        = FWRO + 0x5518,
 274         FWPGFGR         = FWRO + 0x5510,
 275         FWPGFGRR0       = FWRO + 0x5514,
 276         FWPGFGRR1       = FWRO + 0x5518,
 277         FWPGFRIM        = FWRO + 0x5520,
 278         FWPMTRFC0       = FWRO + 0x5600,
 279         FWPMTRCBSC0     = FWRO + 0x5604,
 280         FWPMTRC0RC0     = FWRO + 0x5608,
 281         FWPMTREBSC0     = FWRO + 0x560c,
 282         FWPMTREIRC0     = FWRO + 0x5610,
 283         FWPMTRFM0       = FWRO + 0x5614,
 284         FWFTL0          = FWRO + 0x6000,
 285         FWFTL1          = FWRO + 0x6004,
 286         FWFTLR          = FWRO + 0x6008,
 287         FWFTOC          = FWRO + 0x6010,
 288         FWFTOPC         = FWRO + 0x6014,
 289         FWFTIM          = FWRO + 0x6020,
 290         FWFTR           = FWRO + 0x6030,
 291         FWFTRR0         = FWRO + 0x6034,
 292         FWFTRR1         = FWRO + 0x6038,
 293         FWFTRR2         = FWRO + 0x603c,
 294         FWSEQNGC0       = FWRO + 0x6100,
 295         FWSEQNGM0       = FWRO + 0x6104,
 296         FWSEQNRC        = FWRO + 0x6200,
 297         FWCTFDCN0       = FWRO + 0x6300,
 298         FWLTHFDCN0      = FWRO + 0x6304,
 299         FWIPFDCN0       = FWRO + 0x6308,
 300         FWLTWFDCN0      = FWRO + 0x630c,
 301         FWPBFDCN0       = FWRO + 0x6310,
 302         FWMHLCN0        = FWRO + 0x6314,
 303         FWIHLCN0        = FWRO + 0x6318,
 304         FWICRDCN0       = FWRO + 0x6500,
 305         FWWMRDCN0       = FWRO + 0x6504,
 306         FWCTRDCN0       = FWRO + 0x6508,
 307         FWLTHRDCN0      = FWRO + 0x650c,
 308         FWIPRDCN0       = FWRO + 0x6510,
 309         FWLTWRDCN0      = FWRO + 0x6514,
 310         FWPBRDCN0       = FWRO + 0x6518,
 311         FWPMFDCN0       = FWRO + 0x6700,
 312         FWPGFDCN0       = FWRO + 0x6780,
 313         FWPMGDCN0       = FWRO + 0x6800,
 314         FWPMYDCN0       = FWRO + 0x6804,
 315         FWPMRDCN0       = FWRO + 0x6808,
 316         FWFRPPCN0       = FWRO + 0x6a00,
 317         FWFRDPCN0       = FWRO + 0x6a04,
 318         FWEIS00         = FWRO + 0x7900,
 319         FWEIE00         = FWRO + 0x7904,
 320         FWEID00         = FWRO + 0x7908,
 321         FWEIS1          = FWRO + 0x7a00,
 322         FWEIE1          = FWRO + 0x7a04,
 323         FWEID1          = FWRO + 0x7a08,
 324         FWEIS2          = FWRO + 0x7a10,
 325         FWEIE2          = FWRO + 0x7a14,
 326         FWEID2          = FWRO + 0x7a18,
 327         FWEIS3          = FWRO + 0x7a20,
 328         FWEIE3          = FWRO + 0x7a24,
 329         FWEID3          = FWRO + 0x7a28,
 330         FWEIS4          = FWRO + 0x7a30,
 331         FWEIE4          = FWRO + 0x7a34,
 332         FWEID4          = FWRO + 0x7a38,
 333         FWEIS5          = FWRO + 0x7a40,
 334         FWEIE5          = FWRO + 0x7a44,
 335         FWEID5          = FWRO + 0x7a48,
 336         FWEIS60         = FWRO + 0x7a50,
 337         FWEIE60         = FWRO + 0x7a54,
 338         FWEID60         = FWRO + 0x7a58,
 339         FWEIS61         = FWRO + 0x7a60,
 340         FWEIE61         = FWRO + 0x7a64,
 341         FWEID61         = FWRO + 0x7a68,
 342         FWEIS62         = FWRO + 0x7a70,
 343         FWEIE62         = FWRO + 0x7a74,
 344         FWEID62         = FWRO + 0x7a78,
 345         FWEIS63         = FWRO + 0x7a80,
 346         FWEIE63         = FWRO + 0x7a84,
 347         FWEID63         = FWRO + 0x7a88,
 348         FWEIS70         = FWRO + 0x7a90,
 349         FWEIE70         = FWRO + 0x7A94,
 350         FWEID70         = FWRO + 0x7a98,
 351         FWEIS71         = FWRO + 0x7aa0,
 352         FWEIE71         = FWRO + 0x7aa4,
 353         FWEID71         = FWRO + 0x7aa8,
 354         FWEIS72         = FWRO + 0x7ab0,
 355         FWEIE72         = FWRO + 0x7ab4,
 356         FWEID72         = FWRO + 0x7ab8,
 357         FWEIS73         = FWRO + 0x7ac0,
 358         FWEIE73         = FWRO + 0x7ac4,
 359         FWEID73         = FWRO + 0x7ac8,
 360         FWEIS80         = FWRO + 0x7ad0,
 361         FWEIE80         = FWRO + 0x7ad4,
 362         FWEID80         = FWRO + 0x7ad8,
 363         FWEIS81         = FWRO + 0x7ae0,
 364         FWEIE81         = FWRO + 0x7ae4,
 365         FWEID81         = FWRO + 0x7ae8,
 366         FWEIS82         = FWRO + 0x7af0,
 367         FWEIE82         = FWRO + 0x7af4,
 368         FWEID82         = FWRO + 0x7af8,
 369         FWEIS83         = FWRO + 0x7b00,
 370         FWEIE83         = FWRO + 0x7b04,
 371         FWEID83         = FWRO + 0x7b08,
 372         FWMIS0          = FWRO + 0x7c00,
 373         FWMIE0          = FWRO + 0x7c04,
 374         FWMID0          = FWRO + 0x7c08,
 375         FWSCR0          = FWRO + 0x7d00,
 376         FWSCR1          = FWRO + 0x7d04,
 377         FWSCR2          = FWRO + 0x7d08,
 378         FWSCR3          = FWRO + 0x7d0c,
 379         FWSCR4          = FWRO + 0x7d10,
 380         FWSCR5          = FWRO + 0x7d14,
 381         FWSCR6          = FWRO + 0x7d18,
 382         FWSCR7          = FWRO + 0x7d1c,
 383         FWSCR8          = FWRO + 0x7d20,
 384         FWSCR9          = FWRO + 0x7d24,
 385         FWSCR10         = FWRO + 0x7d28,
 386         FWSCR11         = FWRO + 0x7d2c,
 387         FWSCR12         = FWRO + 0x7d30,
 388         FWSCR13         = FWRO + 0x7d34,
 389         FWSCR14         = FWRO + 0x7d38,
 390         FWSCR15         = FWRO + 0x7d3c,
 391         FWSCR16         = FWRO + 0x7d40,
 392         FWSCR17         = FWRO + 0x7d44,
 393         FWSCR18         = FWRO + 0x7d48,
 394         FWSCR19         = FWRO + 0x7d4c,
 395         FWSCR20         = FWRO + 0x7d50,
 396         FWSCR21         = FWRO + 0x7d54,
 397         FWSCR22         = FWRO + 0x7d58,
 398         FWSCR23         = FWRO + 0x7d5c,
 399         FWSCR24         = FWRO + 0x7d60,
 400         FWSCR25         = FWRO + 0x7d64,
 401         FWSCR26         = FWRO + 0x7d68,
 402         FWSCR27         = FWRO + 0x7d6c,
 403         FWSCR28         = FWRO + 0x7d70,
 404         FWSCR29         = FWRO + 0x7d74,
 405         FWSCR30         = FWRO + 0x7d78,
 406         FWSCR31         = FWRO + 0x7d7c,
 407         FWSCR32         = FWRO + 0x7d80,
 408         FWSCR33         = FWRO + 0x7d84,
 409         FWSCR34         = FWRO + 0x7d88,
 410         FWSCR35         = FWRO + 0x7d8c,
 411         FWSCR36         = FWRO + 0x7d90,
 412         FWSCR37         = FWRO + 0x7d94,
 413         FWSCR38         = FWRO + 0x7d98,
 414         FWSCR39         = FWRO + 0x7d9c,
 415         FWSCR40         = FWRO + 0x7da0,
 416         FWSCR41         = FWRO + 0x7da4,
 417         FWSCR42         = FWRO + 0x7da8,
 418         FWSCR43         = FWRO + 0x7dac,
 419         FWSCR44         = FWRO + 0x7db0,
 420         FWSCR45         = FWRO + 0x7db4,
 421         FWSCR46         = FWRO + 0x7db8,
 422
 423         TPEMIMC0        = TPRO + 0x0000,
 424         TPEMIMC1        = TPRO + 0x0004,
 425         TPEMIMC2        = TPRO + 0x0008,
 426         TPEMIMC3        = TPRO + 0x000c,
 427         TPEMIMC4        = TPRO + 0x0010,
 428         TPEMIMC5        = TPRO + 0x0014,
 429         TPEMIMC60       = TPRO + 0x0080,
 430         TPEMIMC70       = TPRO + 0x0100,
 431         TSIM            = TPRO + 0x0700,
 432         TFIM            = TPRO + 0x0704,
 433         TCIM            = TPRO + 0x0708,
 434         TGIM0           = TPRO + 0x0710,
 435         TGIM1           = TPRO + 0x0714,
 436         TEIM0           = TPRO + 0x0720,
 437         TEIM1           = TPRO + 0x0724,
 438         TEIM2           = TPRO + 0x0728,
 439
 440         RIPV            = CARO + 0x0000,
 441         RRC             = CARO + 0x0004,
 442         RCEC            = CARO + 0x0008,
 443         RCDC            = CARO + 0x000c,
 444         RSSIS           = CARO + 0x0010,
 445         RSSIE           = CARO + 0x0014,
 446         RSSID           = CARO + 0x0018,
 447         CABPIBWMC       = CARO + 0x0020,
 448         CABPWMLC        = CARO + 0x0040,
 449         CABPPFLC0       = CARO + 0x0050,
 450         CABPPWMLC0      = CARO + 0x0060,
 451         CABPPPFLC00     = CARO + 0x00a0,
 452         CABPULC         = CARO + 0x0100,
 453         CABPIRM         = CARO + 0x0140,
 454         CABPPCM         = CARO + 0x0144,
 455         CABPLCM         = CARO + 0x0148,
 456         CABPCPM         = CARO + 0x0180,
 457         CABPMCPM        = CARO + 0x0200,
 458         CARDNM          = CARO + 0x0280,
 459         CARDMNM         = CARO + 0x0284,
 460         CARDCN          = CARO + 0x0290,
 461         CAEIS0          = CARO + 0x0300,
 462         CAEIE0          = CARO + 0x0304,
 463         CAEID0          = CARO + 0x0308,
 464         CAEIS1          = CARO + 0x0310,
 465         CAEIE1          = CARO + 0x0314,
 466         CAEID1          = CARO + 0x0318,
 467         CAMIS0          = CARO + 0x0340,
 468         CAMIE0          = CARO + 0x0344,
 469         CAMID0          = CARO + 0x0348,
 470         CAMIS1          = CARO + 0x0350,
 471         CAMIE1          = CARO + 0x0354,
 472         CAMID1          = CARO + 0x0358,
 473         CASCR           = CARO + 0x0380,
 474
 475         EAMC            = TARO + 0x0000,
 476         EAMS            = TARO + 0x0004,
 477         EAIRC           = TARO + 0x0010,
 478         EATDQSC         = TARO + 0x0014,
 479         EATDQC          = TARO + 0x0018,
 480         EATDQAC         = TARO + 0x001c,
 481         EATPEC          = TARO + 0x0020,
 482         EATMFSC0        = TARO + 0x0040,
 483         EATDQDC0        = TARO + 0x0060,
 484         EATDQM0         = TARO + 0x0080,
 485         EATDQMLM0       = TARO + 0x00a0,
 486         EACTQC          = TARO + 0x0100,
 487         EACTDQDC        = TARO + 0x0104,
 488         EACTDQM         = TARO + 0x0108,
 489         EACTDQMLM       = TARO + 0x010c,
 490         EAVCC           = TARO + 0x0130,
 491         EAVTC           = TARO + 0x0134,
 492         EATTFC          = TARO + 0x0138,
 493         EACAEC          = TARO + 0x0200,
 494         EACC            = TARO + 0x0204,
 495         EACAIVC0        = TARO + 0x0220,
 496         EACAULC0        = TARO + 0x0240,
 497         EACOEM          = TARO + 0x0260,
 498         EACOIVM0        = TARO + 0x0280,
 499         EACOULM0        = TARO + 0x02a0,
 500         EACGSM          = TARO + 0x02c0,
 501         EATASC          = TARO + 0x0300,
 502         EATASENC0       = TARO + 0x0320,
 503         EATASCTENC      = TARO + 0x0340,
 504         EATASENM0       = TARO + 0x0360,
 505         EATASCTENM      = TARO + 0x0380,
 506         EATASCSTC0      = TARO + 0x03a0,
 507         EATASCSTC1      = TARO + 0x03a4,
 508         EATASCSTM0      = TARO + 0x03a8,
 509         EATASCSTM1      = TARO + 0x03ac,
 510         EATASCTC        = TARO + 0x03b0,
 511         EATASCTM        = TARO + 0x03b4,
 512         EATASGL0        = TARO + 0x03c0,
 513         EATASGL1        = TARO + 0x03c4,
 514         EATASGLR        = TARO + 0x03c8,
 515         EATASGR         = TARO + 0x03d0,
 516         EATASGRR        = TARO + 0x03d4,
 517         EATASHCC        = TARO + 0x03e0,
 518         EATASRIRM       = TARO + 0x03e4,
 519         EATASSM         = TARO + 0x03e8,
 520         EAUSMFSECN      = TARO + 0x0400,
 521         EATFECN         = TARO + 0x0404,
 522         EAFSECN         = TARO + 0x0408,
 523         EADQOECN        = TARO + 0x040c,
 524         EADQSECN        = TARO + 0x0410,
 525         EACKSECN        = TARO + 0x0414,
 526         EAEIS0          = TARO + 0x0500,
 527         EAEIE0          = TARO + 0x0504,
 528         EAEID0          = TARO + 0x0508,
 529         EAEIS1          = TARO + 0x0510,
 530         EAEIE1          = TARO + 0x0514,
 531         EAEID1          = TARO + 0x0518,
 532         EAEIS2          = TARO + 0x0520,
 533         EAEIE2          = TARO + 0x0524,
 534         EAEID2          = TARO + 0x0528,
 535         EASCR           = TARO + 0x0580,
 536
 537         MPSM            = RMRO + 0x0000,
 538         MPIC            = RMRO + 0x0004,
 539         MPIM            = RMRO + 0x0008,
 540         MIOC            = RMRO + 0x0010,
 541         MIOM            = RMRO + 0x0014,
 542         MXMS            = RMRO + 0x0018,
 543         MTFFC           = RMRO + 0x0020,
 544         MTPFC           = RMRO + 0x0024,
 545         MTPFC2          = RMRO + 0x0028,
 546         MTPFC30         = RMRO + 0x0030,
 547         MTATC0          = RMRO + 0x0050,
 548         MTIM            = RMRO + 0x0060,
 549         MRGC            = RMRO + 0x0080,
 550         MRMAC0          = RMRO + 0x0084,
 551         MRMAC1          = RMRO + 0x0088,
 552         MRAFC           = RMRO + 0x008c,
 553         MRSCE           = RMRO + 0x0090,
 554         MRSCP           = RMRO + 0x0094,
 555         MRSCC           = RMRO + 0x0098,
 556         MRFSCE          = RMRO + 0x009c,
 557         MRFSCP          = RMRO + 0x00a0,
 558         MTRC            = RMRO + 0x00a4,
 559         MRIM            = RMRO + 0x00a8,
 560         MRPFM           = RMRO + 0x00ac,
 561         MPFC0           = RMRO + 0x0100,
 562         MLVC            = RMRO + 0x0180,
 563         MEEEC           = RMRO + 0x0184,
 564         MLBC            = RMRO + 0x0188,
 565         MXGMIIC         = RMRO + 0x0190,
 566         MPCH            = RMRO + 0x0194,
 567         MANC            = RMRO + 0x0198,
 568         MANM            = RMRO + 0x019c,
 569         MPLCA1          = RMRO + 0x01a0,
 570         MPLCA2          = RMRO + 0x01a4,
 571         MPLCA3          = RMRO + 0x01a8,
 572         MPLCA4          = RMRO + 0x01ac,
 573         MPLCAM          = RMRO + 0x01b0,
 574         MHDC1           = RMRO + 0x01c0,
 575         MHDC2           = RMRO + 0x01c4,
 576         MEIS            = RMRO + 0x0200,
 577         MEIE            = RMRO + 0x0204,
 578         MEID            = RMRO + 0x0208,
 579         MMIS0           = RMRO + 0x0210,
 580         MMIE0           = RMRO + 0x0214,
 581         MMID0           = RMRO + 0x0218,
 582         MMIS1           = RMRO + 0x0220,
 583         MMIE1           = RMRO + 0x0224,
 584         MMID1           = RMRO + 0x0228,
 585         MMIS2           = RMRO + 0x0230,
 586         MMIE2           = RMRO + 0x0234,
 587         MMID2           = RMRO + 0x0238,
 588         MMPFTCT         = RMRO + 0x0300,
 589         MAPFTCT         = RMRO + 0x0304,
 590         MPFRCT          = RMRO + 0x0308,
 591         MFCICT          = RMRO + 0x030c,
 592         MEEECT          = RMRO + 0x0310,
 593         MMPCFTCT0       = RMRO + 0x0320,
 594         MAPCFTCT0       = RMRO + 0x0330,
 595         MPCFRCT0        = RMRO + 0x0340,
 596         MHDCC           = RMRO + 0x0350,
 597         MROVFC          = RMRO + 0x0354,
 598         MRHCRCEC        = RMRO + 0x0358,
 599         MRXBCE          = RMRO + 0x0400,
 600         MRXBCP          = RMRO + 0x0404,
 601         MRGFCE          = RMRO + 0x0408,
 602         MRGFCP          = RMRO + 0x040c,
 603         MRBFC           = RMRO + 0x0410,
 604         MRMFC           = RMRO + 0x0414,
 605         MRUFC           = RMRO + 0x0418,
 606         MRPEFC          = RMRO + 0x041c,
 607         MRNEFC          = RMRO + 0x0420,
 608         MRFMEFC         = RMRO + 0x0424,
 609         MRFFMEFC        = RMRO + 0x0428,
 610         MRCFCEFC        = RMRO + 0x042c,
 611         MRFCEFC         = RMRO + 0x0430,
 612         MRRCFEFC        = RMRO + 0x0434,
 613         MRUEFC          = RMRO + 0x043c,
 614         MROEFC          = RMRO + 0x0440,
 615         MRBOEC          = RMRO + 0x0444,
 616         MTXBCE          = RMRO + 0x0500,
 617         MTXBCP          = RMRO + 0x0504,
 618         MTGFCE          = RMRO + 0x0508,
 619         MTGFCP          = RMRO + 0x050c,
 620         MTBFC           = RMRO + 0x0510,
 621         MTMFC           = RMRO + 0x0514,
 622         MTUFC           = RMRO + 0x0518,
 623         MTEFC           = RMRO + 0x051c,
 624
 625         GWMC            = GWRO + 0x0000,
 626         GWMS            = GWRO + 0x0004,
 627         GWIRC           = GWRO + 0x0010,
 628         GWRDQSC         = GWRO + 0x0014,
 629         GWRDQC          = GWRO + 0x0018,
 630         GWRDQAC         = GWRO + 0x001c,
 631         GWRGC           = GWRO + 0x0020,
 632         GWRMFSC0        = GWRO + 0x0040,
 633         GWRDQDC0        = GWRO + 0x0060,
 634         GWRDQM0         = GWRO + 0x0080,
 635         GWRDQMLM0       = GWRO + 0x00a0,
 636         GWMTIRM         = GWRO + 0x0100,
 637         GWMSTLS         = GWRO + 0x0104,
 638         GWMSTLR         = GWRO + 0x0108,
 639         GWMSTSS         = GWRO + 0x010c,
 640         GWMSTSR         = GWRO + 0x0110,
 641         GWMAC0          = GWRO + 0x0120,
 642         GWMAC1          = GWRO + 0x0124,
 643         GWVCC           = GWRO + 0x0130,
 644         GWVTC           = GWRO + 0x0134,
 645         GWTTFC          = GWRO + 0x0138,
 646         GWTDCAC00       = GWRO + 0x0140,
 647         GWTDCAC10       = GWRO + 0x0144,
 648         GWTSDCC0        = GWRO + 0x0160,
 649         GWTNM           = GWRO + 0x0180,
 650         GWTMNM          = GWRO + 0x0184,
 651         GWAC            = GWRO + 0x0190,
 652         GWDCBAC0        = GWRO + 0x0194,
 653         GWDCBAC1        = GWRO + 0x0198,
 654         GWIICBSC        = GWRO + 0x019c,
 655         GWMDNC          = GWRO + 0x01a0,
 656         GWTRC0          = GWRO + 0x0200,
 657         GWTPC0          = GWRO + 0x0300,
 658         GWARIRM         = GWRO + 0x0380,
 659         GWDCC0          = GWRO + 0x0400,
 660         GWAARSS         = GWRO + 0x0800,
 661         GWAARSR0        = GWRO + 0x0804,
 662         GWAARSR1        = GWRO + 0x0808,
 663         GWIDAUAS0       = GWRO + 0x0840,
 664         GWIDASM0        = GWRO + 0x0880,
 665         GWIDASAM00      = GWRO + 0x0900,
 666         GWIDASAM10      = GWRO + 0x0904,
 667         GWIDACAM00      = GWRO + 0x0980,
 668         GWIDACAM10      = GWRO + 0x0984,
 669         GWGRLC          = GWRO + 0x0a00,
 670         GWGRLULC        = GWRO + 0x0a04,
 671         GWRLIVC0        = GWRO + 0x0a80,
 672         GWRLULC0        = GWRO + 0x0a84,
 673         GWIDPC          = GWRO + 0x0b00,
 674         GWIDC0          = GWRO + 0x0c00,
 675         GWDIS0          = GWRO + 0x1100,
 676         GWDIE0          = GWRO + 0x1104,
 677         GWDID0          = GWRO + 0x1108,
 678         GWTSDIS         = GWRO + 0x1180,
 679         GWTSDIE         = GWRO + 0x1184,
 680         GWTSDID         = GWRO + 0x1188,
 681         GWEIS0          = GWRO + 0x1190,
 682         GWEIE0          = GWRO + 0x1194,
 683         GWEID0          = GWRO + 0x1198,
 684         GWEIS1          = GWRO + 0x11a0,
 685         GWEIE1          = GWRO + 0x11a4,
 686         GWEID1          = GWRO + 0x11a8,
 687         GWEIS20         = GWRO + 0x1200,
 688         GWEIE20         = GWRO + 0x1204,
 689         GWEID20         = GWRO + 0x1208,
 690         GWEIS3          = GWRO + 0x1280,
 691         GWEIE3          = GWRO + 0x1284,
 692         GWEID3          = GWRO + 0x1288,
 693         GWEIS4          = GWRO + 0x1290,
 694         GWEIE4          = GWRO + 0x1294,
 695         GWEID4          = GWRO + 0x1298,
 696         GWEIS5          = GWRO + 0x12a0,
 697         GWEIE5          = GWRO + 0x12a4,
 698         GWEID5          = GWRO + 0x12a8,
 699         GWSCR0          = GWRO + 0x1800,
 700         GWSCR1          = GWRO + 0x1900,
 701 };
 702
 703 /* ETHA/RMAC */
 704 enum rswitch_etha_mode {
 705         EAMC_OPC_RESET,
 706         EAMC_OPC_DISABLE,
 707         EAMC_OPC_CONFIG,
 708         EAMC_OPC_OPERATION,
 709 };
 710
 711 #define EAMS_OPS_MASK           EAMC_OPC_OPERATION
 712
 713 #define EAVCC_VEM_SC_TAG        (0x3 << 16)
 714
 715 #define MPIC_PIS_MII            0x00
 716 #define MPIC_PIS_GMII           0x02
 717 #define MPIC_PIS_XGMII          0x04
 718 #define MPIC_LSC_SHIFT          3
 719 #define MPIC_LSC_100M           (1 << MPIC_LSC_SHIFT)
 720 #define MPIC_LSC_1G             (2 << MPIC_LSC_SHIFT)
 721 #define MPIC_LSC_2_5G           (3 << MPIC_LSC_SHIFT)
 722
 723 #define MDIO_READ_C45           0x03
 724 #define MDIO_WRITE_C45          0x01
 725
 726 #define MPSM_PSME               BIT(0)
 727 #define MPSM_MFF_C45            BIT(2)
 728 #define MPSM_PRD_SHIFT          16
 729 #define MPSM_PRD_MASK           GENMASK(31, MPSM_PRD_SHIFT)
 730
 731 /* Completion flags */
 732 #define MMIS1_PAACS             BIT(2) /* Address */
 733 #define MMIS1_PWACS             BIT(1) /* Write */
 734 #define MMIS1_PRACS             BIT(0) /* Read */
 735 #define MMIS1_CLEAR_FLAGS       0xf
 736
 737 #define MPIC_PSMCS_SHIFT        16
 738 #define MPIC_PSMCS_MASK         GENMASK(22, MPIC_PSMCS_SHIFT)
 739 #define MPIC_PSMCS(val)         ((val) << MPIC_PSMCS_SHIFT)
 740
 741 #define MPIC_PSMHT_SHIFT        24
 742 #define MPIC_PSMHT_MASK         GENMASK(26, MPIC_PSMHT_SHIFT)
 743 #define MPIC_PSMHT(val)         ((val) << MPIC_PSMHT_SHIFT)
 744
 745 #define MLVC_PLV                BIT(16)
 746
 747 /* GWCA */
 748 enum rswitch_gwca_mode {
 749         GWMC_OPC_RESET,
 750         GWMC_OPC_DISABLE,
 751         GWMC_OPC_CONFIG,
 752         GWMC_OPC_OPERATION,
 753 };
 754
 755 #define GWMS_OPS_MASK           GWMC_OPC_OPERATION
 756
 757 #define GWMTIRM_MTIOG           BIT(0)
 758 #define GWMTIRM_MTR             BIT(1)
 759
 760 #define GWVCC_VEM_SC_TAG        (0x3 << 16)
 761
 762 #define GWARIRM_ARIOG           BIT(0)
 763 #define GWARIRM_ARR             BIT(1)
 764
 765 #define GWDCC_BALR              BIT(24)
 766 #define GWDCC_DQT               BIT(11)
 767 #define GWDCC_ETS               BIT(9)
 768 #define GWDCC_EDE               BIT(8)
 769
 770 #define GWTRC(queue)            (GWTRC0 + (queue) / 32 * 4)
 771 #define GWDCC_OFFS(queue)       (GWDCC0 + (queue) * 4)
 772
 773 #define GWDIS(i)                (GWDIS0 + (i) * 0x10)
 774 #define GWDIE(i)                (GWDIE0 + (i) * 0x10)
 775 #define GWDID(i)                (GWDID0 + (i) * 0x10)
 776
 777 /* COMA */
 778 #define RRC_RR                  BIT(0)
 779 #define RRC_RR_CLR              0
 780 #define RCEC_ACE_DEFAULT        (BIT(0) | BIT(AGENT_INDEX_GWCA))
 781 #define RCEC_RCE                BIT(16)
 782 #define RCDC_RCD                BIT(16)
 783
 784 #define CABPIRM_BPIOG           BIT(0)
 785 #define CABPIRM_BPR             BIT(1)
 786
 787 /* MFWD */
 788 #define FWPC0_LTHTA             BIT(0)
 789 #define FWPC0_IP4UE             BIT(3)
 790 #define FWPC0_IP4TE             BIT(4)
 791 #define FWPC0_IP4OE             BIT(5)
 792 #define FWPC0_L2SE              BIT(9)
 793 #define FWPC0_IP4EA             BIT(10)
 794 #define FWPC0_IPDSA             BIT(12)
 795 #define FWPC0_IPHLA             BIT(18)
 796 #define FWPC0_MACSDA            BIT(20)
 797 #define FWPC0_MACHLA            BIT(26)
 798 #define FWPC0_MACHMA            BIT(27)
 799 #define FWPC0_VLANSA            BIT(28)
 800
 801 #define FWPC0(i)                (FWPC00 + (i) * 0x10)
 802 #define FWPC0_DEFAULT           (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \
 803                                  FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \
 804                                  FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \
 805                                  FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA)
 806 #define FWPC1(i)                (FWPC10 + (i) * 0x10)
 807 #define FWPC1_DDE               BIT(0)
 808
 809 #define FWPBFC(i)               (FWPBFC0 + (i) * 0x10)
 810
 811 #define FWPBFCSDC(j, i)         (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)
 812
 813 /* TOP */
 814 #define TPEMIMC7(queue)         (TPEMIMC70 + (queue) * 4)
 815
 816 /* Descriptors */
 817 enum RX_DS_CC_BIT {
 818         RX_DS   = 0x0fff, /* Data size */
 819         RX_TR   = 0x1000, /* Truncation indication */
 820         RX_EI   = 0x2000, /* Error indication */
 821         RX_PS   = 0xc000, /* Padding selection */
 822 };
 823
 824 enum TX_DS_TAGL_BIT {
 825         TX_DS   = 0x0fff, /* Data size */
 826         TX_TAGL = 0xf000, /* Frame tag LSBs */
 827 };
 828
 829 enum DIE_DT {
 830         /* Frame data */
 831         DT_FSINGLE      = 0x80,
 832         DT_FSTART       = 0x90,
 833         DT_FMID         = 0xa0,
 834         DT_FEND         = 0xb8,
 835
 836         /* Chain control */
 837         DT_LEMPTY       = 0xc0,
 838         DT_EEMPTY       = 0xd0,
 839         DT_LINKFIX      = 0x00,
 840         DT_LINK         = 0xe0,
 841         DT_EOS          = 0xf0,
 842         /* HW/SW arbitration */
 843         DT_FEMPTY       = 0x40,
 844         DT_FEMPTY_IS    = 0x10,
 845         DT_FEMPTY_IC    = 0x20,
 846         DT_FEMPTY_ND    = 0x38,
 847         DT_FEMPTY_START = 0x50,
 848         DT_FEMPTY_MID   = 0x60,
 849         DT_FEMPTY_END   = 0x70,
 850
 851         DT_MASK         = 0xf0,
 852         DIE             = 0x08, /* Descriptor Interrupt Enable */
 853 };
 854
 855 /* Both transmission and reception */
 856 #define INFO1_FMT               BIT(2)
 857 #define INFO1_TXC               BIT(3)
 858
 859 /* For transmission */
 860 #define INFO1_TSUN(val)         ((u64)(val) << 8ULL)
 861 #define INFO1_CSD0(index)       ((u64)(index) << 32ULL)
 862 #define INFO1_CSD1(index)       ((u64)(index) << 40ULL)
 863 #define INFO1_DV(port_vector)   ((u64)(port_vector) << 48ULL)
 864
 865 /* For reception */
 866 #define INFO1_SPN(port)         ((u64)(port) << 36ULL)
 867
 868 struct rswitch_desc {
 869         __le16 info_ds; /* Descriptor size */
 870         u8 die_dt;      /* Descriptor interrupt enable and type */
 871         __u8  dptrh;    /* Descriptor pointer MSB */
 872         __le32 dptrl;   /* Descriptor pointer LSW */
 873 } __packed;
 874
 875 struct rswitch_ts_desc {
 876         struct rswitch_desc desc;
 877         __le32 ts_nsec;
 878         __le32 ts_sec;
 879 } __packed;
 880
 881 struct rswitch_ext_desc {
 882         struct rswitch_desc desc;
 883         __le64 info1;
 884 } __packed;
 885
 886 struct rswitch_ext_ts_desc {
 887         struct rswitch_desc desc;
 888         __le64 info1;
 889         __le32 ts_nsec;
 890         __le32 ts_sec;
 891 } __packed;
 892
 893 struct rswitch_etha {
 894         int index;
 895         void __iomem *addr;
 896         void __iomem *coma_addr;
 897         bool external_phy;
 898         struct mii_bus *mii;
 899         phy_interface_t phy_interface;
 900         u8 mac_addr[MAX_ADDR_LEN];
 901         int link;
 902         int speed;
 903
 904         /* This hardware could not be initialized twice so that marked
 905          * this flag to avoid multiple initialization.
 906          */
 907         bool operated;
 908 };
 909
 910 /* The datasheet said descriptor "chain" and/or "queue". For consistency of
 911  * name, this driver calls "queue".
 912  */
 913 struct rswitch_gwca_queue {
 914         int index;
 915         bool dir_tx;
 916         bool gptp;
 917         union {
 918                 struct rswitch_ext_desc *ring;
 919                 struct rswitch_ext_ts_desc *ts_ring;
 920         };
 921         dma_addr_t ring_dma;
 922         int ring_size;
 923         int cur;
 924         int dirty;
 925         struct sk_buff **skbs;
 926
 927         struct net_device *ndev;        /* queue to ndev for irq */
 928 };
 929
 930 #define RSWITCH_NUM_IRQ_REGS    (RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))
 931 struct rswitch_gwca {
 932         int index;
 933         struct rswitch_gwca_queue *queues;
 934         int num_queues;
 935         DECLARE_BITMAP(used, RSWITCH_MAX_NUM_QUEUES);
 936         u32 tx_irq_bits[RSWITCH_NUM_IRQ_REGS];
 937         u32 rx_irq_bits[RSWITCH_NUM_IRQ_REGS];
 938         int speed;
 939 };
 940
 941 #define NUM_QUEUES_PER_NDEV     2
 942 struct rswitch_device {
 943         struct rswitch_private *priv;
 944         struct net_device *ndev;
 945         struct napi_struct napi;
 946         struct phylink *phylink;
 947         struct phylink_config phylink_config;
 948         void __iomem *addr;
 949         struct rswitch_gwca_queue *tx_queue;
 950         struct rswitch_gwca_queue *rx_queue;
 951         u8 ts_tag;
 952         bool disabled;
 953
 954         int port;
 955         struct rswitch_etha *etha;
 956         struct device_node *np_port;
 957         struct phy *serdes;
 958 };
 959
 960 struct rswitch_mfwd_mac_table_entry {
 961         int queue_index;
 962         unsigned char addr[MAX_ADDR_LEN];
 963 };
 964
 965 struct rswitch_mfwd {
 966         struct rswitch_mac_table_entry *mac_table_entries;
 967         int num_mac_table_entries;
 968 };
 969
 970 struct rswitch_private {
 971         struct platform_device *pdev;
 972         void __iomem *addr;
 973         struct rcar_gen4_ptp_private *ptp_priv;
 974         struct rswitch_desc *linkfix_table;
 975         dma_addr_t linkfix_table_dma;
 976         u32 linkfix_table_size;
 977
 978         struct rswitch_device *rdev[RSWITCH_NUM_PORTS];
 979
 980         struct rswitch_gwca gwca;
 981         struct rswitch_etha etha[RSWITCH_NUM_PORTS];
 982         struct rswitch_mfwd mfwd;
 983
 984         bool gwca_halt;
 985 };
 986
 987 #endif  /* #ifndef __RSWITCH_H__ */