1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet Switch device driver
4 * Copyright (C) 2022 Renesas Electronics Corporation
7 #include <linux/dma-mapping.h>
9 #include <linux/etherdevice.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/net_tstamp.h>
15 #include <linux/of_device.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19 #include <linux/phy/phy.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/rtnetlink.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
27 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected)
31 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected,
32 1, RSWITCH_TIMEOUT_US);
35 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set)
37 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg);
40 /* Common Agent block (COMA) */
41 static void rswitch_reset(struct rswitch_private *priv)
43 iowrite32(RRC_RR, priv->addr + RRC);
44 iowrite32(RRC_RR_CLR, priv->addr + RRC);
47 static void rswitch_clock_enable(struct rswitch_private *priv)
49 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC);
52 static void rswitch_clock_disable(struct rswitch_private *priv)
54 iowrite32(RCDC_RCD, priv->addr + RCDC);
57 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port)
59 u32 val = ioread32(coma_addr + RCEC);
62 return (val & BIT(port)) ? true : false;
67 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable)
72 val = ioread32(coma_addr + RCEC);
73 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC);
75 val = ioread32(coma_addr + RCDC);
76 iowrite32(val | BIT(port), coma_addr + RCDC);
80 static int rswitch_bpool_config(struct rswitch_private *priv)
84 val = ioread32(priv->addr + CABPIRM);
85 if (val & CABPIRM_BPR)
88 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM);
90 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR);
93 /* R-Switch-2 block (TOP) */
94 static void rswitch_top_init(struct rswitch_private *priv)
98 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++)
99 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i));
102 /* Forwarding engine block (MFWD) */
103 static void rswitch_fwd_init(struct rswitch_private *priv)
108 for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
109 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i));
110 iowrite32(0, priv->addr + FWPBFC(i));
113 for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
114 iowrite32(priv->rdev[i]->rx_queue->index,
115 priv->addr + FWPBFCSDC(GWCA_INDEX, i));
116 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i));
120 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index));
121 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index));
122 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index));
123 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index));
126 /* Gateway CPU agent block (GWCA) */
127 static int rswitch_gwca_change_mode(struct rswitch_private *priv,
128 enum rswitch_gwca_mode mode)
132 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index))
133 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1);
135 iowrite32(mode, priv->addr + GWMC);
137 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode);
139 if (mode == GWMC_OPC_DISABLE)
140 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0);
145 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv)
147 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM);
149 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR);
152 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv)
154 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM);
156 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR);
159 static void rswitch_gwca_set_rate_limit(struct rswitch_private *priv, int rate)
161 u32 gwgrlulc, gwgrlc;
165 gwgrlulc = 0x0000005f;
169 dev_err(&priv->pdev->dev, "%s: This rate is not supported (%d)\n", __func__, rate);
173 iowrite32(gwgrlulc, priv->addr + GWGRLULC);
174 iowrite32(gwgrlc, priv->addr + GWGRLC);
177 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx)
179 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits;
182 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) {
183 if (dis[i] & mask[i])
190 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis)
194 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) {
195 dis[i] = ioread32(priv->addr + GWDIS(i));
196 dis[i] &= ioread32(priv->addr + GWDIE(i));
200 static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable)
202 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32);
204 iowrite32(BIT(index % 32), priv->addr + offs);
207 static void rswitch_ack_data_irq(struct rswitch_private *priv, int index)
209 u32 offs = GWDIS(index / 32);
211 iowrite32(BIT(index % 32), priv->addr + offs);
214 static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num)
216 int index = cur ? gq->cur : gq->dirty;
218 if (index + num >= gq->ring_size)
219 index = (index + num) % gq->ring_size;
226 static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq)
228 if (gq->cur >= gq->dirty)
229 return gq->cur - gq->dirty;
231 return gq->ring_size - gq->dirty + gq->cur;
234 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq)
236 struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty];
238 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY)
244 static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq,
245 int start_index, int num)
249 for (i = 0; i < num; i++) {
250 index = (i + start_index) % gq->ring_size;
253 gq->skbs[index] = netdev_alloc_skb_ip_align(gq->ndev,
254 PKT_BUF_SZ + RSWITCH_ALIGN - 1);
255 if (!gq->skbs[index])
262 for (i--; i >= 0; i--) {
263 index = (i + start_index) % gq->ring_size;
264 dev_kfree_skb(gq->skbs[index]);
265 gq->skbs[index] = NULL;
271 static void rswitch_gwca_queue_free(struct net_device *ndev,
272 struct rswitch_gwca_queue *gq)
277 dma_free_coherent(ndev->dev.parent,
278 sizeof(struct rswitch_ext_ts_desc) *
279 (gq->ring_size + 1), gq->rx_ring, gq->ring_dma);
282 for (i = 0; i < gq->ring_size; i++)
283 dev_kfree_skb(gq->skbs[i]);
285 dma_free_coherent(ndev->dev.parent,
286 sizeof(struct rswitch_ext_desc) *
287 (gq->ring_size + 1), gq->tx_ring, gq->ring_dma);
295 static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv)
297 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
299 dma_free_coherent(&priv->pdev->dev,
300 sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1),
301 gq->ts_ring, gq->ring_dma);
305 static int rswitch_gwca_queue_alloc(struct net_device *ndev,
306 struct rswitch_private *priv,
307 struct rswitch_gwca_queue *gq,
308 bool dir_tx, int ring_size)
313 gq->ring_size = ring_size;
316 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL);
321 rswitch_gwca_queue_alloc_skb(gq, 0, gq->ring_size);
323 gq->rx_ring = dma_alloc_coherent(ndev->dev.parent,
324 sizeof(struct rswitch_ext_ts_desc) *
325 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL);
327 gq->tx_ring = dma_alloc_coherent(ndev->dev.parent,
328 sizeof(struct rswitch_ext_desc) *
329 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL);
332 if (!gq->rx_ring && !gq->tx_ring)
336 bit = BIT(gq->index % 32);
338 priv->gwca.tx_irq_bits[i] |= bit;
340 priv->gwca.rx_irq_bits[i] |= bit;
345 rswitch_gwca_queue_free(ndev, gq);
350 static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv)
352 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
354 gq->ring_size = TS_RING_SIZE;
355 gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev,
356 sizeof(struct rswitch_ts_desc) *
357 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL);
358 return !gq->ts_ring ? -ENOMEM : 0;
361 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr)
363 desc->dptrl = cpu_to_le32(lower_32_bits(addr));
364 desc->dptrh = upper_32_bits(addr) & 0xff;
367 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc)
369 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32;
372 static int rswitch_gwca_queue_format(struct net_device *ndev,
373 struct rswitch_private *priv,
374 struct rswitch_gwca_queue *gq)
376 int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size;
377 struct rswitch_ext_desc *desc;
378 struct rswitch_desc *linkfix;
382 memset(gq->tx_ring, 0, ring_size);
383 for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) {
385 dma_addr = dma_map_single(ndev->dev.parent,
386 gq->skbs[i]->data, PKT_BUF_SZ,
388 if (dma_mapping_error(ndev->dev.parent, dma_addr))
391 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ);
392 rswitch_desc_set_dptr(&desc->desc, dma_addr);
393 desc->desc.die_dt = DT_FEMPTY | DIE;
395 desc->desc.die_dt = DT_EEMPTY | DIE;
398 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma);
399 desc->desc.die_dt = DT_LINKFIX;
401 linkfix = &priv->gwca.linkfix_table[gq->index];
402 linkfix->die_dt = DT_LINKFIX;
403 rswitch_desc_set_dptr(linkfix, gq->ring_dma);
405 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_EDE,
406 priv->addr + GWDCC_OFFS(gq->index));
412 for (i--, desc = gq->tx_ring; i >= 0; i--, desc++) {
413 dma_addr = rswitch_desc_get_dptr(&desc->desc);
414 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ,
422 static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv,
423 int start_index, int num)
425 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
426 struct rswitch_ts_desc *desc;
429 for (i = 0; i < num; i++) {
430 index = (i + start_index) % gq->ring_size;
431 desc = &gq->ts_ring[index];
432 desc->desc.die_dt = DT_FEMPTY_ND | DIE;
436 static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev,
437 struct rswitch_gwca_queue *gq,
438 int start_index, int num)
440 struct rswitch_device *rdev = netdev_priv(ndev);
441 struct rswitch_ext_ts_desc *desc;
445 for (i = 0; i < num; i++) {
446 index = (i + start_index) % gq->ring_size;
447 desc = &gq->rx_ring[index];
449 dma_addr = dma_map_single(ndev->dev.parent,
450 gq->skbs[index]->data, PKT_BUF_SZ,
452 if (dma_mapping_error(ndev->dev.parent, dma_addr))
455 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ);
456 rswitch_desc_set_dptr(&desc->desc, dma_addr);
458 desc->desc.die_dt = DT_FEMPTY | DIE;
459 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index));
461 desc->desc.die_dt = DT_EEMPTY | DIE;
469 for (i--; i >= 0; i--) {
470 index = (i + start_index) % gq->ring_size;
471 desc = &gq->rx_ring[index];
472 dma_addr = rswitch_desc_get_dptr(&desc->desc);
473 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ,
481 static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev,
482 struct rswitch_private *priv,
483 struct rswitch_gwca_queue *gq)
485 int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size;
486 struct rswitch_ext_ts_desc *desc;
487 struct rswitch_desc *linkfix;
490 memset(gq->rx_ring, 0, ring_size);
491 err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size);
495 desc = &gq->rx_ring[gq->ring_size]; /* Last */
496 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma);
497 desc->desc.die_dt = DT_LINKFIX;
499 linkfix = &priv->gwca.linkfix_table[gq->index];
500 linkfix->die_dt = DT_LINKFIX;
501 rswitch_desc_set_dptr(linkfix, gq->ring_dma);
503 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_ETS | GWDCC_EDE,
504 priv->addr + GWDCC_OFFS(gq->index));
509 static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv)
511 int i, num_queues = priv->gwca.num_queues;
512 struct rswitch_gwca *gwca = &priv->gwca;
513 struct device *dev = &priv->pdev->dev;
515 gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues;
516 gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size,
517 &gwca->linkfix_table_dma, GFP_KERNEL);
518 if (!gwca->linkfix_table)
520 for (i = 0; i < num_queues; i++)
521 gwca->linkfix_table[i].die_dt = DT_EOS;
526 static void rswitch_gwca_linkfix_free(struct rswitch_private *priv)
528 struct rswitch_gwca *gwca = &priv->gwca;
530 if (gwca->linkfix_table)
531 dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size,
532 gwca->linkfix_table, gwca->linkfix_table_dma);
533 gwca->linkfix_table = NULL;
536 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv)
538 struct rswitch_gwca_queue *gq;
541 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues);
542 if (index >= priv->gwca.num_queues)
544 set_bit(index, priv->gwca.used);
545 gq = &priv->gwca.queues[index];
546 memset(gq, 0, sizeof(*gq));
552 static void rswitch_gwca_put(struct rswitch_private *priv,
553 struct rswitch_gwca_queue *gq)
555 clear_bit(gq->index, priv->gwca.used);
558 static int rswitch_txdmac_alloc(struct net_device *ndev)
560 struct rswitch_device *rdev = netdev_priv(ndev);
561 struct rswitch_private *priv = rdev->priv;
564 rdev->tx_queue = rswitch_gwca_get(priv);
568 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE);
570 rswitch_gwca_put(priv, rdev->tx_queue);
577 static void rswitch_txdmac_free(struct net_device *ndev)
579 struct rswitch_device *rdev = netdev_priv(ndev);
581 rswitch_gwca_queue_free(ndev, rdev->tx_queue);
582 rswitch_gwca_put(rdev->priv, rdev->tx_queue);
585 static int rswitch_txdmac_init(struct rswitch_private *priv, int index)
587 struct rswitch_device *rdev = priv->rdev[index];
589 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue);
592 static int rswitch_rxdmac_alloc(struct net_device *ndev)
594 struct rswitch_device *rdev = netdev_priv(ndev);
595 struct rswitch_private *priv = rdev->priv;
598 rdev->rx_queue = rswitch_gwca_get(priv);
602 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE);
604 rswitch_gwca_put(priv, rdev->rx_queue);
611 static void rswitch_rxdmac_free(struct net_device *ndev)
613 struct rswitch_device *rdev = netdev_priv(ndev);
615 rswitch_gwca_queue_free(ndev, rdev->rx_queue);
616 rswitch_gwca_put(rdev->priv, rdev->rx_queue);
619 static int rswitch_rxdmac_init(struct rswitch_private *priv, int index)
621 struct rswitch_device *rdev = priv->rdev[index];
622 struct net_device *ndev = rdev->ndev;
624 return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue);
627 static int rswitch_gwca_hw_init(struct rswitch_private *priv)
631 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
634 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG);
638 err = rswitch_gwca_mcast_table_reset(priv);
641 err = rswitch_gwca_axi_ram_reset(priv);
645 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC);
646 iowrite32(0, priv->addr + GWTTFC);
647 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1);
648 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0);
649 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10);
650 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00);
651 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0);
652 rswitch_gwca_set_rate_limit(priv, priv->gwca.speed);
654 for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
655 err = rswitch_rxdmac_init(priv, i);
658 err = rswitch_txdmac_init(priv, i);
663 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
666 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION);
669 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv)
673 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
676 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET);
680 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
683 static int rswitch_gwca_halt(struct rswitch_private *priv)
687 priv->gwca_halt = true;
688 err = rswitch_gwca_hw_deinit(priv);
689 dev_err(&priv->pdev->dev, "halted (%d)\n", err);
694 static bool rswitch_rx(struct net_device *ndev, int *quota)
696 struct rswitch_device *rdev = netdev_priv(ndev);
697 struct rswitch_gwca_queue *gq = rdev->rx_queue;
698 struct rswitch_ext_ts_desc *desc;
699 int limit, boguscnt, num, ret;
708 boguscnt = min_t(int, gq->ring_size, *quota);
711 desc = &gq->rx_ring[gq->cur];
712 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) {
714 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS;
715 skb = gq->skbs[gq->cur];
716 gq->skbs[gq->cur] = NULL;
717 dma_addr = rswitch_desc_get_dptr(&desc->desc);
718 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE);
719 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT;
721 struct skb_shared_hwtstamps *shhwtstamps;
722 struct timespec64 ts;
724 shhwtstamps = skb_hwtstamps(skb);
725 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
726 ts.tv_sec = __le32_to_cpu(desc->ts_sec);
727 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff));
728 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
730 skb_put(skb, pkt_len);
731 skb->protocol = eth_type_trans(skb, ndev);
732 netif_receive_skb(skb);
733 rdev->ndev->stats.rx_packets++;
734 rdev->ndev->stats.rx_bytes += pkt_len;
736 gq->cur = rswitch_next_queue_index(gq, true, 1);
737 desc = &gq->rx_ring[gq->cur];
743 num = rswitch_get_num_cur_queues(gq);
744 ret = rswitch_gwca_queue_alloc_skb(gq, gq->dirty, num);
747 ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num);
750 gq->dirty = rswitch_next_queue_index(gq, false, num);
752 *quota -= limit - boguscnt;
754 return boguscnt <= 0;
757 rswitch_gwca_halt(rdev->priv);
762 static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only)
764 struct rswitch_device *rdev = netdev_priv(ndev);
765 struct rswitch_gwca_queue *gq = rdev->tx_queue;
766 struct rswitch_ext_desc *desc;
772 for (; rswitch_get_num_cur_queues(gq) > 0;
773 gq->dirty = rswitch_next_queue_index(gq, false, 1)) {
774 desc = &gq->tx_ring[gq->dirty];
775 if (free_txed_only && (desc->desc.die_dt & DT_MASK) != DT_FEMPTY)
779 size = le16_to_cpu(desc->desc.info_ds) & TX_DS;
780 skb = gq->skbs[gq->dirty];
782 dma_addr = rswitch_desc_get_dptr(&desc->desc);
783 dma_unmap_single(ndev->dev.parent, dma_addr,
784 size, DMA_TO_DEVICE);
785 dev_kfree_skb_any(gq->skbs[gq->dirty]);
786 gq->skbs[gq->dirty] = NULL;
789 desc->desc.die_dt = DT_EEMPTY;
790 rdev->ndev->stats.tx_packets++;
791 rdev->ndev->stats.tx_bytes += size;
797 static int rswitch_poll(struct napi_struct *napi, int budget)
799 struct net_device *ndev = napi->dev;
800 struct rswitch_private *priv;
801 struct rswitch_device *rdev;
804 rdev = netdev_priv(ndev);
808 rswitch_tx_free(ndev, true);
810 if (rswitch_rx(ndev, "a))
812 else if (rdev->priv->gwca_halt)
814 else if (rswitch_is_queue_rxed(rdev->rx_queue))
817 netif_wake_subqueue(ndev, 0);
821 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true);
822 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true);
825 return budget - quota;
833 static void rswitch_queue_interrupt(struct net_device *ndev)
835 struct rswitch_device *rdev = netdev_priv(ndev);
837 if (napi_schedule_prep(&rdev->napi)) {
838 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false);
839 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false);
840 __napi_schedule(&rdev->napi);
844 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis)
846 struct rswitch_gwca_queue *gq;
849 for (i = 0; i < priv->gwca.num_queues; i++) {
850 gq = &priv->gwca.queues[i];
851 index = gq->index / 32;
852 bit = BIT(gq->index % 32);
853 if (!(dis[index] & bit))
856 rswitch_ack_data_irq(priv, gq->index);
857 rswitch_queue_interrupt(gq->ndev);
863 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id)
865 struct rswitch_private *priv = dev_id;
866 u32 dis[RSWITCH_NUM_IRQ_REGS];
867 irqreturn_t ret = IRQ_NONE;
869 rswitch_get_data_irq_status(priv, dis);
871 if (rswitch_is_any_data_irq(priv, dis, true) ||
872 rswitch_is_any_data_irq(priv, dis, false))
873 ret = rswitch_data_irq(priv, dis);
878 static int rswitch_gwca_request_irqs(struct rswitch_private *priv)
880 char *resource_name, *irq_name;
883 for (i = 0; i < GWCA_NUM_IRQS; i++) {
884 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i);
888 irq = platform_get_irq_byname(priv->pdev, resource_name);
889 kfree(resource_name);
893 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL,
898 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq,
907 static void rswitch_ts(struct rswitch_private *priv)
909 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
910 struct rswitch_gwca_ts_info *ts_info, *ts_info2;
911 struct skb_shared_hwtstamps shhwtstamps;
912 struct rswitch_ts_desc *desc;
913 struct timespec64 ts;
917 desc = &gq->ts_ring[gq->cur];
918 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) {
921 port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl));
922 tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl));
924 list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) {
925 if (!(ts_info->port == port && ts_info->tag == tag))
928 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
929 ts.tv_sec = __le32_to_cpu(desc->ts_sec);
930 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff));
931 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
932 skb_tstamp_tx(ts_info->skb, &shhwtstamps);
933 dev_consume_skb_irq(ts_info->skb);
934 list_del(&ts_info->list);
939 gq->cur = rswitch_next_queue_index(gq, true, 1);
940 desc = &gq->ts_ring[gq->cur];
943 num = rswitch_get_num_cur_queues(gq);
944 rswitch_gwca_ts_queue_fill(priv, gq->dirty, num);
945 gq->dirty = rswitch_next_queue_index(gq, false, num);
948 static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id)
950 struct rswitch_private *priv = dev_id;
952 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) {
953 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS);
962 static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv)
966 irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME);
970 return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq,
971 0, GWCA_TS_IRQ_NAME, priv);
974 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */
975 static int rswitch_etha_change_mode(struct rswitch_etha *etha,
976 enum rswitch_etha_mode mode)
980 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index))
981 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1);
983 iowrite32(mode, etha->addr + EAMC);
985 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode);
987 if (mode == EAMC_OPC_DISABLE)
988 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0);
993 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha)
995 u32 mrmac0 = ioread32(etha->addr + MRMAC0);
996 u32 mrmac1 = ioread32(etha->addr + MRMAC1);
997 u8 *mac = ða->mac_addr[0];
999 mac[0] = (mrmac0 >> 8) & 0xFF;
1000 mac[1] = (mrmac0 >> 0) & 0xFF;
1001 mac[2] = (mrmac1 >> 24) & 0xFF;
1002 mac[3] = (mrmac1 >> 16) & 0xFF;
1003 mac[4] = (mrmac1 >> 8) & 0xFF;
1004 mac[5] = (mrmac1 >> 0) & 0xFF;
1007 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac)
1009 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
1010 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1011 etha->addr + MRMAC1);
1014 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha)
1016 iowrite32(MLVC_PLV, etha->addr + MLVC);
1018 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0);
1021 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
1025 rswitch_etha_write_mac_address(etha, mac);
1027 switch (etha->speed) {
1029 val = MPIC_LSC_100M;
1035 val = MPIC_LSC_2_5G;
1041 iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC);
1044 static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
1046 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
1047 MPIC_PSMCS(0x05) | MPIC_PSMHT(0x06));
1048 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45);
1051 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)
1055 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);
1058 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG);
1062 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC);
1063 rswitch_rmac_setting(etha, mac);
1064 rswitch_etha_enable_mii(etha);
1066 err = rswitch_etha_wait_link_verification(etha);
1070 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);
1074 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION);
1077 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read,
1078 int phyad, int devad, int regad, int data)
1080 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45;
1084 if (devad == 0xffffffff)
1087 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);
1089 val = MPSM_PSME | MPSM_MFF_C45;
1090 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1092 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1096 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1099 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1101 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1105 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;
1107 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1109 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val,
1112 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS);
1118 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad,
1121 struct rswitch_etha *etha = bus->priv;
1123 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0);
1126 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad,
1129 struct rswitch_etha *etha = bus->priv;
1131 return rswitch_etha_set_access(etha, false, addr, devad, regad, val);
1134 /* Call of_node_put(port) after done */
1135 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev)
1137 struct device_node *ports, *port;
1141 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node,
1146 for_each_child_of_node(ports, port) {
1147 err = of_property_read_u32(port, "reg", &index);
1152 if (index == rdev->etha->index) {
1153 if (!of_device_is_available(port))
1165 static int rswitch_etha_get_params(struct rswitch_device *rdev)
1171 return 0; /* ignored */
1173 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface);
1177 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed);
1179 rdev->etha->speed = max_speed;
1183 /* if no "max-speed" property, let's use default speed */
1184 switch (rdev->etha->phy_interface) {
1185 case PHY_INTERFACE_MODE_MII:
1186 rdev->etha->speed = SPEED_100;
1188 case PHY_INTERFACE_MODE_SGMII:
1189 rdev->etha->speed = SPEED_1000;
1191 case PHY_INTERFACE_MODE_USXGMII:
1192 rdev->etha->speed = SPEED_2500;
1201 static int rswitch_mii_register(struct rswitch_device *rdev)
1203 struct device_node *mdio_np;
1204 struct mii_bus *mii_bus;
1207 mii_bus = mdiobus_alloc();
1211 mii_bus->name = "rswitch_mii";
1212 sprintf(mii_bus->id, "etha%d", rdev->etha->index);
1213 mii_bus->priv = rdev->etha;
1214 mii_bus->read_c45 = rswitch_etha_mii_read_c45;
1215 mii_bus->write_c45 = rswitch_etha_mii_write_c45;
1216 mii_bus->parent = &rdev->priv->pdev->dev;
1218 mdio_np = of_get_child_by_name(rdev->np_port, "mdio");
1219 err = of_mdiobus_register(mii_bus, mdio_np);
1221 mdiobus_free(mii_bus);
1225 rdev->etha->mii = mii_bus;
1228 of_node_put(mdio_np);
1233 static void rswitch_mii_unregister(struct rswitch_device *rdev)
1235 if (rdev->etha->mii) {
1236 mdiobus_unregister(rdev->etha->mii);
1237 mdiobus_free(rdev->etha->mii);
1238 rdev->etha->mii = NULL;
1242 static void rswitch_adjust_link(struct net_device *ndev)
1244 struct rswitch_device *rdev = netdev_priv(ndev);
1245 struct phy_device *phydev = ndev->phydev;
1247 /* Current hardware has a restriction not to change speed at runtime */
1248 if (phydev->link != rdev->etha->link) {
1249 phy_print_status(phydev);
1251 phy_power_on(rdev->serdes);
1253 phy_power_off(rdev->serdes);
1255 rdev->etha->link = phydev->link;
1259 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev,
1260 struct phy_device *phydev)
1262 /* Current hardware has a restriction not to change speed at runtime */
1263 switch (rdev->etha->speed) {
1265 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1266 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
1269 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT);
1270 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
1273 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT);
1274 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1280 phy_set_max_speed(phydev, rdev->etha->speed);
1283 static int rswitch_phy_device_init(struct rswitch_device *rdev)
1285 struct phy_device *phydev;
1286 struct device_node *phy;
1292 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0);
1296 /* Set phydev->host_interfaces before calling of_phy_connect() to
1297 * configure the PHY with the information of host_interfaces.
1299 phydev = of_phy_find_device(phy);
1302 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces);
1304 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0,
1305 rdev->etha->phy_interface);
1309 phy_set_max_speed(phydev, SPEED_2500);
1310 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1311 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1312 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1313 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1314 rswitch_phy_remove_link_mode(rdev, phydev);
1316 phy_attached_info(phydev);
1325 static void rswitch_phy_device_deinit(struct rswitch_device *rdev)
1327 if (rdev->ndev->phydev) {
1328 phy_disconnect(rdev->ndev->phydev);
1329 rdev->ndev->phydev = NULL;
1333 static int rswitch_serdes_set_params(struct rswitch_device *rdev)
1337 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET,
1338 rdev->etha->phy_interface);
1342 return phy_set_speed(rdev->serdes, rdev->etha->speed);
1345 static int rswitch_ether_port_init_one(struct rswitch_device *rdev)
1349 if (!rdev->etha->operated) {
1350 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);
1353 rdev->etha->operated = true;
1356 err = rswitch_mii_register(rdev);
1360 err = rswitch_phy_device_init(rdev);
1362 goto err_phy_device_init;
1364 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL);
1365 if (IS_ERR(rdev->serdes)) {
1366 err = PTR_ERR(rdev->serdes);
1367 goto err_serdes_phy_get;
1370 err = rswitch_serdes_set_params(rdev);
1372 goto err_serdes_set_params;
1376 err_serdes_set_params:
1378 rswitch_phy_device_deinit(rdev);
1380 err_phy_device_init:
1381 rswitch_mii_unregister(rdev);
1386 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev)
1388 rswitch_phy_device_deinit(rdev);
1389 rswitch_mii_unregister(rdev);
1392 static int rswitch_ether_port_init_all(struct rswitch_private *priv)
1396 rswitch_for_each_enabled_port(priv, i) {
1397 err = rswitch_ether_port_init_one(priv->rdev[i]);
1402 rswitch_for_each_enabled_port(priv, i) {
1403 err = phy_init(priv->rdev[i]->serdes);
1411 rswitch_for_each_enabled_port_continue_reverse(priv, i)
1412 phy_exit(priv->rdev[i]->serdes);
1413 i = RSWITCH_NUM_PORTS;
1416 rswitch_for_each_enabled_port_continue_reverse(priv, i)
1417 rswitch_ether_port_deinit_one(priv->rdev[i]);
1422 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv)
1426 for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
1427 phy_exit(priv->rdev[i]->serdes);
1428 rswitch_ether_port_deinit_one(priv->rdev[i]);
1432 static int rswitch_open(struct net_device *ndev)
1434 struct rswitch_device *rdev = netdev_priv(ndev);
1436 phy_start(ndev->phydev);
1438 napi_enable(&rdev->napi);
1439 netif_start_queue(ndev);
1441 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true);
1442 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true);
1444 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS))
1445 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE);
1447 bitmap_set(rdev->priv->opened_ports, rdev->port, 1);
1452 static int rswitch_stop(struct net_device *ndev)
1454 struct rswitch_device *rdev = netdev_priv(ndev);
1455 struct rswitch_gwca_ts_info *ts_info, *ts_info2;
1457 netif_tx_stop_all_queues(ndev);
1458 bitmap_clear(rdev->priv->opened_ports, rdev->port, 1);
1460 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS))
1461 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID);
1463 list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) {
1464 if (ts_info->port != rdev->port)
1466 dev_kfree_skb_irq(ts_info->skb);
1467 list_del(&ts_info->list);
1471 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false);
1472 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false);
1474 phy_stop(ndev->phydev);
1475 napi_disable(&rdev->napi);
1480 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1482 struct rswitch_device *rdev = netdev_priv(ndev);
1483 struct rswitch_gwca_queue *gq = rdev->tx_queue;
1484 struct rswitch_ext_desc *desc;
1485 int ret = NETDEV_TX_OK;
1486 dma_addr_t dma_addr;
1488 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - 1) {
1489 netif_stop_subqueue(ndev, 0);
1493 if (skb_put_padto(skb, ETH_ZLEN))
1496 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE);
1497 if (dma_mapping_error(ndev->dev.parent, dma_addr)) {
1498 dev_kfree_skb_any(skb);
1502 gq->skbs[gq->cur] = skb;
1503 desc = &gq->tx_ring[gq->cur];
1504 rswitch_desc_set_dptr(&desc->desc, dma_addr);
1505 desc->desc.info_ds = cpu_to_le16(skb->len);
1507 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | INFO1_FMT);
1508 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1509 struct rswitch_gwca_ts_info *ts_info;
1511 ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC);
1513 dma_unmap_single(ndev->dev.parent, dma_addr, skb->len, DMA_TO_DEVICE);
1517 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1519 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC);
1521 ts_info->skb = skb_get(skb);
1522 ts_info->port = rdev->port;
1523 ts_info->tag = rdev->ts_tag;
1524 list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list);
1526 skb_tx_timestamp(skb);
1531 desc->desc.die_dt = DT_FSINGLE | DIE;
1532 wmb(); /* gq->cur must be incremented after die_dt was set */
1534 gq->cur = rswitch_next_queue_index(gq, true, 1);
1535 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32));
1540 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev)
1542 return &ndev->stats;
1545 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req)
1547 struct rswitch_device *rdev = netdev_priv(ndev);
1548 struct rcar_gen4_ptp_private *ptp_priv;
1549 struct hwtstamp_config config;
1551 ptp_priv = rdev->priv->ptp_priv;
1554 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1556 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) {
1557 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT:
1558 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1560 case RCAR_GEN4_RXTSTAMP_TYPE_ALL:
1561 config.rx_filter = HWTSTAMP_FILTER_ALL;
1564 config.rx_filter = HWTSTAMP_FILTER_NONE;
1568 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
1571 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req)
1573 struct rswitch_device *rdev = netdev_priv(ndev);
1574 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED;
1575 struct hwtstamp_config config;
1578 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1584 switch (config.tx_type) {
1585 case HWTSTAMP_TX_OFF:
1588 case HWTSTAMP_TX_ON:
1589 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED;
1595 switch (config.rx_filter) {
1596 case HWTSTAMP_FILTER_NONE:
1599 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1600 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT;
1603 config.rx_filter = HWTSTAMP_FILTER_ALL;
1604 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL;
1608 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1609 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1611 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
1614 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1616 if (!netif_running(ndev))
1621 return rswitch_hwstamp_get(ndev, req);
1623 return rswitch_hwstamp_set(ndev, req);
1625 return phy_mii_ioctl(ndev->phydev, req, cmd);
1629 static const struct net_device_ops rswitch_netdev_ops = {
1630 .ndo_open = rswitch_open,
1631 .ndo_stop = rswitch_stop,
1632 .ndo_start_xmit = rswitch_start_xmit,
1633 .ndo_get_stats = rswitch_get_stats,
1634 .ndo_eth_ioctl = rswitch_eth_ioctl,
1635 .ndo_validate_addr = eth_validate_addr,
1636 .ndo_set_mac_address = eth_mac_addr,
1639 static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info)
1641 struct rswitch_device *rdev = netdev_priv(ndev);
1643 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock);
1644 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1645 SOF_TIMESTAMPING_RX_SOFTWARE |
1646 SOF_TIMESTAMPING_SOFTWARE |
1647 SOF_TIMESTAMPING_TX_HARDWARE |
1648 SOF_TIMESTAMPING_RX_HARDWARE |
1649 SOF_TIMESTAMPING_RAW_HARDWARE;
1650 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
1651 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1656 static const struct ethtool_ops rswitch_ethtool_ops = {
1657 .get_ts_info = rswitch_get_ts_info,
1660 static const struct of_device_id renesas_eth_sw_of_table[] = {
1661 { .compatible = "renesas,r8a779f0-ether-switch", },
1664 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table);
1666 static void rswitch_etha_init(struct rswitch_private *priv, int index)
1668 struct rswitch_etha *etha = &priv->etha[index];
1670 memset(etha, 0, sizeof(*etha));
1671 etha->index = index;
1672 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE;
1673 etha->coma_addr = priv->addr;
1676 static int rswitch_device_alloc(struct rswitch_private *priv, int index)
1678 struct platform_device *pdev = priv->pdev;
1679 struct rswitch_device *rdev;
1680 struct net_device *ndev;
1683 if (index >= RSWITCH_NUM_PORTS)
1686 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1);
1690 SET_NETDEV_DEV(ndev, &pdev->dev);
1693 rdev = netdev_priv(ndev);
1696 priv->rdev[index] = rdev;
1698 rdev->etha = &priv->etha[index];
1699 rdev->addr = priv->addr;
1701 ndev->base_addr = (unsigned long)rdev->addr;
1702 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index);
1703 ndev->netdev_ops = &rswitch_netdev_ops;
1704 ndev->ethtool_ops = &rswitch_ethtool_ops;
1706 netif_napi_add(ndev, &rdev->napi, rswitch_poll);
1708 rdev->np_port = rswitch_get_port_node(rdev);
1709 rdev->disabled = !rdev->np_port;
1710 err = of_get_ethdev_address(rdev->np_port, ndev);
1711 of_node_put(rdev->np_port);
1713 if (is_valid_ether_addr(rdev->etha->mac_addr))
1714 eth_hw_addr_set(ndev, rdev->etha->mac_addr);
1716 eth_hw_addr_random(ndev);
1719 err = rswitch_etha_get_params(rdev);
1721 goto out_get_params;
1723 if (rdev->priv->gwca.speed < rdev->etha->speed)
1724 rdev->priv->gwca.speed = rdev->etha->speed;
1726 err = rswitch_rxdmac_alloc(ndev);
1730 err = rswitch_txdmac_alloc(ndev);
1737 rswitch_rxdmac_free(ndev);
1741 netif_napi_del(&rdev->napi);
1747 static void rswitch_device_free(struct rswitch_private *priv, int index)
1749 struct rswitch_device *rdev = priv->rdev[index];
1750 struct net_device *ndev = rdev->ndev;
1752 rswitch_txdmac_free(ndev);
1753 rswitch_rxdmac_free(ndev);
1754 netif_napi_del(&rdev->napi);
1758 static int rswitch_init(struct rswitch_private *priv)
1762 for (i = 0; i < RSWITCH_NUM_PORTS; i++)
1763 rswitch_etha_init(priv, i);
1765 rswitch_clock_enable(priv);
1766 for (i = 0; i < RSWITCH_NUM_PORTS; i++)
1767 rswitch_etha_read_mac_address(&priv->etha[i]);
1769 rswitch_reset(priv);
1771 rswitch_clock_enable(priv);
1772 rswitch_top_init(priv);
1773 err = rswitch_bpool_config(priv);
1777 err = rswitch_gwca_linkfix_alloc(priv);
1781 err = rswitch_gwca_ts_queue_alloc(priv);
1783 goto err_ts_queue_alloc;
1785 rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE);
1786 INIT_LIST_HEAD(&priv->gwca.ts_info_list);
1788 for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
1789 err = rswitch_device_alloc(priv, i);
1791 for (i--; i >= 0; i--)
1792 rswitch_device_free(priv, i);
1793 goto err_device_alloc;
1797 rswitch_fwd_init(priv);
1799 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4,
1800 RCAR_GEN4_PTP_CLOCK_S4);
1802 goto err_ptp_register;
1804 err = rswitch_gwca_request_irqs(priv);
1806 goto err_gwca_request_irq;
1808 err = rswitch_gwca_ts_request_irqs(priv);
1810 goto err_gwca_ts_request_irq;
1812 err = rswitch_gwca_hw_init(priv);
1814 goto err_gwca_hw_init;
1816 err = rswitch_ether_port_init_all(priv);
1818 goto err_ether_port_init_all;
1820 rswitch_for_each_enabled_port(priv, i) {
1821 err = register_netdev(priv->rdev[i]->ndev);
1823 rswitch_for_each_enabled_port_continue_reverse(priv, i)
1824 unregister_netdev(priv->rdev[i]->ndev);
1825 goto err_register_netdev;
1829 rswitch_for_each_enabled_port(priv, i)
1830 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n",
1831 priv->rdev[i]->ndev->dev_addr);
1835 err_register_netdev:
1836 rswitch_ether_port_deinit_all(priv);
1838 err_ether_port_init_all:
1839 rswitch_gwca_hw_deinit(priv);
1842 err_gwca_ts_request_irq:
1843 err_gwca_request_irq:
1844 rcar_gen4_ptp_unregister(priv->ptp_priv);
1847 for (i = 0; i < RSWITCH_NUM_PORTS; i++)
1848 rswitch_device_free(priv, i);
1851 rswitch_gwca_ts_queue_free(priv);
1854 rswitch_gwca_linkfix_free(priv);
1859 static int renesas_eth_sw_probe(struct platform_device *pdev)
1861 struct rswitch_private *priv;
1862 struct resource *res;
1865 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base");
1867 dev_err(&pdev->dev, "invalid resource\n");
1871 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1875 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev);
1876 if (!priv->ptp_priv)
1879 platform_set_drvdata(pdev, priv);
1881 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1882 if (IS_ERR(priv->addr))
1883 return PTR_ERR(priv->addr);
1885 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4;
1887 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
1889 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1894 priv->gwca.index = AGENT_INDEX_GWCA;
1895 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV,
1896 RSWITCH_MAX_NUM_QUEUES);
1897 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues,
1898 sizeof(*priv->gwca.queues), GFP_KERNEL);
1899 if (!priv->gwca.queues)
1902 pm_runtime_enable(&pdev->dev);
1903 pm_runtime_get_sync(&pdev->dev);
1905 ret = rswitch_init(priv);
1907 pm_runtime_put(&pdev->dev);
1908 pm_runtime_disable(&pdev->dev);
1912 device_set_wakeup_capable(&pdev->dev, 1);
1917 static void rswitch_deinit(struct rswitch_private *priv)
1921 rswitch_gwca_hw_deinit(priv);
1922 rcar_gen4_ptp_unregister(priv->ptp_priv);
1924 for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
1925 struct rswitch_device *rdev = priv->rdev[i];
1927 phy_exit(priv->rdev[i]->serdes);
1928 rswitch_ether_port_deinit_one(rdev);
1929 unregister_netdev(rdev->ndev);
1930 rswitch_device_free(priv, i);
1933 rswitch_gwca_ts_queue_free(priv);
1934 rswitch_gwca_linkfix_free(priv);
1936 rswitch_clock_disable(priv);
1939 static int renesas_eth_sw_remove(struct platform_device *pdev)
1941 struct rswitch_private *priv = platform_get_drvdata(pdev);
1943 rswitch_deinit(priv);
1945 pm_runtime_put(&pdev->dev);
1946 pm_runtime_disable(&pdev->dev);
1948 platform_set_drvdata(pdev, NULL);
1953 static struct platform_driver renesas_eth_sw_driver_platform = {
1954 .probe = renesas_eth_sw_probe,
1955 .remove = renesas_eth_sw_remove,
1957 .name = "renesas_eth_sw",
1958 .of_match_table = renesas_eth_sw_of_table,
1961 module_platform_driver(renesas_eth_sw_driver_platform);
1962 MODULE_AUTHOR("Yoshihiro Shimoda");
1963 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver");
1964 MODULE_LICENSE("GPL");