1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
30 #include <linux/reset.h>
31 #include <linux/math64.h>
36 #define RAVB_DEF_MSG_ENABLE \
42 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
45 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
48 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
52 for (i = 0; i < 10000; i++) {
53 if ((ravb_read(ndev, reg) & mask) == value)
60 static int ravb_set_opmode(struct net_device *ndev, u32 opmode)
62 u32 csr_ops = 1U << (opmode & CCC_OPC);
63 u32 ccc_mask = CCC_OPC;
66 /* If gPTP active in config mode is supported it needs to be configured
67 * along with CSEL and operating mode in the same access. This is a
68 * hardware limitation.
71 ccc_mask |= CCC_GAC | CCC_CSEL;
73 /* Set operating mode */
74 ravb_modify(ndev, CCC, ccc_mask, opmode);
75 /* Check if the operating mode is changed to the requested one */
76 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops);
78 netdev_err(ndev, "failed to switch device to requested mode (%u)\n",
85 static void ravb_set_rate_gbeth(struct net_device *ndev)
87 struct ravb_private *priv = netdev_priv(ndev);
89 switch (priv->speed) {
91 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
93 case 100: /* 100BASE */
94 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
96 case 1000: /* 1000BASE */
97 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
102 static void ravb_set_rate_rcar(struct net_device *ndev)
104 struct ravb_private *priv = netdev_priv(ndev);
106 switch (priv->speed) {
107 case 100: /* 100BASE */
108 ravb_write(ndev, GECMR_SPEED_100, GECMR);
110 case 1000: /* 1000BASE */
111 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
116 static struct sk_buff *
117 ravb_alloc_skb(struct net_device *ndev, const struct ravb_hw_info *info,
123 skb = __netdev_alloc_skb(ndev, info->rx_max_frame_size + RAVB_ALIGN - 1,
128 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
130 skb_reserve(skb, RAVB_ALIGN - reserve);
135 /* Get MAC address from the MAC address registers
137 * Ethernet AVB device doesn't have ROM for MAC address.
138 * This function gets the MAC address that was used by a bootloader.
140 static void ravb_read_mac_address(struct device_node *np,
141 struct net_device *ndev)
145 ret = of_get_ethdev_address(np, ndev);
147 u32 mahr = ravb_read(ndev, MAHR);
148 u32 malr = ravb_read(ndev, MALR);
151 addr[0] = (mahr >> 24) & 0xFF;
152 addr[1] = (mahr >> 16) & 0xFF;
153 addr[2] = (mahr >> 8) & 0xFF;
154 addr[3] = (mahr >> 0) & 0xFF;
155 addr[4] = (malr >> 8) & 0xFF;
156 addr[5] = (malr >> 0) & 0xFF;
157 eth_hw_addr_set(ndev, addr);
161 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
163 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
166 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
169 /* MDC pin control */
170 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
172 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
175 /* Data I/O pin control */
176 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
178 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
182 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
184 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
188 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
190 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
193 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
196 /* MDIO bus control struct */
197 static const struct mdiobb_ops bb_ops = {
198 .owner = THIS_MODULE,
199 .set_mdc = ravb_set_mdc,
200 .set_mdio_dir = ravb_set_mdio_dir,
201 .set_mdio_data = ravb_set_mdio_data,
202 .get_mdio_data = ravb_get_mdio_data,
205 static struct ravb_rx_desc *
206 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q,
209 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i;
212 /* Free TX skb function for AVB-IP */
213 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
215 struct ravb_private *priv = netdev_priv(ndev);
216 struct net_device_stats *stats = &priv->stats[q];
217 unsigned int num_tx_desc = priv->num_tx_desc;
218 struct ravb_tx_desc *desc;
223 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
226 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
228 desc = &priv->tx_ring[q][entry];
229 txed = desc->die_dt == DT_FEMPTY;
230 if (free_txed_only && !txed)
232 /* Descriptor type must be checked before all other reads */
234 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
235 /* Free the original skb. */
236 if (priv->tx_skb[q][entry / num_tx_desc]) {
237 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
238 size, DMA_TO_DEVICE);
239 /* Last packet descriptor? */
240 if (entry % num_tx_desc == num_tx_desc - 1) {
241 entry /= num_tx_desc;
242 dev_kfree_skb_any(priv->tx_skb[q][entry]);
243 priv->tx_skb[q][entry] = NULL;
250 stats->tx_bytes += size;
251 desc->die_dt = DT_EEMPTY;
256 static void ravb_rx_ring_free(struct net_device *ndev, int q)
258 struct ravb_private *priv = netdev_priv(ndev);
259 unsigned int ring_size;
262 if (!priv->rx_ring[q].raw)
265 for (i = 0; i < priv->num_rx_ring[q]; i++) {
266 struct ravb_rx_desc *desc = ravb_rx_get_desc(priv, q, i);
268 if (!dma_mapping_error(ndev->dev.parent,
269 le32_to_cpu(desc->dptr)))
270 dma_unmap_single(ndev->dev.parent,
271 le32_to_cpu(desc->dptr),
272 priv->info->rx_max_frame_size,
275 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1);
276 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw,
277 priv->rx_desc_dma[q]);
278 priv->rx_ring[q].raw = NULL;
281 /* Free skb's and DMA buffers for Ethernet AVB */
282 static void ravb_ring_free(struct net_device *ndev, int q)
284 struct ravb_private *priv = netdev_priv(ndev);
285 unsigned int num_tx_desc = priv->num_tx_desc;
286 unsigned int ring_size;
289 ravb_rx_ring_free(ndev, q);
291 if (priv->tx_ring[q]) {
292 ravb_tx_free(ndev, q, false);
294 ring_size = sizeof(struct ravb_tx_desc) *
295 (priv->num_tx_ring[q] * num_tx_desc + 1);
296 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
297 priv->tx_desc_dma[q]);
298 priv->tx_ring[q] = NULL;
301 /* Free RX skb ringbuffer */
302 if (priv->rx_skb[q]) {
303 for (i = 0; i < priv->num_rx_ring[q]; i++)
304 dev_kfree_skb(priv->rx_skb[q][i]);
306 kfree(priv->rx_skb[q]);
307 priv->rx_skb[q] = NULL;
309 /* Free aligned TX buffers */
310 kfree(priv->tx_align[q]);
311 priv->tx_align[q] = NULL;
313 /* Free TX skb ringbuffer.
314 * SKBs are freed by ravb_tx_free() call above.
316 kfree(priv->tx_skb[q]);
317 priv->tx_skb[q] = NULL;
320 static void ravb_rx_ring_format(struct net_device *ndev, int q)
322 struct ravb_private *priv = netdev_priv(ndev);
323 struct ravb_rx_desc *rx_desc;
324 unsigned int rx_ring_size;
328 rx_ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q];
329 memset(priv->rx_ring[q].raw, 0, rx_ring_size);
330 /* Build RX ring buffer */
331 for (i = 0; i < priv->num_rx_ring[q]; i++) {
333 rx_desc = ravb_rx_get_desc(priv, q, i);
334 rx_desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
335 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
336 priv->info->rx_max_frame_size,
338 /* We just set the data size to 0 for a failed mapping which
339 * should prevent DMA from happening...
341 if (dma_mapping_error(ndev->dev.parent, dma_addr))
342 rx_desc->ds_cc = cpu_to_le16(0);
343 rx_desc->dptr = cpu_to_le32(dma_addr);
344 rx_desc->die_dt = DT_FEMPTY;
346 rx_desc = ravb_rx_get_desc(priv, q, i);
347 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
348 rx_desc->die_dt = DT_LINKFIX; /* type */
351 /* Format skb and descriptor buffer for Ethernet AVB */
352 static void ravb_ring_format(struct net_device *ndev, int q)
354 struct ravb_private *priv = netdev_priv(ndev);
355 unsigned int num_tx_desc = priv->num_tx_desc;
356 struct ravb_tx_desc *tx_desc;
357 struct ravb_desc *desc;
358 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
364 priv->dirty_rx[q] = 0;
365 priv->dirty_tx[q] = 0;
367 ravb_rx_ring_format(ndev, q);
369 memset(priv->tx_ring[q], 0, tx_ring_size);
370 /* Build TX ring buffer */
371 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
373 tx_desc->die_dt = DT_EEMPTY;
374 if (num_tx_desc > 1) {
376 tx_desc->die_dt = DT_EEMPTY;
379 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
380 tx_desc->die_dt = DT_LINKFIX; /* type */
382 /* RX descriptor base address for best effort */
383 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
384 desc->die_dt = DT_LINKFIX; /* type */
385 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
387 /* TX descriptor base address for best effort */
388 desc = &priv->desc_bat[q];
389 desc->die_dt = DT_LINKFIX; /* type */
390 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
393 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q)
395 struct ravb_private *priv = netdev_priv(ndev);
396 unsigned int ring_size;
398 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1);
400 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size,
401 &priv->rx_desc_dma[q],
404 return priv->rx_ring[q].raw;
407 /* Init skb and descriptor buffer for Ethernet AVB */
408 static int ravb_ring_init(struct net_device *ndev, int q)
410 struct ravb_private *priv = netdev_priv(ndev);
411 const struct ravb_hw_info *info = priv->info;
412 unsigned int num_tx_desc = priv->num_tx_desc;
413 unsigned int ring_size;
417 /* Allocate RX and TX skb rings */
418 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
419 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
420 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
421 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
422 if (!priv->rx_skb[q] || !priv->tx_skb[q])
425 for (i = 0; i < priv->num_rx_ring[q]; i++) {
426 skb = ravb_alloc_skb(ndev, info, GFP_KERNEL);
429 priv->rx_skb[q][i] = skb;
432 if (num_tx_desc > 1) {
433 /* Allocate rings for the aligned buffers */
434 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
435 DPTR_ALIGN - 1, GFP_KERNEL);
436 if (!priv->tx_align[q])
440 /* Allocate all RX descriptors. */
441 if (!ravb_alloc_rx_desc(ndev, q))
444 priv->dirty_rx[q] = 0;
446 /* Allocate all TX descriptors. */
447 ring_size = sizeof(struct ravb_tx_desc) *
448 (priv->num_tx_ring[q] * num_tx_desc + 1);
449 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
450 &priv->tx_desc_dma[q],
452 if (!priv->tx_ring[q])
458 ravb_ring_free(ndev, q);
463 static void ravb_csum_init_gbeth(struct net_device *ndev)
465 bool tx_enable = ndev->features & NETIF_F_HW_CSUM;
466 bool rx_enable = ndev->features & NETIF_F_RXCSUM;
468 if (!(tx_enable || rx_enable))
471 ravb_write(ndev, 0, CSR0);
472 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) {
473 netdev_err(ndev, "Timeout enabling hardware checksum\n");
476 ndev->features &= ~NETIF_F_HW_CSUM;
479 ndev->features &= ~NETIF_F_RXCSUM;
482 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1);
485 ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4,
490 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
493 static void ravb_emac_init_gbeth(struct net_device *ndev)
495 struct ravb_private *priv = netdev_priv(ndev);
497 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
498 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
499 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
501 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35);
502 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
506 /* Receive frame limit set register */
507 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR);
509 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
510 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
511 ECMR_TE | ECMR_RE | ECMR_RCPT |
512 ECMR_TXF | ECMR_RXF, ECMR);
514 ravb_set_rate_gbeth(ndev);
516 /* Set MAC address */
518 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
519 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
520 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
522 /* E-MAC status register clear */
523 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
525 ravb_csum_init_gbeth(ndev);
527 /* E-MAC interrupt enable register */
528 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
531 static void ravb_emac_init_rcar(struct net_device *ndev)
533 /* Receive frame limit set register */
534 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
536 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
537 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
538 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
539 ECMR_TE | ECMR_RE, ECMR);
541 ravb_set_rate_rcar(ndev);
543 /* Set MAC address */
545 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
546 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
548 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
550 /* E-MAC status register clear */
551 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
553 /* E-MAC interrupt enable register */
554 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
557 /* E-MAC init function */
558 static void ravb_emac_init(struct net_device *ndev)
560 struct ravb_private *priv = netdev_priv(ndev);
561 const struct ravb_hw_info *info = priv->info;
563 info->emac_init(ndev);
566 static int ravb_dmac_init_gbeth(struct net_device *ndev)
568 struct ravb_private *priv = netdev_priv(ndev);
571 error = ravb_ring_init(ndev, RAVB_BE);
575 /* Descriptor format */
576 ravb_ring_format(ndev, RAVB_BE);
579 ravb_write(ndev, 0x60000000, RCR);
581 /* Set Max Frame Length (RTC) */
582 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC);
585 ravb_write(ndev, 0x00222200, TGC);
587 ravb_write(ndev, 0, TCCR);
590 ravb_write(ndev, RIC0_FRE0, RIC0);
591 /* Disable FIFO full warning */
592 ravb_write(ndev, 0x0, RIC1);
593 /* Receive FIFO full error, descriptor empty */
594 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
596 ravb_write(ndev, TIC_FTE0, TIC);
601 static int ravb_dmac_init_rcar(struct net_device *ndev)
603 struct ravb_private *priv = netdev_priv(ndev);
604 const struct ravb_hw_info *info = priv->info;
607 error = ravb_ring_init(ndev, RAVB_BE);
610 error = ravb_ring_init(ndev, RAVB_NC);
612 ravb_ring_free(ndev, RAVB_BE);
616 /* Descriptor format */
617 ravb_ring_format(ndev, RAVB_BE);
618 ravb_ring_format(ndev, RAVB_NC);
622 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
625 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
627 /* Timestamp enable */
628 ravb_write(ndev, TCCR_TFEN, TCCR);
630 /* Interrupt init: */
631 if (info->multi_irqs) {
633 ravb_write(ndev, 0, DIL);
634 /* Set queue specific interrupt */
635 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
638 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
639 /* Disable FIFO full warning */
640 ravb_write(ndev, 0, RIC1);
641 /* Receive FIFO full error, descriptor empty */
642 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
643 /* Frame transmitted, timestamp FIFO updated */
644 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
649 /* Device init function for Ethernet AVB */
650 static int ravb_dmac_init(struct net_device *ndev)
652 struct ravb_private *priv = netdev_priv(ndev);
653 const struct ravb_hw_info *info = priv->info;
656 /* Set CONFIG mode */
657 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
661 error = info->dmac_init(ndev);
665 /* Setting the control will start the AVB-DMAC process. */
666 return ravb_set_opmode(ndev, CCC_OPC_OPERATION);
669 static void ravb_get_tx_tstamp(struct net_device *ndev)
671 struct ravb_private *priv = netdev_priv(ndev);
672 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
673 struct skb_shared_hwtstamps shhwtstamps;
675 struct timespec64 ts;
680 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
682 tfa2 = ravb_read(ndev, TFA2);
683 tfa_tag = (tfa2 & TFA2_TST) >> 16;
684 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
685 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
686 ravb_read(ndev, TFA1);
687 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
688 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
689 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
693 list_del(&ts_skb->list);
695 if (tag == tfa_tag) {
696 skb_tstamp_tx(skb, &shhwtstamps);
697 dev_consume_skb_any(skb);
700 dev_kfree_skb_any(skb);
703 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
707 static void ravb_rx_csum_gbeth(struct sk_buff *skb)
709 __wsum csum_ip_hdr, csum_proto;
712 /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4
713 * bytes appended to packet data. First 2 bytes is ip header checksum
714 * and last 2 bytes is protocol checksum.
716 if (unlikely(skb->len < sizeof(__sum16) * 2))
719 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
720 csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
722 hw_csum -= sizeof(__sum16);
723 csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
724 skb_trim(skb, skb->len - 2 * sizeof(__sum16));
726 /* TODO: IPV6 Rx checksum */
727 if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto)
728 skb->ip_summed = CHECKSUM_UNNECESSARY;
731 static void ravb_rx_csum(struct sk_buff *skb)
735 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
736 * appended to packet data
738 if (unlikely(skb->len < sizeof(__sum16)))
740 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
741 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
742 skb->ip_summed = CHECKSUM_COMPLETE;
743 skb_trim(skb, skb->len - sizeof(__sum16));
746 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
747 struct ravb_rx_desc *desc)
749 struct ravb_private *priv = netdev_priv(ndev);
752 skb = priv->rx_skb[RAVB_BE][entry];
753 priv->rx_skb[RAVB_BE][entry] = NULL;
754 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
755 ALIGN(priv->info->rx_max_frame_size, 16),
761 /* Packet receive function for Gigabit Ethernet */
762 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
764 struct ravb_private *priv = netdev_priv(ndev);
765 const struct ravb_hw_info *info = priv->info;
766 struct net_device_stats *stats;
767 struct ravb_rx_desc *desc;
778 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
779 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
780 stats = &priv->stats[q];
782 desc = &priv->rx_ring[q].desc[entry];
783 for (i = 0; i < limit && rx_packets < *quota && desc->die_dt != DT_FEMPTY; i++) {
784 /* Descriptor type must be checked before all other reads */
786 desc_status = desc->msc;
787 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
789 /* We use 0-byte descriptors to mark the DMA mapping errors */
793 if (desc_status & MSC_MC)
796 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
798 if (desc_status & MSC_CRC)
799 stats->rx_crc_errors++;
800 if (desc_status & MSC_RFE)
801 stats->rx_frame_errors++;
802 if (desc_status & (MSC_RTLF | MSC_RTSF))
803 stats->rx_length_errors++;
804 if (desc_status & MSC_CEEF)
805 stats->rx_missed_errors++;
807 die_dt = desc->die_dt & 0xF0;
810 skb = ravb_get_skb_gbeth(ndev, entry, desc);
811 skb_put(skb, pkt_len);
812 skb->protocol = eth_type_trans(skb, ndev);
813 if (ndev->features & NETIF_F_RXCSUM)
814 ravb_rx_csum_gbeth(skb);
815 napi_gro_receive(&priv->napi[q], skb);
817 stats->rx_bytes += pkt_len;
820 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
821 skb_put(priv->rx_1st_skb, pkt_len);
824 skb = ravb_get_skb_gbeth(ndev, entry, desc);
825 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
826 priv->rx_1st_skb->len,
829 skb_put(priv->rx_1st_skb, pkt_len);
833 skb = ravb_get_skb_gbeth(ndev, entry, desc);
834 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
835 priv->rx_1st_skb->len,
838 skb_put(priv->rx_1st_skb, pkt_len);
840 priv->rx_1st_skb->protocol =
841 eth_type_trans(priv->rx_1st_skb, ndev);
842 if (ndev->features & NETIF_F_RXCSUM)
843 ravb_rx_csum_gbeth(skb);
844 napi_gro_receive(&priv->napi[q],
847 stats->rx_bytes += pkt_len;
852 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
853 desc = &priv->rx_ring[q].desc[entry];
856 /* Refill the RX ring buffers. */
857 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
858 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
859 desc = &priv->rx_ring[q].desc[entry];
860 desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
862 if (!priv->rx_skb[q][entry]) {
863 skb = ravb_alloc_skb(ndev, info, GFP_ATOMIC);
866 dma_addr = dma_map_single(ndev->dev.parent,
868 priv->info->rx_max_frame_size,
870 skb_checksum_none_assert(skb);
871 /* We just set the data size to 0 for a failed mapping
872 * which should prevent DMA from happening...
874 if (dma_mapping_error(ndev->dev.parent, dma_addr))
875 desc->ds_cc = cpu_to_le16(0);
876 desc->dptr = cpu_to_le32(dma_addr);
877 priv->rx_skb[q][entry] = skb;
879 /* Descriptor type must be set after all the above writes */
881 desc->die_dt = DT_FEMPTY;
884 stats->rx_packets += rx_packets;
885 *quota -= rx_packets;
889 /* Packet receive function for Ethernet AVB */
890 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
892 struct ravb_private *priv = netdev_priv(ndev);
893 const struct ravb_hw_info *info = priv->info;
894 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
895 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
897 struct net_device_stats *stats = &priv->stats[q];
898 struct ravb_ex_rx_desc *desc;
901 struct timespec64 ts;
906 boguscnt = min(boguscnt, *quota);
908 desc = &priv->rx_ring[q].ex_desc[entry];
909 while (desc->die_dt != DT_FEMPTY) {
910 /* Descriptor type must be checked before all other reads */
912 desc_status = desc->msc;
913 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
918 /* We use 0-byte descriptors to mark the DMA mapping errors */
922 if (desc_status & MSC_MC)
925 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
928 if (desc_status & MSC_CRC)
929 stats->rx_crc_errors++;
930 if (desc_status & MSC_RFE)
931 stats->rx_frame_errors++;
932 if (desc_status & (MSC_RTLF | MSC_RTSF))
933 stats->rx_length_errors++;
934 if (desc_status & MSC_CEEF)
935 stats->rx_missed_errors++;
937 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
939 skb = priv->rx_skb[q][entry];
940 priv->rx_skb[q][entry] = NULL;
941 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
942 priv->info->rx_max_frame_size,
944 get_ts &= (q == RAVB_NC) ?
945 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
946 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
948 struct skb_shared_hwtstamps *shhwtstamps;
950 shhwtstamps = skb_hwtstamps(skb);
951 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
952 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
953 32) | le32_to_cpu(desc->ts_sl);
954 ts.tv_nsec = le32_to_cpu(desc->ts_n);
955 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
958 skb_put(skb, pkt_len);
959 skb->protocol = eth_type_trans(skb, ndev);
960 if (ndev->features & NETIF_F_RXCSUM)
962 napi_gro_receive(&priv->napi[q], skb);
964 stats->rx_bytes += pkt_len;
967 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
968 desc = &priv->rx_ring[q].ex_desc[entry];
971 /* Refill the RX ring buffers. */
972 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
973 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
974 desc = &priv->rx_ring[q].ex_desc[entry];
975 desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
977 if (!priv->rx_skb[q][entry]) {
978 skb = ravb_alloc_skb(ndev, info, GFP_ATOMIC);
980 break; /* Better luck next round. */
981 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
982 priv->info->rx_max_frame_size,
984 skb_checksum_none_assert(skb);
985 /* We just set the data size to 0 for a failed mapping
986 * which should prevent DMA from happening...
988 if (dma_mapping_error(ndev->dev.parent, dma_addr))
989 desc->ds_cc = cpu_to_le16(0);
990 desc->dptr = cpu_to_le32(dma_addr);
991 priv->rx_skb[q][entry] = skb;
993 /* Descriptor type must be set after all the above writes */
995 desc->die_dt = DT_FEMPTY;
998 *quota -= limit - (++boguscnt);
1000 return boguscnt <= 0;
1003 /* Packet receive function for Ethernet AVB */
1004 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
1006 struct ravb_private *priv = netdev_priv(ndev);
1007 const struct ravb_hw_info *info = priv->info;
1009 return info->receive(ndev, quota, q);
1012 static void ravb_rcv_snd_disable(struct net_device *ndev)
1014 /* Disable TX and RX */
1015 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1018 static void ravb_rcv_snd_enable(struct net_device *ndev)
1020 /* Enable TX and RX */
1021 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1024 /* function for waiting dma process finished */
1025 static int ravb_stop_dma(struct net_device *ndev)
1027 struct ravb_private *priv = netdev_priv(ndev);
1028 const struct ravb_hw_info *info = priv->info;
1031 /* Wait for stopping the hardware TX process */
1032 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1037 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1042 /* Stop the E-MAC's RX/TX processes. */
1043 ravb_rcv_snd_disable(ndev);
1045 /* Wait for stopping the RX DMA process */
1046 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1050 /* Stop AVB-DMAC process */
1051 return ravb_set_opmode(ndev, CCC_OPC_CONFIG);
1054 /* E-MAC interrupt handler */
1055 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1057 struct ravb_private *priv = netdev_priv(ndev);
1060 ecsr = ravb_read(ndev, ECSR);
1061 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
1063 if (ecsr & ECSR_MPD)
1064 pm_wakeup_event(&priv->pdev->dev, 0);
1065 if (ecsr & ECSR_ICD)
1066 ndev->stats.tx_carrier_errors++;
1067 if (ecsr & ECSR_LCHNG) {
1069 if (priv->no_avb_link)
1071 psr = ravb_read(ndev, PSR);
1072 if (priv->avb_link_active_low)
1074 if (!(psr & PSR_LMON)) {
1075 /* DIsable RX and TX */
1076 ravb_rcv_snd_disable(ndev);
1078 /* Enable RX and TX */
1079 ravb_rcv_snd_enable(ndev);
1084 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1086 struct net_device *ndev = dev_id;
1087 struct ravb_private *priv = netdev_priv(ndev);
1088 struct device *dev = &priv->pdev->dev;
1089 irqreturn_t result = IRQ_HANDLED;
1091 pm_runtime_get_noresume(dev);
1093 if (unlikely(!pm_runtime_active(dev))) {
1098 spin_lock(&priv->lock);
1099 ravb_emac_interrupt_unlocked(ndev);
1100 spin_unlock(&priv->lock);
1103 pm_runtime_put_noidle(dev);
1107 /* Error interrupt handler */
1108 static void ravb_error_interrupt(struct net_device *ndev)
1110 struct ravb_private *priv = netdev_priv(ndev);
1113 eis = ravb_read(ndev, EIS);
1114 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1115 if (eis & EIS_QFS) {
1116 ris2 = ravb_read(ndev, RIS2);
1117 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
1120 /* Receive Descriptor Empty int */
1121 if (ris2 & RIS2_QFF0)
1122 priv->stats[RAVB_BE].rx_over_errors++;
1124 /* Receive Descriptor Empty int */
1125 if (ris2 & RIS2_QFF1)
1126 priv->stats[RAVB_NC].rx_over_errors++;
1128 /* Receive FIFO Overflow int */
1129 if (ris2 & RIS2_RFFF)
1130 priv->rx_fifo_errors++;
1134 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1136 struct ravb_private *priv = netdev_priv(ndev);
1137 const struct ravb_hw_info *info = priv->info;
1138 u32 ris0 = ravb_read(ndev, RIS0);
1139 u32 ric0 = ravb_read(ndev, RIC0);
1140 u32 tis = ravb_read(ndev, TIS);
1141 u32 tic = ravb_read(ndev, TIC);
1143 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
1144 if (napi_schedule_prep(&priv->napi[q])) {
1145 /* Mask RX and TX interrupts */
1146 if (!info->irq_en_dis) {
1147 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1148 ravb_write(ndev, tic & ~BIT(q), TIC);
1150 ravb_write(ndev, BIT(q), RID0);
1151 ravb_write(ndev, BIT(q), TID);
1153 __napi_schedule(&priv->napi[q]);
1156 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1159 " tx status 0x%08x, tx mask 0x%08x.\n",
1167 static bool ravb_timestamp_interrupt(struct net_device *ndev)
1169 u32 tis = ravb_read(ndev, TIS);
1171 if (tis & TIS_TFUF) {
1172 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1173 ravb_get_tx_tstamp(ndev);
1179 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1181 struct net_device *ndev = dev_id;
1182 struct ravb_private *priv = netdev_priv(ndev);
1183 const struct ravb_hw_info *info = priv->info;
1184 struct device *dev = &priv->pdev->dev;
1185 irqreturn_t result = IRQ_NONE;
1188 pm_runtime_get_noresume(dev);
1190 if (unlikely(!pm_runtime_active(dev)))
1193 spin_lock(&priv->lock);
1194 /* Get interrupt status */
1195 iss = ravb_read(ndev, ISS);
1197 /* Received and transmitted interrupts */
1198 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1201 /* Timestamp updated */
1202 if (ravb_timestamp_interrupt(ndev))
1203 result = IRQ_HANDLED;
1205 /* Network control and best effort queue RX/TX */
1206 if (info->nc_queues) {
1207 for (q = RAVB_NC; q >= RAVB_BE; q--) {
1208 if (ravb_queue_interrupt(ndev, q))
1209 result = IRQ_HANDLED;
1212 if (ravb_queue_interrupt(ndev, RAVB_BE))
1213 result = IRQ_HANDLED;
1217 /* E-MAC status summary */
1219 ravb_emac_interrupt_unlocked(ndev);
1220 result = IRQ_HANDLED;
1223 /* Error status summary */
1225 ravb_error_interrupt(ndev);
1226 result = IRQ_HANDLED;
1229 /* gPTP interrupt status summary */
1230 if (iss & ISS_CGIS) {
1231 ravb_ptp_interrupt(ndev);
1232 result = IRQ_HANDLED;
1235 spin_unlock(&priv->lock);
1238 pm_runtime_put_noidle(dev);
1242 /* Timestamp/Error/gPTP interrupt handler */
1243 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1245 struct net_device *ndev = dev_id;
1246 struct ravb_private *priv = netdev_priv(ndev);
1247 struct device *dev = &priv->pdev->dev;
1248 irqreturn_t result = IRQ_NONE;
1251 pm_runtime_get_noresume(dev);
1253 if (unlikely(!pm_runtime_active(dev)))
1256 spin_lock(&priv->lock);
1257 /* Get interrupt status */
1258 iss = ravb_read(ndev, ISS);
1260 /* Timestamp updated */
1261 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1262 result = IRQ_HANDLED;
1264 /* Error status summary */
1266 ravb_error_interrupt(ndev);
1267 result = IRQ_HANDLED;
1270 /* gPTP interrupt status summary */
1271 if (iss & ISS_CGIS) {
1272 ravb_ptp_interrupt(ndev);
1273 result = IRQ_HANDLED;
1276 spin_unlock(&priv->lock);
1279 pm_runtime_put_noidle(dev);
1283 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1285 struct net_device *ndev = dev_id;
1286 struct ravb_private *priv = netdev_priv(ndev);
1287 struct device *dev = &priv->pdev->dev;
1288 irqreturn_t result = IRQ_NONE;
1290 pm_runtime_get_noresume(dev);
1292 if (unlikely(!pm_runtime_active(dev)))
1295 spin_lock(&priv->lock);
1297 /* Network control/Best effort queue RX/TX */
1298 if (ravb_queue_interrupt(ndev, q))
1299 result = IRQ_HANDLED;
1301 spin_unlock(&priv->lock);
1304 pm_runtime_put_noidle(dev);
1308 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1310 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1313 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1315 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1318 static int ravb_poll(struct napi_struct *napi, int budget)
1320 struct net_device *ndev = napi->dev;
1321 struct ravb_private *priv = netdev_priv(ndev);
1322 const struct ravb_hw_info *info = priv->info;
1323 unsigned long flags;
1324 int q = napi - priv->napi;
1329 /* Processing RX Descriptor Ring */
1330 /* Clear RX interrupt */
1331 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1332 unmask = !ravb_rx(ndev, "a, q);
1334 /* Processing TX Descriptor Ring */
1335 spin_lock_irqsave(&priv->lock, flags);
1336 /* Clear TX interrupt */
1337 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1338 ravb_tx_free(ndev, q, true);
1339 netif_wake_subqueue(ndev, q);
1340 spin_unlock_irqrestore(&priv->lock, flags);
1342 /* Receive error message handling */
1343 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1344 if (info->nc_queues)
1345 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1346 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1347 ndev->stats.rx_over_errors = priv->rx_over_errors;
1348 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1349 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1354 napi_complete(napi);
1356 /* Re-enable RX/TX interrupts */
1357 spin_lock_irqsave(&priv->lock, flags);
1358 if (!info->irq_en_dis) {
1359 ravb_modify(ndev, RIC0, mask, mask);
1360 ravb_modify(ndev, TIC, mask, mask);
1362 ravb_write(ndev, mask, RIE0);
1363 ravb_write(ndev, mask, TIE);
1365 spin_unlock_irqrestore(&priv->lock, flags);
1368 return budget - quota;
1371 static void ravb_set_duplex_gbeth(struct net_device *ndev)
1373 struct ravb_private *priv = netdev_priv(ndev);
1375 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1378 /* PHY state control function */
1379 static void ravb_adjust_link(struct net_device *ndev)
1381 struct ravb_private *priv = netdev_priv(ndev);
1382 const struct ravb_hw_info *info = priv->info;
1383 struct phy_device *phydev = ndev->phydev;
1384 bool new_state = false;
1385 unsigned long flags;
1387 spin_lock_irqsave(&priv->lock, flags);
1389 /* Disable TX and RX right over here, if E-MAC change is ignored */
1390 if (priv->no_avb_link)
1391 ravb_rcv_snd_disable(ndev);
1394 if (info->half_duplex && phydev->duplex != priv->duplex) {
1396 priv->duplex = phydev->duplex;
1397 ravb_set_duplex_gbeth(ndev);
1400 if (phydev->speed != priv->speed) {
1402 priv->speed = phydev->speed;
1403 info->set_rate(ndev);
1406 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1408 priv->link = phydev->link;
1410 } else if (priv->link) {
1414 if (info->half_duplex)
1418 /* Enable TX and RX right over here, if E-MAC change is ignored */
1419 if (priv->no_avb_link && phydev->link)
1420 ravb_rcv_snd_enable(ndev);
1422 spin_unlock_irqrestore(&priv->lock, flags);
1424 if (new_state && netif_msg_link(priv))
1425 phy_print_status(phydev);
1428 /* PHY init function */
1429 static int ravb_phy_init(struct net_device *ndev)
1431 struct device_node *np = ndev->dev.parent->of_node;
1432 struct ravb_private *priv = netdev_priv(ndev);
1433 const struct ravb_hw_info *info = priv->info;
1434 struct phy_device *phydev;
1435 struct device_node *pn;
1436 phy_interface_t iface;
1443 /* Try connecting to PHY */
1444 pn = of_parse_phandle(np, "phy-handle", 0);
1446 /* In the case of a fixed PHY, the DT node associated
1447 * to the PHY is the Ethernet MAC DT node.
1449 if (of_phy_is_fixed_link(np)) {
1450 err = of_phy_register_fixed_link(np);
1454 pn = of_node_get(np);
1457 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1458 : priv->phy_interface;
1459 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1462 netdev_err(ndev, "failed to connect PHY\n");
1464 goto err_deregister_fixed_link;
1467 if (!info->half_duplex) {
1468 /* 10BASE, Pause and Asym Pause is not supported */
1469 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1470 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1471 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1472 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1474 /* Half Duplex is not supported */
1475 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1476 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1479 phy_attached_info(phydev);
1483 err_deregister_fixed_link:
1484 if (of_phy_is_fixed_link(np))
1485 of_phy_deregister_fixed_link(np);
1490 /* PHY control start function */
1491 static int ravb_phy_start(struct net_device *ndev)
1495 error = ravb_phy_init(ndev);
1499 phy_start(ndev->phydev);
1504 static u32 ravb_get_msglevel(struct net_device *ndev)
1506 struct ravb_private *priv = netdev_priv(ndev);
1508 return priv->msg_enable;
1511 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1513 struct ravb_private *priv = netdev_priv(ndev);
1515 priv->msg_enable = value;
1518 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1519 "rx_queue_0_current",
1520 "tx_queue_0_current",
1523 "rx_queue_0_packets",
1524 "tx_queue_0_packets",
1527 "rx_queue_0_mcast_packets",
1528 "rx_queue_0_errors",
1529 "rx_queue_0_crc_errors",
1530 "rx_queue_0_frame_errors",
1531 "rx_queue_0_length_errors",
1532 "rx_queue_0_csum_offload_errors",
1533 "rx_queue_0_over_errors",
1536 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1537 "rx_queue_0_current",
1538 "tx_queue_0_current",
1541 "rx_queue_0_packets",
1542 "tx_queue_0_packets",
1545 "rx_queue_0_mcast_packets",
1546 "rx_queue_0_errors",
1547 "rx_queue_0_crc_errors",
1548 "rx_queue_0_frame_errors",
1549 "rx_queue_0_length_errors",
1550 "rx_queue_0_missed_errors",
1551 "rx_queue_0_over_errors",
1553 "rx_queue_1_current",
1554 "tx_queue_1_current",
1557 "rx_queue_1_packets",
1558 "tx_queue_1_packets",
1561 "rx_queue_1_mcast_packets",
1562 "rx_queue_1_errors",
1563 "rx_queue_1_crc_errors",
1564 "rx_queue_1_frame_errors",
1565 "rx_queue_1_length_errors",
1566 "rx_queue_1_missed_errors",
1567 "rx_queue_1_over_errors",
1570 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1572 struct ravb_private *priv = netdev_priv(netdev);
1573 const struct ravb_hw_info *info = priv->info;
1577 return info->stats_len;
1583 static void ravb_get_ethtool_stats(struct net_device *ndev,
1584 struct ethtool_stats *estats, u64 *data)
1586 struct ravb_private *priv = netdev_priv(ndev);
1587 const struct ravb_hw_info *info = priv->info;
1592 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1593 /* Device-specific stats */
1594 for (q = RAVB_BE; q < num_rx_q; q++) {
1595 struct net_device_stats *stats = &priv->stats[q];
1597 data[i++] = priv->cur_rx[q];
1598 data[i++] = priv->cur_tx[q];
1599 data[i++] = priv->dirty_rx[q];
1600 data[i++] = priv->dirty_tx[q];
1601 data[i++] = stats->rx_packets;
1602 data[i++] = stats->tx_packets;
1603 data[i++] = stats->rx_bytes;
1604 data[i++] = stats->tx_bytes;
1605 data[i++] = stats->multicast;
1606 data[i++] = stats->rx_errors;
1607 data[i++] = stats->rx_crc_errors;
1608 data[i++] = stats->rx_frame_errors;
1609 data[i++] = stats->rx_length_errors;
1610 data[i++] = stats->rx_missed_errors;
1611 data[i++] = stats->rx_over_errors;
1615 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1617 struct ravb_private *priv = netdev_priv(ndev);
1618 const struct ravb_hw_info *info = priv->info;
1620 switch (stringset) {
1622 memcpy(data, info->gstrings_stats, info->gstrings_size);
1627 static void ravb_get_ringparam(struct net_device *ndev,
1628 struct ethtool_ringparam *ring,
1629 struct kernel_ethtool_ringparam *kernel_ring,
1630 struct netlink_ext_ack *extack)
1632 struct ravb_private *priv = netdev_priv(ndev);
1634 ring->rx_max_pending = BE_RX_RING_MAX;
1635 ring->tx_max_pending = BE_TX_RING_MAX;
1636 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1637 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1640 static int ravb_set_ringparam(struct net_device *ndev,
1641 struct ethtool_ringparam *ring,
1642 struct kernel_ethtool_ringparam *kernel_ring,
1643 struct netlink_ext_ack *extack)
1645 struct ravb_private *priv = netdev_priv(ndev);
1646 const struct ravb_hw_info *info = priv->info;
1649 if (ring->tx_pending > BE_TX_RING_MAX ||
1650 ring->rx_pending > BE_RX_RING_MAX ||
1651 ring->tx_pending < BE_TX_RING_MIN ||
1652 ring->rx_pending < BE_RX_RING_MIN)
1654 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1657 if (netif_running(ndev)) {
1658 netif_device_detach(ndev);
1659 /* Stop PTP Clock driver */
1661 ravb_ptp_stop(ndev);
1662 /* Wait for DMA stopping */
1663 error = ravb_stop_dma(ndev);
1666 "cannot set ringparam! Any AVB processes are still running?\n");
1669 synchronize_irq(ndev->irq);
1671 /* Free all the skb's in the RX queue and the DMA buffers. */
1672 ravb_ring_free(ndev, RAVB_BE);
1673 if (info->nc_queues)
1674 ravb_ring_free(ndev, RAVB_NC);
1677 /* Set new parameters */
1678 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1679 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1681 if (netif_running(ndev)) {
1682 error = ravb_dmac_init(ndev);
1685 "%s: ravb_dmac_init() failed, error %d\n",
1690 ravb_emac_init(ndev);
1692 /* Initialise PTP Clock driver */
1694 ravb_ptp_init(ndev, priv->pdev);
1696 netif_device_attach(ndev);
1702 static int ravb_get_ts_info(struct net_device *ndev,
1703 struct ethtool_ts_info *info)
1705 struct ravb_private *priv = netdev_priv(ndev);
1706 const struct ravb_hw_info *hw_info = priv->info;
1708 info->so_timestamping =
1709 SOF_TIMESTAMPING_TX_SOFTWARE |
1710 SOF_TIMESTAMPING_RX_SOFTWARE |
1711 SOF_TIMESTAMPING_SOFTWARE |
1712 SOF_TIMESTAMPING_TX_HARDWARE |
1713 SOF_TIMESTAMPING_RX_HARDWARE |
1714 SOF_TIMESTAMPING_RAW_HARDWARE;
1715 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1717 (1 << HWTSTAMP_FILTER_NONE) |
1718 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1719 (1 << HWTSTAMP_FILTER_ALL);
1720 if (hw_info->gptp || hw_info->ccc_gac)
1721 info->phc_index = ptp_clock_index(priv->ptp.clock);
1726 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1728 struct ravb_private *priv = netdev_priv(ndev);
1730 wol->supported = WAKE_MAGIC;
1731 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1734 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1736 struct ravb_private *priv = netdev_priv(ndev);
1737 const struct ravb_hw_info *info = priv->info;
1739 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1742 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1744 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1749 static const struct ethtool_ops ravb_ethtool_ops = {
1750 .nway_reset = phy_ethtool_nway_reset,
1751 .get_msglevel = ravb_get_msglevel,
1752 .set_msglevel = ravb_set_msglevel,
1753 .get_link = ethtool_op_get_link,
1754 .get_strings = ravb_get_strings,
1755 .get_ethtool_stats = ravb_get_ethtool_stats,
1756 .get_sset_count = ravb_get_sset_count,
1757 .get_ringparam = ravb_get_ringparam,
1758 .set_ringparam = ravb_set_ringparam,
1759 .get_ts_info = ravb_get_ts_info,
1760 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1761 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1762 .get_wol = ravb_get_wol,
1763 .set_wol = ravb_set_wol,
1766 static int ravb_set_config_mode(struct net_device *ndev)
1768 struct ravb_private *priv = netdev_priv(ndev);
1769 const struct ravb_hw_info *info = priv->info;
1773 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
1776 /* Set CSEL value */
1777 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1778 } else if (info->ccc_gac) {
1779 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB);
1781 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
1787 static void ravb_set_gti(struct net_device *ndev)
1789 struct ravb_private *priv = netdev_priv(ndev);
1790 const struct ravb_hw_info *info = priv->info;
1792 if (!(info->gptp || info->ccc_gac))
1795 ravb_write(ndev, priv->gti_tiv, GTI);
1797 /* Request GTI loading */
1798 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
1801 static int ravb_compute_gti(struct net_device *ndev)
1803 struct ravb_private *priv = netdev_priv(ndev);
1804 const struct ravb_hw_info *info = priv->info;
1805 struct device *dev = ndev->dev.parent;
1809 if (!(info->gptp || info->ccc_gac))
1812 if (info->gptp_ref_clk)
1813 rate = clk_get_rate(priv->gptp_clk);
1815 rate = clk_get_rate(priv->clk);
1819 inc = div64_ul(1000000000ULL << 20, rate);
1821 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1822 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1823 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1826 priv->gti_tiv = inc;
1831 /* Set tx and rx clock internal delay modes */
1832 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
1834 struct ravb_private *priv = netdev_priv(ndev);
1835 bool explicit_delay = false;
1838 if (!priv->info->internal_delay)
1841 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
1842 /* Valid values are 0 and 1800, according to DT bindings */
1843 priv->rxcidm = !!delay;
1844 explicit_delay = true;
1846 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
1847 /* Valid values are 0 and 2000, according to DT bindings */
1848 priv->txcidm = !!delay;
1849 explicit_delay = true;
1855 /* Fall back to legacy rgmii-*id behavior */
1856 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1857 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
1859 priv->rgmii_override = 1;
1862 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1863 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1865 priv->rgmii_override = 1;
1869 static void ravb_set_delay_mode(struct net_device *ndev)
1871 struct ravb_private *priv = netdev_priv(ndev);
1874 if (!priv->info->internal_delay)
1881 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
1884 /* Network device open function for Ethernet AVB */
1885 static int ravb_open(struct net_device *ndev)
1887 struct ravb_private *priv = netdev_priv(ndev);
1888 const struct ravb_hw_info *info = priv->info;
1889 struct device *dev = &priv->pdev->dev;
1892 napi_enable(&priv->napi[RAVB_BE]);
1893 if (info->nc_queues)
1894 napi_enable(&priv->napi[RAVB_NC]);
1896 error = pm_runtime_resume_and_get(dev);
1900 /* Set AVB config mode */
1901 error = ravb_set_config_mode(ndev);
1905 ravb_set_delay_mode(ndev);
1906 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1909 error = ravb_dmac_init(ndev);
1913 ravb_emac_init(ndev);
1917 /* Initialise PTP Clock driver */
1918 if (info->gptp || info->ccc_gac)
1919 ravb_ptp_init(ndev, priv->pdev);
1921 /* PHY control start */
1922 error = ravb_phy_start(ndev);
1926 netif_tx_start_all_queues(ndev);
1931 /* Stop PTP Clock driver */
1932 if (info->gptp || info->ccc_gac)
1933 ravb_ptp_stop(ndev);
1934 ravb_stop_dma(ndev);
1936 ravb_set_opmode(ndev, CCC_OPC_RESET);
1938 pm_runtime_mark_last_busy(dev);
1939 pm_runtime_put_autosuspend(dev);
1941 if (info->nc_queues)
1942 napi_disable(&priv->napi[RAVB_NC]);
1943 napi_disable(&priv->napi[RAVB_BE]);
1947 /* Timeout function for Ethernet AVB */
1948 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1950 struct ravb_private *priv = netdev_priv(ndev);
1952 netif_err(priv, tx_err, ndev,
1953 "transmit timed out, status %08x, resetting...\n",
1954 ravb_read(ndev, ISS));
1956 /* tx_errors count up */
1957 ndev->stats.tx_errors++;
1959 schedule_work(&priv->work);
1962 static void ravb_tx_timeout_work(struct work_struct *work)
1964 struct ravb_private *priv = container_of(work, struct ravb_private,
1966 const struct ravb_hw_info *info = priv->info;
1967 struct net_device *ndev = priv->ndev;
1970 if (!rtnl_trylock()) {
1971 usleep_range(1000, 2000);
1972 schedule_work(&priv->work);
1976 netif_tx_stop_all_queues(ndev);
1978 /* Stop PTP Clock driver */
1980 ravb_ptp_stop(ndev);
1982 /* Wait for DMA stopping */
1983 if (ravb_stop_dma(ndev)) {
1984 /* If ravb_stop_dma() fails, the hardware is still operating
1985 * for TX and/or RX. So, this should not call the following
1986 * functions because ravb_dmac_init() is possible to fail too.
1987 * Also, this should not retry ravb_stop_dma() again and again
1988 * here because it's possible to wait forever. So, this just
1989 * re-enables the TX and RX and skip the following
1990 * re-initialization procedure.
1992 ravb_rcv_snd_enable(ndev);
1996 ravb_ring_free(ndev, RAVB_BE);
1997 if (info->nc_queues)
1998 ravb_ring_free(ndev, RAVB_NC);
2001 error = ravb_dmac_init(ndev);
2003 /* If ravb_dmac_init() fails, descriptors are freed. So, this
2004 * should return here to avoid re-enabling the TX and RX in
2007 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
2011 ravb_emac_init(ndev);
2014 /* Initialise PTP Clock driver */
2016 ravb_ptp_init(ndev, priv->pdev);
2018 netif_tx_start_all_queues(ndev);
2024 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb)
2026 struct iphdr *ip = ip_hdr(skb);
2028 /* TODO: Need to add support for VLAN tag 802.1Q */
2029 if (skb_vlan_tag_present(skb))
2032 /* TODO: Need to add hardware checksum for IPv6 */
2033 if (skb->protocol != htons(ETH_P_IP))
2036 switch (ip->protocol) {
2040 /* If the checksum value in the UDP header field is 0, TOE does
2041 * not calculate checksum for UDP part of this frame as it is
2042 * optional function as per standards.
2044 if (udp_hdr(skb)->check == 0)
2054 /* Packet transmit function for Ethernet AVB */
2055 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2057 struct ravb_private *priv = netdev_priv(ndev);
2058 const struct ravb_hw_info *info = priv->info;
2059 unsigned int num_tx_desc = priv->num_tx_desc;
2060 u16 q = skb_get_queue_mapping(skb);
2061 struct ravb_tstamp_skb *ts_skb;
2062 struct ravb_tx_desc *desc;
2063 unsigned long flags;
2064 dma_addr_t dma_addr;
2069 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb))
2070 skb_checksum_help(skb);
2072 spin_lock_irqsave(&priv->lock, flags);
2073 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
2075 netif_err(priv, tx_queued, ndev,
2076 "still transmitting with the full ring!\n");
2077 netif_stop_subqueue(ndev, q);
2078 spin_unlock_irqrestore(&priv->lock, flags);
2079 return NETDEV_TX_BUSY;
2082 if (skb_put_padto(skb, ETH_ZLEN))
2085 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
2086 priv->tx_skb[q][entry / num_tx_desc] = skb;
2088 if (num_tx_desc > 1) {
2089 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
2090 entry / num_tx_desc * DPTR_ALIGN;
2091 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
2093 /* Zero length DMA descriptors are problematic as they seem
2094 * to terminate DMA transfers. Avoid them by simply using a
2095 * length of DPTR_ALIGN (4) when skb data is aligned to
2098 * As skb is guaranteed to have at least ETH_ZLEN (60)
2099 * bytes of data by the call to skb_put_padto() above this
2100 * is safe with respect to both the length of the first DMA
2101 * descriptor (len) overflowing the available data and the
2102 * length of the second DMA descriptor (skb->len - len)
2108 memcpy(buffer, skb->data, len);
2109 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
2111 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2114 desc = &priv->tx_ring[q][entry];
2115 desc->ds_tagl = cpu_to_le16(len);
2116 desc->dptr = cpu_to_le32(dma_addr);
2118 buffer = skb->data + len;
2119 len = skb->len - len;
2120 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
2122 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2127 desc = &priv->tx_ring[q][entry];
2129 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
2131 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2134 desc->ds_tagl = cpu_to_le16(len);
2135 desc->dptr = cpu_to_le32(dma_addr);
2137 /* TX timestamp required */
2138 if (info->gptp || info->ccc_gac) {
2140 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2142 if (num_tx_desc > 1) {
2144 dma_unmap_single(ndev->dev.parent, dma_addr,
2145 len, DMA_TO_DEVICE);
2149 ts_skb->skb = skb_get(skb);
2150 ts_skb->tag = priv->ts_skb_tag++;
2151 priv->ts_skb_tag &= 0x3ff;
2152 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2154 /* TAG and timestamp required flag */
2155 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2156 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2157 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2160 skb_tx_timestamp(skb);
2162 /* Descriptor type must be set after all the above writes */
2164 if (num_tx_desc > 1) {
2165 desc->die_dt = DT_FEND;
2167 desc->die_dt = DT_FSTART;
2169 desc->die_dt = DT_FSINGLE;
2171 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2173 priv->cur_tx[q] += num_tx_desc;
2174 if (priv->cur_tx[q] - priv->dirty_tx[q] >
2175 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2176 !ravb_tx_free(ndev, q, true))
2177 netif_stop_subqueue(ndev, q);
2180 spin_unlock_irqrestore(&priv->lock, flags);
2181 return NETDEV_TX_OK;
2184 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2185 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2187 dev_kfree_skb_any(skb);
2188 priv->tx_skb[q][entry / num_tx_desc] = NULL;
2192 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2193 struct net_device *sb_dev)
2195 /* If skb needs TX timestamp, it is handled in network control queue */
2196 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2201 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2203 struct ravb_private *priv = netdev_priv(ndev);
2204 const struct ravb_hw_info *info = priv->info;
2205 struct net_device_stats *nstats, *stats0, *stats1;
2206 struct device *dev = &priv->pdev->dev;
2208 nstats = &ndev->stats;
2210 pm_runtime_get_noresume(dev);
2212 if (!pm_runtime_active(dev))
2215 stats0 = &priv->stats[RAVB_BE];
2217 if (info->tx_counters) {
2218 nstats->tx_dropped += ravb_read(ndev, TROCR);
2219 ravb_write(ndev, 0, TROCR); /* (write clear) */
2222 if (info->carrier_counters) {
2223 nstats->collisions += ravb_read(ndev, CXR41);
2224 ravb_write(ndev, 0, CXR41); /* (write clear) */
2225 nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2226 ravb_write(ndev, 0, CXR42); /* (write clear) */
2229 nstats->rx_packets = stats0->rx_packets;
2230 nstats->tx_packets = stats0->tx_packets;
2231 nstats->rx_bytes = stats0->rx_bytes;
2232 nstats->tx_bytes = stats0->tx_bytes;
2233 nstats->multicast = stats0->multicast;
2234 nstats->rx_errors = stats0->rx_errors;
2235 nstats->rx_crc_errors = stats0->rx_crc_errors;
2236 nstats->rx_frame_errors = stats0->rx_frame_errors;
2237 nstats->rx_length_errors = stats0->rx_length_errors;
2238 nstats->rx_missed_errors = stats0->rx_missed_errors;
2239 nstats->rx_over_errors = stats0->rx_over_errors;
2240 if (info->nc_queues) {
2241 stats1 = &priv->stats[RAVB_NC];
2243 nstats->rx_packets += stats1->rx_packets;
2244 nstats->tx_packets += stats1->tx_packets;
2245 nstats->rx_bytes += stats1->rx_bytes;
2246 nstats->tx_bytes += stats1->tx_bytes;
2247 nstats->multicast += stats1->multicast;
2248 nstats->rx_errors += stats1->rx_errors;
2249 nstats->rx_crc_errors += stats1->rx_crc_errors;
2250 nstats->rx_frame_errors += stats1->rx_frame_errors;
2251 nstats->rx_length_errors += stats1->rx_length_errors;
2252 nstats->rx_missed_errors += stats1->rx_missed_errors;
2253 nstats->rx_over_errors += stats1->rx_over_errors;
2257 pm_runtime_put_noidle(dev);
2261 /* Update promiscuous bit */
2262 static void ravb_set_rx_mode(struct net_device *ndev)
2264 struct ravb_private *priv = netdev_priv(ndev);
2265 unsigned long flags;
2267 spin_lock_irqsave(&priv->lock, flags);
2268 ravb_modify(ndev, ECMR, ECMR_PRM,
2269 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2270 spin_unlock_irqrestore(&priv->lock, flags);
2273 /* Device close function for Ethernet AVB */
2274 static int ravb_close(struct net_device *ndev)
2276 struct device_node *np = ndev->dev.parent->of_node;
2277 struct ravb_private *priv = netdev_priv(ndev);
2278 const struct ravb_hw_info *info = priv->info;
2279 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2280 struct device *dev = &priv->pdev->dev;
2283 netif_tx_stop_all_queues(ndev);
2285 /* Disable interrupts by clearing the interrupt masks. */
2286 ravb_write(ndev, 0, RIC0);
2287 ravb_write(ndev, 0, RIC2);
2288 ravb_write(ndev, 0, TIC);
2290 /* PHY disconnect */
2292 phy_stop(ndev->phydev);
2293 phy_disconnect(ndev->phydev);
2294 if (of_phy_is_fixed_link(np))
2295 of_phy_deregister_fixed_link(np);
2298 /* Stop PTP Clock driver */
2299 if (info->gptp || info->ccc_gac)
2300 ravb_ptp_stop(ndev);
2302 /* Set the config mode to stop the AVB-DMAC's processes */
2303 if (ravb_stop_dma(ndev) < 0)
2305 "device will be stopped after h/w processes are done.\n");
2307 /* Clear the timestamp list */
2308 if (info->gptp || info->ccc_gac) {
2309 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2310 list_del(&ts_skb->list);
2311 kfree_skb(ts_skb->skb);
2316 cancel_work_sync(&priv->work);
2318 if (info->nc_queues)
2319 napi_disable(&priv->napi[RAVB_NC]);
2320 napi_disable(&priv->napi[RAVB_BE]);
2322 /* Free all the skb's in the RX queue and the DMA buffers. */
2323 ravb_ring_free(ndev, RAVB_BE);
2324 if (info->nc_queues)
2325 ravb_ring_free(ndev, RAVB_NC);
2327 /* Update statistics. */
2328 ravb_get_stats(ndev);
2330 /* Set reset mode. */
2331 error = ravb_set_opmode(ndev, CCC_OPC_RESET);
2335 pm_runtime_mark_last_busy(dev);
2336 pm_runtime_put_autosuspend(dev);
2341 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2343 struct ravb_private *priv = netdev_priv(ndev);
2344 struct hwtstamp_config config;
2347 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2349 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2350 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2351 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2353 case RAVB_RXTSTAMP_TYPE_ALL:
2354 config.rx_filter = HWTSTAMP_FILTER_ALL;
2357 config.rx_filter = HWTSTAMP_FILTER_NONE;
2360 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2364 /* Control hardware time stamping */
2365 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2367 struct ravb_private *priv = netdev_priv(ndev);
2368 struct hwtstamp_config config;
2369 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2372 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2375 switch (config.tx_type) {
2376 case HWTSTAMP_TX_OFF:
2379 case HWTSTAMP_TX_ON:
2380 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2386 switch (config.rx_filter) {
2387 case HWTSTAMP_FILTER_NONE:
2390 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2391 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2394 config.rx_filter = HWTSTAMP_FILTER_ALL;
2395 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2398 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2399 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2401 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2405 /* ioctl to device function */
2406 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2408 struct phy_device *phydev = ndev->phydev;
2410 if (!netif_running(ndev))
2418 return ravb_hwtstamp_get(ndev, req);
2420 return ravb_hwtstamp_set(ndev, req);
2423 return phy_mii_ioctl(phydev, req, cmd);
2426 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2428 struct ravb_private *priv = netdev_priv(ndev);
2430 ndev->mtu = new_mtu;
2432 if (netif_running(ndev)) {
2433 synchronize_irq(priv->emac_irq);
2434 ravb_emac_init(ndev);
2437 netdev_update_features(ndev);
2442 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2444 struct ravb_private *priv = netdev_priv(ndev);
2445 unsigned long flags;
2447 spin_lock_irqsave(&priv->lock, flags);
2449 /* Disable TX and RX */
2450 ravb_rcv_snd_disable(ndev);
2452 /* Modify RX Checksum setting */
2453 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2455 /* Enable TX and RX */
2456 ravb_rcv_snd_enable(ndev);
2458 spin_unlock_irqrestore(&priv->lock, flags);
2461 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg,
2464 u32 csr0 = CSR0_TPE | CSR0_RPE;
2467 ravb_write(ndev, csr0 & ~mask, CSR0);
2468 ret = ravb_wait(ndev, CSR0, mask, 0);
2470 ravb_write(ndev, val, reg);
2472 ravb_write(ndev, csr0, CSR0);
2477 static int ravb_set_features_gbeth(struct net_device *ndev,
2478 netdev_features_t features)
2480 netdev_features_t changed = ndev->features ^ features;
2481 struct ravb_private *priv = netdev_priv(ndev);
2482 unsigned long flags;
2486 spin_lock_irqsave(&priv->lock, flags);
2487 if (changed & NETIF_F_RXCSUM) {
2488 if (features & NETIF_F_RXCSUM)
2489 val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4;
2493 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE);
2498 if (changed & NETIF_F_HW_CSUM) {
2499 if (features & NETIF_F_HW_CSUM)
2500 val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4;
2504 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE);
2510 spin_unlock_irqrestore(&priv->lock, flags);
2515 static int ravb_set_features_rcar(struct net_device *ndev,
2516 netdev_features_t features)
2518 netdev_features_t changed = ndev->features ^ features;
2520 if (changed & NETIF_F_RXCSUM)
2521 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2526 static int ravb_set_features(struct net_device *ndev,
2527 netdev_features_t features)
2529 struct ravb_private *priv = netdev_priv(ndev);
2530 const struct ravb_hw_info *info = priv->info;
2531 struct device *dev = &priv->pdev->dev;
2534 pm_runtime_get_noresume(dev);
2536 if (pm_runtime_active(dev))
2537 ret = info->set_feature(ndev, features);
2541 pm_runtime_put_noidle(dev);
2546 ndev->features = features;
2551 static const struct net_device_ops ravb_netdev_ops = {
2552 .ndo_open = ravb_open,
2553 .ndo_stop = ravb_close,
2554 .ndo_start_xmit = ravb_start_xmit,
2555 .ndo_select_queue = ravb_select_queue,
2556 .ndo_get_stats = ravb_get_stats,
2557 .ndo_set_rx_mode = ravb_set_rx_mode,
2558 .ndo_tx_timeout = ravb_tx_timeout,
2559 .ndo_eth_ioctl = ravb_do_ioctl,
2560 .ndo_change_mtu = ravb_change_mtu,
2561 .ndo_validate_addr = eth_validate_addr,
2562 .ndo_set_mac_address = eth_mac_addr,
2563 .ndo_set_features = ravb_set_features,
2566 /* MDIO bus init function */
2567 static int ravb_mdio_init(struct ravb_private *priv)
2569 struct platform_device *pdev = priv->pdev;
2570 struct device *dev = &pdev->dev;
2571 struct phy_device *phydev;
2572 struct device_node *pn;
2576 priv->mdiobb.ops = &bb_ops;
2578 /* MII controller setting */
2579 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2583 /* Hook up MII support for ethtool */
2584 priv->mii_bus->name = "ravb_mii";
2585 priv->mii_bus->parent = dev;
2586 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2587 pdev->name, pdev->id);
2589 /* Register MDIO bus */
2590 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2594 pn = of_parse_phandle(dev->of_node, "phy-handle", 0);
2595 phydev = of_phy_find_device(pn);
2597 phydev->mac_managed_pm = true;
2598 put_device(&phydev->mdio.dev);
2605 free_mdio_bitbang(priv->mii_bus);
2609 /* MDIO bus release function */
2610 static int ravb_mdio_release(struct ravb_private *priv)
2612 /* Unregister mdio bus */
2613 mdiobus_unregister(priv->mii_bus);
2615 /* Free bitbang info */
2616 free_mdio_bitbang(priv->mii_bus);
2621 static const struct ravb_hw_info ravb_gen3_hw_info = {
2622 .receive = ravb_rx_rcar,
2623 .set_rate = ravb_set_rate_rcar,
2624 .set_feature = ravb_set_features_rcar,
2625 .dmac_init = ravb_dmac_init_rcar,
2626 .emac_init = ravb_emac_init_rcar,
2627 .gstrings_stats = ravb_gstrings_stats,
2628 .gstrings_size = sizeof(ravb_gstrings_stats),
2629 .net_hw_features = NETIF_F_RXCSUM,
2630 .net_features = NETIF_F_RXCSUM,
2631 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2632 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2633 .rx_max_frame_size = SZ_2K,
2634 .rx_max_desc_use = SZ_2K - ETH_FCS_LEN + sizeof(__sum16),
2635 .rx_desc_size = sizeof(struct ravb_ex_rx_desc),
2636 .internal_delay = 1,
2645 static const struct ravb_hw_info ravb_gen2_hw_info = {
2646 .receive = ravb_rx_rcar,
2647 .set_rate = ravb_set_rate_rcar,
2648 .set_feature = ravb_set_features_rcar,
2649 .dmac_init = ravb_dmac_init_rcar,
2650 .emac_init = ravb_emac_init_rcar,
2651 .gstrings_stats = ravb_gstrings_stats,
2652 .gstrings_size = sizeof(ravb_gstrings_stats),
2653 .net_hw_features = NETIF_F_RXCSUM,
2654 .net_features = NETIF_F_RXCSUM,
2655 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2656 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2657 .rx_max_frame_size = SZ_2K,
2658 .rx_max_desc_use = SZ_2K - ETH_FCS_LEN + sizeof(__sum16),
2659 .rx_desc_size = sizeof(struct ravb_ex_rx_desc),
2666 static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2667 .receive = ravb_rx_rcar,
2668 .set_rate = ravb_set_rate_rcar,
2669 .set_feature = ravb_set_features_rcar,
2670 .dmac_init = ravb_dmac_init_rcar,
2671 .emac_init = ravb_emac_init_rcar,
2672 .gstrings_stats = ravb_gstrings_stats,
2673 .gstrings_size = sizeof(ravb_gstrings_stats),
2674 .net_hw_features = NETIF_F_RXCSUM,
2675 .net_features = NETIF_F_RXCSUM,
2676 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2677 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2678 .rx_max_frame_size = SZ_2K,
2679 .rx_max_desc_use = SZ_2K - ETH_FCS_LEN + sizeof(__sum16),
2680 .rx_desc_size = sizeof(struct ravb_ex_rx_desc),
2689 static const struct ravb_hw_info gbeth_hw_info = {
2690 .receive = ravb_rx_gbeth,
2691 .set_rate = ravb_set_rate_gbeth,
2692 .set_feature = ravb_set_features_gbeth,
2693 .dmac_init = ravb_dmac_init_gbeth,
2694 .emac_init = ravb_emac_init_gbeth,
2695 .gstrings_stats = ravb_gstrings_stats_gbeth,
2696 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2697 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM,
2698 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM,
2699 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2700 .tccr_mask = TCCR_TSRQ0,
2701 .rx_max_frame_size = SZ_8K,
2702 .rx_max_desc_use = 4080,
2703 .rx_desc_size = sizeof(struct ravb_rx_desc),
2706 .carrier_counters = 1,
2710 static const struct of_device_id ravb_match_table[] = {
2711 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2712 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2713 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2714 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2715 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2716 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info },
2717 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2718 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2721 MODULE_DEVICE_TABLE(of, ravb_match_table);
2723 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name,
2724 const char *ch, int *irq, irq_handler_t handler)
2726 struct platform_device *pdev = priv->pdev;
2727 struct net_device *ndev = priv->ndev;
2728 struct device *dev = &pdev->dev;
2729 const char *dev_name;
2730 unsigned long flags;
2734 dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
2738 irq_num = platform_get_irq_byname(pdev, irq_name);
2741 dev_name = ndev->name;
2742 irq_num = platform_get_irq(pdev, 0);
2743 flags = IRQF_SHARED;
2751 error = devm_request_irq(dev, irq_num, handler, flags, dev_name, ndev);
2753 netdev_err(ndev, "cannot request IRQ %s\n", dev_name);
2758 static int ravb_setup_irqs(struct ravb_private *priv)
2760 const struct ravb_hw_info *info = priv->info;
2761 struct net_device *ndev = priv->ndev;
2762 const char *irq_name, *emac_irq_name;
2765 if (!info->multi_irqs)
2766 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt);
2768 if (info->err_mgmt_irqs) {
2770 emac_irq_name = "line3";
2773 emac_irq_name = "ch24";
2776 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt);
2780 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq,
2781 ravb_emac_interrupt);
2785 if (info->err_mgmt_irqs) {
2786 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt);
2790 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt);
2795 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt);
2799 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt);
2803 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt);
2807 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt);
2810 static int ravb_probe(struct platform_device *pdev)
2812 struct device_node *np = pdev->dev.of_node;
2813 const struct ravb_hw_info *info;
2814 struct reset_control *rstc;
2815 struct ravb_private *priv;
2816 struct net_device *ndev;
2817 struct resource *res;
2822 "this driver is required to be instantiated from device tree\n");
2826 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
2828 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2829 "failed to get cpg reset\n");
2831 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2832 NUM_TX_QUEUE, NUM_RX_QUEUE);
2836 info = of_device_get_match_data(&pdev->dev);
2838 ndev->features = info->net_features;
2839 ndev->hw_features = info->net_hw_features;
2841 error = reset_control_deassert(rstc);
2843 goto out_free_netdev;
2845 SET_NETDEV_DEV(ndev, &pdev->dev);
2847 priv = netdev_priv(ndev);
2852 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2853 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2854 if (info->nc_queues) {
2855 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2856 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2859 error = ravb_setup_irqs(priv);
2861 goto out_reset_assert;
2863 priv->clk = devm_clk_get(&pdev->dev, NULL);
2864 if (IS_ERR(priv->clk)) {
2865 error = PTR_ERR(priv->clk);
2866 goto out_reset_assert;
2869 if (info->gptp_ref_clk) {
2870 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2871 if (IS_ERR(priv->gptp_clk)) {
2872 error = PTR_ERR(priv->gptp_clk);
2873 goto out_reset_assert;
2877 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2878 if (IS_ERR(priv->refclk)) {
2879 error = PTR_ERR(priv->refclk);
2880 goto out_reset_assert;
2882 clk_prepare(priv->refclk);
2884 platform_set_drvdata(pdev, ndev);
2885 pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
2886 pm_runtime_use_autosuspend(&pdev->dev);
2887 pm_runtime_enable(&pdev->dev);
2888 error = pm_runtime_resume_and_get(&pdev->dev);
2890 goto out_rpm_disable;
2892 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2893 if (IS_ERR(priv->addr)) {
2894 error = PTR_ERR(priv->addr);
2898 /* The Ether-specific entries in the device structure. */
2899 ndev->base_addr = res->start;
2901 spin_lock_init(&priv->lock);
2902 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2904 error = of_get_phy_mode(np, &priv->phy_interface);
2905 if (error && error != -ENODEV)
2908 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2909 priv->avb_link_active_low =
2910 of_property_read_bool(np, "renesas,ether-link-active-low");
2912 ndev->max_mtu = info->rx_max_frame_size -
2913 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2914 ndev->min_mtu = ETH_MIN_MTU;
2916 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2917 * Use two descriptor to handle such situation. First descriptor to
2918 * handle aligned data buffer and second descriptor to handle the
2919 * overflow data because of alignment.
2921 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2924 ndev->netdev_ops = &ravb_netdev_ops;
2925 ndev->ethtool_ops = &ravb_ethtool_ops;
2927 error = ravb_compute_gti(ndev);
2931 ravb_parse_delay_mode(np, ndev);
2933 /* Allocate descriptor base address table */
2934 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2935 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2936 &priv->desc_bat_dma, GFP_KERNEL);
2937 if (!priv->desc_bat) {
2939 "Cannot allocate desc base address table (size %d bytes)\n",
2940 priv->desc_bat_size);
2944 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2945 priv->desc_bat[q].die_dt = DT_EOS;
2947 /* Initialise HW timestamp list */
2948 INIT_LIST_HEAD(&priv->ts_skb_list);
2950 /* Debug message level */
2951 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2953 /* Set config mode as this is needed for PHY initialization. */
2954 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
2958 /* Read and set MAC address */
2959 ravb_read_mac_address(np, ndev);
2960 if (!is_valid_ether_addr(ndev->dev_addr)) {
2961 dev_warn(&pdev->dev,
2962 "no valid MAC address supplied, using a random one\n");
2963 eth_hw_addr_random(ndev);
2967 error = ravb_mdio_init(priv);
2969 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2970 goto out_reset_mode;
2973 /* Undo previous switch to config opmode. */
2974 error = ravb_set_opmode(ndev, CCC_OPC_RESET);
2976 goto out_mdio_release;
2978 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll);
2979 if (info->nc_queues)
2980 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll);
2982 /* Network device register */
2983 error = register_netdev(ndev);
2987 device_set_wakeup_capable(&pdev->dev, 1);
2989 /* Print device information */
2990 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2991 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2993 pm_runtime_mark_last_busy(&pdev->dev);
2994 pm_runtime_put_autosuspend(&pdev->dev);
2999 if (info->nc_queues)
3000 netif_napi_del(&priv->napi[RAVB_NC]);
3002 netif_napi_del(&priv->napi[RAVB_BE]);
3004 ravb_mdio_release(priv);
3006 ravb_set_opmode(ndev, CCC_OPC_RESET);
3007 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
3008 priv->desc_bat_dma);
3010 pm_runtime_put(&pdev->dev);
3012 pm_runtime_disable(&pdev->dev);
3013 pm_runtime_dont_use_autosuspend(&pdev->dev);
3014 clk_unprepare(priv->refclk);
3016 reset_control_assert(rstc);
3022 static void ravb_remove(struct platform_device *pdev)
3024 struct net_device *ndev = platform_get_drvdata(pdev);
3025 struct ravb_private *priv = netdev_priv(ndev);
3026 const struct ravb_hw_info *info = priv->info;
3027 struct device *dev = &priv->pdev->dev;
3030 error = pm_runtime_resume_and_get(dev);
3034 unregister_netdev(ndev);
3035 if (info->nc_queues)
3036 netif_napi_del(&priv->napi[RAVB_NC]);
3037 netif_napi_del(&priv->napi[RAVB_BE]);
3039 ravb_mdio_release(priv);
3041 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
3042 priv->desc_bat_dma);
3044 pm_runtime_put_sync_suspend(&pdev->dev);
3045 pm_runtime_disable(&pdev->dev);
3046 pm_runtime_dont_use_autosuspend(dev);
3047 clk_unprepare(priv->refclk);
3048 reset_control_assert(priv->rstc);
3050 platform_set_drvdata(pdev, NULL);
3053 static int ravb_wol_setup(struct net_device *ndev)
3055 struct ravb_private *priv = netdev_priv(ndev);
3056 const struct ravb_hw_info *info = priv->info;
3058 /* Disable interrupts by clearing the interrupt masks. */
3059 ravb_write(ndev, 0, RIC0);
3060 ravb_write(ndev, 0, RIC2);
3061 ravb_write(ndev, 0, TIC);
3063 /* Only allow ECI interrupts */
3064 synchronize_irq(priv->emac_irq);
3065 if (info->nc_queues)
3066 napi_disable(&priv->napi[RAVB_NC]);
3067 napi_disable(&priv->napi[RAVB_BE]);
3068 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
3070 /* Enable MagicPacket */
3071 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3073 if (priv->info->ccc_gac)
3074 ravb_ptp_stop(ndev);
3076 return enable_irq_wake(priv->emac_irq);
3079 static int ravb_wol_restore(struct net_device *ndev)
3081 struct ravb_private *priv = netdev_priv(ndev);
3082 const struct ravb_hw_info *info = priv->info;
3085 /* Set reset mode to rearm the WoL logic. */
3086 error = ravb_set_opmode(ndev, CCC_OPC_RESET);
3090 /* Set AVB config mode. */
3091 error = ravb_set_config_mode(ndev);
3095 if (priv->info->ccc_gac)
3096 ravb_ptp_init(ndev, priv->pdev);
3098 if (info->nc_queues)
3099 napi_enable(&priv->napi[RAVB_NC]);
3100 napi_enable(&priv->napi[RAVB_BE]);
3102 /* Disable MagicPacket */
3103 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
3107 return disable_irq_wake(priv->emac_irq);
3110 static int ravb_suspend(struct device *dev)
3112 struct net_device *ndev = dev_get_drvdata(dev);
3113 struct ravb_private *priv = netdev_priv(ndev);
3116 if (!netif_running(ndev))
3119 netif_device_detach(ndev);
3121 if (priv->wol_enabled)
3122 return ravb_wol_setup(ndev);
3124 ret = ravb_close(ndev);
3128 ret = pm_runtime_force_suspend(&priv->pdev->dev);
3133 return reset_control_assert(priv->rstc);
3136 static int ravb_resume(struct device *dev)
3138 struct net_device *ndev = dev_get_drvdata(dev);
3139 struct ravb_private *priv = netdev_priv(ndev);
3142 ret = reset_control_deassert(priv->rstc);
3146 if (!netif_running(ndev))
3149 /* If WoL is enabled restore the interface. */
3150 if (priv->wol_enabled) {
3151 ret = ravb_wol_restore(ndev);
3155 ret = pm_runtime_force_resume(dev);
3160 /* Reopening the interface will restore the device to the working state. */
3161 ret = ravb_open(ndev);
3165 ravb_set_rx_mode(ndev);
3166 netif_device_attach(ndev);
3171 if (!priv->wol_enabled) {
3172 pm_runtime_mark_last_busy(dev);
3173 pm_runtime_put_autosuspend(dev);
3179 static int ravb_runtime_suspend(struct device *dev)
3181 struct net_device *ndev = dev_get_drvdata(dev);
3182 struct ravb_private *priv = netdev_priv(ndev);
3184 clk_disable(priv->refclk);
3189 static int ravb_runtime_resume(struct device *dev)
3191 struct net_device *ndev = dev_get_drvdata(dev);
3192 struct ravb_private *priv = netdev_priv(ndev);
3194 return clk_enable(priv->refclk);
3197 static const struct dev_pm_ops ravb_dev_pm_ops = {
3198 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3199 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL)
3202 static struct platform_driver ravb_driver = {
3203 .probe = ravb_probe,
3204 .remove_new = ravb_remove,
3207 .pm = pm_ptr(&ravb_dev_pm_ops),
3208 .of_match_table = ravb_match_table,
3212 module_platform_driver(ravb_driver);
3214 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3215 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3216 MODULE_LICENSE("GPL v2");