drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #include "r8169.h"
  35 #include "r8169_firmware.h"
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  40 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  41 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  42 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  43 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  46 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  47 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  48 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  49 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  50 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  51 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  56 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  57
  58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  59    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  60 #define MC_FILTER_LIMIT 32
  61
  62 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  63 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  64
  65 #define R8169_REGS_SIZE         256
  66 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  67 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  68 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  69 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  70 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  71
  72 #define OCP_STD_PHY_BASE        0xa400
  73
  74 #define RTL_CFG_NO_GBIT 1
  75
  76 /* write/read MMIO register */
  77 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  80 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  81 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  82 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  83
  84 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  85 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  86 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  87 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88
  89 static const struct {
  90         const char *name;
  91         const char *fw_name;
  92 } rtl_chip_infos[] = {
  93         /* PCI devices. */
  94         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  95         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  96         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
  97         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
  98         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
  99         /* PCI-E devices. */
 100         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 101         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 102         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 103         [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"                    },
 104         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 105         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 106         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 107         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 108         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 109         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 110         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 111         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 112         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 113         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 115         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 116         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 117         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 118         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 119         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 120         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 121         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 122         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 123         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 124         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 125         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 126         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 127         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 128         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 129         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 130         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 131         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 132         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 133         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 134         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 135         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 136         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 137         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 138         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 139         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 140 };
 141
 142 static const struct pci_device_id rtl8169_pci_tbl[] = {
 143         { PCI_VDEVICE(REALTEK,  0x2502) },
 144         { PCI_VDEVICE(REALTEK,  0x2600) },
 145         { PCI_VDEVICE(REALTEK,  0x8129) },
 146         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 147         { PCI_VDEVICE(REALTEK,  0x8161) },
 148         { PCI_VDEVICE(REALTEK,  0x8162) },
 149         { PCI_VDEVICE(REALTEK,  0x8167) },
 150         { PCI_VDEVICE(REALTEK,  0x8168) },
 151         { PCI_VDEVICE(NCUBE,    0x8168) },
 152         { PCI_VDEVICE(REALTEK,  0x8169) },
 153         { PCI_VENDOR_ID_DLINK,  0x4300,
 154                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 155         { PCI_VDEVICE(DLINK,    0x4300) },
 156         { PCI_VDEVICE(DLINK,    0x4302) },
 157         { PCI_VDEVICE(AT,       0xc107) },
 158         { PCI_VDEVICE(USR,      0x0116) },
 159         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 160         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 161         { PCI_VDEVICE(REALTEK,  0x8125) },
 162         { PCI_VDEVICE(REALTEK,  0x3000) },
 163         {}
 164 };
 165
 166 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 167
 168 enum rtl_registers {
 169         MAC0            = 0,    /* Ethernet hardware address. */
 170         MAC4            = 4,
 171         MAR0            = 8,    /* Multicast filter. */
 172         CounterAddrLow          = 0x10,
 173         CounterAddrHigh         = 0x14,
 174         TxDescStartAddrLow      = 0x20,
 175         TxDescStartAddrHigh     = 0x24,
 176         TxHDescStartAddrLow     = 0x28,
 177         TxHDescStartAddrHigh    = 0x2c,
 178         FLASH           = 0x30,
 179         ERSR            = 0x36,
 180         ChipCmd         = 0x37,
 181         TxPoll          = 0x38,
 182         IntrMask        = 0x3c,
 183         IntrStatus      = 0x3e,
 184
 185         TxConfig        = 0x40,
 186 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 187 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 188
 189         RxConfig        = 0x44,
 190 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 191 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 192 #define RXCFG_FIFO_SHIFT                13
 193                                         /* No threshold before first PCI xfer */
 194 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 195 #define RX_EARLY_OFF                    (1 << 11)
 196 #define RXCFG_DMA_SHIFT                 8
 197                                         /* Unlimited maximum PCI burst. */
 198 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 199
 200         Cfg9346         = 0x50,
 201         Config0         = 0x51,
 202         Config1         = 0x52,
 203         Config2         = 0x53,
 204 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 205
 206         Config3         = 0x54,
 207         Config4         = 0x55,
 208         Config5         = 0x56,
 209         PHYAR           = 0x60,
 210         PHYstatus       = 0x6c,
 211         RxMaxSize       = 0xda,
 212         CPlusCmd        = 0xe0,
 213         IntrMitigate    = 0xe2,
 214
 215 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 216 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 217 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 218 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 219
 220 #define RTL_COALESCE_T_MAX      0x0fU
 221 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 222
 223         RxDescAddrLow   = 0xe4,
 224         RxDescAddrHigh  = 0xe8,
 225         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 226
 227 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 228
 229         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 230
 231 #define TxPacketMax     (8064 >> 7)
 232 #define EarlySize       0x27
 233
 234         FuncEvent       = 0xf0,
 235         FuncEventMask   = 0xf4,
 236         FuncPresetState = 0xf8,
 237         IBCR0           = 0xf8,
 238         IBCR2           = 0xf9,
 239         IBIMR0          = 0xfa,
 240         IBISR0          = 0xfb,
 241         FuncForceEvent  = 0xfc,
 242 };
 243
 244 enum rtl8168_8101_registers {
 245         CSIDR                   = 0x64,
 246         CSIAR                   = 0x68,
 247 #define CSIAR_FLAG                      0x80000000
 248 #define CSIAR_WRITE_CMD                 0x80000000
 249 #define CSIAR_BYTE_ENABLE               0x0000f000
 250 #define CSIAR_ADDR_MASK                 0x00000fff
 251         PMCH                    = 0x6f,
 252 #define D3COLD_NO_PLL_DOWN              BIT(7)
 253 #define D3HOT_NO_PLL_DOWN               BIT(6)
 254 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 255         EPHYAR                  = 0x80,
 256 #define EPHYAR_FLAG                     0x80000000
 257 #define EPHYAR_WRITE_CMD                0x80000000
 258 #define EPHYAR_REG_MASK                 0x1f
 259 #define EPHYAR_REG_SHIFT                16
 260 #define EPHYAR_DATA_MASK                0xffff
 261         DLLPR                   = 0xd0,
 262 #define PFM_EN                          (1 << 6)
 263 #define TX_10M_PS_EN                    (1 << 7)
 264         DBG_REG                 = 0xd1,
 265 #define FIX_NAK_1                       (1 << 4)
 266 #define FIX_NAK_2                       (1 << 3)
 267         TWSI                    = 0xd2,
 268         MCU                     = 0xd3,
 269 #define NOW_IS_OOB                      (1 << 7)
 270 #define TX_EMPTY                        (1 << 5)
 271 #define RX_EMPTY                        (1 << 4)
 272 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 273 #define EN_NDP                          (1 << 3)
 274 #define EN_OOB_RESET                    (1 << 2)
 275 #define LINK_LIST_RDY                   (1 << 1)
 276         EFUSEAR                 = 0xdc,
 277 #define EFUSEAR_FLAG                    0x80000000
 278 #define EFUSEAR_WRITE_CMD               0x80000000
 279 #define EFUSEAR_READ_CMD                0x00000000
 280 #define EFUSEAR_REG_MASK                0x03ff
 281 #define EFUSEAR_REG_SHIFT               8
 282 #define EFUSEAR_DATA_MASK               0xff
 283         MISC_1                  = 0xf2,
 284 #define PFM_D3COLD_EN                   (1 << 6)
 285 };
 286
 287 enum rtl8168_registers {
 288         LED_FREQ                = 0x1a,
 289         EEE_LED                 = 0x1b,
 290         ERIDR                   = 0x70,
 291         ERIAR                   = 0x74,
 292 #define ERIAR_FLAG                      0x80000000
 293 #define ERIAR_WRITE_CMD                 0x80000000
 294 #define ERIAR_READ_CMD                  0x00000000
 295 #define ERIAR_ADDR_BYTE_ALIGN           4
 296 #define ERIAR_TYPE_SHIFT                16
 297 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 298 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 299 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 300 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 301 #define ERIAR_MASK_SHIFT                12
 302 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 303 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 304 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 305 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 306 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 307         EPHY_RXER_NUM           = 0x7c,
 308         OCPDR                   = 0xb0, /* OCP GPHY access */
 309 #define OCPDR_WRITE_CMD                 0x80000000
 310 #define OCPDR_READ_CMD                  0x00000000
 311 #define OCPDR_REG_MASK                  0x7f
 312 #define OCPDR_GPHY_REG_SHIFT            16
 313 #define OCPDR_DATA_MASK                 0xffff
 314         OCPAR                   = 0xb4,
 315 #define OCPAR_FLAG                      0x80000000
 316 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 317 #define OCPAR_GPHY_READ_CMD             0x0000f060
 318         GPHY_OCP                = 0xb8,
 319         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 320         MISC                    = 0xf0, /* 8168e only. */
 321 #define TXPLA_RST                       (1 << 29)
 322 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 323 #define PWM_EN                          (1 << 22)
 324 #define RXDV_GATED_EN                   (1 << 19)
 325 #define EARLY_TALLY_EN                  (1 << 16)
 326 };
 327
 328 enum rtl8125_registers {
 329         IntrMask_8125           = 0x38,
 330         IntrStatus_8125         = 0x3c,
 331         TxPoll_8125             = 0x90,
 332         MAC0_BKP                = 0x19e0,
 333         EEE_TXIDLE_TIMER_8125   = 0x6048,
 334 };
 335
 336 #define RX_VLAN_INNER_8125      BIT(22)
 337 #define RX_VLAN_OUTER_8125      BIT(23)
 338 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 339
 340 #define RX_FETCH_DFLT_8125      (8 << 27)
 341
 342 enum rtl_register_content {
 343         /* InterruptStatusBits */
 344         SYSErr          = 0x8000,
 345         PCSTimeout      = 0x4000,
 346         SWInt           = 0x0100,
 347         TxDescUnavail   = 0x0080,
 348         RxFIFOOver      = 0x0040,
 349         LinkChg         = 0x0020,
 350         RxOverflow      = 0x0010,
 351         TxErr           = 0x0008,
 352         TxOK            = 0x0004,
 353         RxErr           = 0x0002,
 354         RxOK            = 0x0001,
 355
 356         /* RxStatusDesc */
 357         RxRWT   = (1 << 22),
 358         RxRES   = (1 << 21),
 359         RxRUNT  = (1 << 20),
 360         RxCRC   = (1 << 19),
 361
 362         /* ChipCmdBits */
 363         StopReq         = 0x80,
 364         CmdReset        = 0x10,
 365         CmdRxEnb        = 0x08,
 366         CmdTxEnb        = 0x04,
 367         RxBufEmpty      = 0x01,
 368
 369         /* TXPoll register p.5 */
 370         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 371         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 372         FSWInt          = 0x01,         /* Forced software interrupt */
 373
 374         /* Cfg9346Bits */
 375         Cfg9346_Lock    = 0x00,
 376         Cfg9346_Unlock  = 0xc0,
 377
 378         /* rx_mode_bits */
 379         AcceptErr       = 0x20,
 380         AcceptRunt      = 0x10,
 381 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 382         AcceptBroadcast = 0x08,
 383         AcceptMulticast = 0x04,
 384         AcceptMyPhys    = 0x02,
 385         AcceptAllPhys   = 0x01,
 386 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 387 #define RX_CONFIG_ACCEPT_MASK           0x3f
 388
 389         /* TxConfigBits */
 390         TxInterFrameGapShift = 24,
 391         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 392
 393         /* Config1 register p.24 */
 394         LEDS1           = (1 << 7),
 395         LEDS0           = (1 << 6),
 396         Speed_down      = (1 << 4),
 397         MEMMAP          = (1 << 3),
 398         IOMAP           = (1 << 2),
 399         VPD             = (1 << 1),
 400         PMEnable        = (1 << 0),     /* Power Management Enable */
 401
 402         /* Config2 register p. 25 */
 403         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 404         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 405         PCI_Clock_66MHz = 0x01,
 406         PCI_Clock_33MHz = 0x00,
 407
 408         /* Config3 register p.25 */
 409         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 410         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 411         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 412         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 413         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 414
 415         /* Config4 register */
 416         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 417
 418         /* Config5 register p.27 */
 419         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 420         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 421         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 422         Spi_en          = (1 << 3),
 423         LanWake         = (1 << 1),     /* LanWake enable/disable */
 424         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 425         ASPM_en         = (1 << 0),     /* ASPM enable */
 426
 427         /* CPlusCmd p.31 */
 428         EnableBist      = (1 << 15),    // 8168 8101
 429         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 430         EnAnaPLL        = (1 << 14),    // 8169
 431         Normal_mode     = (1 << 13),    // unused
 432         Force_half_dup  = (1 << 12),    // 8168 8101
 433         Force_rxflow_en = (1 << 11),    // 8168 8101
 434         Force_txflow_en = (1 << 10),    // 8168 8101
 435         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 436         ASF             = (1 << 8),     // 8168 8101
 437         PktCntrDisable  = (1 << 7),     // 8168 8101
 438         Mac_dbgo_sel    = 0x001c,       // 8168
 439         RxVlan          = (1 << 6),
 440         RxChkSum        = (1 << 5),
 441         PCIDAC          = (1 << 4),
 442         PCIMulRW        = (1 << 3),
 443 #define INTT_MASK       GENMASK(1, 0)
 444 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 445
 446         /* rtl8169_PHYstatus */
 447         TBI_Enable      = 0x80,
 448         TxFlowCtrl      = 0x40,
 449         RxFlowCtrl      = 0x20,
 450         _1000bpsF       = 0x10,
 451         _100bps         = 0x08,
 452         _10bps          = 0x04,
 453         LinkStatus      = 0x02,
 454         FullDup         = 0x01,
 455
 456         /* ResetCounterCommand */
 457         CounterReset    = 0x1,
 458
 459         /* DumpCounterCommand */
 460         CounterDump     = 0x8,
 461
 462         /* magic enable v2 */
 463         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 464 };
 465
 466 enum rtl_desc_bit {
 467         /* First doubleword. */
 468         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 469         RingEnd         = (1 << 30), /* End of descriptor ring */
 470         FirstFrag       = (1 << 29), /* First segment of a packet */
 471         LastFrag        = (1 << 28), /* Final segment of a packet */
 472 };
 473
 474 /* Generic case. */
 475 enum rtl_tx_desc_bit {
 476         /* First doubleword. */
 477         TD_LSO          = (1 << 27),            /* Large Send Offload */
 478 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 479
 480         /* Second doubleword. */
 481         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 482 };
 483
 484 /* 8169, 8168b and 810x except 8102e. */
 485 enum rtl_tx_desc_bit_0 {
 486         /* First doubleword. */
 487 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 488         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 489         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 490         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 491 };
 492
 493 /* 8102e, 8168c and beyond. */
 494 enum rtl_tx_desc_bit_1 {
 495         /* First doubleword. */
 496         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 497         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 498 #define GTTCPHO_SHIFT                   18
 499 #define GTTCPHO_MAX                     0x7f
 500
 501         /* Second doubleword. */
 502 #define TCPHO_SHIFT                     18
 503 #define TCPHO_MAX                       0x3ff
 504 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 505         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 506         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 507         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 508         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 509 };
 510
 511 enum rtl_rx_desc_bit {
 512         /* Rx private */
 513         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 514         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 515
 516 #define RxProtoUDP      (PID1)
 517 #define RxProtoTCP      (PID0)
 518 #define RxProtoIP       (PID1 | PID0)
 519 #define RxProtoMask     RxProtoIP
 520
 521         IPFail          = (1 << 16), /* IP checksum failed */
 522         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 523         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 524
 525 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 526
 527         RxVlanTag       = (1 << 16), /* VLAN tag available */
 528 };
 529
 530 #define RTL_GSO_MAX_SIZE_V1     32000
 531 #define RTL_GSO_MAX_SEGS_V1     24
 532 #define RTL_GSO_MAX_SIZE_V2     64000
 533 #define RTL_GSO_MAX_SEGS_V2     64
 534
 535 struct TxDesc {
 536         __le32 opts1;
 537         __le32 opts2;
 538         __le64 addr;
 539 };
 540
 541 struct RxDesc {
 542         __le32 opts1;
 543         __le32 opts2;
 544         __le64 addr;
 545 };
 546
 547 struct ring_info {
 548         struct sk_buff  *skb;
 549         u32             len;
 550 };
 551
 552 struct rtl8169_counters {
 553         __le64  tx_packets;
 554         __le64  rx_packets;
 555         __le64  tx_errors;
 556         __le32  rx_errors;
 557         __le16  rx_missed;
 558         __le16  align_errors;
 559         __le32  tx_one_collision;
 560         __le32  tx_multi_collision;
 561         __le64  rx_unicast;
 562         __le64  rx_broadcast;
 563         __le32  rx_multicast;
 564         __le16  tx_aborted;
 565         __le16  tx_underun;
 566 };
 567
 568 struct rtl8169_tc_offsets {
 569         bool    inited;
 570         __le64  tx_errors;
 571         __le32  tx_multi_collision;
 572         __le16  tx_aborted;
 573         __le16  rx_missed;
 574 };
 575
 576 enum rtl_flag {
 577         RTL_FLAG_TASK_ENABLED = 0,
 578         RTL_FLAG_TASK_RESET_PENDING,
 579         RTL_FLAG_MAX
 580 };
 581
 582 enum rtl_dash_type {
 583         RTL_DASH_NONE,
 584         RTL_DASH_DP,
 585         RTL_DASH_EP,
 586 };
 587
 588 struct rtl8169_private {
 589         void __iomem *mmio_addr;        /* memory map physical address */
 590         struct pci_dev *pci_dev;
 591         struct net_device *dev;
 592         struct phy_device *phydev;
 593         struct napi_struct napi;
 594         enum mac_version mac_version;
 595         enum rtl_dash_type dash_type;
 596         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 597         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 598         u32 dirty_tx;
 599         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 600         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 601         dma_addr_t TxPhyAddr;
 602         dma_addr_t RxPhyAddr;
 603         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 604         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 605         u16 cp_cmd;
 606         u32 irq_mask;
 607         int irq;
 608         struct clk *clk;
 609
 610         struct {
 611                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 612                 struct work_struct work;
 613         } wk;
 614
 615         unsigned supports_gmii:1;
 616         unsigned aspm_manageable:1;
 617         dma_addr_t counters_phys_addr;
 618         struct rtl8169_counters *counters;
 619         struct rtl8169_tc_offsets tc_offset;
 620         u32 saved_wolopts;
 621         int eee_adv;
 622
 623         const char *fw_name;
 624         struct rtl_fw *rtl_fw;
 625
 626         u32 ocp_base;
 627 };
 628
 629 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 630
 631 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 632 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 633 MODULE_SOFTDEP("pre: realtek");
 634 MODULE_LICENSE("GPL");
 635 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 636 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 637 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 638 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 639 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 640 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 641 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 642 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 643 MODULE_FIRMWARE(FIRMWARE_8402_1);
 644 MODULE_FIRMWARE(FIRMWARE_8411_1);
 645 MODULE_FIRMWARE(FIRMWARE_8411_2);
 646 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 647 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 648 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 649 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 650 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 651 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 652 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 653 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 654 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 655
 656 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 657 {
 658         return &tp->pci_dev->dev;
 659 }
 660
 661 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 662 {
 663         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 664 }
 665
 666 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 667 {
 668         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 669 }
 670
 671 static void rtl_pci_commit(struct rtl8169_private *tp)
 672 {
 673         /* Read an arbitrary register to commit a preceding PCI write */
 674         RTL_R8(tp, ChipCmd);
 675 }
 676
 677 static bool rtl_is_8125(struct rtl8169_private *tp)
 678 {
 679         return tp->mac_version >= RTL_GIGA_MAC_VER_61;
 680 }
 681
 682 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 683 {
 684         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 685                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 686                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 687 }
 688
 689 static bool rtl_supports_eee(struct rtl8169_private *tp)
 690 {
 691         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 692                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 693                tp->mac_version != RTL_GIGA_MAC_VER_39;
 694 }
 695
 696 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 697 {
 698         int i;
 699
 700         for (i = 0; i < ETH_ALEN; i++)
 701                 mac[i] = RTL_R8(tp, reg + i);
 702 }
 703
 704 struct rtl_cond {
 705         bool (*check)(struct rtl8169_private *);
 706         const char *msg;
 707 };
 708
 709 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 710                           unsigned long usecs, int n, bool high)
 711 {
 712         int i;
 713
 714         for (i = 0; i < n; i++) {
 715                 if (c->check(tp) == high)
 716                         return true;
 717                 fsleep(usecs);
 718         }
 719
 720         if (net_ratelimit())
 721                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 722                            c->msg, !high, n, usecs);
 723         return false;
 724 }
 725
 726 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 727                                const struct rtl_cond *c,
 728                                unsigned long d, int n)
 729 {
 730         return rtl_loop_wait(tp, c, d, n, true);
 731 }
 732
 733 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 734                               const struct rtl_cond *c,
 735                               unsigned long d, int n)
 736 {
 737         return rtl_loop_wait(tp, c, d, n, false);
 738 }
 739
 740 #define DECLARE_RTL_COND(name)                          \
 741 static bool name ## _check(struct rtl8169_private *);   \
 742                                                         \
 743 static const struct rtl_cond name = {                   \
 744         .check  = name ## _check,                       \
 745         .msg    = #name                                 \
 746 };                                                      \
 747                                                         \
 748 static bool name ## _check(struct rtl8169_private *tp)
 749
 750 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 751 {
 752         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 753         if (type == ERIAR_OOB &&
 754             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 755              tp->mac_version == RTL_GIGA_MAC_VER_53))
 756                 *cmd |= 0xf70 << 18;
 757 }
 758
 759 DECLARE_RTL_COND(rtl_eriar_cond)
 760 {
 761         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 762 }
 763
 764 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 765                            u32 val, int type)
 766 {
 767         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 768
 769         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 770                 return;
 771
 772         RTL_W32(tp, ERIDR, val);
 773         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 774         RTL_W32(tp, ERIAR, cmd);
 775
 776         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 777 }
 778
 779 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 780                           u32 val)
 781 {
 782         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 783 }
 784
 785 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 786 {
 787         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 788
 789         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 790         RTL_W32(tp, ERIAR, cmd);
 791
 792         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 793                 RTL_R32(tp, ERIDR) : ~0;
 794 }
 795
 796 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 797 {
 798         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 799 }
 800
 801 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 802 {
 803         u32 val = rtl_eri_read(tp, addr);
 804
 805         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 806 }
 807
 808 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 809 {
 810         rtl_w0w1_eri(tp, addr, p, 0);
 811 }
 812
 813 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 814 {
 815         rtl_w0w1_eri(tp, addr, 0, m);
 816 }
 817
 818 static bool rtl_ocp_reg_failure(u32 reg)
 819 {
 820         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 821 }
 822
 823 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 824 {
 825         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 826 }
 827
 828 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 829 {
 830         if (rtl_ocp_reg_failure(reg))
 831                 return;
 832
 833         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 834
 835         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 836 }
 837
 838 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 839 {
 840         if (rtl_ocp_reg_failure(reg))
 841                 return 0;
 842
 843         RTL_W32(tp, GPHY_OCP, reg << 15);
 844
 845         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 846                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 847 }
 848
 849 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 850 {
 851         if (rtl_ocp_reg_failure(reg))
 852                 return;
 853
 854         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 855 }
 856
 857 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 858 {
 859         if (rtl_ocp_reg_failure(reg))
 860                 return 0;
 861
 862         RTL_W32(tp, OCPDR, reg << 15);
 863
 864         return RTL_R32(tp, OCPDR);
 865 }
 866
 867 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 868                                  u16 set)
 869 {
 870         u16 data = r8168_mac_ocp_read(tp, reg);
 871
 872         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 873 }
 874
 875 /* Work around a hw issue with RTL8168g PHY, the quirk disables
 876  * PHY MCU interrupts before PHY power-down.
 877  */
 878 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 879 {
 880         switch (tp->mac_version) {
 881         case RTL_GIGA_MAC_VER_40:
 882                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 883                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 884                 else
 885                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 886                 break;
 887         default:
 888                 break;
 889         }
 890 };
 891
 892 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 893 {
 894         if (reg == 0x1f) {
 895                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 896                 return;
 897         }
 898
 899         if (tp->ocp_base != OCP_STD_PHY_BASE)
 900                 reg -= 0x10;
 901
 902         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 903                 rtl8168g_phy_suspend_quirk(tp, value);
 904
 905         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 906 }
 907
 908 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 909 {
 910         if (reg == 0x1f)
 911                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 912
 913         if (tp->ocp_base != OCP_STD_PHY_BASE)
 914                 reg -= 0x10;
 915
 916         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 917 }
 918
 919 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 920 {
 921         if (reg == 0x1f) {
 922                 tp->ocp_base = value << 4;
 923                 return;
 924         }
 925
 926         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 927 }
 928
 929 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 930 {
 931         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 932 }
 933
 934 DECLARE_RTL_COND(rtl_phyar_cond)
 935 {
 936         return RTL_R32(tp, PHYAR) & 0x80000000;
 937 }
 938
 939 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 940 {
 941         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 942
 943         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 944         /*
 945          * According to hardware specs a 20us delay is required after write
 946          * complete indication, but before sending next command.
 947          */
 948         udelay(20);
 949 }
 950
 951 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 952 {
 953         int value;
 954
 955         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 956
 957         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 958                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 959
 960         /*
 961          * According to hardware specs a 20us delay is required after read
 962          * complete indication, but before sending next command.
 963          */
 964         udelay(20);
 965
 966         return value;
 967 }
 968
 969 DECLARE_RTL_COND(rtl_ocpar_cond)
 970 {
 971         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 972 }
 973
 974 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 975
 976 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 977 {
 978         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 979 }
 980
 981 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 982 {
 983         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 984 }
 985
 986 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 987 {
 988         r8168dp_2_mdio_start(tp);
 989
 990         r8169_mdio_write(tp, reg, value);
 991
 992         r8168dp_2_mdio_stop(tp);
 993 }
 994
 995 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 996 {
 997         int value;
 998
 999         /* Work around issue with chip reporting wrong PHY ID */
1000         if (reg == MII_PHYSID2)
1001                 return 0xc912;
1002
1003         r8168dp_2_mdio_start(tp);
1004
1005         value = r8169_mdio_read(tp, reg);
1006
1007         r8168dp_2_mdio_stop(tp);
1008
1009         return value;
1010 }
1011
1012 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1013 {
1014         switch (tp->mac_version) {
1015         case RTL_GIGA_MAC_VER_28:
1016         case RTL_GIGA_MAC_VER_31:
1017                 r8168dp_2_mdio_write(tp, location, val);
1018                 break;
1019         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1020                 r8168g_mdio_write(tp, location, val);
1021                 break;
1022         default:
1023                 r8169_mdio_write(tp, location, val);
1024                 break;
1025         }
1026 }
1027
1028 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 {
1030         switch (tp->mac_version) {
1031         case RTL_GIGA_MAC_VER_28:
1032         case RTL_GIGA_MAC_VER_31:
1033                 return r8168dp_2_mdio_read(tp, location);
1034         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1035                 return r8168g_mdio_read(tp, location);
1036         default:
1037                 return r8169_mdio_read(tp, location);
1038         }
1039 }
1040
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1042 {
1043         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044 }
1045
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047 {
1048         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053         udelay(10);
1054 }
1055
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057 {
1058         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062 }
1063
1064 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1065 {
1066         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1067         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1068                 RTL_R32(tp, OCPDR) : ~0;
1069 }
1070
1071 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1072 {
1073         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1074 }
1075
1076 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1077                               u32 data)
1078 {
1079         RTL_W32(tp, OCPDR, data);
1080         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1081         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1082 }
1083
1084 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1085                               u32 data)
1086 {
1087         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1088                        data, ERIAR_OOB);
1089 }
1090
1091 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1092 {
1093         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1094
1095         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1096 }
1097
1098 #define OOB_CMD_RESET           0x00
1099 #define OOB_CMD_DRIVER_START    0x05
1100 #define OOB_CMD_DRIVER_STOP     0x06
1101
1102 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1103 {
1104         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1105 }
1106
1107 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1108 {
1109         u16 reg;
1110
1111         reg = rtl8168_get_ocp_reg(tp);
1112
1113         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1114 }
1115
1116 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1117 {
1118         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1119 }
1120
1121 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1122 {
1123         return RTL_R8(tp, IBISR0) & 0x20;
1124 }
1125
1126 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1127 {
1128         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1129         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1130         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1131         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1132 }
1133
1134 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1135 {
1136         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1137         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1138 }
1139
1140 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1141 {
1142         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1143         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1144         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1145 }
1146
1147 static void rtl8168_driver_start(struct rtl8169_private *tp)
1148 {
1149         if (tp->dash_type == RTL_DASH_DP)
1150                 rtl8168dp_driver_start(tp);
1151         else
1152                 rtl8168ep_driver_start(tp);
1153 }
1154
1155 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1156 {
1157         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1158         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1159 }
1160
1161 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1162 {
1163         rtl8168ep_stop_cmac(tp);
1164         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1165         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1166         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1167 }
1168
1169 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1170 {
1171         if (tp->dash_type == RTL_DASH_DP)
1172                 rtl8168dp_driver_stop(tp);
1173         else
1174                 rtl8168ep_driver_stop(tp);
1175 }
1176
1177 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1178 {
1179         u16 reg = rtl8168_get_ocp_reg(tp);
1180
1181         return r8168dp_ocp_read(tp, reg) & BIT(15);
1182 }
1183
1184 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1185 {
1186         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1187 }
1188
1189 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1190 {
1191         switch (tp->mac_version) {
1192         case RTL_GIGA_MAC_VER_28:
1193         case RTL_GIGA_MAC_VER_31:
1194                 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1195         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1196                 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1197         default:
1198                 return RTL_DASH_NONE;
1199         }
1200 }
1201
1202 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1203 {
1204         switch (tp->mac_version) {
1205         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1206         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1207         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1208         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1209                 if (enable)
1210                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1211                 else
1212                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1213                 break;
1214         default:
1215                 break;
1216         }
1217 }
1218
1219 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1220 {
1221         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1222         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1223 }
1224
1225 DECLARE_RTL_COND(rtl_efusear_cond)
1226 {
1227         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1228 }
1229
1230 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1231 {
1232         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1233
1234         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1235                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1236 }
1237
1238 static u32 rtl_get_events(struct rtl8169_private *tp)
1239 {
1240         if (rtl_is_8125(tp))
1241                 return RTL_R32(tp, IntrStatus_8125);
1242         else
1243                 return RTL_R16(tp, IntrStatus);
1244 }
1245
1246 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1247 {
1248         if (rtl_is_8125(tp))
1249                 RTL_W32(tp, IntrStatus_8125, bits);
1250         else
1251                 RTL_W16(tp, IntrStatus, bits);
1252 }
1253
1254 static void rtl_irq_disable(struct rtl8169_private *tp)
1255 {
1256         if (rtl_is_8125(tp))
1257                 RTL_W32(tp, IntrMask_8125, 0);
1258         else
1259                 RTL_W16(tp, IntrMask, 0);
1260 }
1261
1262 static void rtl_irq_enable(struct rtl8169_private *tp)
1263 {
1264         if (rtl_is_8125(tp))
1265                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1266         else
1267                 RTL_W16(tp, IntrMask, tp->irq_mask);
1268 }
1269
1270 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1271 {
1272         rtl_irq_disable(tp);
1273         rtl_ack_events(tp, 0xffffffff);
1274         rtl_pci_commit(tp);
1275 }
1276
1277 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1278 {
1279         struct phy_device *phydev = tp->phydev;
1280
1281         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1282             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1283                 if (phydev->speed == SPEED_1000) {
1284                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1285                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1286                 } else if (phydev->speed == SPEED_100) {
1287                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1288                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1289                 } else {
1290                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1291                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1292                 }
1293                 rtl_reset_packet_filter(tp);
1294         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1295                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1296                 if (phydev->speed == SPEED_1000) {
1297                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1298                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1299                 } else {
1300                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1301                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1302                 }
1303         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1304                 if (phydev->speed == SPEED_10) {
1305                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1306                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1307                 } else {
1308                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1309                 }
1310         }
1311 }
1312
1313 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1314
1315 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1316 {
1317         struct rtl8169_private *tp = netdev_priv(dev);
1318
1319         wol->supported = WAKE_ANY;
1320         wol->wolopts = tp->saved_wolopts;
1321 }
1322
1323 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1324 {
1325         static const struct {
1326                 u32 opt;
1327                 u16 reg;
1328                 u8  mask;
1329         } cfg[] = {
1330                 { WAKE_PHY,   Config3, LinkUp },
1331                 { WAKE_UCAST, Config5, UWF },
1332                 { WAKE_BCAST, Config5, BWF },
1333                 { WAKE_MCAST, Config5, MWF },
1334                 { WAKE_ANY,   Config5, LanWake },
1335                 { WAKE_MAGIC, Config3, MagicPacket }
1336         };
1337         unsigned int i, tmp = ARRAY_SIZE(cfg);
1338         u8 options;
1339
1340         rtl_unlock_config_regs(tp);
1341
1342         if (rtl_is_8168evl_up(tp)) {
1343                 tmp--;
1344                 if (wolopts & WAKE_MAGIC)
1345                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1346                 else
1347                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1348         } else if (rtl_is_8125(tp)) {
1349                 tmp--;
1350                 if (wolopts & WAKE_MAGIC)
1351                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1352                 else
1353                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1354         }
1355
1356         for (i = 0; i < tmp; i++) {
1357                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1358                 if (wolopts & cfg[i].opt)
1359                         options |= cfg[i].mask;
1360                 RTL_W8(tp, cfg[i].reg, options);
1361         }
1362
1363         switch (tp->mac_version) {
1364         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1365                 options = RTL_R8(tp, Config1) & ~PMEnable;
1366                 if (wolopts)
1367                         options |= PMEnable;
1368                 RTL_W8(tp, Config1, options);
1369                 break;
1370         case RTL_GIGA_MAC_VER_34:
1371         case RTL_GIGA_MAC_VER_37:
1372         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1373                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1374                 if (wolopts)
1375                         options |= PME_SIGNAL;
1376                 RTL_W8(tp, Config2, options);
1377                 break;
1378         default:
1379                 break;
1380         }
1381
1382         rtl_lock_config_regs(tp);
1383
1384         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1385
1386         if (tp->dash_type == RTL_DASH_NONE) {
1387                 rtl_set_d3_pll_down(tp, !wolopts);
1388                 tp->dev->wol_enabled = wolopts ? 1 : 0;
1389         }
1390 }
1391
1392 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1393 {
1394         struct rtl8169_private *tp = netdev_priv(dev);
1395
1396         if (wol->wolopts & ~WAKE_ANY)
1397                 return -EINVAL;
1398
1399         tp->saved_wolopts = wol->wolopts;
1400         __rtl8169_set_wol(tp, tp->saved_wolopts);
1401
1402         return 0;
1403 }
1404
1405 static void rtl8169_get_drvinfo(struct net_device *dev,
1406                                 struct ethtool_drvinfo *info)
1407 {
1408         struct rtl8169_private *tp = netdev_priv(dev);
1409         struct rtl_fw *rtl_fw = tp->rtl_fw;
1410
1411         strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1412         strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1413         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1414         if (rtl_fw)
1415                 strscpy(info->fw_version, rtl_fw->version,
1416                         sizeof(info->fw_version));
1417 }
1418
1419 static int rtl8169_get_regs_len(struct net_device *dev)
1420 {
1421         return R8169_REGS_SIZE;
1422 }
1423
1424 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1425         netdev_features_t features)
1426 {
1427         struct rtl8169_private *tp = netdev_priv(dev);
1428
1429         if (dev->mtu > TD_MSS_MAX)
1430                 features &= ~NETIF_F_ALL_TSO;
1431
1432         if (dev->mtu > ETH_DATA_LEN &&
1433             tp->mac_version > RTL_GIGA_MAC_VER_06)
1434                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1435
1436         return features;
1437 }
1438
1439 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1440                                        netdev_features_t features)
1441 {
1442         u32 rx_config = RTL_R32(tp, RxConfig);
1443
1444         if (features & NETIF_F_RXALL)
1445                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1446         else
1447                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1448
1449         if (rtl_is_8125(tp)) {
1450                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1451                         rx_config |= RX_VLAN_8125;
1452                 else
1453                         rx_config &= ~RX_VLAN_8125;
1454         }
1455
1456         RTL_W32(tp, RxConfig, rx_config);
1457 }
1458
1459 static int rtl8169_set_features(struct net_device *dev,
1460                                 netdev_features_t features)
1461 {
1462         struct rtl8169_private *tp = netdev_priv(dev);
1463
1464         rtl_set_rx_config_features(tp, features);
1465
1466         if (features & NETIF_F_RXCSUM)
1467                 tp->cp_cmd |= RxChkSum;
1468         else
1469                 tp->cp_cmd &= ~RxChkSum;
1470
1471         if (!rtl_is_8125(tp)) {
1472                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1473                         tp->cp_cmd |= RxVlan;
1474                 else
1475                         tp->cp_cmd &= ~RxVlan;
1476         }
1477
1478         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1479         rtl_pci_commit(tp);
1480
1481         return 0;
1482 }
1483
1484 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1485 {
1486         return (skb_vlan_tag_present(skb)) ?
1487                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1488 }
1489
1490 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1491 {
1492         u32 opts2 = le32_to_cpu(desc->opts2);
1493
1494         if (opts2 & RxVlanTag)
1495                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1496 }
1497
1498 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1499                              void *p)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         u32 __iomem *data = tp->mmio_addr;
1503         u32 *dw = p;
1504         int i;
1505
1506         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1507                 memcpy_fromio(dw++, data++, 4);
1508 }
1509
1510 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1511         "tx_packets",
1512         "rx_packets",
1513         "tx_errors",
1514         "rx_errors",
1515         "rx_missed",
1516         "align_errors",
1517         "tx_single_collisions",
1518         "tx_multi_collisions",
1519         "unicast",
1520         "broadcast",
1521         "multicast",
1522         "tx_aborted",
1523         "tx_underrun",
1524 };
1525
1526 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1527 {
1528         switch (sset) {
1529         case ETH_SS_STATS:
1530                 return ARRAY_SIZE(rtl8169_gstrings);
1531         default:
1532                 return -EOPNOTSUPP;
1533         }
1534 }
1535
1536 DECLARE_RTL_COND(rtl_counters_cond)
1537 {
1538         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1539 }
1540
1541 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1542 {
1543         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1544
1545         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1546         rtl_pci_commit(tp);
1547         RTL_W32(tp, CounterAddrLow, cmd);
1548         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1549
1550         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1551 }
1552
1553 static void rtl8169_update_counters(struct rtl8169_private *tp)
1554 {
1555         u8 val = RTL_R8(tp, ChipCmd);
1556
1557         /*
1558          * Some chips are unable to dump tally counters when the receiver
1559          * is disabled. If 0xff chip may be in a PCI power-save state.
1560          */
1561         if (val & CmdRxEnb && val != 0xff)
1562                 rtl8169_do_counters(tp, CounterDump);
1563 }
1564
1565 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1566 {
1567         struct rtl8169_counters *counters = tp->counters;
1568
1569         /*
1570          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1571          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1572          * reset by a power cycle, while the counter values collected by the
1573          * driver are reset at every driver unload/load cycle.
1574          *
1575          * To make sure the HW values returned by @get_stats64 match the SW
1576          * values, we collect the initial values at first open(*) and use them
1577          * as offsets to normalize the values returned by @get_stats64.
1578          *
1579          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1580          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1581          * set at open time by rtl_hw_start.
1582          */
1583
1584         if (tp->tc_offset.inited)
1585                 return;
1586
1587         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1588                 rtl8169_do_counters(tp, CounterReset);
1589         } else {
1590                 rtl8169_update_counters(tp);
1591                 tp->tc_offset.tx_errors = counters->tx_errors;
1592                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1593                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1594                 tp->tc_offset.rx_missed = counters->rx_missed;
1595         }
1596
1597         tp->tc_offset.inited = true;
1598 }
1599
1600 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1601                                       struct ethtool_stats *stats, u64 *data)
1602 {
1603         struct rtl8169_private *tp = netdev_priv(dev);
1604         struct rtl8169_counters *counters;
1605
1606         counters = tp->counters;
1607         rtl8169_update_counters(tp);
1608
1609         data[0] = le64_to_cpu(counters->tx_packets);
1610         data[1] = le64_to_cpu(counters->rx_packets);
1611         data[2] = le64_to_cpu(counters->tx_errors);
1612         data[3] = le32_to_cpu(counters->rx_errors);
1613         data[4] = le16_to_cpu(counters->rx_missed);
1614         data[5] = le16_to_cpu(counters->align_errors);
1615         data[6] = le32_to_cpu(counters->tx_one_collision);
1616         data[7] = le32_to_cpu(counters->tx_multi_collision);
1617         data[8] = le64_to_cpu(counters->rx_unicast);
1618         data[9] = le64_to_cpu(counters->rx_broadcast);
1619         data[10] = le32_to_cpu(counters->rx_multicast);
1620         data[11] = le16_to_cpu(counters->tx_aborted);
1621         data[12] = le16_to_cpu(counters->tx_underun);
1622 }
1623
1624 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1625 {
1626         switch(stringset) {
1627         case ETH_SS_STATS:
1628                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1629                 break;
1630         }
1631 }
1632
1633 /*
1634  * Interrupt coalescing
1635  *
1636  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1637  * >     8169, 8168 and 810x line of chipsets
1638  *
1639  * 8169, 8168, and 8136(810x) serial chipsets support it.
1640  *
1641  * > 2 - the Tx timer unit at gigabit speed
1642  *
1643  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1644  * (0xe0) bit 1 and bit 0.
1645  *
1646  * For 8169
1647  * bit[1:0] \ speed        1000M           100M            10M
1648  * 0 0                     320ns           2.56us          40.96us
1649  * 0 1                     2.56us          20.48us         327.7us
1650  * 1 0                     5.12us          40.96us         655.4us
1651  * 1 1                     10.24us         81.92us         1.31ms
1652  *
1653  * For the other
1654  * bit[1:0] \ speed        1000M           100M            10M
1655  * 0 0                     5us             2.56us          40.96us
1656  * 0 1                     40us            20.48us         327.7us
1657  * 1 0                     80us            40.96us         655.4us
1658  * 1 1                     160us           81.92us         1.31ms
1659  */
1660
1661 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1662 struct rtl_coalesce_info {
1663         u32 speed;
1664         u32 scale_nsecs[4];
1665 };
1666
1667 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1668 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1669
1670 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1671         { SPEED_1000,   COALESCE_DELAY(320) },
1672         { SPEED_100,    COALESCE_DELAY(2560) },
1673         { SPEED_10,     COALESCE_DELAY(40960) },
1674         { 0 },
1675 };
1676
1677 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1678         { SPEED_1000,   COALESCE_DELAY(5000) },
1679         { SPEED_100,    COALESCE_DELAY(2560) },
1680         { SPEED_10,     COALESCE_DELAY(40960) },
1681         { 0 },
1682 };
1683 #undef COALESCE_DELAY
1684
1685 /* get rx/tx scale vector corresponding to current speed */
1686 static const struct rtl_coalesce_info *
1687 rtl_coalesce_info(struct rtl8169_private *tp)
1688 {
1689         const struct rtl_coalesce_info *ci;
1690
1691         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1692                 ci = rtl_coalesce_info_8169;
1693         else
1694                 ci = rtl_coalesce_info_8168_8136;
1695
1696         /* if speed is unknown assume highest one */
1697         if (tp->phydev->speed == SPEED_UNKNOWN)
1698                 return ci;
1699
1700         for (; ci->speed; ci++) {
1701                 if (tp->phydev->speed == ci->speed)
1702                         return ci;
1703         }
1704
1705         return ERR_PTR(-ELNRNG);
1706 }
1707
1708 static int rtl_get_coalesce(struct net_device *dev,
1709                             struct ethtool_coalesce *ec,
1710                             struct kernel_ethtool_coalesce *kernel_coal,
1711                             struct netlink_ext_ack *extack)
1712 {
1713         struct rtl8169_private *tp = netdev_priv(dev);
1714         const struct rtl_coalesce_info *ci;
1715         u32 scale, c_us, c_fr;
1716         u16 intrmit;
1717
1718         if (rtl_is_8125(tp))
1719                 return -EOPNOTSUPP;
1720
1721         memset(ec, 0, sizeof(*ec));
1722
1723         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1724         ci = rtl_coalesce_info(tp);
1725         if (IS_ERR(ci))
1726                 return PTR_ERR(ci);
1727
1728         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1729
1730         intrmit = RTL_R16(tp, IntrMitigate);
1731
1732         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1733         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1734
1735         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1736         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1737         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1738
1739         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1740         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1741
1742         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1743         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1744
1745         return 0;
1746 }
1747
1748 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1749 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1750                                      u16 *cp01)
1751 {
1752         const struct rtl_coalesce_info *ci;
1753         u16 i;
1754
1755         ci = rtl_coalesce_info(tp);
1756         if (IS_ERR(ci))
1757                 return PTR_ERR(ci);
1758
1759         for (i = 0; i < 4; i++) {
1760                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1761                         *cp01 = i;
1762                         return ci->scale_nsecs[i];
1763                 }
1764         }
1765
1766         return -ERANGE;
1767 }
1768
1769 static int rtl_set_coalesce(struct net_device *dev,
1770                             struct ethtool_coalesce *ec,
1771                             struct kernel_ethtool_coalesce *kernel_coal,
1772                             struct netlink_ext_ack *extack)
1773 {
1774         struct rtl8169_private *tp = netdev_priv(dev);
1775         u32 tx_fr = ec->tx_max_coalesced_frames;
1776         u32 rx_fr = ec->rx_max_coalesced_frames;
1777         u32 coal_usec_max, units;
1778         u16 w = 0, cp01 = 0;
1779         int scale;
1780
1781         if (rtl_is_8125(tp))
1782                 return -EOPNOTSUPP;
1783
1784         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1785                 return -ERANGE;
1786
1787         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1788         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1789         if (scale < 0)
1790                 return scale;
1791
1792         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1793          * not only when usecs=0 because of e.g. the following scenario:
1794          *
1795          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1796          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1797          * - then user does `ethtool -C eth0 rx-usecs 100`
1798          *
1799          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1800          * if we want to ignore rx_frames then it has to be set to 0.
1801          */
1802         if (rx_fr == 1)
1803                 rx_fr = 0;
1804         if (tx_fr == 1)
1805                 tx_fr = 0;
1806
1807         /* HW requires time limit to be set if frame limit is set */
1808         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1809             (rx_fr && !ec->rx_coalesce_usecs))
1810                 return -EINVAL;
1811
1812         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1813         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1814
1815         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1816         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1817         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1818         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1819
1820         RTL_W16(tp, IntrMitigate, w);
1821
1822         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1823         if (rtl_is_8168evl_up(tp)) {
1824                 if (!rx_fr && !tx_fr)
1825                         /* disable packet counter */
1826                         tp->cp_cmd |= PktCntrDisable;
1827                 else
1828                         tp->cp_cmd &= ~PktCntrDisable;
1829         }
1830
1831         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1832         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1833         rtl_pci_commit(tp);
1834
1835         return 0;
1836 }
1837
1838 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1839 {
1840         struct rtl8169_private *tp = netdev_priv(dev);
1841
1842         if (!rtl_supports_eee(tp))
1843                 return -EOPNOTSUPP;
1844
1845         return phy_ethtool_get_eee(tp->phydev, data);
1846 }
1847
1848 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1849 {
1850         struct rtl8169_private *tp = netdev_priv(dev);
1851         int ret;
1852
1853         if (!rtl_supports_eee(tp))
1854                 return -EOPNOTSUPP;
1855
1856         ret = phy_ethtool_set_eee(tp->phydev, data);
1857
1858         if (!ret)
1859                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1860                                            MDIO_AN_EEE_ADV);
1861         return ret;
1862 }
1863
1864 static void rtl8169_get_ringparam(struct net_device *dev,
1865                                   struct ethtool_ringparam *data,
1866                                   struct kernel_ethtool_ringparam *kernel_data,
1867                                   struct netlink_ext_ack *extack)
1868 {
1869         data->rx_max_pending = NUM_RX_DESC;
1870         data->rx_pending = NUM_RX_DESC;
1871         data->tx_max_pending = NUM_TX_DESC;
1872         data->tx_pending = NUM_TX_DESC;
1873 }
1874
1875 static void rtl8169_get_pauseparam(struct net_device *dev,
1876                                    struct ethtool_pauseparam *data)
1877 {
1878         struct rtl8169_private *tp = netdev_priv(dev);
1879         bool tx_pause, rx_pause;
1880
1881         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1882
1883         data->autoneg = tp->phydev->autoneg;
1884         data->tx_pause = tx_pause ? 1 : 0;
1885         data->rx_pause = rx_pause ? 1 : 0;
1886 }
1887
1888 static int rtl8169_set_pauseparam(struct net_device *dev,
1889                                   struct ethtool_pauseparam *data)
1890 {
1891         struct rtl8169_private *tp = netdev_priv(dev);
1892
1893         if (dev->mtu > ETH_DATA_LEN)
1894                 return -EOPNOTSUPP;
1895
1896         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1897
1898         return 0;
1899 }
1900
1901 static const struct ethtool_ops rtl8169_ethtool_ops = {
1902         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1903                                      ETHTOOL_COALESCE_MAX_FRAMES,
1904         .get_drvinfo            = rtl8169_get_drvinfo,
1905         .get_regs_len           = rtl8169_get_regs_len,
1906         .get_link               = ethtool_op_get_link,
1907         .get_coalesce           = rtl_get_coalesce,
1908         .set_coalesce           = rtl_set_coalesce,
1909         .get_regs               = rtl8169_get_regs,
1910         .get_wol                = rtl8169_get_wol,
1911         .set_wol                = rtl8169_set_wol,
1912         .get_strings            = rtl8169_get_strings,
1913         .get_sset_count         = rtl8169_get_sset_count,
1914         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1915         .get_ts_info            = ethtool_op_get_ts_info,
1916         .nway_reset             = phy_ethtool_nway_reset,
1917         .get_eee                = rtl8169_get_eee,
1918         .set_eee                = rtl8169_set_eee,
1919         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1920         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1921         .get_ringparam          = rtl8169_get_ringparam,
1922         .get_pauseparam         = rtl8169_get_pauseparam,
1923         .set_pauseparam         = rtl8169_set_pauseparam,
1924 };
1925
1926 static void rtl_enable_eee(struct rtl8169_private *tp)
1927 {
1928         struct phy_device *phydev = tp->phydev;
1929         int adv;
1930
1931         /* respect EEE advertisement the user may have set */
1932         if (tp->eee_adv >= 0)
1933                 adv = tp->eee_adv;
1934         else
1935                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1936
1937         if (adv >= 0)
1938                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1939 }
1940
1941 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1942 {
1943         /*
1944          * The driver currently handles the 8168Bf and the 8168Be identically
1945          * but they can be identified more specifically through the test below
1946          * if needed:
1947          *
1948          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1949          *
1950          * Same thing for the 8101Eb and the 8101Ec:
1951          *
1952          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1953          */
1954         static const struct rtl_mac_info {
1955                 u16 mask;
1956                 u16 val;
1957                 enum mac_version ver;
1958         } mac_info[] = {
1959                 /* 8125B family. */
1960                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1961
1962                 /* 8125A family. */
1963                 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
1964                 /* It seems only XID 609 made it to the mass market.
1965                  * { 0x7cf, 0x608,      RTL_GIGA_MAC_VER_60 },
1966                  * { 0x7c8, 0x608,      RTL_GIGA_MAC_VER_61 },
1967                  */
1968
1969                 /* RTL8117 */
1970                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
1971                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1972
1973                 /* 8168EP family. */
1974                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1975                 /* It seems this chip version never made it to
1976                  * the wild. Let's disable detection.
1977                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
1978                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
1979                  */
1980
1981                 /* 8168H family. */
1982                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1983                 /* It seems this chip version never made it to
1984                  * the wild. Let's disable detection.
1985                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
1986                  */
1987
1988                 /* 8168G family. */
1989                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1990                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1991                 /* It seems this chip version never made it to
1992                  * the wild. Let's disable detection.
1993                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
1994                  */
1995                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1996
1997                 /* 8168F family. */
1998                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1999                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2000                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2001
2002                 /* 8168E family. */
2003                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2004                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2005                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2006
2007                 /* 8168D family. */
2008                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2009                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2010
2011                 /* 8168DP family. */
2012                 /* It seems this early RTL8168dp version never made it to
2013                  * the wild. Support has been removed.
2014                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2015                  */
2016                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2017                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2018
2019                 /* 8168C family. */
2020                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2021                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2022                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2023                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2024                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2025                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2026                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2027
2028                 /* 8168B family. */
2029                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2030                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2031
2032                 /* 8101 family. */
2033                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2034                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2035                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2036                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2037                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2038                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2039                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2040                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2041                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2042                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2043                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2044                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2045
2046                 /* 8110 family. */
2047                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2048                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2049                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2050                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2051                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2052
2053                 /* Catch-all */
2054                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2055         };
2056         const struct rtl_mac_info *p = mac_info;
2057         enum mac_version ver;
2058
2059         while ((xid & p->mask) != p->val)
2060                 p++;
2061         ver = p->ver;
2062
2063         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2064                 if (ver == RTL_GIGA_MAC_VER_42)
2065                         ver = RTL_GIGA_MAC_VER_43;
2066                 else if (ver == RTL_GIGA_MAC_VER_46)
2067                         ver = RTL_GIGA_MAC_VER_48;
2068         }
2069
2070         return ver;
2071 }
2072
2073 static void rtl_release_firmware(struct rtl8169_private *tp)
2074 {
2075         if (tp->rtl_fw) {
2076                 rtl_fw_release_firmware(tp->rtl_fw);
2077                 kfree(tp->rtl_fw);
2078                 tp->rtl_fw = NULL;
2079         }
2080 }
2081
2082 void r8169_apply_firmware(struct rtl8169_private *tp)
2083 {
2084         int val;
2085
2086         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2087         if (tp->rtl_fw) {
2088                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2089                 /* At least one firmware doesn't reset tp->ocp_base. */
2090                 tp->ocp_base = OCP_STD_PHY_BASE;
2091
2092                 /* PHY soft reset may still be in progress */
2093                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2094                                       !(val & BMCR_RESET),
2095                                       50000, 600000, true);
2096         }
2097 }
2098
2099 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2100 {
2101         /* Adjust EEE LED frequency */
2102         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2103                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2104
2105         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2106 }
2107
2108 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2109 {
2110         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2111         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2112 }
2113
2114 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2115 {
2116         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2117 }
2118
2119 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2120 {
2121         rtl8125_set_eee_txidle_timer(tp);
2122         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2123 }
2124
2125 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2126 {
2127         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2128         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2129         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2130         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2131 }
2132
2133 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2134 {
2135         u16 data1, data2, ioffset;
2136
2137         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2138         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2139         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2140
2141         ioffset = (data2 >> 1) & 0x7ff8;
2142         ioffset |= data2 & 0x0007;
2143         if (data1 & BIT(7))
2144                 ioffset |= BIT(15);
2145
2146         return ioffset;
2147 }
2148
2149 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2150 {
2151         set_bit(flag, tp->wk.flags);
2152         schedule_work(&tp->wk.work);
2153 }
2154
2155 static void rtl8169_init_phy(struct rtl8169_private *tp)
2156 {
2157         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2158
2159         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2160                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2161                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2162                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2163                 RTL_W8(tp, 0x82, 0x01);
2164         }
2165
2166         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2167             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2168             tp->pci_dev->subsystem_device == 0xe000)
2169                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2170
2171         /* We may have called phy_speed_down before */
2172         phy_speed_up(tp->phydev);
2173
2174         if (rtl_supports_eee(tp))
2175                 rtl_enable_eee(tp);
2176
2177         genphy_soft_reset(tp->phydev);
2178 }
2179
2180 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2181 {
2182         rtl_unlock_config_regs(tp);
2183
2184         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2185         rtl_pci_commit(tp);
2186
2187         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2188         rtl_pci_commit(tp);
2189
2190         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2191                 rtl_rar_exgmac_set(tp, addr);
2192
2193         rtl_lock_config_regs(tp);
2194 }
2195
2196 static int rtl_set_mac_address(struct net_device *dev, void *p)
2197 {
2198         struct rtl8169_private *tp = netdev_priv(dev);
2199         int ret;
2200
2201         ret = eth_mac_addr(dev, p);
2202         if (ret)
2203                 return ret;
2204
2205         rtl_rar_set(tp, dev->dev_addr);
2206
2207         return 0;
2208 }
2209
2210 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2211 {
2212         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2213                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2214                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2215 }
2216
2217 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2218 {
2219         if (tp->dash_type != RTL_DASH_NONE)
2220                 return;
2221
2222         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2223             tp->mac_version == RTL_GIGA_MAC_VER_33)
2224                 rtl_ephy_write(tp, 0x19, 0xff64);
2225
2226         if (device_may_wakeup(tp_to_dev(tp))) {
2227                 phy_speed_down(tp->phydev, false);
2228                 rtl_wol_enable_rx(tp);
2229         }
2230 }
2231
2232 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2233 {
2234         switch (tp->mac_version) {
2235         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2236         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2237                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2238                 break;
2239         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2240         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2241         case RTL_GIGA_MAC_VER_38:
2242                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2243                 break;
2244         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2245                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2246                 break;
2247         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2248                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2249                 break;
2250         default:
2251                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2252                 break;
2253         }
2254 }
2255
2256 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2257 {
2258         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2259 }
2260
2261 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2262 {
2263         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2264         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2265 }
2266
2267 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2268 {
2269         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2270         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2271 }
2272
2273 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2274 {
2275         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2276 }
2277
2278 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2279 {
2280         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2281 }
2282
2283 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2284 {
2285         RTL_W8(tp, MaxTxPacketSize, 0x24);
2286         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2287         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2288 }
2289
2290 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2291 {
2292         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2293         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2294         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2295 }
2296
2297 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2298 {
2299         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2300 }
2301
2302 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2303 {
2304         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2305 }
2306
2307 static void rtl_jumbo_config(struct rtl8169_private *tp)
2308 {
2309         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2310         int readrq = 4096;
2311
2312         rtl_unlock_config_regs(tp);
2313         switch (tp->mac_version) {
2314         case RTL_GIGA_MAC_VER_17:
2315                 if (jumbo) {
2316                         readrq = 512;
2317                         r8168b_1_hw_jumbo_enable(tp);
2318                 } else {
2319                         r8168b_1_hw_jumbo_disable(tp);
2320                 }
2321                 break;
2322         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2323                 if (jumbo) {
2324                         readrq = 512;
2325                         r8168c_hw_jumbo_enable(tp);
2326                 } else {
2327                         r8168c_hw_jumbo_disable(tp);
2328                 }
2329                 break;
2330         case RTL_GIGA_MAC_VER_28:
2331                 if (jumbo)
2332                         r8168dp_hw_jumbo_enable(tp);
2333                 else
2334                         r8168dp_hw_jumbo_disable(tp);
2335                 break;
2336         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2337                 if (jumbo)
2338                         r8168e_hw_jumbo_enable(tp);
2339                 else
2340                         r8168e_hw_jumbo_disable(tp);
2341                 break;
2342         default:
2343                 break;
2344         }
2345         rtl_lock_config_regs(tp);
2346
2347         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2348                 pcie_set_readrq(tp->pci_dev, readrq);
2349
2350         /* Chip doesn't support pause in jumbo mode */
2351         if (jumbo) {
2352                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2353                                    tp->phydev->advertising);
2354                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2355                                    tp->phydev->advertising);
2356                 phy_start_aneg(tp->phydev);
2357         }
2358 }
2359
2360 DECLARE_RTL_COND(rtl_chipcmd_cond)
2361 {
2362         return RTL_R8(tp, ChipCmd) & CmdReset;
2363 }
2364
2365 static void rtl_hw_reset(struct rtl8169_private *tp)
2366 {
2367         RTL_W8(tp, ChipCmd, CmdReset);
2368
2369         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2370 }
2371
2372 static void rtl_request_firmware(struct rtl8169_private *tp)
2373 {
2374         struct rtl_fw *rtl_fw;
2375
2376         /* firmware loaded already or no firmware available */
2377         if (tp->rtl_fw || !tp->fw_name)
2378                 return;
2379
2380         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2381         if (!rtl_fw)
2382                 return;
2383
2384         rtl_fw->phy_write = rtl_writephy;
2385         rtl_fw->phy_read = rtl_readphy;
2386         rtl_fw->mac_mcu_write = mac_mcu_write;
2387         rtl_fw->mac_mcu_read = mac_mcu_read;
2388         rtl_fw->fw_name = tp->fw_name;
2389         rtl_fw->dev = tp_to_dev(tp);
2390
2391         if (rtl_fw_request_firmware(rtl_fw))
2392                 kfree(rtl_fw);
2393         else
2394                 tp->rtl_fw = rtl_fw;
2395 }
2396
2397 static void rtl_rx_close(struct rtl8169_private *tp)
2398 {
2399         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2400 }
2401
2402 DECLARE_RTL_COND(rtl_npq_cond)
2403 {
2404         return RTL_R8(tp, TxPoll) & NPQ;
2405 }
2406
2407 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2408 {
2409         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2410 }
2411
2412 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2413 {
2414         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2415 }
2416
2417 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2418 {
2419         /* IntrMitigate has new functionality on RTL8125 */
2420         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2421 }
2422
2423 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2424 {
2425         switch (tp->mac_version) {
2426         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2427                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2428                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2429                 break;
2430         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2431                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2432                 break;
2433         case RTL_GIGA_MAC_VER_63:
2434                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2435                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2436                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2437                 break;
2438         default:
2439                 break;
2440         }
2441 }
2442
2443 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2444 {
2445         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2446         fsleep(2000);
2447         rtl_wait_txrx_fifo_empty(tp);
2448 }
2449
2450 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2451 {
2452         u32 val = TX_DMA_BURST << TxDMAShift |
2453                   InterFrameGap << TxInterFrameGapShift;
2454
2455         if (rtl_is_8168evl_up(tp))
2456                 val |= TXCFG_AUTO_FIFO;
2457
2458         RTL_W32(tp, TxConfig, val);
2459 }
2460
2461 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2462 {
2463         /* Low hurts. Let's disable the filtering. */
2464         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2465 }
2466
2467 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2468 {
2469         /*
2470          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2471          * register to be written before TxDescAddrLow to work.
2472          * Switching from MMIO to I/O access fixes the issue as well.
2473          */
2474         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2475         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2476         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2477         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2478 }
2479
2480 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2481 {
2482         u32 val;
2483
2484         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2485                 val = 0x000fff00;
2486         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2487                 val = 0x00ffff00;
2488         else
2489                 return;
2490
2491         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2492                 val |= 0xff;
2493
2494         RTL_W32(tp, 0x7c, val);
2495 }
2496
2497 static void rtl_set_rx_mode(struct net_device *dev)
2498 {
2499         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2500         /* Multicast hash filter */
2501         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2502         struct rtl8169_private *tp = netdev_priv(dev);
2503         u32 tmp;
2504
2505         if (dev->flags & IFF_PROMISC) {
2506                 rx_mode |= AcceptAllPhys;
2507         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2508                    dev->flags & IFF_ALLMULTI ||
2509                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2510                 /* accept all multicasts */
2511         } else if (netdev_mc_empty(dev)) {
2512                 rx_mode &= ~AcceptMulticast;
2513         } else {
2514                 struct netdev_hw_addr *ha;
2515
2516                 mc_filter[1] = mc_filter[0] = 0;
2517                 netdev_for_each_mc_addr(ha, dev) {
2518                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2519                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2520                 }
2521
2522                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2523                         tmp = mc_filter[0];
2524                         mc_filter[0] = swab32(mc_filter[1]);
2525                         mc_filter[1] = swab32(tmp);
2526                 }
2527         }
2528
2529         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2530         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2531
2532         tmp = RTL_R32(tp, RxConfig);
2533         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2534 }
2535
2536 DECLARE_RTL_COND(rtl_csiar_cond)
2537 {
2538         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2539 }
2540
2541 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2542 {
2543         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2544
2545         RTL_W32(tp, CSIDR, value);
2546         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2547                 CSIAR_BYTE_ENABLE | func << 16);
2548
2549         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2550 }
2551
2552 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2553 {
2554         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2555
2556         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2557                 CSIAR_BYTE_ENABLE);
2558
2559         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2560                 RTL_R32(tp, CSIDR) : ~0;
2561 }
2562
2563 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2564 {
2565         struct pci_dev *pdev = tp->pci_dev;
2566         u32 csi;
2567
2568         /* According to Realtek the value at config space address 0x070f
2569          * controls the L0s/L1 entrance latency. We try standard ECAM access
2570          * first and if it fails fall back to CSI.
2571          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2572          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2573          */
2574         if (pdev->cfg_size > 0x070f &&
2575             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2576                 return;
2577
2578         netdev_notice_once(tp->dev,
2579                 "No native access to PCI extended config space, falling back to CSI\n");
2580         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2581         rtl_csi_write(tp, 0x070c, csi | val << 24);
2582 }
2583
2584 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2585 {
2586         /* L0 7us, L1 16us */
2587         rtl_set_aspm_entry_latency(tp, 0x27);
2588 }
2589
2590 struct ephy_info {
2591         unsigned int offset;
2592         u16 mask;
2593         u16 bits;
2594 };
2595
2596 static void __rtl_ephy_init(struct rtl8169_private *tp,
2597                             const struct ephy_info *e, int len)
2598 {
2599         u16 w;
2600
2601         while (len-- > 0) {
2602                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2603                 rtl_ephy_write(tp, e->offset, w);
2604                 e++;
2605         }
2606 }
2607
2608 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2609
2610 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2611 {
2612         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2613                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2614 }
2615
2616 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2617 {
2618         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2619                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2620 }
2621
2622 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2623 {
2624         /* work around an issue when PCI reset occurs during L2/L3 state */
2625         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2626 }
2627
2628 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2629 {
2630         /* Bits control which events trigger ASPM L1 exit:
2631          * Bit 12: rxdv
2632          * Bit 11: ltr_msg
2633          * Bit 10: txdma_poll
2634          * Bit  9: xadm
2635          * Bit  8: pktavi
2636          * Bit  7: txpla
2637          */
2638         switch (tp->mac_version) {
2639         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2640                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2641                 break;
2642         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2643                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2644                 break;
2645         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2646                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2647                 break;
2648         default:
2649                 break;
2650         }
2651 }
2652
2653 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2654 {
2655         switch (tp->mac_version) {
2656         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2657                 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2658                 break;
2659         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2660                 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2661                 break;
2662         default:
2663                 break;
2664         }
2665 }
2666
2667 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2668 {
2669         /* Don't enable ASPM in the chip if OS can't control ASPM */
2670         if (enable && tp->aspm_manageable) {
2671                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2672                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2673
2674                 switch (tp->mac_version) {
2675                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2676                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2677                         /* reset ephy tx/rx disable timer */
2678                         r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2679                         /* chip can trigger L1.2 */
2680                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2681                         break;
2682                 default:
2683                         break;
2684                 }
2685         } else {
2686                 switch (tp->mac_version) {
2687                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2688                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2689                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2690                         break;
2691                 default:
2692                         break;
2693                 }
2694
2695                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2696                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2697         }
2698
2699         udelay(10);
2700 }
2701
2702 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2703                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2704 {
2705         /* Usage of dynamic vs. static FIFO is controlled by bit
2706          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2707          */
2708         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2709         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2710 }
2711
2712 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2713                                           u8 low, u8 high)
2714 {
2715         /* FIFO thresholds for pause flow control */
2716         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2717         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2718 }
2719
2720 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2721 {
2722         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2723 }
2724
2725 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2726 {
2727         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2728
2729         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2730
2731         rtl_disable_clock_request(tp);
2732 }
2733
2734 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2735 {
2736         static const struct ephy_info e_info_8168cp[] = {
2737                 { 0x01, 0,      0x0001 },
2738                 { 0x02, 0x0800, 0x1000 },
2739                 { 0x03, 0,      0x0042 },
2740                 { 0x06, 0x0080, 0x0000 },
2741                 { 0x07, 0,      0x2000 }
2742         };
2743
2744         rtl_set_def_aspm_entry_latency(tp);
2745
2746         rtl_ephy_init(tp, e_info_8168cp);
2747
2748         __rtl_hw_start_8168cp(tp);
2749 }
2750
2751 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2752 {
2753         rtl_set_def_aspm_entry_latency(tp);
2754
2755         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2756 }
2757
2758 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2759 {
2760         rtl_set_def_aspm_entry_latency(tp);
2761
2762         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2763
2764         /* Magic. */
2765         RTL_W8(tp, DBG_REG, 0x20);
2766 }
2767
2768 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2769 {
2770         static const struct ephy_info e_info_8168c_1[] = {
2771                 { 0x02, 0x0800, 0x1000 },
2772                 { 0x03, 0,      0x0002 },
2773                 { 0x06, 0x0080, 0x0000 }
2774         };
2775
2776         rtl_set_def_aspm_entry_latency(tp);
2777
2778         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2779
2780         rtl_ephy_init(tp, e_info_8168c_1);
2781
2782         __rtl_hw_start_8168cp(tp);
2783 }
2784
2785 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2786 {
2787         static const struct ephy_info e_info_8168c_2[] = {
2788                 { 0x01, 0,      0x0001 },
2789                 { 0x03, 0x0400, 0x0020 }
2790         };
2791
2792         rtl_set_def_aspm_entry_latency(tp);
2793
2794         rtl_ephy_init(tp, e_info_8168c_2);
2795
2796         __rtl_hw_start_8168cp(tp);
2797 }
2798
2799 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2800 {
2801         rtl_set_def_aspm_entry_latency(tp);
2802
2803         __rtl_hw_start_8168cp(tp);
2804 }
2805
2806 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2807 {
2808         rtl_set_def_aspm_entry_latency(tp);
2809
2810         rtl_disable_clock_request(tp);
2811 }
2812
2813 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2814 {
2815         static const struct ephy_info e_info_8168d_4[] = {
2816                 { 0x0b, 0x0000, 0x0048 },
2817                 { 0x19, 0x0020, 0x0050 },
2818                 { 0x0c, 0x0100, 0x0020 },
2819                 { 0x10, 0x0004, 0x0000 },
2820         };
2821
2822         rtl_set_def_aspm_entry_latency(tp);
2823
2824         rtl_ephy_init(tp, e_info_8168d_4);
2825
2826         rtl_enable_clock_request(tp);
2827 }
2828
2829 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2830 {
2831         static const struct ephy_info e_info_8168e_1[] = {
2832                 { 0x00, 0x0200, 0x0100 },
2833                 { 0x00, 0x0000, 0x0004 },
2834                 { 0x06, 0x0002, 0x0001 },
2835                 { 0x06, 0x0000, 0x0030 },
2836                 { 0x07, 0x0000, 0x2000 },
2837                 { 0x00, 0x0000, 0x0020 },
2838                 { 0x03, 0x5800, 0x2000 },
2839                 { 0x03, 0x0000, 0x0001 },
2840                 { 0x01, 0x0800, 0x1000 },
2841                 { 0x07, 0x0000, 0x4000 },
2842                 { 0x1e, 0x0000, 0x2000 },
2843                 { 0x19, 0xffff, 0xfe6c },
2844                 { 0x0a, 0x0000, 0x0040 }
2845         };
2846
2847         rtl_set_def_aspm_entry_latency(tp);
2848
2849         rtl_ephy_init(tp, e_info_8168e_1);
2850
2851         rtl_disable_clock_request(tp);
2852
2853         /* Reset tx FIFO pointer */
2854         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2855         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2856
2857         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2858 }
2859
2860 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2861 {
2862         static const struct ephy_info e_info_8168e_2[] = {
2863                 { 0x09, 0x0000, 0x0080 },
2864                 { 0x19, 0x0000, 0x0224 },
2865                 { 0x00, 0x0000, 0x0004 },
2866                 { 0x0c, 0x3df0, 0x0200 },
2867         };
2868
2869         rtl_set_def_aspm_entry_latency(tp);
2870
2871         rtl_ephy_init(tp, e_info_8168e_2);
2872
2873         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2874         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2875         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2876         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2877         rtl_reset_packet_filter(tp);
2878         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2879         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2880         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2881
2882         rtl_disable_clock_request(tp);
2883
2884         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2885
2886         rtl8168_config_eee_mac(tp);
2887
2888         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2889         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2890         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2891
2892         rtl_hw_aspm_clkreq_enable(tp, true);
2893 }
2894
2895 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2896 {
2897         rtl_set_def_aspm_entry_latency(tp);
2898
2899         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2900         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2901         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2902         rtl_reset_packet_filter(tp);
2903         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2904         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2905         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2906         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2907
2908         rtl_disable_clock_request(tp);
2909
2910         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2911         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2912         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2913         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2914
2915         rtl8168_config_eee_mac(tp);
2916 }
2917
2918 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2919 {
2920         static const struct ephy_info e_info_8168f_1[] = {
2921                 { 0x06, 0x00c0, 0x0020 },
2922                 { 0x08, 0x0001, 0x0002 },
2923                 { 0x09, 0x0000, 0x0080 },
2924                 { 0x19, 0x0000, 0x0224 },
2925                 { 0x00, 0x0000, 0x0008 },
2926                 { 0x0c, 0x3df0, 0x0200 },
2927         };
2928
2929         rtl_hw_start_8168f(tp);
2930
2931         rtl_ephy_init(tp, e_info_8168f_1);
2932 }
2933
2934 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2935 {
2936         static const struct ephy_info e_info_8168f_1[] = {
2937                 { 0x06, 0x00c0, 0x0020 },
2938                 { 0x0f, 0xffff, 0x5200 },
2939                 { 0x19, 0x0000, 0x0224 },
2940                 { 0x00, 0x0000, 0x0008 },
2941                 { 0x0c, 0x3df0, 0x0200 },
2942         };
2943
2944         rtl_hw_start_8168f(tp);
2945         rtl_pcie_state_l2l3_disable(tp);
2946
2947         rtl_ephy_init(tp, e_info_8168f_1);
2948 }
2949
2950 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2951 {
2952         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2953         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2954
2955         rtl_set_def_aspm_entry_latency(tp);
2956
2957         rtl_reset_packet_filter(tp);
2958         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2959
2960         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2961
2962         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2963         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2964
2965         rtl8168_config_eee_mac(tp);
2966
2967         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2968         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2969
2970         rtl_pcie_state_l2l3_disable(tp);
2971 }
2972
2973 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2974 {
2975         static const struct ephy_info e_info_8168g_1[] = {
2976                 { 0x00, 0x0008, 0x0000 },
2977                 { 0x0c, 0x3ff0, 0x0820 },
2978                 { 0x1e, 0x0000, 0x0001 },
2979                 { 0x19, 0x8000, 0x0000 }
2980         };
2981
2982         rtl_hw_start_8168g(tp);
2983
2984         /* disable aspm and clock request before access ephy */
2985         rtl_hw_aspm_clkreq_enable(tp, false);
2986         rtl_ephy_init(tp, e_info_8168g_1);
2987         rtl_hw_aspm_clkreq_enable(tp, true);
2988 }
2989
2990 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2991 {
2992         static const struct ephy_info e_info_8168g_2[] = {
2993                 { 0x00, 0x0008, 0x0000 },
2994                 { 0x0c, 0x3ff0, 0x0820 },
2995                 { 0x19, 0xffff, 0x7c00 },
2996                 { 0x1e, 0xffff, 0x20eb },
2997                 { 0x0d, 0xffff, 0x1666 },
2998                 { 0x00, 0xffff, 0x10a3 },
2999                 { 0x06, 0xffff, 0xf050 },
3000                 { 0x04, 0x0000, 0x0010 },
3001                 { 0x1d, 0x4000, 0x0000 },
3002         };
3003
3004         rtl_hw_start_8168g(tp);
3005
3006         /* disable aspm and clock request before access ephy */
3007         rtl_hw_aspm_clkreq_enable(tp, false);
3008         rtl_ephy_init(tp, e_info_8168g_2);
3009 }
3010
3011 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3012 {
3013         static const struct ephy_info e_info_8411_2[] = {
3014                 { 0x00, 0x0008, 0x0000 },
3015                 { 0x0c, 0x37d0, 0x0820 },
3016                 { 0x1e, 0x0000, 0x0001 },
3017                 { 0x19, 0x8021, 0x0000 },
3018                 { 0x1e, 0x0000, 0x2000 },
3019                 { 0x0d, 0x0100, 0x0200 },
3020                 { 0x00, 0x0000, 0x0080 },
3021                 { 0x06, 0x0000, 0x0010 },
3022                 { 0x04, 0x0000, 0x0010 },
3023                 { 0x1d, 0x0000, 0x4000 },
3024         };
3025
3026         rtl_hw_start_8168g(tp);
3027
3028         /* disable aspm and clock request before access ephy */
3029         rtl_hw_aspm_clkreq_enable(tp, false);
3030         rtl_ephy_init(tp, e_info_8411_2);
3031
3032         /* The following Realtek-provided magic fixes an issue with the RX unit
3033          * getting confused after the PHY having been powered-down.
3034          */
3035         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3036         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3037         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3038         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3039         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3040         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3041         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3042         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3043         mdelay(3);
3044         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3045
3046         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3047         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3048         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3049         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3050         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3051         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3052         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3053         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3054         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3055         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3056         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3057         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3058         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3059         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3060         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3061         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3062         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3063         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3064         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3065         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3066         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3067         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3068         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3069         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3070         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3071         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3072         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3073         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3074         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3075         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3076         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3077         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3078         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3079         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3080         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3081         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3082         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3083         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3084         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3085         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3086         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3087         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3088         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3089         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3090         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3091         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3092         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3093         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3094         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3095         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3096         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3097         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3098         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3099         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3100         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3101         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3102         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3103         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3104         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3105         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3106         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3107         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3108         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3109         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3110         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3111         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3112         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3113         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3114         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3115         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3116         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3117         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3118         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3119         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3120         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3121         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3122         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3123         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3124         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3125         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3126         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3127         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3128         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3129         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3130         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3131         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3132         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3133         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3134         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3135         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3136         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3137         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3138         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3139         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3140         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3141         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3142         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3143         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3144         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3145         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3146         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3147         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3148         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3149         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3150         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3151         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3152         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3153         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3154         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3155         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3156         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3157
3158         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3159
3160         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3161         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3162         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3163         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3164         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3165         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3166         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3167
3168         rtl_hw_aspm_clkreq_enable(tp, true);
3169 }
3170
3171 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3172 {
3173         static const struct ephy_info e_info_8168h_1[] = {
3174                 { 0x1e, 0x0800, 0x0001 },
3175                 { 0x1d, 0x0000, 0x0800 },
3176                 { 0x05, 0xffff, 0x2089 },
3177                 { 0x06, 0xffff, 0x5881 },
3178                 { 0x04, 0xffff, 0x854a },
3179                 { 0x01, 0xffff, 0x068b }
3180         };
3181         int rg_saw_cnt;
3182
3183         /* disable aspm and clock request before access ephy */
3184         rtl_hw_aspm_clkreq_enable(tp, false);
3185         rtl_ephy_init(tp, e_info_8168h_1);
3186
3187         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3188         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3189
3190         rtl_set_def_aspm_entry_latency(tp);
3191
3192         rtl_reset_packet_filter(tp);
3193
3194         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3195
3196         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3197
3198         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3199
3200         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3201         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3202
3203         rtl8168_config_eee_mac(tp);
3204
3205         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3206         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3207
3208         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3209
3210         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3211
3212         rtl_pcie_state_l2l3_disable(tp);
3213
3214         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3215         if (rg_saw_cnt > 0) {
3216                 u16 sw_cnt_1ms_ini;
3217
3218                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3219                 sw_cnt_1ms_ini &= 0x0fff;
3220                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3221         }
3222
3223         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3224         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3225         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3226         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3227
3228         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3229         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3230         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3231         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3232
3233         rtl_hw_aspm_clkreq_enable(tp, true);
3234 }
3235
3236 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3237 {
3238         rtl8168ep_stop_cmac(tp);
3239
3240         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3241         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3242
3243         rtl_set_def_aspm_entry_latency(tp);
3244
3245         rtl_reset_packet_filter(tp);
3246
3247         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3248
3249         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3250
3251         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3252         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3253
3254         rtl8168_config_eee_mac(tp);
3255
3256         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3257
3258         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3259
3260         rtl_pcie_state_l2l3_disable(tp);
3261 }
3262
3263 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3264 {
3265         static const struct ephy_info e_info_8168ep_3[] = {
3266                 { 0x00, 0x0000, 0x0080 },
3267                 { 0x0d, 0x0100, 0x0200 },
3268                 { 0x19, 0x8021, 0x0000 },
3269                 { 0x1e, 0x0000, 0x2000 },
3270         };
3271
3272         /* disable aspm and clock request before access ephy */
3273         rtl_hw_aspm_clkreq_enable(tp, false);
3274         rtl_ephy_init(tp, e_info_8168ep_3);
3275
3276         rtl_hw_start_8168ep(tp);
3277
3278         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3279         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3280
3281         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3282         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3283         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3284
3285         rtl_hw_aspm_clkreq_enable(tp, true);
3286 }
3287
3288 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3289 {
3290         static const struct ephy_info e_info_8117[] = {
3291                 { 0x19, 0x0040, 0x1100 },
3292                 { 0x59, 0x0040, 0x1100 },
3293         };
3294         int rg_saw_cnt;
3295
3296         rtl8168ep_stop_cmac(tp);
3297
3298         /* disable aspm and clock request before access ephy */
3299         rtl_hw_aspm_clkreq_enable(tp, false);
3300         rtl_ephy_init(tp, e_info_8117);
3301
3302         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3303         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3304
3305         rtl_set_def_aspm_entry_latency(tp);
3306
3307         rtl_reset_packet_filter(tp);
3308
3309         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3310
3311         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3312
3313         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3314
3315         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3316         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3317
3318         rtl8168_config_eee_mac(tp);
3319
3320         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3321         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3322
3323         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3324
3325         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3326
3327         rtl_pcie_state_l2l3_disable(tp);
3328
3329         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3330         if (rg_saw_cnt > 0) {
3331                 u16 sw_cnt_1ms_ini;
3332
3333                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3334                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3335         }
3336
3337         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3338         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3339         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3340         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3341
3342         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3343         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3344         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3345         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3346
3347         /* firmware is for MAC only */
3348         r8169_apply_firmware(tp);
3349
3350         rtl_hw_aspm_clkreq_enable(tp, true);
3351 }
3352
3353 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3354 {
3355         static const struct ephy_info e_info_8102e_1[] = {
3356                 { 0x01, 0, 0x6e65 },
3357                 { 0x02, 0, 0x091f },
3358                 { 0x03, 0, 0xc2f9 },
3359                 { 0x06, 0, 0xafb5 },
3360                 { 0x07, 0, 0x0e00 },
3361                 { 0x19, 0, 0xec80 },
3362                 { 0x01, 0, 0x2e65 },
3363                 { 0x01, 0, 0x6e65 }
3364         };
3365         u8 cfg1;
3366
3367         rtl_set_def_aspm_entry_latency(tp);
3368
3369         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3370
3371         RTL_W8(tp, Config1,
3372                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3373         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3374
3375         cfg1 = RTL_R8(tp, Config1);
3376         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3377                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3378
3379         rtl_ephy_init(tp, e_info_8102e_1);
3380 }
3381
3382 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3383 {
3384         rtl_set_def_aspm_entry_latency(tp);
3385
3386         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3387         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3388 }
3389
3390 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3391 {
3392         rtl_hw_start_8102e_2(tp);
3393
3394         rtl_ephy_write(tp, 0x03, 0xc2f9);
3395 }
3396
3397 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3398 {
3399         static const struct ephy_info e_info_8401[] = {
3400                 { 0x01, 0xffff, 0x6fe5 },
3401                 { 0x03, 0xffff, 0x0599 },
3402                 { 0x06, 0xffff, 0xaf25 },
3403                 { 0x07, 0xffff, 0x8e68 },
3404         };
3405
3406         rtl_ephy_init(tp, e_info_8401);
3407         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3408 }
3409
3410 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3411 {
3412         static const struct ephy_info e_info_8105e_1[] = {
3413                 { 0x07, 0, 0x4000 },
3414                 { 0x19, 0, 0x0200 },
3415                 { 0x19, 0, 0x0020 },
3416                 { 0x1e, 0, 0x2000 },
3417                 { 0x03, 0, 0x0001 },
3418                 { 0x19, 0, 0x0100 },
3419                 { 0x19, 0, 0x0004 },
3420                 { 0x0a, 0, 0x0020 }
3421         };
3422
3423         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3424         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3425
3426         /* Disable Early Tally Counter */
3427         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3428
3429         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3430         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3431
3432         rtl_ephy_init(tp, e_info_8105e_1);
3433
3434         rtl_pcie_state_l2l3_disable(tp);
3435 }
3436
3437 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3438 {
3439         rtl_hw_start_8105e_1(tp);
3440         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3441 }
3442
3443 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3444 {
3445         static const struct ephy_info e_info_8402[] = {
3446                 { 0x19, 0xffff, 0xff64 },
3447                 { 0x1e, 0, 0x4000 }
3448         };
3449
3450         rtl_set_def_aspm_entry_latency(tp);
3451
3452         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3453         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3454
3455         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3456
3457         rtl_ephy_init(tp, e_info_8402);
3458
3459         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3460         rtl_reset_packet_filter(tp);
3461         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3462         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3463         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3464
3465         /* disable EEE */
3466         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3467
3468         rtl_pcie_state_l2l3_disable(tp);
3469 }
3470
3471 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3472 {
3473         rtl_hw_aspm_clkreq_enable(tp, false);
3474
3475         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3476         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3477
3478         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3479         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3480         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3481
3482         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3483         rtl_set_aspm_entry_latency(tp, 0x2f);
3484
3485         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3486
3487         /* disable EEE */
3488         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3489
3490         rtl_pcie_state_l2l3_disable(tp);
3491         rtl_hw_aspm_clkreq_enable(tp, true);
3492 }
3493
3494 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3495 {
3496         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3497 }
3498
3499 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3500 {
3501         rtl_pcie_state_l2l3_disable(tp);
3502
3503         RTL_W16(tp, 0x382, 0x221b);
3504         RTL_W8(tp, 0x4500, 0);
3505         RTL_W16(tp, 0x4800, 0);
3506
3507         /* disable UPS */
3508         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3509
3510         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3511
3512         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3513         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3514
3515         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3516         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3517         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3518
3519         /* disable new tx descriptor format */
3520         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3521
3522         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3523                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3524         else
3525                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3526
3527         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3528                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3529         else
3530                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3531
3532         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3533         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3534         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3535         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3536         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3537         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3538         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3539         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3540         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3541
3542         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3543         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3544         udelay(1);
3545         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3546         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3547
3548         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3549
3550         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3551
3552         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3553                 rtl8125b_config_eee_mac(tp);
3554         else
3555                 rtl8125a_config_eee_mac(tp);
3556
3557         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3558         udelay(10);
3559 }
3560
3561 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3562 {
3563         static const struct ephy_info e_info_8125a_2[] = {
3564                 { 0x04, 0xffff, 0xd000 },
3565                 { 0x0a, 0xffff, 0x8653 },
3566                 { 0x23, 0xffff, 0xab66 },
3567                 { 0x20, 0xffff, 0x9455 },
3568                 { 0x21, 0xffff, 0x99ff },
3569                 { 0x29, 0xffff, 0xfe04 },
3570
3571                 { 0x44, 0xffff, 0xd000 },
3572                 { 0x4a, 0xffff, 0x8653 },
3573                 { 0x63, 0xffff, 0xab66 },
3574                 { 0x60, 0xffff, 0x9455 },
3575                 { 0x61, 0xffff, 0x99ff },
3576                 { 0x69, 0xffff, 0xfe04 },
3577         };
3578
3579         rtl_set_def_aspm_entry_latency(tp);
3580
3581         /* disable aspm and clock request before access ephy */
3582         rtl_hw_aspm_clkreq_enable(tp, false);
3583         rtl_ephy_init(tp, e_info_8125a_2);
3584
3585         rtl_hw_start_8125_common(tp);
3586         rtl_hw_aspm_clkreq_enable(tp, true);
3587 }
3588
3589 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3590 {
3591         static const struct ephy_info e_info_8125b[] = {
3592                 { 0x0b, 0xffff, 0xa908 },
3593                 { 0x1e, 0xffff, 0x20eb },
3594                 { 0x4b, 0xffff, 0xa908 },
3595                 { 0x5e, 0xffff, 0x20eb },
3596                 { 0x22, 0x0030, 0x0020 },
3597                 { 0x62, 0x0030, 0x0020 },
3598         };
3599
3600         rtl_set_def_aspm_entry_latency(tp);
3601         rtl_hw_aspm_clkreq_enable(tp, false);
3602
3603         rtl_ephy_init(tp, e_info_8125b);
3604         rtl_hw_start_8125_common(tp);
3605
3606         rtl_hw_aspm_clkreq_enable(tp, true);
3607 }
3608
3609 static void rtl_hw_config(struct rtl8169_private *tp)
3610 {
3611         static const rtl_generic_fct hw_configs[] = {
3612                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3613                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3614                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3615                 [RTL_GIGA_MAC_VER_10] = NULL,
3616                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3617                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3618                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3619                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3620                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3621                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3622                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3623                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3624                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3625                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3626                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3627                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3628                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3629                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3630                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3631                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3632                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3633                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3634                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3635                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3636                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3637                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3638                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3639                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3640                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3641                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3642                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3643                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3644                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3645                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3646                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3647                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3648                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3649                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3650                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3651         };
3652
3653         if (hw_configs[tp->mac_version])
3654                 hw_configs[tp->mac_version](tp);
3655 }
3656
3657 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3658 {
3659         int i;
3660
3661         /* disable interrupt coalescing */
3662         for (i = 0xa00; i < 0xb00; i += 4)
3663                 RTL_W32(tp, i, 0);
3664
3665         rtl_hw_config(tp);
3666 }
3667
3668 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3669 {
3670         if (rtl_is_8168evl_up(tp))
3671                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3672         else
3673                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3674
3675         rtl_hw_config(tp);
3676
3677         /* disable interrupt coalescing */
3678         RTL_W16(tp, IntrMitigate, 0x0000);
3679 }
3680
3681 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3682 {
3683         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3684
3685         tp->cp_cmd |= PCIMulRW;
3686
3687         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3688             tp->mac_version == RTL_GIGA_MAC_VER_03)
3689                 tp->cp_cmd |= EnAnaPLL;
3690
3691         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3692
3693         rtl8169_set_magic_reg(tp);
3694
3695         /* disable interrupt coalescing */
3696         RTL_W16(tp, IntrMitigate, 0x0000);
3697 }
3698
3699 static void rtl_hw_start(struct  rtl8169_private *tp)
3700 {
3701         rtl_unlock_config_regs(tp);
3702
3703         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3704
3705         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3706                 rtl_hw_start_8169(tp);
3707         else if (rtl_is_8125(tp))
3708                 rtl_hw_start_8125(tp);
3709         else
3710                 rtl_hw_start_8168(tp);
3711
3712         rtl_enable_exit_l1(tp);
3713         rtl_set_rx_max_size(tp);
3714         rtl_set_rx_tx_desc_registers(tp);
3715         rtl_lock_config_regs(tp);
3716
3717         rtl_jumbo_config(tp);
3718
3719         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3720         rtl_pci_commit(tp);
3721
3722         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3723         rtl_init_rxcfg(tp);
3724         rtl_set_tx_config_registers(tp);
3725         rtl_set_rx_config_features(tp, tp->dev->features);
3726         rtl_set_rx_mode(tp->dev);
3727         rtl_irq_enable(tp);
3728 }
3729
3730 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3731 {
3732         struct rtl8169_private *tp = netdev_priv(dev);
3733
3734         dev->mtu = new_mtu;
3735         netdev_update_features(dev);
3736         rtl_jumbo_config(tp);
3737
3738         switch (tp->mac_version) {
3739         case RTL_GIGA_MAC_VER_61:
3740         case RTL_GIGA_MAC_VER_63:
3741                 rtl8125_set_eee_txidle_timer(tp);
3742                 break;
3743         default:
3744                 break;
3745         }
3746
3747         return 0;
3748 }
3749
3750 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3751 {
3752         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3753
3754         desc->opts2 = 0;
3755         /* Force memory writes to complete before releasing descriptor */
3756         dma_wmb();
3757         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3758 }
3759
3760 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3761                                           struct RxDesc *desc)
3762 {
3763         struct device *d = tp_to_dev(tp);
3764         int node = dev_to_node(d);
3765         dma_addr_t mapping;
3766         struct page *data;
3767
3768         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3769         if (!data)
3770                 return NULL;
3771
3772         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3773         if (unlikely(dma_mapping_error(d, mapping))) {
3774                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3775                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3776                 return NULL;
3777         }
3778
3779         desc->addr = cpu_to_le64(mapping);
3780         rtl8169_mark_to_asic(desc);
3781
3782         return data;
3783 }
3784
3785 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3786 {
3787         int i;
3788
3789         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3790                 dma_unmap_page(tp_to_dev(tp),
3791                                le64_to_cpu(tp->RxDescArray[i].addr),
3792                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3793                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3794                 tp->Rx_databuff[i] = NULL;
3795                 tp->RxDescArray[i].addr = 0;
3796                 tp->RxDescArray[i].opts1 = 0;
3797         }
3798 }
3799
3800 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3801 {
3802         int i;
3803
3804         for (i = 0; i < NUM_RX_DESC; i++) {
3805                 struct page *data;
3806
3807                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3808                 if (!data) {
3809                         rtl8169_rx_clear(tp);
3810                         return -ENOMEM;
3811                 }
3812                 tp->Rx_databuff[i] = data;
3813         }
3814
3815         /* mark as last descriptor in the ring */
3816         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3817
3818         return 0;
3819 }
3820
3821 static int rtl8169_init_ring(struct rtl8169_private *tp)
3822 {
3823         rtl8169_init_ring_indexes(tp);
3824
3825         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3826         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3827
3828         return rtl8169_rx_fill(tp);
3829 }
3830
3831 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3832 {
3833         struct ring_info *tx_skb = tp->tx_skb + entry;
3834         struct TxDesc *desc = tp->TxDescArray + entry;
3835
3836         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3837                          DMA_TO_DEVICE);
3838         memset(desc, 0, sizeof(*desc));
3839         memset(tx_skb, 0, sizeof(*tx_skb));
3840 }
3841
3842 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3843                                    unsigned int n)
3844 {
3845         unsigned int i;
3846
3847         for (i = 0; i < n; i++) {
3848                 unsigned int entry = (start + i) % NUM_TX_DESC;
3849                 struct ring_info *tx_skb = tp->tx_skb + entry;
3850                 unsigned int len = tx_skb->len;
3851
3852                 if (len) {
3853                         struct sk_buff *skb = tx_skb->skb;
3854
3855                         rtl8169_unmap_tx_skb(tp, entry);
3856                         if (skb)
3857                                 dev_consume_skb_any(skb);
3858                 }
3859         }
3860 }
3861
3862 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3863 {
3864         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3865         netdev_reset_queue(tp->dev);
3866 }
3867
3868 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3869 {
3870         napi_disable(&tp->napi);
3871
3872         /* Give a racing hard_start_xmit a few cycles to complete. */
3873         synchronize_net();
3874
3875         /* Disable interrupts */
3876         rtl8169_irq_mask_and_ack(tp);
3877
3878         rtl_rx_close(tp);
3879
3880         if (going_down && tp->dev->wol_enabled)
3881                 goto no_reset;
3882
3883         switch (tp->mac_version) {
3884         case RTL_GIGA_MAC_VER_28:
3885         case RTL_GIGA_MAC_VER_31:
3886                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3887                 break;
3888         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3889                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3890                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3891                 break;
3892         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3893                 rtl_enable_rxdvgate(tp);
3894                 fsleep(2000);
3895                 break;
3896         default:
3897                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3898                 fsleep(100);
3899                 break;
3900         }
3901
3902         rtl_hw_reset(tp);
3903 no_reset:
3904         rtl8169_tx_clear(tp);
3905         rtl8169_init_ring_indexes(tp);
3906 }
3907
3908 static void rtl_reset_work(struct rtl8169_private *tp)
3909 {
3910         int i;
3911
3912         netif_stop_queue(tp->dev);
3913
3914         rtl8169_cleanup(tp, false);
3915
3916         for (i = 0; i < NUM_RX_DESC; i++)
3917                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3918
3919         napi_enable(&tp->napi);
3920         rtl_hw_start(tp);
3921 }
3922
3923 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3924 {
3925         struct rtl8169_private *tp = netdev_priv(dev);
3926
3927         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3928 }
3929
3930 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3931                           void *addr, unsigned int entry, bool desc_own)
3932 {
3933         struct TxDesc *txd = tp->TxDescArray + entry;
3934         struct device *d = tp_to_dev(tp);
3935         dma_addr_t mapping;
3936         u32 opts1;
3937         int ret;
3938
3939         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3940         ret = dma_mapping_error(d, mapping);
3941         if (unlikely(ret)) {
3942                 if (net_ratelimit())
3943                         netdev_err(tp->dev, "Failed to map TX data!\n");
3944                 return ret;
3945         }
3946
3947         txd->addr = cpu_to_le64(mapping);
3948         txd->opts2 = cpu_to_le32(opts[1]);
3949
3950         opts1 = opts[0] | len;
3951         if (entry == NUM_TX_DESC - 1)
3952                 opts1 |= RingEnd;
3953         if (desc_own)
3954                 opts1 |= DescOwn;
3955         txd->opts1 = cpu_to_le32(opts1);
3956
3957         tp->tx_skb[entry].len = len;
3958
3959         return 0;
3960 }
3961
3962 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3963                               const u32 *opts, unsigned int entry)
3964 {
3965         struct skb_shared_info *info = skb_shinfo(skb);
3966         unsigned int cur_frag;
3967
3968         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3969                 const skb_frag_t *frag = info->frags + cur_frag;
3970                 void *addr = skb_frag_address(frag);
3971                 u32 len = skb_frag_size(frag);
3972
3973                 entry = (entry + 1) % NUM_TX_DESC;
3974
3975                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
3976                         goto err_out;
3977         }
3978
3979         return 0;
3980
3981 err_out:
3982         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3983         return -EIO;
3984 }
3985
3986 static bool rtl_skb_is_udp(struct sk_buff *skb)
3987 {
3988         int no = skb_network_offset(skb);
3989         struct ipv6hdr *i6h, _i6h;
3990         struct iphdr *ih, _ih;
3991
3992         switch (vlan_get_protocol(skb)) {
3993         case htons(ETH_P_IP):
3994                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
3995                 return ih && ih->protocol == IPPROTO_UDP;
3996         case htons(ETH_P_IPV6):
3997                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
3998                 return i6h && i6h->nexthdr == IPPROTO_UDP;
3999         default:
4000                 return false;
4001         }
4002 }
4003
4004 #define RTL_MIN_PATCH_LEN       47
4005
4006 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4007 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4008                                             struct sk_buff *skb)
4009 {
4010         unsigned int padto = 0, len = skb->len;
4011
4012         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4013             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4014                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4015                                               skb_transport_header(skb);
4016
4017                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4018                     trans_data_len < RTL_MIN_PATCH_LEN) {
4019                         u16 dest = ntohs(udp_hdr(skb)->dest);
4020
4021                         /* dest is a standard PTP port */
4022                         if (dest == 319 || dest == 320)
4023                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4024                 }
4025
4026                 if (trans_data_len < sizeof(struct udphdr))
4027                         padto = max_t(unsigned int, padto,
4028                                       len + sizeof(struct udphdr) - trans_data_len);
4029         }
4030
4031         return padto;
4032 }
4033
4034 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4035                                            struct sk_buff *skb)
4036 {
4037         unsigned int padto;
4038
4039         padto = rtl8125_quirk_udp_padto(tp, skb);
4040
4041         switch (tp->mac_version) {
4042         case RTL_GIGA_MAC_VER_34:
4043         case RTL_GIGA_MAC_VER_61:
4044         case RTL_GIGA_MAC_VER_63:
4045                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4046                 break;
4047         default:
4048                 break;
4049         }
4050
4051         return padto;
4052 }
4053
4054 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4055 {
4056         u32 mss = skb_shinfo(skb)->gso_size;
4057
4058         if (mss) {
4059                 opts[0] |= TD_LSO;
4060                 opts[0] |= mss << TD0_MSS_SHIFT;
4061         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4062                 const struct iphdr *ip = ip_hdr(skb);
4063
4064                 if (ip->protocol == IPPROTO_TCP)
4065                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4066                 else if (ip->protocol == IPPROTO_UDP)
4067                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4068                 else
4069                         WARN_ON_ONCE(1);
4070         }
4071 }
4072
4073 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4074                                 struct sk_buff *skb, u32 *opts)
4075 {
4076         struct skb_shared_info *shinfo = skb_shinfo(skb);
4077         u32 mss = shinfo->gso_size;
4078
4079         if (mss) {
4080                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4081                         opts[0] |= TD1_GTSENV4;
4082                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4083                         if (skb_cow_head(skb, 0))
4084                                 return false;
4085
4086                         tcp_v6_gso_csum_prep(skb);
4087                         opts[0] |= TD1_GTSENV6;
4088                 } else {
4089                         WARN_ON_ONCE(1);
4090                 }
4091
4092                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4093                 opts[1] |= mss << TD1_MSS_SHIFT;
4094         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4095                 u8 ip_protocol;
4096
4097                 switch (vlan_get_protocol(skb)) {
4098                 case htons(ETH_P_IP):
4099                         opts[1] |= TD1_IPv4_CS;
4100                         ip_protocol = ip_hdr(skb)->protocol;
4101                         break;
4102
4103                 case htons(ETH_P_IPV6):
4104                         opts[1] |= TD1_IPv6_CS;
4105                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4106                         break;
4107
4108                 default:
4109                         ip_protocol = IPPROTO_RAW;
4110                         break;
4111                 }
4112
4113                 if (ip_protocol == IPPROTO_TCP)
4114                         opts[1] |= TD1_TCP_CS;
4115                 else if (ip_protocol == IPPROTO_UDP)
4116                         opts[1] |= TD1_UDP_CS;
4117                 else
4118                         WARN_ON_ONCE(1);
4119
4120                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4121         } else {
4122                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4123
4124                 /* skb_padto would free the skb on error */
4125                 return !__skb_put_padto(skb, padto, false);
4126         }
4127
4128         return true;
4129 }
4130
4131 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4132 {
4133         unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4134                                         - READ_ONCE(tp->cur_tx);
4135
4136         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4137         return slots_avail > MAX_SKB_FRAGS;
4138 }
4139
4140 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4141 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4142 {
4143         switch (tp->mac_version) {
4144         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4145         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4146                 return false;
4147         default:
4148                 return true;
4149         }
4150 }
4151
4152 static void rtl8169_doorbell(struct rtl8169_private *tp)
4153 {
4154         if (rtl_is_8125(tp))
4155                 RTL_W16(tp, TxPoll_8125, BIT(0));
4156         else
4157                 RTL_W8(tp, TxPoll, NPQ);
4158 }
4159
4160 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4161                                       struct net_device *dev)
4162 {
4163         unsigned int frags = skb_shinfo(skb)->nr_frags;
4164         struct rtl8169_private *tp = netdev_priv(dev);
4165         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4166         struct TxDesc *txd_first, *txd_last;
4167         bool stop_queue, door_bell;
4168         u32 opts[2];
4169
4170         if (unlikely(!rtl_tx_slots_avail(tp))) {
4171                 if (net_ratelimit())
4172                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4173                 goto err_stop_0;
4174         }
4175
4176         opts[1] = rtl8169_tx_vlan_tag(skb);
4177         opts[0] = 0;
4178
4179         if (!rtl_chip_supports_csum_v2(tp))
4180                 rtl8169_tso_csum_v1(skb, opts);
4181         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4182                 goto err_dma_0;
4183
4184         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4185                                     entry, false)))
4186                 goto err_dma_0;
4187
4188         txd_first = tp->TxDescArray + entry;
4189
4190         if (frags) {
4191                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4192                         goto err_dma_1;
4193                 entry = (entry + frags) % NUM_TX_DESC;
4194         }
4195
4196         txd_last = tp->TxDescArray + entry;
4197         txd_last->opts1 |= cpu_to_le32(LastFrag);
4198         tp->tx_skb[entry].skb = skb;
4199
4200         skb_tx_timestamp(skb);
4201
4202         /* Force memory writes to complete before releasing descriptor */
4203         dma_wmb();
4204
4205         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4206
4207         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4208
4209         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4210         smp_wmb();
4211
4212         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4213
4214         stop_queue = !rtl_tx_slots_avail(tp);
4215         if (unlikely(stop_queue)) {
4216                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4217                  * not miss a ring update when it notices a stopped queue.
4218                  */
4219                 smp_wmb();
4220                 netif_stop_queue(dev);
4221                 /* Sync with rtl_tx:
4222                  * - publish queue status and cur_tx ring index (write barrier)
4223                  * - refresh dirty_tx ring index (read barrier).
4224                  * May the current thread have a pessimistic view of the ring
4225                  * status and forget to wake up queue, a racing rtl_tx thread
4226                  * can't.
4227                  */
4228                 smp_mb__after_atomic();
4229                 if (rtl_tx_slots_avail(tp))
4230                         netif_start_queue(dev);
4231                 door_bell = true;
4232         }
4233
4234         if (door_bell)
4235                 rtl8169_doorbell(tp);
4236
4237         return NETDEV_TX_OK;
4238
4239 err_dma_1:
4240         rtl8169_unmap_tx_skb(tp, entry);
4241 err_dma_0:
4242         dev_kfree_skb_any(skb);
4243         dev->stats.tx_dropped++;
4244         return NETDEV_TX_OK;
4245
4246 err_stop_0:
4247         netif_stop_queue(dev);
4248         dev->stats.tx_dropped++;
4249         return NETDEV_TX_BUSY;
4250 }
4251
4252 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4253 {
4254         struct skb_shared_info *info = skb_shinfo(skb);
4255         unsigned int nr_frags = info->nr_frags;
4256
4257         if (!nr_frags)
4258                 return UINT_MAX;
4259
4260         return skb_frag_size(info->frags + nr_frags - 1);
4261 }
4262
4263 /* Workaround for hw issues with TSO on RTL8168evl */
4264 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4265                                             netdev_features_t features)
4266 {
4267         /* IPv4 header has options field */
4268         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4269             ip_hdrlen(skb) > sizeof(struct iphdr))
4270                 features &= ~NETIF_F_ALL_TSO;
4271
4272         /* IPv4 TCP header has options field */
4273         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4274                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4275                 features &= ~NETIF_F_ALL_TSO;
4276
4277         else if (rtl_last_frag_len(skb) <= 6)
4278                 features &= ~NETIF_F_ALL_TSO;
4279
4280         return features;
4281 }
4282
4283 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4284                                                 struct net_device *dev,
4285                                                 netdev_features_t features)
4286 {
4287         struct rtl8169_private *tp = netdev_priv(dev);
4288
4289         if (skb_is_gso(skb)) {
4290                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4291                         features = rtl8168evl_fix_tso(skb, features);
4292
4293                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4294                     rtl_chip_supports_csum_v2(tp))
4295                         features &= ~NETIF_F_ALL_TSO;
4296         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4297                 /* work around hw bug on some chip versions */
4298                 if (skb->len < ETH_ZLEN)
4299                         features &= ~NETIF_F_CSUM_MASK;
4300
4301                 if (rtl_quirk_packet_padto(tp, skb))
4302                         features &= ~NETIF_F_CSUM_MASK;
4303
4304                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4305                     rtl_chip_supports_csum_v2(tp))
4306                         features &= ~NETIF_F_CSUM_MASK;
4307         }
4308
4309         return vlan_features_check(skb, features);
4310 }
4311
4312 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4313 {
4314         struct rtl8169_private *tp = netdev_priv(dev);
4315         struct pci_dev *pdev = tp->pci_dev;
4316         int pci_status_errs;
4317         u16 pci_cmd;
4318
4319         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4320
4321         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4322
4323         if (net_ratelimit())
4324                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4325                            pci_cmd, pci_status_errs);
4326
4327         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4328 }
4329
4330 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4331                    int budget)
4332 {
4333         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4334         struct sk_buff *skb;
4335
4336         dirty_tx = tp->dirty_tx;
4337
4338         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4339                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4340                 u32 status;
4341
4342                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4343                 if (status & DescOwn)
4344                         break;
4345
4346                 skb = tp->tx_skb[entry].skb;
4347                 rtl8169_unmap_tx_skb(tp, entry);
4348
4349                 if (skb) {
4350                         pkts_compl++;
4351                         bytes_compl += skb->len;
4352                         napi_consume_skb(skb, budget);
4353                 }
4354                 dirty_tx++;
4355         }
4356
4357         if (tp->dirty_tx != dirty_tx) {
4358                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4359                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4360
4361                 /* Sync with rtl8169_start_xmit:
4362                  * - publish dirty_tx ring index (write barrier)
4363                  * - refresh cur_tx ring index and queue status (read barrier)
4364                  * May the current thread miss the stopped queue condition,
4365                  * a racing xmit thread can only have a right view of the
4366                  * ring status.
4367                  */
4368                 smp_store_mb(tp->dirty_tx, dirty_tx);
4369                 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4370                         netif_wake_queue(dev);
4371                 /*
4372                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4373                  * too close. Let's kick an extra TxPoll request when a burst
4374                  * of start_xmit activity is detected (if it is not detected,
4375                  * it is slow enough). -- FR
4376                  * If skb is NULL then we come here again once a tx irq is
4377                  * triggered after the last fragment is marked transmitted.
4378                  */
4379                 if (tp->cur_tx != dirty_tx && skb)
4380                         rtl8169_doorbell(tp);
4381         }
4382 }
4383
4384 static inline int rtl8169_fragmented_frame(u32 status)
4385 {
4386         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4387 }
4388
4389 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4390 {
4391         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4392
4393         if (status == RxProtoTCP || status == RxProtoUDP)
4394                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4395         else
4396                 skb_checksum_none_assert(skb);
4397 }
4398
4399 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4400 {
4401         struct device *d = tp_to_dev(tp);
4402         int count;
4403
4404         for (count = 0; count < budget; count++, tp->cur_rx++) {
4405                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4406                 struct RxDesc *desc = tp->RxDescArray + entry;
4407                 struct sk_buff *skb;
4408                 const void *rx_buf;
4409                 dma_addr_t addr;
4410                 u32 status;
4411
4412                 status = le32_to_cpu(desc->opts1);
4413                 if (status & DescOwn)
4414                         break;
4415
4416                 /* This barrier is needed to keep us from reading
4417                  * any other fields out of the Rx descriptor until
4418                  * we know the status of DescOwn
4419                  */
4420                 dma_rmb();
4421
4422                 if (unlikely(status & RxRES)) {
4423                         if (net_ratelimit())
4424                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4425                                             status);
4426                         dev->stats.rx_errors++;
4427                         if (status & (RxRWT | RxRUNT))
4428                                 dev->stats.rx_length_errors++;
4429                         if (status & RxCRC)
4430                                 dev->stats.rx_crc_errors++;
4431
4432                         if (!(dev->features & NETIF_F_RXALL))
4433                                 goto release_descriptor;
4434                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4435                                 goto release_descriptor;
4436                 }
4437
4438                 pkt_size = status & GENMASK(13, 0);
4439                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4440                         pkt_size -= ETH_FCS_LEN;
4441
4442                 /* The driver does not support incoming fragmented frames.
4443                  * They are seen as a symptom of over-mtu sized frames.
4444                  */
4445                 if (unlikely(rtl8169_fragmented_frame(status))) {
4446                         dev->stats.rx_dropped++;
4447                         dev->stats.rx_length_errors++;
4448                         goto release_descriptor;
4449                 }
4450
4451                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4452                 if (unlikely(!skb)) {
4453                         dev->stats.rx_dropped++;
4454                         goto release_descriptor;
4455                 }
4456
4457                 addr = le64_to_cpu(desc->addr);
4458                 rx_buf = page_address(tp->Rx_databuff[entry]);
4459
4460                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4461                 prefetch(rx_buf);
4462                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4463                 skb->tail += pkt_size;
4464                 skb->len = pkt_size;
4465                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4466
4467                 rtl8169_rx_csum(skb, status);
4468                 skb->protocol = eth_type_trans(skb, dev);
4469
4470                 rtl8169_rx_vlan_tag(desc, skb);
4471
4472                 if (skb->pkt_type == PACKET_MULTICAST)
4473                         dev->stats.multicast++;
4474
4475                 napi_gro_receive(&tp->napi, skb);
4476
4477                 dev_sw_netstats_rx_add(dev, pkt_size);
4478 release_descriptor:
4479                 rtl8169_mark_to_asic(desc);
4480         }
4481
4482         return count;
4483 }
4484
4485 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4486 {
4487         struct rtl8169_private *tp = dev_instance;
4488         u32 status = rtl_get_events(tp);
4489
4490         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4491                 return IRQ_NONE;
4492
4493         if (unlikely(status & SYSErr)) {
4494                 rtl8169_pcierr_interrupt(tp->dev);
4495                 goto out;
4496         }
4497
4498         if (status & LinkChg)
4499                 phy_mac_interrupt(tp->phydev);
4500
4501         if (unlikely(status & RxFIFOOver &&
4502             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4503                 netif_stop_queue(tp->dev);
4504                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4505         }
4506
4507         if (napi_schedule_prep(&tp->napi)) {
4508                 rtl_irq_disable(tp);
4509                 __napi_schedule(&tp->napi);
4510         }
4511 out:
4512         rtl_ack_events(tp, status);
4513
4514         return IRQ_HANDLED;
4515 }
4516
4517 static void rtl_task(struct work_struct *work)
4518 {
4519         struct rtl8169_private *tp =
4520                 container_of(work, struct rtl8169_private, wk.work);
4521
4522         rtnl_lock();
4523
4524         if (!netif_running(tp->dev) ||
4525             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4526                 goto out_unlock;
4527
4528         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4529                 rtl_reset_work(tp);
4530                 netif_wake_queue(tp->dev);
4531         }
4532 out_unlock:
4533         rtnl_unlock();
4534 }
4535
4536 static int rtl8169_poll(struct napi_struct *napi, int budget)
4537 {
4538         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4539         struct net_device *dev = tp->dev;
4540         int work_done;
4541
4542         rtl_tx(dev, tp, budget);
4543
4544         work_done = rtl_rx(dev, tp, budget);
4545
4546         if (work_done < budget && napi_complete_done(napi, work_done))
4547                 rtl_irq_enable(tp);
4548
4549         return work_done;
4550 }
4551
4552 static void r8169_phylink_handler(struct net_device *ndev)
4553 {
4554         struct rtl8169_private *tp = netdev_priv(ndev);
4555
4556         if (netif_carrier_ok(ndev)) {
4557                 rtl_link_chg_patch(tp);
4558                 pm_request_resume(&tp->pci_dev->dev);
4559         } else {
4560                 pm_runtime_idle(&tp->pci_dev->dev);
4561         }
4562
4563         phy_print_status(tp->phydev);
4564 }
4565
4566 static int r8169_phy_connect(struct rtl8169_private *tp)
4567 {
4568         struct phy_device *phydev = tp->phydev;
4569         phy_interface_t phy_mode;
4570         int ret;
4571
4572         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4573                    PHY_INTERFACE_MODE_MII;
4574
4575         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4576                                  phy_mode);
4577         if (ret)
4578                 return ret;
4579
4580         if (!tp->supports_gmii)
4581                 phy_set_max_speed(phydev, SPEED_100);
4582
4583         phy_attached_info(phydev);
4584
4585         return 0;
4586 }
4587
4588 static void rtl8169_down(struct rtl8169_private *tp)
4589 {
4590         /* Clear all task flags */
4591         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4592
4593         phy_stop(tp->phydev);
4594
4595         rtl8169_update_counters(tp);
4596
4597         pci_clear_master(tp->pci_dev);
4598         rtl_pci_commit(tp);
4599
4600         rtl8169_cleanup(tp, true);
4601         rtl_disable_exit_l1(tp);
4602         rtl_prepare_power_down(tp);
4603 }
4604
4605 static void rtl8169_up(struct rtl8169_private *tp)
4606 {
4607         pci_set_master(tp->pci_dev);
4608         phy_init_hw(tp->phydev);
4609         phy_resume(tp->phydev);
4610         rtl8169_init_phy(tp);
4611         napi_enable(&tp->napi);
4612         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4613         rtl_reset_work(tp);
4614
4615         phy_start(tp->phydev);
4616 }
4617
4618 static int rtl8169_close(struct net_device *dev)
4619 {
4620         struct rtl8169_private *tp = netdev_priv(dev);
4621         struct pci_dev *pdev = tp->pci_dev;
4622
4623         pm_runtime_get_sync(&pdev->dev);
4624
4625         netif_stop_queue(dev);
4626         rtl8169_down(tp);
4627         rtl8169_rx_clear(tp);
4628
4629         cancel_work_sync(&tp->wk.work);
4630
4631         free_irq(tp->irq, tp);
4632
4633         phy_disconnect(tp->phydev);
4634
4635         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4636                           tp->RxPhyAddr);
4637         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4638                           tp->TxPhyAddr);
4639         tp->TxDescArray = NULL;
4640         tp->RxDescArray = NULL;
4641
4642         pm_runtime_put_sync(&pdev->dev);
4643
4644         return 0;
4645 }
4646
4647 #ifdef CONFIG_NET_POLL_CONTROLLER
4648 static void rtl8169_netpoll(struct net_device *dev)
4649 {
4650         struct rtl8169_private *tp = netdev_priv(dev);
4651
4652         rtl8169_interrupt(tp->irq, tp);
4653 }
4654 #endif
4655
4656 static int rtl_open(struct net_device *dev)
4657 {
4658         struct rtl8169_private *tp = netdev_priv(dev);
4659         struct pci_dev *pdev = tp->pci_dev;
4660         unsigned long irqflags;
4661         int retval = -ENOMEM;
4662
4663         pm_runtime_get_sync(&pdev->dev);
4664
4665         /*
4666          * Rx and Tx descriptors needs 256 bytes alignment.
4667          * dma_alloc_coherent provides more.
4668          */
4669         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4670                                              &tp->TxPhyAddr, GFP_KERNEL);
4671         if (!tp->TxDescArray)
4672                 goto out;
4673
4674         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4675                                              &tp->RxPhyAddr, GFP_KERNEL);
4676         if (!tp->RxDescArray)
4677                 goto err_free_tx_0;
4678
4679         retval = rtl8169_init_ring(tp);
4680         if (retval < 0)
4681                 goto err_free_rx_1;
4682
4683         rtl_request_firmware(tp);
4684
4685         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4686         retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4687         if (retval < 0)
4688                 goto err_release_fw_2;
4689
4690         retval = r8169_phy_connect(tp);
4691         if (retval)
4692                 goto err_free_irq;
4693
4694         rtl8169_up(tp);
4695         rtl8169_init_counter_offsets(tp);
4696         netif_start_queue(dev);
4697 out:
4698         pm_runtime_put_sync(&pdev->dev);
4699
4700         return retval;
4701
4702 err_free_irq:
4703         free_irq(tp->irq, tp);
4704 err_release_fw_2:
4705         rtl_release_firmware(tp);
4706         rtl8169_rx_clear(tp);
4707 err_free_rx_1:
4708         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4709                           tp->RxPhyAddr);
4710         tp->RxDescArray = NULL;
4711 err_free_tx_0:
4712         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4713                           tp->TxPhyAddr);
4714         tp->TxDescArray = NULL;
4715         goto out;
4716 }
4717
4718 static void
4719 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4720 {
4721         struct rtl8169_private *tp = netdev_priv(dev);
4722         struct pci_dev *pdev = tp->pci_dev;
4723         struct rtl8169_counters *counters = tp->counters;
4724
4725         pm_runtime_get_noresume(&pdev->dev);
4726
4727         netdev_stats_to_stats64(stats, &dev->stats);
4728         dev_fetch_sw_netstats(stats, dev->tstats);
4729
4730         /*
4731          * Fetch additional counter values missing in stats collected by driver
4732          * from tally counters.
4733          */
4734         if (pm_runtime_active(&pdev->dev))
4735                 rtl8169_update_counters(tp);
4736
4737         /*
4738          * Subtract values fetched during initalization.
4739          * See rtl8169_init_counter_offsets for a description why we do that.
4740          */
4741         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4742                 le64_to_cpu(tp->tc_offset.tx_errors);
4743         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4744                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4745         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4746                 le16_to_cpu(tp->tc_offset.tx_aborted);
4747         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4748                 le16_to_cpu(tp->tc_offset.rx_missed);
4749
4750         pm_runtime_put_noidle(&pdev->dev);
4751 }
4752
4753 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4754 {
4755         netif_device_detach(tp->dev);
4756
4757         if (netif_running(tp->dev))
4758                 rtl8169_down(tp);
4759 }
4760
4761 static int rtl8169_runtime_resume(struct device *dev)
4762 {
4763         struct rtl8169_private *tp = dev_get_drvdata(dev);
4764
4765         rtl_rar_set(tp, tp->dev->dev_addr);
4766         __rtl8169_set_wol(tp, tp->saved_wolopts);
4767
4768         if (tp->TxDescArray)
4769                 rtl8169_up(tp);
4770
4771         netif_device_attach(tp->dev);
4772
4773         return 0;
4774 }
4775
4776 static int rtl8169_suspend(struct device *device)
4777 {
4778         struct rtl8169_private *tp = dev_get_drvdata(device);
4779
4780         rtnl_lock();
4781         rtl8169_net_suspend(tp);
4782         if (!device_may_wakeup(tp_to_dev(tp)))
4783                 clk_disable_unprepare(tp->clk);
4784         rtnl_unlock();
4785
4786         return 0;
4787 }
4788
4789 static int rtl8169_resume(struct device *device)
4790 {
4791         struct rtl8169_private *tp = dev_get_drvdata(device);
4792
4793         if (!device_may_wakeup(tp_to_dev(tp)))
4794                 clk_prepare_enable(tp->clk);
4795
4796         /* Reportedly at least Asus X453MA truncates packets otherwise */
4797         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4798                 rtl_init_rxcfg(tp);
4799
4800         return rtl8169_runtime_resume(device);
4801 }
4802
4803 static int rtl8169_runtime_suspend(struct device *device)
4804 {
4805         struct rtl8169_private *tp = dev_get_drvdata(device);
4806
4807         if (!tp->TxDescArray) {
4808                 netif_device_detach(tp->dev);
4809                 return 0;
4810         }
4811
4812         rtnl_lock();
4813         __rtl8169_set_wol(tp, WAKE_PHY);
4814         rtl8169_net_suspend(tp);
4815         rtnl_unlock();
4816
4817         return 0;
4818 }
4819
4820 static int rtl8169_runtime_idle(struct device *device)
4821 {
4822         struct rtl8169_private *tp = dev_get_drvdata(device);
4823
4824         if (tp->dash_type != RTL_DASH_NONE)
4825                 return -EBUSY;
4826
4827         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4828                 pm_schedule_suspend(device, 10000);
4829
4830         return -EBUSY;
4831 }
4832
4833 static const struct dev_pm_ops rtl8169_pm_ops = {
4834         SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4835         RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4836                        rtl8169_runtime_idle)
4837 };
4838
4839 static void rtl_shutdown(struct pci_dev *pdev)
4840 {
4841         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4842
4843         rtnl_lock();
4844         rtl8169_net_suspend(tp);
4845         rtnl_unlock();
4846
4847         /* Restore original MAC address */
4848         rtl_rar_set(tp, tp->dev->perm_addr);
4849
4850         if (system_state == SYSTEM_POWER_OFF &&
4851             tp->dash_type == RTL_DASH_NONE) {
4852                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4853                 pci_set_power_state(pdev, PCI_D3hot);
4854         }
4855 }
4856
4857 static void rtl_remove_one(struct pci_dev *pdev)
4858 {
4859         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4860
4861         if (pci_dev_run_wake(pdev))
4862                 pm_runtime_get_noresume(&pdev->dev);
4863
4864         unregister_netdev(tp->dev);
4865
4866         if (tp->dash_type != RTL_DASH_NONE)
4867                 rtl8168_driver_stop(tp);
4868
4869         rtl_release_firmware(tp);
4870
4871         /* restore original MAC address */
4872         rtl_rar_set(tp, tp->dev->perm_addr);
4873 }
4874
4875 static const struct net_device_ops rtl_netdev_ops = {
4876         .ndo_open               = rtl_open,
4877         .ndo_stop               = rtl8169_close,
4878         .ndo_get_stats64        = rtl8169_get_stats64,
4879         .ndo_start_xmit         = rtl8169_start_xmit,
4880         .ndo_features_check     = rtl8169_features_check,
4881         .ndo_tx_timeout         = rtl8169_tx_timeout,
4882         .ndo_validate_addr      = eth_validate_addr,
4883         .ndo_change_mtu         = rtl8169_change_mtu,
4884         .ndo_fix_features       = rtl8169_fix_features,
4885         .ndo_set_features       = rtl8169_set_features,
4886         .ndo_set_mac_address    = rtl_set_mac_address,
4887         .ndo_eth_ioctl          = phy_do_ioctl_running,
4888         .ndo_set_rx_mode        = rtl_set_rx_mode,
4889 #ifdef CONFIG_NET_POLL_CONTROLLER
4890         .ndo_poll_controller    = rtl8169_netpoll,
4891 #endif
4892
4893 };
4894
4895 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4896 {
4897         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4898
4899         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4900                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4901         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4902                 /* special workaround needed */
4903                 tp->irq_mask |= RxFIFOOver;
4904         else
4905                 tp->irq_mask |= RxOverflow;
4906 }
4907
4908 static int rtl_alloc_irq(struct rtl8169_private *tp)
4909 {
4910         unsigned int flags;
4911
4912         switch (tp->mac_version) {
4913         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4914                 rtl_unlock_config_regs(tp);
4915                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4916                 rtl_lock_config_regs(tp);
4917                 fallthrough;
4918         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4919                 flags = PCI_IRQ_LEGACY;
4920                 break;
4921         default:
4922                 flags = PCI_IRQ_ALL_TYPES;
4923                 break;
4924         }
4925
4926         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4927 }
4928
4929 static void rtl_read_mac_address(struct rtl8169_private *tp,
4930                                  u8 mac_addr[ETH_ALEN])
4931 {
4932         /* Get MAC address */
4933         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4934                 u32 value;
4935
4936                 value = rtl_eri_read(tp, 0xe0);
4937                 put_unaligned_le32(value, mac_addr);
4938                 value = rtl_eri_read(tp, 0xe4);
4939                 put_unaligned_le16(value, mac_addr + 4);
4940         } else if (rtl_is_8125(tp)) {
4941                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4942         }
4943 }
4944
4945 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4946 {
4947         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4948 }
4949
4950 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
4951 {
4952         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
4953 }
4954
4955 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
4956 {
4957         struct rtl8169_private *tp = mii_bus->priv;
4958
4959         if (phyaddr > 0)
4960                 return -ENODEV;
4961
4962         return rtl_readphy(tp, phyreg);
4963 }
4964
4965 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
4966                                 int phyreg, u16 val)
4967 {
4968         struct rtl8169_private *tp = mii_bus->priv;
4969
4970         if (phyaddr > 0)
4971                 return -ENODEV;
4972
4973         rtl_writephy(tp, phyreg, val);
4974
4975         return 0;
4976 }
4977
4978 static int r8169_mdio_register(struct rtl8169_private *tp)
4979 {
4980         struct pci_dev *pdev = tp->pci_dev;
4981         struct mii_bus *new_bus;
4982         int ret;
4983
4984         new_bus = devm_mdiobus_alloc(&pdev->dev);
4985         if (!new_bus)
4986                 return -ENOMEM;
4987
4988         new_bus->name = "r8169";
4989         new_bus->priv = tp;
4990         new_bus->parent = &pdev->dev;
4991         new_bus->irq[0] = PHY_MAC_INTERRUPT;
4992         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
4993                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
4994
4995         new_bus->read = r8169_mdio_read_reg;
4996         new_bus->write = r8169_mdio_write_reg;
4997
4998         ret = devm_mdiobus_register(&pdev->dev, new_bus);
4999         if (ret)
5000                 return ret;
5001
5002         tp->phydev = mdiobus_get_phy(new_bus, 0);
5003         if (!tp->phydev) {
5004                 return -ENODEV;
5005         } else if (!tp->phydev->drv) {
5006                 /* Most chip versions fail with the genphy driver.
5007                  * Therefore ensure that the dedicated PHY driver is loaded.
5008                  */
5009                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5010                         tp->phydev->phy_id);
5011                 return -EUNATCH;
5012         }
5013
5014         tp->phydev->mac_managed_pm = 1;
5015
5016         phy_support_asym_pause(tp->phydev);
5017
5018         /* PHY will be woken up in rtl_open() */
5019         phy_suspend(tp->phydev);
5020
5021         return 0;
5022 }
5023
5024 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5025 {
5026         rtl_enable_rxdvgate(tp);
5027
5028         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5029         msleep(1);
5030         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5031
5032         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5033         r8168g_wait_ll_share_fifo_ready(tp);
5034
5035         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5036         r8168g_wait_ll_share_fifo_ready(tp);
5037 }
5038
5039 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5040 {
5041         rtl_enable_rxdvgate(tp);
5042
5043         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5044         msleep(1);
5045         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5046
5047         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5048         r8168g_wait_ll_share_fifo_ready(tp);
5049
5050         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5051         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5052         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5053         r8168g_wait_ll_share_fifo_ready(tp);
5054 }
5055
5056 static void rtl_hw_initialize(struct rtl8169_private *tp)
5057 {
5058         switch (tp->mac_version) {
5059         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5060                 rtl8168ep_stop_cmac(tp);
5061                 fallthrough;
5062         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5063                 rtl_hw_init_8168g(tp);
5064                 break;
5065         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5066                 rtl_hw_init_8125(tp);
5067                 break;
5068         default:
5069                 break;
5070         }
5071 }
5072
5073 static int rtl_jumbo_max(struct rtl8169_private *tp)
5074 {
5075         /* Non-GBit versions don't support jumbo frames */
5076         if (!tp->supports_gmii)
5077                 return 0;
5078
5079         switch (tp->mac_version) {
5080         /* RTL8169 */
5081         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5082                 return JUMBO_7K;
5083         /* RTL8168b */
5084         case RTL_GIGA_MAC_VER_11:
5085         case RTL_GIGA_MAC_VER_17:
5086                 return JUMBO_4K;
5087         /* RTL8168c */
5088         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5089                 return JUMBO_6K;
5090         default:
5091                 return JUMBO_9K;
5092         }
5093 }
5094
5095 static void rtl_init_mac_address(struct rtl8169_private *tp)
5096 {
5097         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5098         struct net_device *dev = tp->dev;
5099         int rc;
5100
5101         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5102         if (!rc)
5103                 goto done;
5104
5105         rtl_read_mac_address(tp, mac_addr);
5106         if (is_valid_ether_addr(mac_addr))
5107                 goto done;
5108
5109         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5110         if (is_valid_ether_addr(mac_addr))
5111                 goto done;
5112
5113         eth_random_addr(mac_addr);
5114         dev->addr_assign_type = NET_ADDR_RANDOM;
5115         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5116 done:
5117         eth_hw_addr_set(dev, mac_addr);
5118         rtl_rar_set(tp, mac_addr);
5119 }
5120
5121 /* register is set if system vendor successfully tested ASPM 1.2 */
5122 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5123 {
5124         if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5125             r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5126                 return true;
5127
5128         return false;
5129 }
5130
5131 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5132 {
5133         struct rtl8169_private *tp;
5134         int jumbo_max, region, rc;
5135         enum mac_version chipset;
5136         struct net_device *dev;
5137         u16 xid;
5138
5139         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5140         if (!dev)
5141                 return -ENOMEM;
5142
5143         SET_NETDEV_DEV(dev, &pdev->dev);
5144         dev->netdev_ops = &rtl_netdev_ops;
5145         tp = netdev_priv(dev);
5146         tp->dev = dev;
5147         tp->pci_dev = pdev;
5148         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5149         tp->eee_adv = -1;
5150         tp->ocp_base = OCP_STD_PHY_BASE;
5151
5152         dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5153                                                    struct pcpu_sw_netstats);
5154         if (!dev->tstats)
5155                 return -ENOMEM;
5156
5157         /* Get the *optional* external "ether_clk" used on some boards */
5158         tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5159         if (IS_ERR(tp->clk))
5160                 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5161
5162         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5163         rc = pcim_enable_device(pdev);
5164         if (rc < 0) {
5165                 dev_err(&pdev->dev, "enable failure\n");
5166                 return rc;
5167         }
5168
5169         if (pcim_set_mwi(pdev) < 0)
5170                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5171
5172         /* use first MMIO region */
5173         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5174         if (region < 0) {
5175                 dev_err(&pdev->dev, "no MMIO resource found\n");
5176                 return -ENODEV;
5177         }
5178
5179         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5180         if (rc < 0) {
5181                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5182                 return rc;
5183         }
5184
5185         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5186
5187         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5188
5189         /* Identify chip attached to board */
5190         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5191         if (chipset == RTL_GIGA_MAC_NONE) {
5192                 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5193                 return -ENODEV;
5194         }
5195
5196         tp->mac_version = chipset;
5197
5198         /* Disable ASPM L1 as that cause random device stop working
5199          * problems as well as full system hangs for some PCIe devices users.
5200          * Chips from RTL8168h partially have issues with L1.2, but seem
5201          * to work fine with L1 and L1.1.
5202          */
5203         if (rtl_aspm_is_safe(tp))
5204                 rc = 0;
5205         else if (tp->mac_version >= RTL_GIGA_MAC_VER_46)
5206                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
5207         else
5208                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5209         tp->aspm_manageable = !rc;
5210
5211         tp->dash_type = rtl_check_dash(tp);
5212
5213         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5214
5215         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5216             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5217                 dev->features |= NETIF_F_HIGHDMA;
5218
5219         rtl_init_rxcfg(tp);
5220
5221         rtl8169_irq_mask_and_ack(tp);
5222
5223         rtl_hw_initialize(tp);
5224
5225         rtl_hw_reset(tp);
5226
5227         rc = rtl_alloc_irq(tp);
5228         if (rc < 0) {
5229                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5230                 return rc;
5231         }
5232         tp->irq = pci_irq_vector(pdev, 0);
5233
5234         INIT_WORK(&tp->wk.work, rtl_task);
5235
5236         rtl_init_mac_address(tp);
5237
5238         dev->ethtool_ops = &rtl8169_ethtool_ops;
5239
5240         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5241
5242         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5243                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5244         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5245         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5246
5247         /*
5248          * Pretend we are using VLANs; This bypasses a nasty bug where
5249          * Interrupts stop flowing on high load on 8110SCd controllers.
5250          */
5251         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5252                 /* Disallow toggling */
5253                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5254
5255         if (rtl_chip_supports_csum_v2(tp))
5256                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5257
5258         dev->features |= dev->hw_features;
5259
5260         /* There has been a number of reports that using SG/TSO results in
5261          * tx timeouts. However for a lot of people SG/TSO works fine.
5262          * Therefore disable both features by default, but allow users to
5263          * enable them. Use at own risk!
5264          */
5265         if (rtl_chip_supports_csum_v2(tp)) {
5266                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5267                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5268                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5269         } else {
5270                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5271                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5272                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5273         }
5274
5275         dev->hw_features |= NETIF_F_RXALL;
5276         dev->hw_features |= NETIF_F_RXFCS;
5277
5278         /* configure chip for default features */
5279         rtl8169_set_features(dev, dev->features);
5280
5281         if (tp->dash_type == RTL_DASH_NONE) {
5282                 rtl_set_d3_pll_down(tp, true);
5283         } else {
5284                 rtl_set_d3_pll_down(tp, false);
5285                 dev->wol_enabled = 1;
5286         }
5287
5288         jumbo_max = rtl_jumbo_max(tp);
5289         if (jumbo_max)
5290                 dev->max_mtu = jumbo_max;
5291
5292         rtl_set_irq_mask(tp);
5293
5294         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5295
5296         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5297                                             &tp->counters_phys_addr,
5298                                             GFP_KERNEL);
5299         if (!tp->counters)
5300                 return -ENOMEM;
5301
5302         pci_set_drvdata(pdev, tp);
5303
5304         rc = r8169_mdio_register(tp);
5305         if (rc)
5306                 return rc;
5307
5308         rc = register_netdev(dev);
5309         if (rc)
5310                 return rc;
5311
5312         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5313                     rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5314
5315         if (jumbo_max)
5316                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5317                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5318                             "ok" : "ko");
5319
5320         if (tp->dash_type != RTL_DASH_NONE) {
5321                 netdev_info(dev, "DASH enabled\n");
5322                 rtl8168_driver_start(tp);
5323         }
5324
5325         if (pci_dev_run_wake(pdev))
5326                 pm_runtime_put_sync(&pdev->dev);
5327
5328         return 0;
5329 }
5330
5331 static struct pci_driver rtl8169_pci_driver = {
5332         .name           = KBUILD_MODNAME,
5333         .id_table       = rtl8169_pci_tbl,
5334         .probe          = rtl_init_one,
5335         .remove         = rtl_remove_one,
5336         .shutdown       = rtl_shutdown,
5337         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5338 };
5339
5340 module_pci_driver(rtl8169_pci_driver);