1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
35 #include "r8169_firmware.h"
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
55 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
56 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
60 #define MC_FILTER_LIMIT 32
62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
65 #define R8169_REGS_SIZE 256
66 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
72 #define OCP_STD_PHY_BASE 0xa400
74 #define RTL_CFG_NO_GBIT 1
76 /* write/read MMIO register */
77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
92 } rtl_chip_infos[] = {
94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" },
104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
142 static const struct pci_device_id rtl8169_pci_tbl[] = {
143 { PCI_VDEVICE(REALTEK, 0x2502) },
144 { PCI_VDEVICE(REALTEK, 0x2600) },
145 { PCI_VDEVICE(REALTEK, 0x8129) },
146 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
147 { PCI_VDEVICE(REALTEK, 0x8161) },
148 { PCI_VDEVICE(REALTEK, 0x8162) },
149 { PCI_VDEVICE(REALTEK, 0x8167) },
150 { PCI_VDEVICE(REALTEK, 0x8168) },
151 { PCI_VDEVICE(NCUBE, 0x8168) },
152 { PCI_VDEVICE(REALTEK, 0x8169) },
153 { PCI_VENDOR_ID_DLINK, 0x4300,
154 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
155 { PCI_VDEVICE(DLINK, 0x4300) },
156 { PCI_VDEVICE(DLINK, 0x4302) },
157 { PCI_VDEVICE(AT, 0xc107) },
158 { PCI_VDEVICE(USR, 0x0116) },
159 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
160 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
161 { PCI_VDEVICE(REALTEK, 0x8125) },
162 { PCI_VDEVICE(REALTEK, 0x3000) },
166 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
169 MAC0 = 0, /* Ethernet hardware address. */
171 MAR0 = 8, /* Multicast filter. */
172 CounterAddrLow = 0x10,
173 CounterAddrHigh = 0x14,
174 TxDescStartAddrLow = 0x20,
175 TxDescStartAddrHigh = 0x24,
176 TxHDescStartAddrLow = 0x28,
177 TxHDescStartAddrHigh = 0x2c,
186 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
187 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
190 #define RX128_INT_EN (1 << 15) /* 8111c and later */
191 #define RX_MULTI_EN (1 << 14) /* 8111c only */
192 #define RXCFG_FIFO_SHIFT 13
193 /* No threshold before first PCI xfer */
194 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
195 #define RX_EARLY_OFF (1 << 11)
196 #define RXCFG_DMA_SHIFT 8
197 /* Unlimited maximum PCI burst. */
198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
204 #define PME_SIGNAL (1 << 5) /* 8168c and later */
215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
220 #define RTL_COALESCE_T_MAX 0x0fU
221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
231 #define TxPacketMax (8064 >> 7)
232 #define EarlySize 0x27
235 FuncEventMask = 0xf4,
236 FuncPresetState = 0xf8,
241 FuncForceEvent = 0xfc,
244 enum rtl8168_8101_registers {
247 #define CSIAR_FLAG 0x80000000
248 #define CSIAR_WRITE_CMD 0x80000000
249 #define CSIAR_BYTE_ENABLE 0x0000f000
250 #define CSIAR_ADDR_MASK 0x00000fff
252 #define D3COLD_NO_PLL_DOWN BIT(7)
253 #define D3HOT_NO_PLL_DOWN BIT(6)
254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
256 #define EPHYAR_FLAG 0x80000000
257 #define EPHYAR_WRITE_CMD 0x80000000
258 #define EPHYAR_REG_MASK 0x1f
259 #define EPHYAR_REG_SHIFT 16
260 #define EPHYAR_DATA_MASK 0xffff
262 #define PFM_EN (1 << 6)
263 #define TX_10M_PS_EN (1 << 7)
265 #define FIX_NAK_1 (1 << 4)
266 #define FIX_NAK_2 (1 << 3)
269 #define NOW_IS_OOB (1 << 7)
270 #define TX_EMPTY (1 << 5)
271 #define RX_EMPTY (1 << 4)
272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
273 #define EN_NDP (1 << 3)
274 #define EN_OOB_RESET (1 << 2)
275 #define LINK_LIST_RDY (1 << 1)
277 #define EFUSEAR_FLAG 0x80000000
278 #define EFUSEAR_WRITE_CMD 0x80000000
279 #define EFUSEAR_READ_CMD 0x00000000
280 #define EFUSEAR_REG_MASK 0x03ff
281 #define EFUSEAR_REG_SHIFT 8
282 #define EFUSEAR_DATA_MASK 0xff
284 #define PFM_D3COLD_EN (1 << 6)
287 enum rtl8168_registers {
292 #define ERIAR_FLAG 0x80000000
293 #define ERIAR_WRITE_CMD 0x80000000
294 #define ERIAR_READ_CMD 0x00000000
295 #define ERIAR_ADDR_BYTE_ALIGN 4
296 #define ERIAR_TYPE_SHIFT 16
297 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
298 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
299 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
300 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
301 #define ERIAR_MASK_SHIFT 12
302 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
303 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
304 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
305 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
306 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
307 EPHY_RXER_NUM = 0x7c,
308 OCPDR = 0xb0, /* OCP GPHY access */
309 #define OCPDR_WRITE_CMD 0x80000000
310 #define OCPDR_READ_CMD 0x00000000
311 #define OCPDR_REG_MASK 0x7f
312 #define OCPDR_GPHY_REG_SHIFT 16
313 #define OCPDR_DATA_MASK 0xffff
315 #define OCPAR_FLAG 0x80000000
316 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
317 #define OCPAR_GPHY_READ_CMD 0x0000f060
319 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
320 MISC = 0xf0, /* 8168e only. */
321 #define TXPLA_RST (1 << 29)
322 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
323 #define PWM_EN (1 << 22)
324 #define RXDV_GATED_EN (1 << 19)
325 #define EARLY_TALLY_EN (1 << 16)
328 enum rtl8125_registers {
329 IntrMask_8125 = 0x38,
330 IntrStatus_8125 = 0x3c,
333 EEE_TXIDLE_TIMER_8125 = 0x6048,
336 #define RX_VLAN_INNER_8125 BIT(22)
337 #define RX_VLAN_OUTER_8125 BIT(23)
338 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
340 #define RX_FETCH_DFLT_8125 (8 << 27)
342 enum rtl_register_content {
343 /* InterruptStatusBits */
347 TxDescUnavail = 0x0080,
369 /* TXPoll register p.5 */
370 HPQ = 0x80, /* Poll cmd on the high prio queue */
371 NPQ = 0x40, /* Poll cmd on the low prio queue */
372 FSWInt = 0x01, /* Forced software interrupt */
376 Cfg9346_Unlock = 0xc0,
381 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
382 AcceptBroadcast = 0x08,
383 AcceptMulticast = 0x04,
385 AcceptAllPhys = 0x01,
386 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
387 #define RX_CONFIG_ACCEPT_MASK 0x3f
390 TxInterFrameGapShift = 24,
391 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
393 /* Config1 register p.24 */
396 Speed_down = (1 << 4),
400 PMEnable = (1 << 0), /* Power Management Enable */
402 /* Config2 register p. 25 */
403 ClkReqEn = (1 << 7), /* Clock Request Enable */
404 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
405 PCI_Clock_66MHz = 0x01,
406 PCI_Clock_33MHz = 0x00,
408 /* Config3 register p.25 */
409 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
410 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
411 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
412 Rdy_to_L23 = (1 << 1), /* L23 Enable */
413 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
415 /* Config4 register */
416 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
418 /* Config5 register p.27 */
419 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
420 MWF = (1 << 5), /* Accept Multicast wakeup frame */
421 UWF = (1 << 4), /* Accept Unicast wakeup frame */
423 LanWake = (1 << 1), /* LanWake enable/disable */
424 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
425 ASPM_en = (1 << 0), /* ASPM enable */
428 EnableBist = (1 << 15), // 8168 8101
429 Mac_dbgo_oe = (1 << 14), // 8168 8101
430 EnAnaPLL = (1 << 14), // 8169
431 Normal_mode = (1 << 13), // unused
432 Force_half_dup = (1 << 12), // 8168 8101
433 Force_rxflow_en = (1 << 11), // 8168 8101
434 Force_txflow_en = (1 << 10), // 8168 8101
435 Cxpl_dbg_sel = (1 << 9), // 8168 8101
436 ASF = (1 << 8), // 8168 8101
437 PktCntrDisable = (1 << 7), // 8168 8101
438 Mac_dbgo_sel = 0x001c, // 8168
443 #define INTT_MASK GENMASK(1, 0)
444 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
446 /* rtl8169_PHYstatus */
456 /* ResetCounterCommand */
459 /* DumpCounterCommand */
462 /* magic enable v2 */
463 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
467 /* First doubleword. */
468 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
469 RingEnd = (1 << 30), /* End of descriptor ring */
470 FirstFrag = (1 << 29), /* First segment of a packet */
471 LastFrag = (1 << 28), /* Final segment of a packet */
475 enum rtl_tx_desc_bit {
476 /* First doubleword. */
477 TD_LSO = (1 << 27), /* Large Send Offload */
478 #define TD_MSS_MAX 0x07ffu /* MSS value */
480 /* Second doubleword. */
481 TxVlanTag = (1 << 17), /* Add VLAN tag */
484 /* 8169, 8168b and 810x except 8102e. */
485 enum rtl_tx_desc_bit_0 {
486 /* First doubleword. */
487 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
488 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
489 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
490 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
493 /* 8102e, 8168c and beyond. */
494 enum rtl_tx_desc_bit_1 {
495 /* First doubleword. */
496 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
497 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
498 #define GTTCPHO_SHIFT 18
499 #define GTTCPHO_MAX 0x7f
501 /* Second doubleword. */
502 #define TCPHO_SHIFT 18
503 #define TCPHO_MAX 0x3ff
504 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
505 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
506 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
511 enum rtl_rx_desc_bit {
513 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
514 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
516 #define RxProtoUDP (PID1)
517 #define RxProtoTCP (PID0)
518 #define RxProtoIP (PID1 | PID0)
519 #define RxProtoMask RxProtoIP
521 IPFail = (1 << 16), /* IP checksum failed */
522 UDPFail = (1 << 15), /* UDP/IP checksum failed */
523 TCPFail = (1 << 14), /* TCP/IP checksum failed */
525 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
527 RxVlanTag = (1 << 16), /* VLAN tag available */
530 #define RTL_GSO_MAX_SIZE_V1 32000
531 #define RTL_GSO_MAX_SEGS_V1 24
532 #define RTL_GSO_MAX_SIZE_V2 64000
533 #define RTL_GSO_MAX_SEGS_V2 64
552 struct rtl8169_counters {
559 __le32 tx_one_collision;
560 __le32 tx_multi_collision;
568 struct rtl8169_tc_offsets {
571 __le32 tx_multi_collision;
577 RTL_FLAG_TASK_ENABLED = 0,
578 RTL_FLAG_TASK_RESET_PENDING,
588 struct rtl8169_private {
589 void __iomem *mmio_addr; /* memory map physical address */
590 struct pci_dev *pci_dev;
591 struct net_device *dev;
592 struct phy_device *phydev;
593 struct napi_struct napi;
594 enum mac_version mac_version;
595 enum rtl_dash_type dash_type;
596 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
597 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
599 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
600 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
601 dma_addr_t TxPhyAddr;
602 dma_addr_t RxPhyAddr;
603 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
604 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
611 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
612 struct work_struct work;
615 unsigned supports_gmii:1;
616 unsigned aspm_manageable:1;
617 dma_addr_t counters_phys_addr;
618 struct rtl8169_counters *counters;
619 struct rtl8169_tc_offsets tc_offset;
624 struct rtl_fw *rtl_fw;
629 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
631 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
632 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
633 MODULE_SOFTDEP("pre: realtek");
634 MODULE_LICENSE("GPL");
635 MODULE_FIRMWARE(FIRMWARE_8168D_1);
636 MODULE_FIRMWARE(FIRMWARE_8168D_2);
637 MODULE_FIRMWARE(FIRMWARE_8168E_1);
638 MODULE_FIRMWARE(FIRMWARE_8168E_2);
639 MODULE_FIRMWARE(FIRMWARE_8168E_3);
640 MODULE_FIRMWARE(FIRMWARE_8105E_1);
641 MODULE_FIRMWARE(FIRMWARE_8168F_1);
642 MODULE_FIRMWARE(FIRMWARE_8168F_2);
643 MODULE_FIRMWARE(FIRMWARE_8402_1);
644 MODULE_FIRMWARE(FIRMWARE_8411_1);
645 MODULE_FIRMWARE(FIRMWARE_8411_2);
646 MODULE_FIRMWARE(FIRMWARE_8106E_1);
647 MODULE_FIRMWARE(FIRMWARE_8106E_2);
648 MODULE_FIRMWARE(FIRMWARE_8168G_2);
649 MODULE_FIRMWARE(FIRMWARE_8168G_3);
650 MODULE_FIRMWARE(FIRMWARE_8168H_2);
651 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
652 MODULE_FIRMWARE(FIRMWARE_8107E_2);
653 MODULE_FIRMWARE(FIRMWARE_8125A_3);
654 MODULE_FIRMWARE(FIRMWARE_8125B_2);
656 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
658 return &tp->pci_dev->dev;
661 static void rtl_lock_config_regs(struct rtl8169_private *tp)
663 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
666 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
668 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
671 static void rtl_pci_commit(struct rtl8169_private *tp)
673 /* Read an arbitrary register to commit a preceding PCI write */
677 static bool rtl_is_8125(struct rtl8169_private *tp)
679 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
682 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
684 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
685 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
686 tp->mac_version <= RTL_GIGA_MAC_VER_53;
689 static bool rtl_supports_eee(struct rtl8169_private *tp)
691 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
692 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
693 tp->mac_version != RTL_GIGA_MAC_VER_39;
696 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
700 for (i = 0; i < ETH_ALEN; i++)
701 mac[i] = RTL_R8(tp, reg + i);
705 bool (*check)(struct rtl8169_private *);
709 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
710 unsigned long usecs, int n, bool high)
714 for (i = 0; i < n; i++) {
715 if (c->check(tp) == high)
721 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
722 c->msg, !high, n, usecs);
726 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
727 const struct rtl_cond *c,
728 unsigned long d, int n)
730 return rtl_loop_wait(tp, c, d, n, true);
733 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
734 const struct rtl_cond *c,
735 unsigned long d, int n)
737 return rtl_loop_wait(tp, c, d, n, false);
740 #define DECLARE_RTL_COND(name) \
741 static bool name ## _check(struct rtl8169_private *); \
743 static const struct rtl_cond name = { \
744 .check = name ## _check, \
748 static bool name ## _check(struct rtl8169_private *tp)
750 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
752 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
753 if (type == ERIAR_OOB &&
754 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
755 tp->mac_version == RTL_GIGA_MAC_VER_53))
759 DECLARE_RTL_COND(rtl_eriar_cond)
761 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
764 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
767 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
769 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
772 RTL_W32(tp, ERIDR, val);
773 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
774 RTL_W32(tp, ERIAR, cmd);
776 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
779 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
782 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
785 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
787 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
789 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
790 RTL_W32(tp, ERIAR, cmd);
792 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
793 RTL_R32(tp, ERIDR) : ~0;
796 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
798 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
801 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
803 u32 val = rtl_eri_read(tp, addr);
805 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
808 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
810 rtl_w0w1_eri(tp, addr, p, 0);
813 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
815 rtl_w0w1_eri(tp, addr, 0, m);
818 static bool rtl_ocp_reg_failure(u32 reg)
820 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
823 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
825 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
828 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
830 if (rtl_ocp_reg_failure(reg))
833 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
835 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
838 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
840 if (rtl_ocp_reg_failure(reg))
843 RTL_W32(tp, GPHY_OCP, reg << 15);
845 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
846 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
849 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
851 if (rtl_ocp_reg_failure(reg))
854 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
857 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
859 if (rtl_ocp_reg_failure(reg))
862 RTL_W32(tp, OCPDR, reg << 15);
864 return RTL_R32(tp, OCPDR);
867 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
870 u16 data = r8168_mac_ocp_read(tp, reg);
872 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
875 /* Work around a hw issue with RTL8168g PHY, the quirk disables
876 * PHY MCU interrupts before PHY power-down.
878 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
880 switch (tp->mac_version) {
881 case RTL_GIGA_MAC_VER_40:
882 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
883 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
885 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
892 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
895 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
899 if (tp->ocp_base != OCP_STD_PHY_BASE)
902 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
903 rtl8168g_phy_suspend_quirk(tp, value);
905 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
908 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
911 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
913 if (tp->ocp_base != OCP_STD_PHY_BASE)
916 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
919 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
922 tp->ocp_base = value << 4;
926 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
929 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
931 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
934 DECLARE_RTL_COND(rtl_phyar_cond)
936 return RTL_R32(tp, PHYAR) & 0x80000000;
939 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
941 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
943 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
945 * According to hardware specs a 20us delay is required after write
946 * complete indication, but before sending next command.
951 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
955 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
957 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
958 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
961 * According to hardware specs a 20us delay is required after read
962 * complete indication, but before sending next command.
969 DECLARE_RTL_COND(rtl_ocpar_cond)
971 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
974 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
976 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
978 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
981 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
983 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
986 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
988 r8168dp_2_mdio_start(tp);
990 r8169_mdio_write(tp, reg, value);
992 r8168dp_2_mdio_stop(tp);
995 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
999 /* Work around issue with chip reporting wrong PHY ID */
1000 if (reg == MII_PHYSID2)
1003 r8168dp_2_mdio_start(tp);
1005 value = r8169_mdio_read(tp, reg);
1007 r8168dp_2_mdio_stop(tp);
1012 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1014 switch (tp->mac_version) {
1015 case RTL_GIGA_MAC_VER_28:
1016 case RTL_GIGA_MAC_VER_31:
1017 r8168dp_2_mdio_write(tp, location, val);
1019 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1020 r8168g_mdio_write(tp, location, val);
1023 r8169_mdio_write(tp, location, val);
1028 static int rtl_readphy(struct rtl8169_private *tp, int location)
1030 switch (tp->mac_version) {
1031 case RTL_GIGA_MAC_VER_28:
1032 case RTL_GIGA_MAC_VER_31:
1033 return r8168dp_2_mdio_read(tp, location);
1034 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1035 return r8168g_mdio_read(tp, location);
1037 return r8169_mdio_read(tp, location);
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1043 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1051 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1060 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1064 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1066 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1067 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1068 RTL_R32(tp, OCPDR) : ~0;
1071 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1073 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1076 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1079 RTL_W32(tp, OCPDR, data);
1080 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1081 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1084 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1087 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1091 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1093 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1095 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1098 #define OOB_CMD_RESET 0x00
1099 #define OOB_CMD_DRIVER_START 0x05
1100 #define OOB_CMD_DRIVER_STOP 0x06
1102 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1104 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1107 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1111 reg = rtl8168_get_ocp_reg(tp);
1113 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1116 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1118 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1121 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1123 return RTL_R8(tp, IBISR0) & 0x20;
1126 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1128 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1129 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1130 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1131 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1134 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1136 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1137 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1140 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1142 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1143 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1144 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1147 static void rtl8168_driver_start(struct rtl8169_private *tp)
1149 if (tp->dash_type == RTL_DASH_DP)
1150 rtl8168dp_driver_start(tp);
1152 rtl8168ep_driver_start(tp);
1155 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1157 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1158 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1161 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1163 rtl8168ep_stop_cmac(tp);
1164 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1165 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1166 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1169 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1171 if (tp->dash_type == RTL_DASH_DP)
1172 rtl8168dp_driver_stop(tp);
1174 rtl8168ep_driver_stop(tp);
1177 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1179 u16 reg = rtl8168_get_ocp_reg(tp);
1181 return r8168dp_ocp_read(tp, reg) & BIT(15);
1184 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1186 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1189 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1191 switch (tp->mac_version) {
1192 case RTL_GIGA_MAC_VER_28:
1193 case RTL_GIGA_MAC_VER_31:
1194 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1195 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1196 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1198 return RTL_DASH_NONE;
1202 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1204 switch (tp->mac_version) {
1205 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1206 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1207 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1208 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1210 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1212 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1219 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1221 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1222 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1225 DECLARE_RTL_COND(rtl_efusear_cond)
1227 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1230 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1232 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1234 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1235 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1238 static u32 rtl_get_events(struct rtl8169_private *tp)
1240 if (rtl_is_8125(tp))
1241 return RTL_R32(tp, IntrStatus_8125);
1243 return RTL_R16(tp, IntrStatus);
1246 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1248 if (rtl_is_8125(tp))
1249 RTL_W32(tp, IntrStatus_8125, bits);
1251 RTL_W16(tp, IntrStatus, bits);
1254 static void rtl_irq_disable(struct rtl8169_private *tp)
1256 if (rtl_is_8125(tp))
1257 RTL_W32(tp, IntrMask_8125, 0);
1259 RTL_W16(tp, IntrMask, 0);
1262 static void rtl_irq_enable(struct rtl8169_private *tp)
1264 if (rtl_is_8125(tp))
1265 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1267 RTL_W16(tp, IntrMask, tp->irq_mask);
1270 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1272 rtl_irq_disable(tp);
1273 rtl_ack_events(tp, 0xffffffff);
1277 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1279 struct phy_device *phydev = tp->phydev;
1281 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1282 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1283 if (phydev->speed == SPEED_1000) {
1284 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1285 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1286 } else if (phydev->speed == SPEED_100) {
1287 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1288 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1290 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1291 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1293 rtl_reset_packet_filter(tp);
1294 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1295 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1296 if (phydev->speed == SPEED_1000) {
1297 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1298 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1300 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1301 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1303 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1304 if (phydev->speed == SPEED_10) {
1305 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1306 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1308 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1313 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1315 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1317 struct rtl8169_private *tp = netdev_priv(dev);
1319 wol->supported = WAKE_ANY;
1320 wol->wolopts = tp->saved_wolopts;
1323 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1325 static const struct {
1330 { WAKE_PHY, Config3, LinkUp },
1331 { WAKE_UCAST, Config5, UWF },
1332 { WAKE_BCAST, Config5, BWF },
1333 { WAKE_MCAST, Config5, MWF },
1334 { WAKE_ANY, Config5, LanWake },
1335 { WAKE_MAGIC, Config3, MagicPacket }
1337 unsigned int i, tmp = ARRAY_SIZE(cfg);
1340 rtl_unlock_config_regs(tp);
1342 if (rtl_is_8168evl_up(tp)) {
1344 if (wolopts & WAKE_MAGIC)
1345 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1347 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1348 } else if (rtl_is_8125(tp)) {
1350 if (wolopts & WAKE_MAGIC)
1351 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1353 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1356 for (i = 0; i < tmp; i++) {
1357 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1358 if (wolopts & cfg[i].opt)
1359 options |= cfg[i].mask;
1360 RTL_W8(tp, cfg[i].reg, options);
1363 switch (tp->mac_version) {
1364 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1365 options = RTL_R8(tp, Config1) & ~PMEnable;
1367 options |= PMEnable;
1368 RTL_W8(tp, Config1, options);
1370 case RTL_GIGA_MAC_VER_34:
1371 case RTL_GIGA_MAC_VER_37:
1372 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1373 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1375 options |= PME_SIGNAL;
1376 RTL_W8(tp, Config2, options);
1382 rtl_lock_config_regs(tp);
1384 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1386 if (tp->dash_type == RTL_DASH_NONE) {
1387 rtl_set_d3_pll_down(tp, !wolopts);
1388 tp->dev->wol_enabled = wolopts ? 1 : 0;
1392 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1394 struct rtl8169_private *tp = netdev_priv(dev);
1396 if (wol->wolopts & ~WAKE_ANY)
1399 tp->saved_wolopts = wol->wolopts;
1400 __rtl8169_set_wol(tp, tp->saved_wolopts);
1405 static void rtl8169_get_drvinfo(struct net_device *dev,
1406 struct ethtool_drvinfo *info)
1408 struct rtl8169_private *tp = netdev_priv(dev);
1409 struct rtl_fw *rtl_fw = tp->rtl_fw;
1411 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1412 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1413 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1415 strscpy(info->fw_version, rtl_fw->version,
1416 sizeof(info->fw_version));
1419 static int rtl8169_get_regs_len(struct net_device *dev)
1421 return R8169_REGS_SIZE;
1424 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1425 netdev_features_t features)
1427 struct rtl8169_private *tp = netdev_priv(dev);
1429 if (dev->mtu > TD_MSS_MAX)
1430 features &= ~NETIF_F_ALL_TSO;
1432 if (dev->mtu > ETH_DATA_LEN &&
1433 tp->mac_version > RTL_GIGA_MAC_VER_06)
1434 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1439 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1440 netdev_features_t features)
1442 u32 rx_config = RTL_R32(tp, RxConfig);
1444 if (features & NETIF_F_RXALL)
1445 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1447 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1449 if (rtl_is_8125(tp)) {
1450 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1451 rx_config |= RX_VLAN_8125;
1453 rx_config &= ~RX_VLAN_8125;
1456 RTL_W32(tp, RxConfig, rx_config);
1459 static int rtl8169_set_features(struct net_device *dev,
1460 netdev_features_t features)
1462 struct rtl8169_private *tp = netdev_priv(dev);
1464 rtl_set_rx_config_features(tp, features);
1466 if (features & NETIF_F_RXCSUM)
1467 tp->cp_cmd |= RxChkSum;
1469 tp->cp_cmd &= ~RxChkSum;
1471 if (!rtl_is_8125(tp)) {
1472 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1473 tp->cp_cmd |= RxVlan;
1475 tp->cp_cmd &= ~RxVlan;
1478 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1484 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1486 return (skb_vlan_tag_present(skb)) ?
1487 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1490 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1492 u32 opts2 = le32_to_cpu(desc->opts2);
1494 if (opts2 & RxVlanTag)
1495 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1498 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1501 struct rtl8169_private *tp = netdev_priv(dev);
1502 u32 __iomem *data = tp->mmio_addr;
1506 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1507 memcpy_fromio(dw++, data++, 4);
1510 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1517 "tx_single_collisions",
1518 "tx_multi_collisions",
1526 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1530 return ARRAY_SIZE(rtl8169_gstrings);
1536 DECLARE_RTL_COND(rtl_counters_cond)
1538 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1541 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1543 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1545 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1547 RTL_W32(tp, CounterAddrLow, cmd);
1548 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1550 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1553 static void rtl8169_update_counters(struct rtl8169_private *tp)
1555 u8 val = RTL_R8(tp, ChipCmd);
1558 * Some chips are unable to dump tally counters when the receiver
1559 * is disabled. If 0xff chip may be in a PCI power-save state.
1561 if (val & CmdRxEnb && val != 0xff)
1562 rtl8169_do_counters(tp, CounterDump);
1565 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1567 struct rtl8169_counters *counters = tp->counters;
1570 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1571 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1572 * reset by a power cycle, while the counter values collected by the
1573 * driver are reset at every driver unload/load cycle.
1575 * To make sure the HW values returned by @get_stats64 match the SW
1576 * values, we collect the initial values at first open(*) and use them
1577 * as offsets to normalize the values returned by @get_stats64.
1579 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1580 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1581 * set at open time by rtl_hw_start.
1584 if (tp->tc_offset.inited)
1587 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1588 rtl8169_do_counters(tp, CounterReset);
1590 rtl8169_update_counters(tp);
1591 tp->tc_offset.tx_errors = counters->tx_errors;
1592 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1593 tp->tc_offset.tx_aborted = counters->tx_aborted;
1594 tp->tc_offset.rx_missed = counters->rx_missed;
1597 tp->tc_offset.inited = true;
1600 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1601 struct ethtool_stats *stats, u64 *data)
1603 struct rtl8169_private *tp = netdev_priv(dev);
1604 struct rtl8169_counters *counters;
1606 counters = tp->counters;
1607 rtl8169_update_counters(tp);
1609 data[0] = le64_to_cpu(counters->tx_packets);
1610 data[1] = le64_to_cpu(counters->rx_packets);
1611 data[2] = le64_to_cpu(counters->tx_errors);
1612 data[3] = le32_to_cpu(counters->rx_errors);
1613 data[4] = le16_to_cpu(counters->rx_missed);
1614 data[5] = le16_to_cpu(counters->align_errors);
1615 data[6] = le32_to_cpu(counters->tx_one_collision);
1616 data[7] = le32_to_cpu(counters->tx_multi_collision);
1617 data[8] = le64_to_cpu(counters->rx_unicast);
1618 data[9] = le64_to_cpu(counters->rx_broadcast);
1619 data[10] = le32_to_cpu(counters->rx_multicast);
1620 data[11] = le16_to_cpu(counters->tx_aborted);
1621 data[12] = le16_to_cpu(counters->tx_underun);
1624 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1628 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1634 * Interrupt coalescing
1636 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1637 * > 8169, 8168 and 810x line of chipsets
1639 * 8169, 8168, and 8136(810x) serial chipsets support it.
1641 * > 2 - the Tx timer unit at gigabit speed
1643 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1644 * (0xe0) bit 1 and bit 0.
1647 * bit[1:0] \ speed 1000M 100M 10M
1648 * 0 0 320ns 2.56us 40.96us
1649 * 0 1 2.56us 20.48us 327.7us
1650 * 1 0 5.12us 40.96us 655.4us
1651 * 1 1 10.24us 81.92us 1.31ms
1654 * bit[1:0] \ speed 1000M 100M 10M
1655 * 0 0 5us 2.56us 40.96us
1656 * 0 1 40us 20.48us 327.7us
1657 * 1 0 80us 40.96us 655.4us
1658 * 1 1 160us 81.92us 1.31ms
1661 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1662 struct rtl_coalesce_info {
1667 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1668 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1670 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1671 { SPEED_1000, COALESCE_DELAY(320) },
1672 { SPEED_100, COALESCE_DELAY(2560) },
1673 { SPEED_10, COALESCE_DELAY(40960) },
1677 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1678 { SPEED_1000, COALESCE_DELAY(5000) },
1679 { SPEED_100, COALESCE_DELAY(2560) },
1680 { SPEED_10, COALESCE_DELAY(40960) },
1683 #undef COALESCE_DELAY
1685 /* get rx/tx scale vector corresponding to current speed */
1686 static const struct rtl_coalesce_info *
1687 rtl_coalesce_info(struct rtl8169_private *tp)
1689 const struct rtl_coalesce_info *ci;
1691 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1692 ci = rtl_coalesce_info_8169;
1694 ci = rtl_coalesce_info_8168_8136;
1696 /* if speed is unknown assume highest one */
1697 if (tp->phydev->speed == SPEED_UNKNOWN)
1700 for (; ci->speed; ci++) {
1701 if (tp->phydev->speed == ci->speed)
1705 return ERR_PTR(-ELNRNG);
1708 static int rtl_get_coalesce(struct net_device *dev,
1709 struct ethtool_coalesce *ec,
1710 struct kernel_ethtool_coalesce *kernel_coal,
1711 struct netlink_ext_ack *extack)
1713 struct rtl8169_private *tp = netdev_priv(dev);
1714 const struct rtl_coalesce_info *ci;
1715 u32 scale, c_us, c_fr;
1718 if (rtl_is_8125(tp))
1721 memset(ec, 0, sizeof(*ec));
1723 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1724 ci = rtl_coalesce_info(tp);
1728 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1730 intrmit = RTL_R16(tp, IntrMitigate);
1732 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1733 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1735 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1736 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1737 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1739 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1740 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1742 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1743 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1748 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1749 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1752 const struct rtl_coalesce_info *ci;
1755 ci = rtl_coalesce_info(tp);
1759 for (i = 0; i < 4; i++) {
1760 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1762 return ci->scale_nsecs[i];
1769 static int rtl_set_coalesce(struct net_device *dev,
1770 struct ethtool_coalesce *ec,
1771 struct kernel_ethtool_coalesce *kernel_coal,
1772 struct netlink_ext_ack *extack)
1774 struct rtl8169_private *tp = netdev_priv(dev);
1775 u32 tx_fr = ec->tx_max_coalesced_frames;
1776 u32 rx_fr = ec->rx_max_coalesced_frames;
1777 u32 coal_usec_max, units;
1778 u16 w = 0, cp01 = 0;
1781 if (rtl_is_8125(tp))
1784 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1787 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1788 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1792 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1793 * not only when usecs=0 because of e.g. the following scenario:
1795 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1796 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1797 * - then user does `ethtool -C eth0 rx-usecs 100`
1799 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1800 * if we want to ignore rx_frames then it has to be set to 0.
1807 /* HW requires time limit to be set if frame limit is set */
1808 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1809 (rx_fr && !ec->rx_coalesce_usecs))
1812 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1813 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1815 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1816 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1817 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1818 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1820 RTL_W16(tp, IntrMitigate, w);
1822 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1823 if (rtl_is_8168evl_up(tp)) {
1824 if (!rx_fr && !tx_fr)
1825 /* disable packet counter */
1826 tp->cp_cmd |= PktCntrDisable;
1828 tp->cp_cmd &= ~PktCntrDisable;
1831 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1832 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1838 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1840 struct rtl8169_private *tp = netdev_priv(dev);
1842 if (!rtl_supports_eee(tp))
1845 return phy_ethtool_get_eee(tp->phydev, data);
1848 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1850 struct rtl8169_private *tp = netdev_priv(dev);
1853 if (!rtl_supports_eee(tp))
1856 ret = phy_ethtool_set_eee(tp->phydev, data);
1859 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1864 static void rtl8169_get_ringparam(struct net_device *dev,
1865 struct ethtool_ringparam *data,
1866 struct kernel_ethtool_ringparam *kernel_data,
1867 struct netlink_ext_ack *extack)
1869 data->rx_max_pending = NUM_RX_DESC;
1870 data->rx_pending = NUM_RX_DESC;
1871 data->tx_max_pending = NUM_TX_DESC;
1872 data->tx_pending = NUM_TX_DESC;
1875 static void rtl8169_get_pauseparam(struct net_device *dev,
1876 struct ethtool_pauseparam *data)
1878 struct rtl8169_private *tp = netdev_priv(dev);
1879 bool tx_pause, rx_pause;
1881 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1883 data->autoneg = tp->phydev->autoneg;
1884 data->tx_pause = tx_pause ? 1 : 0;
1885 data->rx_pause = rx_pause ? 1 : 0;
1888 static int rtl8169_set_pauseparam(struct net_device *dev,
1889 struct ethtool_pauseparam *data)
1891 struct rtl8169_private *tp = netdev_priv(dev);
1893 if (dev->mtu > ETH_DATA_LEN)
1896 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1901 static const struct ethtool_ops rtl8169_ethtool_ops = {
1902 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1903 ETHTOOL_COALESCE_MAX_FRAMES,
1904 .get_drvinfo = rtl8169_get_drvinfo,
1905 .get_regs_len = rtl8169_get_regs_len,
1906 .get_link = ethtool_op_get_link,
1907 .get_coalesce = rtl_get_coalesce,
1908 .set_coalesce = rtl_set_coalesce,
1909 .get_regs = rtl8169_get_regs,
1910 .get_wol = rtl8169_get_wol,
1911 .set_wol = rtl8169_set_wol,
1912 .get_strings = rtl8169_get_strings,
1913 .get_sset_count = rtl8169_get_sset_count,
1914 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1915 .get_ts_info = ethtool_op_get_ts_info,
1916 .nway_reset = phy_ethtool_nway_reset,
1917 .get_eee = rtl8169_get_eee,
1918 .set_eee = rtl8169_set_eee,
1919 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1920 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1921 .get_ringparam = rtl8169_get_ringparam,
1922 .get_pauseparam = rtl8169_get_pauseparam,
1923 .set_pauseparam = rtl8169_set_pauseparam,
1926 static void rtl_enable_eee(struct rtl8169_private *tp)
1928 struct phy_device *phydev = tp->phydev;
1931 /* respect EEE advertisement the user may have set */
1932 if (tp->eee_adv >= 0)
1935 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1938 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1941 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1944 * The driver currently handles the 8168Bf and the 8168Be identically
1945 * but they can be identified more specifically through the test below
1948 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1950 * Same thing for the 8101Eb and the 8101Ec:
1952 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1954 static const struct rtl_mac_info {
1957 enum mac_version ver;
1960 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1963 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
1964 /* It seems only XID 609 made it to the mass market.
1965 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1966 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1970 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
1971 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1973 /* 8168EP family. */
1974 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1975 /* It seems this chip version never made it to
1976 * the wild. Let's disable detection.
1977 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1978 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1982 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1983 /* It seems this chip version never made it to
1984 * the wild. Let's disable detection.
1985 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1989 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1990 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1991 /* It seems this chip version never made it to
1992 * the wild. Let's disable detection.
1993 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1995 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1998 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1999 /* It seems this chip version never made it to
2000 * the wild. Let's disable detection.
2001 * { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2003 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2006 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2007 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2008 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2011 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2012 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2014 /* 8168DP family. */
2015 /* It seems this early RTL8168dp version never made it to
2016 * the wild. Support has been removed.
2017 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2019 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2020 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2023 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2024 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2025 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2026 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2027 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2028 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2029 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2032 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2033 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2036 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2037 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2038 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2039 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2040 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2041 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2042 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2043 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2044 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2045 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2046 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2047 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2050 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2051 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2052 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2053 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2054 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2057 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2059 const struct rtl_mac_info *p = mac_info;
2060 enum mac_version ver;
2062 while ((xid & p->mask) != p->val)
2066 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2067 if (ver == RTL_GIGA_MAC_VER_42)
2068 ver = RTL_GIGA_MAC_VER_43;
2069 else if (ver == RTL_GIGA_MAC_VER_46)
2070 ver = RTL_GIGA_MAC_VER_48;
2076 static void rtl_release_firmware(struct rtl8169_private *tp)
2079 rtl_fw_release_firmware(tp->rtl_fw);
2085 void r8169_apply_firmware(struct rtl8169_private *tp)
2089 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2091 rtl_fw_write_firmware(tp, tp->rtl_fw);
2092 /* At least one firmware doesn't reset tp->ocp_base. */
2093 tp->ocp_base = OCP_STD_PHY_BASE;
2095 /* PHY soft reset may still be in progress */
2096 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2097 !(val & BMCR_RESET),
2098 50000, 600000, true);
2102 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2104 /* Adjust EEE LED frequency */
2105 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2106 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2108 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2111 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2113 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2114 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2117 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2119 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2122 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2124 rtl8125_set_eee_txidle_timer(tp);
2125 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2128 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2130 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2131 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2132 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2133 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2136 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2138 u16 data1, data2, ioffset;
2140 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2141 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2142 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2144 ioffset = (data2 >> 1) & 0x7ff8;
2145 ioffset |= data2 & 0x0007;
2152 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2154 set_bit(flag, tp->wk.flags);
2155 schedule_work(&tp->wk.work);
2158 static void rtl8169_init_phy(struct rtl8169_private *tp)
2160 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2162 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2163 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2164 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2165 /* set undocumented MAC Reg C+CR Offset 0x82h */
2166 RTL_W8(tp, 0x82, 0x01);
2169 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2170 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2171 tp->pci_dev->subsystem_device == 0xe000)
2172 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2174 /* We may have called phy_speed_down before */
2175 phy_speed_up(tp->phydev);
2177 if (rtl_supports_eee(tp))
2180 genphy_soft_reset(tp->phydev);
2183 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2185 rtl_unlock_config_regs(tp);
2187 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2190 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2193 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2194 rtl_rar_exgmac_set(tp, addr);
2196 rtl_lock_config_regs(tp);
2199 static int rtl_set_mac_address(struct net_device *dev, void *p)
2201 struct rtl8169_private *tp = netdev_priv(dev);
2204 ret = eth_mac_addr(dev, p);
2208 rtl_rar_set(tp, dev->dev_addr);
2213 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2215 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2216 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2217 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2220 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2222 if (tp->dash_type != RTL_DASH_NONE)
2225 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2226 tp->mac_version == RTL_GIGA_MAC_VER_33)
2227 rtl_ephy_write(tp, 0x19, 0xff64);
2229 if (device_may_wakeup(tp_to_dev(tp))) {
2230 phy_speed_down(tp->phydev, false);
2231 rtl_wol_enable_rx(tp);
2235 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2237 switch (tp->mac_version) {
2238 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2239 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2240 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2242 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2243 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2244 case RTL_GIGA_MAC_VER_38:
2245 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2247 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2248 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2250 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2251 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2254 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2259 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2261 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2264 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2266 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2267 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2270 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2272 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2273 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2276 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2278 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2281 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2283 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2286 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2288 RTL_W8(tp, MaxTxPacketSize, 0x24);
2289 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2290 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2293 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2295 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2296 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2297 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2300 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2302 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2305 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2310 static void rtl_jumbo_config(struct rtl8169_private *tp)
2312 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2315 rtl_unlock_config_regs(tp);
2316 switch (tp->mac_version) {
2317 case RTL_GIGA_MAC_VER_17:
2320 r8168b_1_hw_jumbo_enable(tp);
2322 r8168b_1_hw_jumbo_disable(tp);
2325 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2328 r8168c_hw_jumbo_enable(tp);
2330 r8168c_hw_jumbo_disable(tp);
2333 case RTL_GIGA_MAC_VER_28:
2335 r8168dp_hw_jumbo_enable(tp);
2337 r8168dp_hw_jumbo_disable(tp);
2339 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2341 r8168e_hw_jumbo_enable(tp);
2343 r8168e_hw_jumbo_disable(tp);
2348 rtl_lock_config_regs(tp);
2350 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2351 pcie_set_readrq(tp->pci_dev, readrq);
2353 /* Chip doesn't support pause in jumbo mode */
2355 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2356 tp->phydev->advertising);
2357 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2358 tp->phydev->advertising);
2359 phy_start_aneg(tp->phydev);
2363 DECLARE_RTL_COND(rtl_chipcmd_cond)
2365 return RTL_R8(tp, ChipCmd) & CmdReset;
2368 static void rtl_hw_reset(struct rtl8169_private *tp)
2370 RTL_W8(tp, ChipCmd, CmdReset);
2372 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2375 static void rtl_request_firmware(struct rtl8169_private *tp)
2377 struct rtl_fw *rtl_fw;
2379 /* firmware loaded already or no firmware available */
2380 if (tp->rtl_fw || !tp->fw_name)
2383 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2387 rtl_fw->phy_write = rtl_writephy;
2388 rtl_fw->phy_read = rtl_readphy;
2389 rtl_fw->mac_mcu_write = mac_mcu_write;
2390 rtl_fw->mac_mcu_read = mac_mcu_read;
2391 rtl_fw->fw_name = tp->fw_name;
2392 rtl_fw->dev = tp_to_dev(tp);
2394 if (rtl_fw_request_firmware(rtl_fw))
2397 tp->rtl_fw = rtl_fw;
2400 static void rtl_rx_close(struct rtl8169_private *tp)
2402 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2405 DECLARE_RTL_COND(rtl_npq_cond)
2407 return RTL_R8(tp, TxPoll) & NPQ;
2410 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2412 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2415 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2417 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2420 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2422 /* IntrMitigate has new functionality on RTL8125 */
2423 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2426 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2428 switch (tp->mac_version) {
2429 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2430 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2431 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2433 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2434 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2436 case RTL_GIGA_MAC_VER_63:
2437 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2438 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2439 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2446 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2448 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2450 rtl_wait_txrx_fifo_empty(tp);
2453 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2455 u32 val = TX_DMA_BURST << TxDMAShift |
2456 InterFrameGap << TxInterFrameGapShift;
2458 if (rtl_is_8168evl_up(tp))
2459 val |= TXCFG_AUTO_FIFO;
2461 RTL_W32(tp, TxConfig, val);
2464 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2466 /* Low hurts. Let's disable the filtering. */
2467 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2470 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2473 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2474 * register to be written before TxDescAddrLow to work.
2475 * Switching from MMIO to I/O access fixes the issue as well.
2477 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2478 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2479 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2480 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2483 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2487 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2489 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2494 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2497 RTL_W32(tp, 0x7c, val);
2500 static void rtl_set_rx_mode(struct net_device *dev)
2502 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2503 /* Multicast hash filter */
2504 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2505 struct rtl8169_private *tp = netdev_priv(dev);
2508 if (dev->flags & IFF_PROMISC) {
2509 rx_mode |= AcceptAllPhys;
2510 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2511 dev->flags & IFF_ALLMULTI ||
2512 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2513 /* accept all multicasts */
2514 } else if (netdev_mc_empty(dev)) {
2515 rx_mode &= ~AcceptMulticast;
2517 struct netdev_hw_addr *ha;
2519 mc_filter[1] = mc_filter[0] = 0;
2520 netdev_for_each_mc_addr(ha, dev) {
2521 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2522 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2525 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2527 mc_filter[0] = swab32(mc_filter[1]);
2528 mc_filter[1] = swab32(tmp);
2532 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2533 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2535 tmp = RTL_R32(tp, RxConfig);
2536 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2539 DECLARE_RTL_COND(rtl_csiar_cond)
2541 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2544 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2546 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2548 RTL_W32(tp, CSIDR, value);
2549 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2550 CSIAR_BYTE_ENABLE | func << 16);
2552 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2555 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2557 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2559 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2562 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2563 RTL_R32(tp, CSIDR) : ~0;
2566 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2568 struct pci_dev *pdev = tp->pci_dev;
2571 /* According to Realtek the value at config space address 0x070f
2572 * controls the L0s/L1 entrance latency. We try standard ECAM access
2573 * first and if it fails fall back to CSI.
2574 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2575 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2577 if (pdev->cfg_size > 0x070f &&
2578 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2581 netdev_notice_once(tp->dev,
2582 "No native access to PCI extended config space, falling back to CSI\n");
2583 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2584 rtl_csi_write(tp, 0x070c, csi | val << 24);
2587 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2589 /* L0 7us, L1 16us */
2590 rtl_set_aspm_entry_latency(tp, 0x27);
2594 unsigned int offset;
2599 static void __rtl_ephy_init(struct rtl8169_private *tp,
2600 const struct ephy_info *e, int len)
2605 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2606 rtl_ephy_write(tp, e->offset, w);
2611 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2613 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2615 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2616 PCI_EXP_LNKCTL_CLKREQ_EN);
2619 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2621 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2622 PCI_EXP_LNKCTL_CLKREQ_EN);
2625 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2627 /* work around an issue when PCI reset occurs during L2/L3 state */
2628 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2631 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2633 /* Bits control which events trigger ASPM L1 exit:
2636 * Bit 10: txdma_poll
2641 switch (tp->mac_version) {
2642 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2643 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2645 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2646 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2648 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2649 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2656 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2658 switch (tp->mac_version) {
2659 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2660 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2662 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2663 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2670 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2672 /* Don't enable ASPM in the chip if OS can't control ASPM */
2673 if (enable && tp->aspm_manageable) {
2674 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2675 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2677 switch (tp->mac_version) {
2678 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2679 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2680 /* reset ephy tx/rx disable timer */
2681 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2682 /* chip can trigger L1.2 */
2683 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2689 switch (tp->mac_version) {
2690 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2691 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2692 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2698 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2699 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2705 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2706 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2708 /* Usage of dynamic vs. static FIFO is controlled by bit
2709 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2711 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2712 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2715 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2718 /* FIFO thresholds for pause flow control */
2719 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2720 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2723 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2725 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2728 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2730 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2732 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2734 rtl_disable_clock_request(tp);
2737 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2739 static const struct ephy_info e_info_8168cp[] = {
2740 { 0x01, 0, 0x0001 },
2741 { 0x02, 0x0800, 0x1000 },
2742 { 0x03, 0, 0x0042 },
2743 { 0x06, 0x0080, 0x0000 },
2747 rtl_set_def_aspm_entry_latency(tp);
2749 rtl_ephy_init(tp, e_info_8168cp);
2751 __rtl_hw_start_8168cp(tp);
2754 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2756 rtl_set_def_aspm_entry_latency(tp);
2758 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2761 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2763 rtl_set_def_aspm_entry_latency(tp);
2765 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2768 RTL_W8(tp, DBG_REG, 0x20);
2771 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2773 static const struct ephy_info e_info_8168c_1[] = {
2774 { 0x02, 0x0800, 0x1000 },
2775 { 0x03, 0, 0x0002 },
2776 { 0x06, 0x0080, 0x0000 }
2779 rtl_set_def_aspm_entry_latency(tp);
2781 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2783 rtl_ephy_init(tp, e_info_8168c_1);
2785 __rtl_hw_start_8168cp(tp);
2788 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2790 static const struct ephy_info e_info_8168c_2[] = {
2791 { 0x01, 0, 0x0001 },
2792 { 0x03, 0x0400, 0x0020 }
2795 rtl_set_def_aspm_entry_latency(tp);
2797 rtl_ephy_init(tp, e_info_8168c_2);
2799 __rtl_hw_start_8168cp(tp);
2802 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2804 rtl_set_def_aspm_entry_latency(tp);
2806 __rtl_hw_start_8168cp(tp);
2809 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2811 rtl_set_def_aspm_entry_latency(tp);
2813 rtl_disable_clock_request(tp);
2816 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2818 static const struct ephy_info e_info_8168d_4[] = {
2819 { 0x0b, 0x0000, 0x0048 },
2820 { 0x19, 0x0020, 0x0050 },
2821 { 0x0c, 0x0100, 0x0020 },
2822 { 0x10, 0x0004, 0x0000 },
2825 rtl_set_def_aspm_entry_latency(tp);
2827 rtl_ephy_init(tp, e_info_8168d_4);
2829 rtl_enable_clock_request(tp);
2832 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2834 static const struct ephy_info e_info_8168e_1[] = {
2835 { 0x00, 0x0200, 0x0100 },
2836 { 0x00, 0x0000, 0x0004 },
2837 { 0x06, 0x0002, 0x0001 },
2838 { 0x06, 0x0000, 0x0030 },
2839 { 0x07, 0x0000, 0x2000 },
2840 { 0x00, 0x0000, 0x0020 },
2841 { 0x03, 0x5800, 0x2000 },
2842 { 0x03, 0x0000, 0x0001 },
2843 { 0x01, 0x0800, 0x1000 },
2844 { 0x07, 0x0000, 0x4000 },
2845 { 0x1e, 0x0000, 0x2000 },
2846 { 0x19, 0xffff, 0xfe6c },
2847 { 0x0a, 0x0000, 0x0040 }
2850 rtl_set_def_aspm_entry_latency(tp);
2852 rtl_ephy_init(tp, e_info_8168e_1);
2854 rtl_disable_clock_request(tp);
2856 /* Reset tx FIFO pointer */
2857 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2858 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2860 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2863 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2865 static const struct ephy_info e_info_8168e_2[] = {
2866 { 0x09, 0x0000, 0x0080 },
2867 { 0x19, 0x0000, 0x0224 },
2868 { 0x00, 0x0000, 0x0004 },
2869 { 0x0c, 0x3df0, 0x0200 },
2872 rtl_set_def_aspm_entry_latency(tp);
2874 rtl_ephy_init(tp, e_info_8168e_2);
2876 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2877 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2878 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2879 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2880 rtl_reset_packet_filter(tp);
2881 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2882 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2883 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2885 rtl_disable_clock_request(tp);
2887 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2889 rtl8168_config_eee_mac(tp);
2891 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2892 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2893 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2895 rtl_hw_aspm_clkreq_enable(tp, true);
2898 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2900 rtl_set_def_aspm_entry_latency(tp);
2902 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2903 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2904 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2905 rtl_reset_packet_filter(tp);
2906 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2907 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2908 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2909 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2911 rtl_disable_clock_request(tp);
2913 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2914 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2915 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2916 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2918 rtl8168_config_eee_mac(tp);
2921 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2923 static const struct ephy_info e_info_8168f_1[] = {
2924 { 0x06, 0x00c0, 0x0020 },
2925 { 0x08, 0x0001, 0x0002 },
2926 { 0x09, 0x0000, 0x0080 },
2927 { 0x19, 0x0000, 0x0224 },
2928 { 0x00, 0x0000, 0x0008 },
2929 { 0x0c, 0x3df0, 0x0200 },
2932 rtl_hw_start_8168f(tp);
2934 rtl_ephy_init(tp, e_info_8168f_1);
2937 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2939 static const struct ephy_info e_info_8168f_1[] = {
2940 { 0x06, 0x00c0, 0x0020 },
2941 { 0x0f, 0xffff, 0x5200 },
2942 { 0x19, 0x0000, 0x0224 },
2943 { 0x00, 0x0000, 0x0008 },
2944 { 0x0c, 0x3df0, 0x0200 },
2947 rtl_hw_start_8168f(tp);
2948 rtl_pcie_state_l2l3_disable(tp);
2950 rtl_ephy_init(tp, e_info_8168f_1);
2953 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2955 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2956 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2958 rtl_set_def_aspm_entry_latency(tp);
2960 rtl_reset_packet_filter(tp);
2961 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2963 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2965 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2966 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2968 rtl8168_config_eee_mac(tp);
2970 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2971 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2973 rtl_pcie_state_l2l3_disable(tp);
2976 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2978 static const struct ephy_info e_info_8168g_1[] = {
2979 { 0x00, 0x0008, 0x0000 },
2980 { 0x0c, 0x3ff0, 0x0820 },
2981 { 0x1e, 0x0000, 0x0001 },
2982 { 0x19, 0x8000, 0x0000 }
2985 rtl_hw_start_8168g(tp);
2987 /* disable aspm and clock request before access ephy */
2988 rtl_hw_aspm_clkreq_enable(tp, false);
2989 rtl_ephy_init(tp, e_info_8168g_1);
2990 rtl_hw_aspm_clkreq_enable(tp, true);
2993 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2995 static const struct ephy_info e_info_8168g_2[] = {
2996 { 0x00, 0x0008, 0x0000 },
2997 { 0x0c, 0x3ff0, 0x0820 },
2998 { 0x19, 0xffff, 0x7c00 },
2999 { 0x1e, 0xffff, 0x20eb },
3000 { 0x0d, 0xffff, 0x1666 },
3001 { 0x00, 0xffff, 0x10a3 },
3002 { 0x06, 0xffff, 0xf050 },
3003 { 0x04, 0x0000, 0x0010 },
3004 { 0x1d, 0x4000, 0x0000 },
3007 rtl_hw_start_8168g(tp);
3009 /* disable aspm and clock request before access ephy */
3010 rtl_hw_aspm_clkreq_enable(tp, false);
3011 rtl_ephy_init(tp, e_info_8168g_2);
3014 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3016 static const struct ephy_info e_info_8411_2[] = {
3017 { 0x00, 0x0008, 0x0000 },
3018 { 0x0c, 0x37d0, 0x0820 },
3019 { 0x1e, 0x0000, 0x0001 },
3020 { 0x19, 0x8021, 0x0000 },
3021 { 0x1e, 0x0000, 0x2000 },
3022 { 0x0d, 0x0100, 0x0200 },
3023 { 0x00, 0x0000, 0x0080 },
3024 { 0x06, 0x0000, 0x0010 },
3025 { 0x04, 0x0000, 0x0010 },
3026 { 0x1d, 0x0000, 0x4000 },
3029 rtl_hw_start_8168g(tp);
3031 /* disable aspm and clock request before access ephy */
3032 rtl_hw_aspm_clkreq_enable(tp, false);
3033 rtl_ephy_init(tp, e_info_8411_2);
3035 /* The following Realtek-provided magic fixes an issue with the RX unit
3036 * getting confused after the PHY having been powered-down.
3038 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3039 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3040 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3041 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3042 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3043 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3044 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3045 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3047 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3049 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3050 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3051 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3052 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3053 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3054 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3055 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3056 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3057 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3058 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3059 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3060 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3061 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3062 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3063 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3064 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3065 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3066 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3067 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3068 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3069 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3070 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3071 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3072 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3073 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3074 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3075 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3076 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3077 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3078 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3079 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3080 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3081 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3082 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3083 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3084 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3085 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3086 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3087 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3088 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3089 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3090 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3091 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3092 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3093 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3094 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3095 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3096 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3097 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3098 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3099 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3100 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3101 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3102 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3103 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3104 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3105 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3106 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3107 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3108 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3109 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3110 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3111 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3112 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3113 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3114 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3115 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3116 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3117 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3118 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3119 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3120 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3121 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3122 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3123 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3124 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3125 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3126 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3127 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3128 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3129 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3130 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3131 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3132 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3133 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3134 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3135 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3136 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3137 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3138 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3139 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3140 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3141 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3142 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3143 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3144 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3145 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3146 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3147 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3148 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3149 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3150 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3151 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3152 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3153 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3154 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3155 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3156 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3157 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3158 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3159 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3161 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3163 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3164 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3165 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3166 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3167 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3168 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3169 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3171 rtl_hw_aspm_clkreq_enable(tp, true);
3174 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3176 static const struct ephy_info e_info_8168h_1[] = {
3177 { 0x1e, 0x0800, 0x0001 },
3178 { 0x1d, 0x0000, 0x0800 },
3179 { 0x05, 0xffff, 0x2089 },
3180 { 0x06, 0xffff, 0x5881 },
3181 { 0x04, 0xffff, 0x854a },
3182 { 0x01, 0xffff, 0x068b }
3186 /* disable aspm and clock request before access ephy */
3187 rtl_hw_aspm_clkreq_enable(tp, false);
3188 rtl_ephy_init(tp, e_info_8168h_1);
3190 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3191 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3193 rtl_set_def_aspm_entry_latency(tp);
3195 rtl_reset_packet_filter(tp);
3197 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3199 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3201 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3203 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3204 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3206 rtl8168_config_eee_mac(tp);
3208 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3209 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3211 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3213 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3215 rtl_pcie_state_l2l3_disable(tp);
3217 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3218 if (rg_saw_cnt > 0) {
3221 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3222 sw_cnt_1ms_ini &= 0x0fff;
3223 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3226 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3227 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3228 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3229 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3231 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3232 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3233 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3234 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3236 rtl_hw_aspm_clkreq_enable(tp, true);
3239 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3241 rtl8168ep_stop_cmac(tp);
3243 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3244 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3246 rtl_set_def_aspm_entry_latency(tp);
3248 rtl_reset_packet_filter(tp);
3250 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3252 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3254 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3255 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3257 rtl8168_config_eee_mac(tp);
3259 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3261 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3263 rtl_pcie_state_l2l3_disable(tp);
3266 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3268 static const struct ephy_info e_info_8168ep_3[] = {
3269 { 0x00, 0x0000, 0x0080 },
3270 { 0x0d, 0x0100, 0x0200 },
3271 { 0x19, 0x8021, 0x0000 },
3272 { 0x1e, 0x0000, 0x2000 },
3275 /* disable aspm and clock request before access ephy */
3276 rtl_hw_aspm_clkreq_enable(tp, false);
3277 rtl_ephy_init(tp, e_info_8168ep_3);
3279 rtl_hw_start_8168ep(tp);
3281 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3282 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3284 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3285 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3286 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3288 rtl_hw_aspm_clkreq_enable(tp, true);
3291 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3293 static const struct ephy_info e_info_8117[] = {
3294 { 0x19, 0x0040, 0x1100 },
3295 { 0x59, 0x0040, 0x1100 },
3299 rtl8168ep_stop_cmac(tp);
3301 /* disable aspm and clock request before access ephy */
3302 rtl_hw_aspm_clkreq_enable(tp, false);
3303 rtl_ephy_init(tp, e_info_8117);
3305 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3306 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3308 rtl_set_def_aspm_entry_latency(tp);
3310 rtl_reset_packet_filter(tp);
3312 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3314 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3316 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3318 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3319 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3321 rtl8168_config_eee_mac(tp);
3323 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3324 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3326 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3328 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3330 rtl_pcie_state_l2l3_disable(tp);
3332 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3333 if (rg_saw_cnt > 0) {
3336 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3337 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3340 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3341 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3342 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3343 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3345 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3346 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3347 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3348 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3350 /* firmware is for MAC only */
3351 r8169_apply_firmware(tp);
3353 rtl_hw_aspm_clkreq_enable(tp, true);
3356 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3358 static const struct ephy_info e_info_8102e_1[] = {
3359 { 0x01, 0, 0x6e65 },
3360 { 0x02, 0, 0x091f },
3361 { 0x03, 0, 0xc2f9 },
3362 { 0x06, 0, 0xafb5 },
3363 { 0x07, 0, 0x0e00 },
3364 { 0x19, 0, 0xec80 },
3365 { 0x01, 0, 0x2e65 },
3370 rtl_set_def_aspm_entry_latency(tp);
3372 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3375 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3376 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3378 cfg1 = RTL_R8(tp, Config1);
3379 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3380 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3382 rtl_ephy_init(tp, e_info_8102e_1);
3385 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3387 rtl_set_def_aspm_entry_latency(tp);
3389 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3390 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3393 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3395 rtl_hw_start_8102e_2(tp);
3397 rtl_ephy_write(tp, 0x03, 0xc2f9);
3400 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3402 static const struct ephy_info e_info_8401[] = {
3403 { 0x01, 0xffff, 0x6fe5 },
3404 { 0x03, 0xffff, 0x0599 },
3405 { 0x06, 0xffff, 0xaf25 },
3406 { 0x07, 0xffff, 0x8e68 },
3409 rtl_ephy_init(tp, e_info_8401);
3410 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3413 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3415 static const struct ephy_info e_info_8105e_1[] = {
3416 { 0x07, 0, 0x4000 },
3417 { 0x19, 0, 0x0200 },
3418 { 0x19, 0, 0x0020 },
3419 { 0x1e, 0, 0x2000 },
3420 { 0x03, 0, 0x0001 },
3421 { 0x19, 0, 0x0100 },
3422 { 0x19, 0, 0x0004 },
3426 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3427 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3429 /* Disable Early Tally Counter */
3430 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3432 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3433 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3435 rtl_ephy_init(tp, e_info_8105e_1);
3437 rtl_pcie_state_l2l3_disable(tp);
3440 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3442 rtl_hw_start_8105e_1(tp);
3443 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3446 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3448 static const struct ephy_info e_info_8402[] = {
3449 { 0x19, 0xffff, 0xff64 },
3453 rtl_set_def_aspm_entry_latency(tp);
3455 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3456 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3458 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3460 rtl_ephy_init(tp, e_info_8402);
3462 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3463 rtl_reset_packet_filter(tp);
3464 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3465 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3466 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3469 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3471 rtl_pcie_state_l2l3_disable(tp);
3474 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3476 rtl_hw_aspm_clkreq_enable(tp, false);
3478 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3479 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3481 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3482 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3483 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3485 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3486 rtl_set_aspm_entry_latency(tp, 0x2f);
3488 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3491 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3493 rtl_pcie_state_l2l3_disable(tp);
3494 rtl_hw_aspm_clkreq_enable(tp, true);
3497 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3499 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3502 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3504 rtl_pcie_state_l2l3_disable(tp);
3506 RTL_W16(tp, 0x382, 0x221b);
3507 RTL_W8(tp, 0x4500, 0);
3508 RTL_W16(tp, 0x4800, 0);
3511 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3513 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3515 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3516 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3518 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3519 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3520 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3522 /* disable new tx descriptor format */
3523 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3525 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3526 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3528 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3530 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3531 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3533 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3535 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3536 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3537 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3538 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3539 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3540 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3541 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3542 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3543 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3545 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3546 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3548 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3549 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3551 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3553 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3555 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3556 rtl8125b_config_eee_mac(tp);
3558 rtl8125a_config_eee_mac(tp);
3560 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3564 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3566 static const struct ephy_info e_info_8125a_2[] = {
3567 { 0x04, 0xffff, 0xd000 },
3568 { 0x0a, 0xffff, 0x8653 },
3569 { 0x23, 0xffff, 0xab66 },
3570 { 0x20, 0xffff, 0x9455 },
3571 { 0x21, 0xffff, 0x99ff },
3572 { 0x29, 0xffff, 0xfe04 },
3574 { 0x44, 0xffff, 0xd000 },
3575 { 0x4a, 0xffff, 0x8653 },
3576 { 0x63, 0xffff, 0xab66 },
3577 { 0x60, 0xffff, 0x9455 },
3578 { 0x61, 0xffff, 0x99ff },
3579 { 0x69, 0xffff, 0xfe04 },
3582 rtl_set_def_aspm_entry_latency(tp);
3584 /* disable aspm and clock request before access ephy */
3585 rtl_hw_aspm_clkreq_enable(tp, false);
3586 rtl_ephy_init(tp, e_info_8125a_2);
3588 rtl_hw_start_8125_common(tp);
3589 rtl_hw_aspm_clkreq_enable(tp, true);
3592 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3594 static const struct ephy_info e_info_8125b[] = {
3595 { 0x0b, 0xffff, 0xa908 },
3596 { 0x1e, 0xffff, 0x20eb },
3597 { 0x4b, 0xffff, 0xa908 },
3598 { 0x5e, 0xffff, 0x20eb },
3599 { 0x22, 0x0030, 0x0020 },
3600 { 0x62, 0x0030, 0x0020 },
3603 rtl_set_def_aspm_entry_latency(tp);
3604 rtl_hw_aspm_clkreq_enable(tp, false);
3606 rtl_ephy_init(tp, e_info_8125b);
3607 rtl_hw_start_8125_common(tp);
3609 rtl_hw_aspm_clkreq_enable(tp, true);
3612 static void rtl_hw_config(struct rtl8169_private *tp)
3614 static const rtl_generic_fct hw_configs[] = {
3615 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3616 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3617 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3618 [RTL_GIGA_MAC_VER_10] = NULL,
3619 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3620 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3621 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3622 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3623 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3624 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3625 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3626 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3627 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3628 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3629 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3630 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3631 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3632 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3633 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3634 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3635 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3636 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3637 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3638 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3639 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3640 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3641 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3642 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3643 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3644 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3645 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3646 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3647 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3648 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3649 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3650 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3651 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3652 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3653 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3656 if (hw_configs[tp->mac_version])
3657 hw_configs[tp->mac_version](tp);
3660 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3664 /* disable interrupt coalescing */
3665 for (i = 0xa00; i < 0xb00; i += 4)
3671 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3673 if (rtl_is_8168evl_up(tp))
3674 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3676 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3680 /* disable interrupt coalescing */
3681 RTL_W16(tp, IntrMitigate, 0x0000);
3684 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3686 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3688 tp->cp_cmd |= PCIMulRW;
3690 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3691 tp->mac_version == RTL_GIGA_MAC_VER_03)
3692 tp->cp_cmd |= EnAnaPLL;
3694 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3696 rtl8169_set_magic_reg(tp);
3698 /* disable interrupt coalescing */
3699 RTL_W16(tp, IntrMitigate, 0x0000);
3702 static void rtl_hw_start(struct rtl8169_private *tp)
3704 rtl_unlock_config_regs(tp);
3706 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3708 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3709 rtl_hw_start_8169(tp);
3710 else if (rtl_is_8125(tp))
3711 rtl_hw_start_8125(tp);
3713 rtl_hw_start_8168(tp);
3715 rtl_enable_exit_l1(tp);
3716 rtl_set_rx_max_size(tp);
3717 rtl_set_rx_tx_desc_registers(tp);
3718 rtl_lock_config_regs(tp);
3720 rtl_jumbo_config(tp);
3722 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3725 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3727 rtl_set_tx_config_registers(tp);
3728 rtl_set_rx_config_features(tp, tp->dev->features);
3729 rtl_set_rx_mode(tp->dev);
3733 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3735 struct rtl8169_private *tp = netdev_priv(dev);
3738 netdev_update_features(dev);
3739 rtl_jumbo_config(tp);
3741 switch (tp->mac_version) {
3742 case RTL_GIGA_MAC_VER_61:
3743 case RTL_GIGA_MAC_VER_63:
3744 rtl8125_set_eee_txidle_timer(tp);
3753 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3755 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3758 /* Force memory writes to complete before releasing descriptor */
3760 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3763 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3764 struct RxDesc *desc)
3766 struct device *d = tp_to_dev(tp);
3767 int node = dev_to_node(d);
3771 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3775 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3776 if (unlikely(dma_mapping_error(d, mapping))) {
3777 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3778 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3782 desc->addr = cpu_to_le64(mapping);
3783 rtl8169_mark_to_asic(desc);
3788 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3792 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3793 dma_unmap_page(tp_to_dev(tp),
3794 le64_to_cpu(tp->RxDescArray[i].addr),
3795 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3796 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3797 tp->Rx_databuff[i] = NULL;
3798 tp->RxDescArray[i].addr = 0;
3799 tp->RxDescArray[i].opts1 = 0;
3803 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3807 for (i = 0; i < NUM_RX_DESC; i++) {
3810 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3812 rtl8169_rx_clear(tp);
3815 tp->Rx_databuff[i] = data;
3818 /* mark as last descriptor in the ring */
3819 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3824 static int rtl8169_init_ring(struct rtl8169_private *tp)
3826 rtl8169_init_ring_indexes(tp);
3828 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3829 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3831 return rtl8169_rx_fill(tp);
3834 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3836 struct ring_info *tx_skb = tp->tx_skb + entry;
3837 struct TxDesc *desc = tp->TxDescArray + entry;
3839 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3841 memset(desc, 0, sizeof(*desc));
3842 memset(tx_skb, 0, sizeof(*tx_skb));
3845 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3850 for (i = 0; i < n; i++) {
3851 unsigned int entry = (start + i) % NUM_TX_DESC;
3852 struct ring_info *tx_skb = tp->tx_skb + entry;
3853 unsigned int len = tx_skb->len;
3856 struct sk_buff *skb = tx_skb->skb;
3858 rtl8169_unmap_tx_skb(tp, entry);
3860 dev_consume_skb_any(skb);
3865 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3867 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3868 netdev_reset_queue(tp->dev);
3871 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3873 napi_disable(&tp->napi);
3875 /* Give a racing hard_start_xmit a few cycles to complete. */
3878 /* Disable interrupts */
3879 rtl8169_irq_mask_and_ack(tp);
3883 if (going_down && tp->dev->wol_enabled)
3886 switch (tp->mac_version) {
3887 case RTL_GIGA_MAC_VER_28:
3888 case RTL_GIGA_MAC_VER_31:
3889 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3891 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3892 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3893 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3895 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3896 rtl_enable_rxdvgate(tp);
3900 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3907 rtl8169_tx_clear(tp);
3908 rtl8169_init_ring_indexes(tp);
3911 static void rtl_reset_work(struct rtl8169_private *tp)
3915 netif_stop_queue(tp->dev);
3917 rtl8169_cleanup(tp, false);
3919 for (i = 0; i < NUM_RX_DESC; i++)
3920 rtl8169_mark_to_asic(tp->RxDescArray + i);
3922 napi_enable(&tp->napi);
3926 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3928 struct rtl8169_private *tp = netdev_priv(dev);
3930 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3933 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3934 void *addr, unsigned int entry, bool desc_own)
3936 struct TxDesc *txd = tp->TxDescArray + entry;
3937 struct device *d = tp_to_dev(tp);
3942 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3943 ret = dma_mapping_error(d, mapping);
3944 if (unlikely(ret)) {
3945 if (net_ratelimit())
3946 netdev_err(tp->dev, "Failed to map TX data!\n");
3950 txd->addr = cpu_to_le64(mapping);
3951 txd->opts2 = cpu_to_le32(opts[1]);
3953 opts1 = opts[0] | len;
3954 if (entry == NUM_TX_DESC - 1)
3958 txd->opts1 = cpu_to_le32(opts1);
3960 tp->tx_skb[entry].len = len;
3965 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3966 const u32 *opts, unsigned int entry)
3968 struct skb_shared_info *info = skb_shinfo(skb);
3969 unsigned int cur_frag;
3971 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3972 const skb_frag_t *frag = info->frags + cur_frag;
3973 void *addr = skb_frag_address(frag);
3974 u32 len = skb_frag_size(frag);
3976 entry = (entry + 1) % NUM_TX_DESC;
3978 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
3985 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3989 static bool rtl_skb_is_udp(struct sk_buff *skb)
3991 int no = skb_network_offset(skb);
3992 struct ipv6hdr *i6h, _i6h;
3993 struct iphdr *ih, _ih;
3995 switch (vlan_get_protocol(skb)) {
3996 case htons(ETH_P_IP):
3997 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
3998 return ih && ih->protocol == IPPROTO_UDP;
3999 case htons(ETH_P_IPV6):
4000 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4001 return i6h && i6h->nexthdr == IPPROTO_UDP;
4007 #define RTL_MIN_PATCH_LEN 47
4009 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4010 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4011 struct sk_buff *skb)
4013 unsigned int padto = 0, len = skb->len;
4015 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4016 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4017 unsigned int trans_data_len = skb_tail_pointer(skb) -
4018 skb_transport_header(skb);
4020 if (trans_data_len >= offsetof(struct udphdr, len) &&
4021 trans_data_len < RTL_MIN_PATCH_LEN) {
4022 u16 dest = ntohs(udp_hdr(skb)->dest);
4024 /* dest is a standard PTP port */
4025 if (dest == 319 || dest == 320)
4026 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4029 if (trans_data_len < sizeof(struct udphdr))
4030 padto = max_t(unsigned int, padto,
4031 len + sizeof(struct udphdr) - trans_data_len);
4037 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4038 struct sk_buff *skb)
4042 padto = rtl8125_quirk_udp_padto(tp, skb);
4044 switch (tp->mac_version) {
4045 case RTL_GIGA_MAC_VER_34:
4046 case RTL_GIGA_MAC_VER_61:
4047 case RTL_GIGA_MAC_VER_63:
4048 padto = max_t(unsigned int, padto, ETH_ZLEN);
4057 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4059 u32 mss = skb_shinfo(skb)->gso_size;
4063 opts[0] |= mss << TD0_MSS_SHIFT;
4064 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4065 const struct iphdr *ip = ip_hdr(skb);
4067 if (ip->protocol == IPPROTO_TCP)
4068 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4069 else if (ip->protocol == IPPROTO_UDP)
4070 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4076 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4077 struct sk_buff *skb, u32 *opts)
4079 struct skb_shared_info *shinfo = skb_shinfo(skb);
4080 u32 mss = shinfo->gso_size;
4083 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4084 opts[0] |= TD1_GTSENV4;
4085 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4086 if (skb_cow_head(skb, 0))
4089 tcp_v6_gso_csum_prep(skb);
4090 opts[0] |= TD1_GTSENV6;
4095 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4096 opts[1] |= mss << TD1_MSS_SHIFT;
4097 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4100 switch (vlan_get_protocol(skb)) {
4101 case htons(ETH_P_IP):
4102 opts[1] |= TD1_IPv4_CS;
4103 ip_protocol = ip_hdr(skb)->protocol;
4106 case htons(ETH_P_IPV6):
4107 opts[1] |= TD1_IPv6_CS;
4108 ip_protocol = ipv6_hdr(skb)->nexthdr;
4112 ip_protocol = IPPROTO_RAW;
4116 if (ip_protocol == IPPROTO_TCP)
4117 opts[1] |= TD1_TCP_CS;
4118 else if (ip_protocol == IPPROTO_UDP)
4119 opts[1] |= TD1_UDP_CS;
4123 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4125 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4127 /* skb_padto would free the skb on error */
4128 return !__skb_put_padto(skb, padto, false);
4134 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4136 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4137 - READ_ONCE(tp->cur_tx);
4139 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4140 return slots_avail > MAX_SKB_FRAGS;
4143 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4144 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4146 switch (tp->mac_version) {
4147 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4148 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4155 static void rtl8169_doorbell(struct rtl8169_private *tp)
4157 if (rtl_is_8125(tp))
4158 RTL_W16(tp, TxPoll_8125, BIT(0));
4160 RTL_W8(tp, TxPoll, NPQ);
4163 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4164 struct net_device *dev)
4166 unsigned int frags = skb_shinfo(skb)->nr_frags;
4167 struct rtl8169_private *tp = netdev_priv(dev);
4168 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4169 struct TxDesc *txd_first, *txd_last;
4170 bool stop_queue, door_bell;
4173 if (unlikely(!rtl_tx_slots_avail(tp))) {
4174 if (net_ratelimit())
4175 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4179 opts[1] = rtl8169_tx_vlan_tag(skb);
4182 if (!rtl_chip_supports_csum_v2(tp))
4183 rtl8169_tso_csum_v1(skb, opts);
4184 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4187 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4191 txd_first = tp->TxDescArray + entry;
4194 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4196 entry = (entry + frags) % NUM_TX_DESC;
4199 txd_last = tp->TxDescArray + entry;
4200 txd_last->opts1 |= cpu_to_le32(LastFrag);
4201 tp->tx_skb[entry].skb = skb;
4203 skb_tx_timestamp(skb);
4205 /* Force memory writes to complete before releasing descriptor */
4208 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4210 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4212 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4215 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4217 stop_queue = !rtl_tx_slots_avail(tp);
4218 if (unlikely(stop_queue)) {
4219 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4220 * not miss a ring update when it notices a stopped queue.
4223 netif_stop_queue(dev);
4224 /* Sync with rtl_tx:
4225 * - publish queue status and cur_tx ring index (write barrier)
4226 * - refresh dirty_tx ring index (read barrier).
4227 * May the current thread have a pessimistic view of the ring
4228 * status and forget to wake up queue, a racing rtl_tx thread
4231 smp_mb__after_atomic();
4232 if (rtl_tx_slots_avail(tp))
4233 netif_start_queue(dev);
4238 rtl8169_doorbell(tp);
4240 return NETDEV_TX_OK;
4243 rtl8169_unmap_tx_skb(tp, entry);
4245 dev_kfree_skb_any(skb);
4246 dev->stats.tx_dropped++;
4247 return NETDEV_TX_OK;
4250 netif_stop_queue(dev);
4251 dev->stats.tx_dropped++;
4252 return NETDEV_TX_BUSY;
4255 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4257 struct skb_shared_info *info = skb_shinfo(skb);
4258 unsigned int nr_frags = info->nr_frags;
4263 return skb_frag_size(info->frags + nr_frags - 1);
4266 /* Workaround for hw issues with TSO on RTL8168evl */
4267 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4268 netdev_features_t features)
4270 /* IPv4 header has options field */
4271 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4272 ip_hdrlen(skb) > sizeof(struct iphdr))
4273 features &= ~NETIF_F_ALL_TSO;
4275 /* IPv4 TCP header has options field */
4276 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4277 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4278 features &= ~NETIF_F_ALL_TSO;
4280 else if (rtl_last_frag_len(skb) <= 6)
4281 features &= ~NETIF_F_ALL_TSO;
4286 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4287 struct net_device *dev,
4288 netdev_features_t features)
4290 struct rtl8169_private *tp = netdev_priv(dev);
4292 if (skb_is_gso(skb)) {
4293 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4294 features = rtl8168evl_fix_tso(skb, features);
4296 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4297 rtl_chip_supports_csum_v2(tp))
4298 features &= ~NETIF_F_ALL_TSO;
4299 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4300 /* work around hw bug on some chip versions */
4301 if (skb->len < ETH_ZLEN)
4302 features &= ~NETIF_F_CSUM_MASK;
4304 if (rtl_quirk_packet_padto(tp, skb))
4305 features &= ~NETIF_F_CSUM_MASK;
4307 if (skb_transport_offset(skb) > TCPHO_MAX &&
4308 rtl_chip_supports_csum_v2(tp))
4309 features &= ~NETIF_F_CSUM_MASK;
4312 return vlan_features_check(skb, features);
4315 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4317 struct rtl8169_private *tp = netdev_priv(dev);
4318 struct pci_dev *pdev = tp->pci_dev;
4319 int pci_status_errs;
4322 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4324 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4326 if (net_ratelimit())
4327 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4328 pci_cmd, pci_status_errs);
4330 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4333 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4336 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4337 struct sk_buff *skb;
4339 dirty_tx = tp->dirty_tx;
4341 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4342 unsigned int entry = dirty_tx % NUM_TX_DESC;
4345 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4346 if (status & DescOwn)
4349 skb = tp->tx_skb[entry].skb;
4350 rtl8169_unmap_tx_skb(tp, entry);
4354 bytes_compl += skb->len;
4355 napi_consume_skb(skb, budget);
4360 if (tp->dirty_tx != dirty_tx) {
4361 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4362 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4364 /* Sync with rtl8169_start_xmit:
4365 * - publish dirty_tx ring index (write barrier)
4366 * - refresh cur_tx ring index and queue status (read barrier)
4367 * May the current thread miss the stopped queue condition,
4368 * a racing xmit thread can only have a right view of the
4371 smp_store_mb(tp->dirty_tx, dirty_tx);
4372 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4373 netif_wake_queue(dev);
4375 * 8168 hack: TxPoll requests are lost when the Tx packets are
4376 * too close. Let's kick an extra TxPoll request when a burst
4377 * of start_xmit activity is detected (if it is not detected,
4378 * it is slow enough). -- FR
4379 * If skb is NULL then we come here again once a tx irq is
4380 * triggered after the last fragment is marked transmitted.
4382 if (tp->cur_tx != dirty_tx && skb)
4383 rtl8169_doorbell(tp);
4387 static inline int rtl8169_fragmented_frame(u32 status)
4389 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4392 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4394 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4396 if (status == RxProtoTCP || status == RxProtoUDP)
4397 skb->ip_summed = CHECKSUM_UNNECESSARY;
4399 skb_checksum_none_assert(skb);
4402 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4404 struct device *d = tp_to_dev(tp);
4407 for (count = 0; count < budget; count++, tp->cur_rx++) {
4408 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4409 struct RxDesc *desc = tp->RxDescArray + entry;
4410 struct sk_buff *skb;
4415 status = le32_to_cpu(desc->opts1);
4416 if (status & DescOwn)
4419 /* This barrier is needed to keep us from reading
4420 * any other fields out of the Rx descriptor until
4421 * we know the status of DescOwn
4425 if (unlikely(status & RxRES)) {
4426 if (net_ratelimit())
4427 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4429 dev->stats.rx_errors++;
4430 if (status & (RxRWT | RxRUNT))
4431 dev->stats.rx_length_errors++;
4433 dev->stats.rx_crc_errors++;
4435 if (!(dev->features & NETIF_F_RXALL))
4436 goto release_descriptor;
4437 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4438 goto release_descriptor;
4441 pkt_size = status & GENMASK(13, 0);
4442 if (likely(!(dev->features & NETIF_F_RXFCS)))
4443 pkt_size -= ETH_FCS_LEN;
4445 /* The driver does not support incoming fragmented frames.
4446 * They are seen as a symptom of over-mtu sized frames.
4448 if (unlikely(rtl8169_fragmented_frame(status))) {
4449 dev->stats.rx_dropped++;
4450 dev->stats.rx_length_errors++;
4451 goto release_descriptor;
4454 skb = napi_alloc_skb(&tp->napi, pkt_size);
4455 if (unlikely(!skb)) {
4456 dev->stats.rx_dropped++;
4457 goto release_descriptor;
4460 addr = le64_to_cpu(desc->addr);
4461 rx_buf = page_address(tp->Rx_databuff[entry]);
4463 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4465 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4466 skb->tail += pkt_size;
4467 skb->len = pkt_size;
4468 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4470 rtl8169_rx_csum(skb, status);
4471 skb->protocol = eth_type_trans(skb, dev);
4473 rtl8169_rx_vlan_tag(desc, skb);
4475 if (skb->pkt_type == PACKET_MULTICAST)
4476 dev->stats.multicast++;
4478 napi_gro_receive(&tp->napi, skb);
4480 dev_sw_netstats_rx_add(dev, pkt_size);
4482 rtl8169_mark_to_asic(desc);
4488 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4490 struct rtl8169_private *tp = dev_instance;
4491 u32 status = rtl_get_events(tp);
4493 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4496 if (unlikely(status & SYSErr)) {
4497 rtl8169_pcierr_interrupt(tp->dev);
4501 if (status & LinkChg)
4502 phy_mac_interrupt(tp->phydev);
4504 if (unlikely(status & RxFIFOOver &&
4505 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4506 netif_stop_queue(tp->dev);
4507 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4510 if (napi_schedule_prep(&tp->napi)) {
4511 rtl_irq_disable(tp);
4512 __napi_schedule(&tp->napi);
4515 rtl_ack_events(tp, status);
4520 static void rtl_task(struct work_struct *work)
4522 struct rtl8169_private *tp =
4523 container_of(work, struct rtl8169_private, wk.work);
4527 if (!netif_running(tp->dev) ||
4528 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4531 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4533 netif_wake_queue(tp->dev);
4539 static int rtl8169_poll(struct napi_struct *napi, int budget)
4541 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4542 struct net_device *dev = tp->dev;
4545 rtl_tx(dev, tp, budget);
4547 work_done = rtl_rx(dev, tp, budget);
4549 if (work_done < budget && napi_complete_done(napi, work_done))
4555 static void r8169_phylink_handler(struct net_device *ndev)
4557 struct rtl8169_private *tp = netdev_priv(ndev);
4559 if (netif_carrier_ok(ndev)) {
4560 rtl_link_chg_patch(tp);
4561 pm_request_resume(&tp->pci_dev->dev);
4563 pm_runtime_idle(&tp->pci_dev->dev);
4566 phy_print_status(tp->phydev);
4569 static int r8169_phy_connect(struct rtl8169_private *tp)
4571 struct phy_device *phydev = tp->phydev;
4572 phy_interface_t phy_mode;
4575 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4576 PHY_INTERFACE_MODE_MII;
4578 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4583 if (!tp->supports_gmii)
4584 phy_set_max_speed(phydev, SPEED_100);
4586 phy_attached_info(phydev);
4591 static void rtl8169_down(struct rtl8169_private *tp)
4593 /* Clear all task flags */
4594 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4596 phy_stop(tp->phydev);
4598 rtl8169_update_counters(tp);
4600 pci_clear_master(tp->pci_dev);
4603 rtl8169_cleanup(tp, true);
4604 rtl_disable_exit_l1(tp);
4605 rtl_prepare_power_down(tp);
4608 static void rtl8169_up(struct rtl8169_private *tp)
4610 pci_set_master(tp->pci_dev);
4611 phy_init_hw(tp->phydev);
4612 phy_resume(tp->phydev);
4613 rtl8169_init_phy(tp);
4614 napi_enable(&tp->napi);
4615 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4618 phy_start(tp->phydev);
4621 static int rtl8169_close(struct net_device *dev)
4623 struct rtl8169_private *tp = netdev_priv(dev);
4624 struct pci_dev *pdev = tp->pci_dev;
4626 pm_runtime_get_sync(&pdev->dev);
4628 netif_stop_queue(dev);
4630 rtl8169_rx_clear(tp);
4632 cancel_work_sync(&tp->wk.work);
4634 free_irq(tp->irq, tp);
4636 phy_disconnect(tp->phydev);
4638 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4640 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4642 tp->TxDescArray = NULL;
4643 tp->RxDescArray = NULL;
4645 pm_runtime_put_sync(&pdev->dev);
4650 #ifdef CONFIG_NET_POLL_CONTROLLER
4651 static void rtl8169_netpoll(struct net_device *dev)
4653 struct rtl8169_private *tp = netdev_priv(dev);
4655 rtl8169_interrupt(tp->irq, tp);
4659 static int rtl_open(struct net_device *dev)
4661 struct rtl8169_private *tp = netdev_priv(dev);
4662 struct pci_dev *pdev = tp->pci_dev;
4663 unsigned long irqflags;
4664 int retval = -ENOMEM;
4666 pm_runtime_get_sync(&pdev->dev);
4669 * Rx and Tx descriptors needs 256 bytes alignment.
4670 * dma_alloc_coherent provides more.
4672 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4673 &tp->TxPhyAddr, GFP_KERNEL);
4674 if (!tp->TxDescArray)
4677 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4678 &tp->RxPhyAddr, GFP_KERNEL);
4679 if (!tp->RxDescArray)
4682 retval = rtl8169_init_ring(tp);
4686 rtl_request_firmware(tp);
4688 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4689 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4691 goto err_release_fw_2;
4693 retval = r8169_phy_connect(tp);
4698 rtl8169_init_counter_offsets(tp);
4699 netif_start_queue(dev);
4701 pm_runtime_put_sync(&pdev->dev);
4706 free_irq(tp->irq, tp);
4708 rtl_release_firmware(tp);
4709 rtl8169_rx_clear(tp);
4711 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4713 tp->RxDescArray = NULL;
4715 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4717 tp->TxDescArray = NULL;
4722 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4724 struct rtl8169_private *tp = netdev_priv(dev);
4725 struct pci_dev *pdev = tp->pci_dev;
4726 struct rtl8169_counters *counters = tp->counters;
4728 pm_runtime_get_noresume(&pdev->dev);
4730 netdev_stats_to_stats64(stats, &dev->stats);
4731 dev_fetch_sw_netstats(stats, dev->tstats);
4734 * Fetch additional counter values missing in stats collected by driver
4735 * from tally counters.
4737 if (pm_runtime_active(&pdev->dev))
4738 rtl8169_update_counters(tp);
4741 * Subtract values fetched during initalization.
4742 * See rtl8169_init_counter_offsets for a description why we do that.
4744 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4745 le64_to_cpu(tp->tc_offset.tx_errors);
4746 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4747 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4748 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4749 le16_to_cpu(tp->tc_offset.tx_aborted);
4750 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4751 le16_to_cpu(tp->tc_offset.rx_missed);
4753 pm_runtime_put_noidle(&pdev->dev);
4756 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4758 netif_device_detach(tp->dev);
4760 if (netif_running(tp->dev))
4764 static int rtl8169_runtime_resume(struct device *dev)
4766 struct rtl8169_private *tp = dev_get_drvdata(dev);
4768 rtl_rar_set(tp, tp->dev->dev_addr);
4769 __rtl8169_set_wol(tp, tp->saved_wolopts);
4771 if (tp->TxDescArray)
4774 netif_device_attach(tp->dev);
4779 static int rtl8169_suspend(struct device *device)
4781 struct rtl8169_private *tp = dev_get_drvdata(device);
4784 rtl8169_net_suspend(tp);
4785 if (!device_may_wakeup(tp_to_dev(tp)))
4786 clk_disable_unprepare(tp->clk);
4792 static int rtl8169_resume(struct device *device)
4794 struct rtl8169_private *tp = dev_get_drvdata(device);
4796 if (!device_may_wakeup(tp_to_dev(tp)))
4797 clk_prepare_enable(tp->clk);
4799 /* Reportedly at least Asus X453MA truncates packets otherwise */
4800 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4803 return rtl8169_runtime_resume(device);
4806 static int rtl8169_runtime_suspend(struct device *device)
4808 struct rtl8169_private *tp = dev_get_drvdata(device);
4810 if (!tp->TxDescArray) {
4811 netif_device_detach(tp->dev);
4816 __rtl8169_set_wol(tp, WAKE_PHY);
4817 rtl8169_net_suspend(tp);
4823 static int rtl8169_runtime_idle(struct device *device)
4825 struct rtl8169_private *tp = dev_get_drvdata(device);
4827 if (tp->dash_type != RTL_DASH_NONE)
4830 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4831 pm_schedule_suspend(device, 10000);
4836 static const struct dev_pm_ops rtl8169_pm_ops = {
4837 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4838 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4839 rtl8169_runtime_idle)
4842 static void rtl_shutdown(struct pci_dev *pdev)
4844 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4847 rtl8169_net_suspend(tp);
4850 /* Restore original MAC address */
4851 rtl_rar_set(tp, tp->dev->perm_addr);
4853 if (system_state == SYSTEM_POWER_OFF &&
4854 tp->dash_type == RTL_DASH_NONE) {
4855 pci_wake_from_d3(pdev, tp->saved_wolopts);
4856 pci_set_power_state(pdev, PCI_D3hot);
4860 static void rtl_remove_one(struct pci_dev *pdev)
4862 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4864 if (pci_dev_run_wake(pdev))
4865 pm_runtime_get_noresume(&pdev->dev);
4867 unregister_netdev(tp->dev);
4869 if (tp->dash_type != RTL_DASH_NONE)
4870 rtl8168_driver_stop(tp);
4872 rtl_release_firmware(tp);
4874 /* restore original MAC address */
4875 rtl_rar_set(tp, tp->dev->perm_addr);
4878 static const struct net_device_ops rtl_netdev_ops = {
4879 .ndo_open = rtl_open,
4880 .ndo_stop = rtl8169_close,
4881 .ndo_get_stats64 = rtl8169_get_stats64,
4882 .ndo_start_xmit = rtl8169_start_xmit,
4883 .ndo_features_check = rtl8169_features_check,
4884 .ndo_tx_timeout = rtl8169_tx_timeout,
4885 .ndo_validate_addr = eth_validate_addr,
4886 .ndo_change_mtu = rtl8169_change_mtu,
4887 .ndo_fix_features = rtl8169_fix_features,
4888 .ndo_set_features = rtl8169_set_features,
4889 .ndo_set_mac_address = rtl_set_mac_address,
4890 .ndo_eth_ioctl = phy_do_ioctl_running,
4891 .ndo_set_rx_mode = rtl_set_rx_mode,
4892 #ifdef CONFIG_NET_POLL_CONTROLLER
4893 .ndo_poll_controller = rtl8169_netpoll,
4898 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4900 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4902 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4903 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4904 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4905 /* special workaround needed */
4906 tp->irq_mask |= RxFIFOOver;
4908 tp->irq_mask |= RxOverflow;
4911 static int rtl_alloc_irq(struct rtl8169_private *tp)
4915 switch (tp->mac_version) {
4916 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4917 rtl_unlock_config_regs(tp);
4918 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4919 rtl_lock_config_regs(tp);
4921 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4922 flags = PCI_IRQ_LEGACY;
4925 flags = PCI_IRQ_ALL_TYPES;
4929 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4932 static void rtl_read_mac_address(struct rtl8169_private *tp,
4933 u8 mac_addr[ETH_ALEN])
4935 /* Get MAC address */
4936 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4939 value = rtl_eri_read(tp, 0xe0);
4940 put_unaligned_le32(value, mac_addr);
4941 value = rtl_eri_read(tp, 0xe4);
4942 put_unaligned_le16(value, mac_addr + 4);
4943 } else if (rtl_is_8125(tp)) {
4944 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4948 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4950 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4953 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
4955 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
4958 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
4960 struct rtl8169_private *tp = mii_bus->priv;
4965 return rtl_readphy(tp, phyreg);
4968 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
4969 int phyreg, u16 val)
4971 struct rtl8169_private *tp = mii_bus->priv;
4976 rtl_writephy(tp, phyreg, val);
4981 static int r8169_mdio_register(struct rtl8169_private *tp)
4983 struct pci_dev *pdev = tp->pci_dev;
4984 struct mii_bus *new_bus;
4987 new_bus = devm_mdiobus_alloc(&pdev->dev);
4991 new_bus->name = "r8169";
4993 new_bus->parent = &pdev->dev;
4994 new_bus->irq[0] = PHY_MAC_INTERRUPT;
4995 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
4996 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
4998 new_bus->read = r8169_mdio_read_reg;
4999 new_bus->write = r8169_mdio_write_reg;
5001 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5005 tp->phydev = mdiobus_get_phy(new_bus, 0);
5008 } else if (!tp->phydev->drv) {
5009 /* Most chip versions fail with the genphy driver.
5010 * Therefore ensure that the dedicated PHY driver is loaded.
5012 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5013 tp->phydev->phy_id);
5017 tp->phydev->mac_managed_pm = 1;
5019 phy_support_asym_pause(tp->phydev);
5021 /* PHY will be woken up in rtl_open() */
5022 phy_suspend(tp->phydev);
5027 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5029 rtl_enable_rxdvgate(tp);
5031 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5033 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5035 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5036 r8168g_wait_ll_share_fifo_ready(tp);
5038 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5039 r8168g_wait_ll_share_fifo_ready(tp);
5042 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5044 rtl_enable_rxdvgate(tp);
5046 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5048 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5050 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5051 r8168g_wait_ll_share_fifo_ready(tp);
5053 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5054 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5055 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5056 r8168g_wait_ll_share_fifo_ready(tp);
5059 static void rtl_hw_initialize(struct rtl8169_private *tp)
5061 switch (tp->mac_version) {
5062 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5063 rtl8168ep_stop_cmac(tp);
5065 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5066 rtl_hw_init_8168g(tp);
5068 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5069 rtl_hw_init_8125(tp);
5076 static int rtl_jumbo_max(struct rtl8169_private *tp)
5078 /* Non-GBit versions don't support jumbo frames */
5079 if (!tp->supports_gmii)
5082 switch (tp->mac_version) {
5084 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5087 case RTL_GIGA_MAC_VER_11:
5088 case RTL_GIGA_MAC_VER_17:
5091 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5098 static void rtl_init_mac_address(struct rtl8169_private *tp)
5100 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5101 struct net_device *dev = tp->dev;
5104 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5108 rtl_read_mac_address(tp, mac_addr);
5109 if (is_valid_ether_addr(mac_addr))
5112 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5113 if (is_valid_ether_addr(mac_addr))
5116 eth_random_addr(mac_addr);
5117 dev->addr_assign_type = NET_ADDR_RANDOM;
5118 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5120 eth_hw_addr_set(dev, mac_addr);
5121 rtl_rar_set(tp, mac_addr);
5124 /* register is set if system vendor successfully tested ASPM 1.2 */
5125 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5127 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5128 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5134 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5136 struct rtl8169_private *tp;
5137 int jumbo_max, region, rc;
5138 enum mac_version chipset;
5139 struct net_device *dev;
5142 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5146 SET_NETDEV_DEV(dev, &pdev->dev);
5147 dev->netdev_ops = &rtl_netdev_ops;
5148 tp = netdev_priv(dev);
5151 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5153 tp->ocp_base = OCP_STD_PHY_BASE;
5155 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5156 struct pcpu_sw_netstats);
5160 /* Get the *optional* external "ether_clk" used on some boards */
5161 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5162 if (IS_ERR(tp->clk))
5163 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5165 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5166 rc = pcim_enable_device(pdev);
5168 dev_err(&pdev->dev, "enable failure\n");
5172 if (pcim_set_mwi(pdev) < 0)
5173 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5175 /* use first MMIO region */
5176 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5178 dev_err(&pdev->dev, "no MMIO resource found\n");
5182 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5184 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5188 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5190 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5192 /* Identify chip attached to board */
5193 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5194 if (chipset == RTL_GIGA_MAC_NONE) {
5195 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5199 tp->mac_version = chipset;
5201 /* Disable ASPM L1 as that cause random device stop working
5202 * problems as well as full system hangs for some PCIe devices users.
5203 * Chips from RTL8168h partially have issues with L1.2, but seem
5204 * to work fine with L1 and L1.1.
5206 if (rtl_aspm_is_safe(tp))
5208 else if (tp->mac_version >= RTL_GIGA_MAC_VER_46)
5209 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
5211 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5212 tp->aspm_manageable = !rc;
5214 tp->dash_type = rtl_check_dash(tp);
5216 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5218 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5219 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5220 dev->features |= NETIF_F_HIGHDMA;
5224 rtl8169_irq_mask_and_ack(tp);
5226 rtl_hw_initialize(tp);
5230 rc = rtl_alloc_irq(tp);
5232 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5235 tp->irq = pci_irq_vector(pdev, 0);
5237 INIT_WORK(&tp->wk.work, rtl_task);
5239 rtl_init_mac_address(tp);
5241 dev->ethtool_ops = &rtl8169_ethtool_ops;
5243 netif_napi_add(dev, &tp->napi, rtl8169_poll);
5245 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5246 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5247 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5248 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5251 * Pretend we are using VLANs; This bypasses a nasty bug where
5252 * Interrupts stop flowing on high load on 8110SCd controllers.
5254 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5255 /* Disallow toggling */
5256 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5258 if (rtl_chip_supports_csum_v2(tp))
5259 dev->hw_features |= NETIF_F_IPV6_CSUM;
5261 dev->features |= dev->hw_features;
5263 /* There has been a number of reports that using SG/TSO results in
5264 * tx timeouts. However for a lot of people SG/TSO works fine.
5265 * Therefore disable both features by default, but allow users to
5266 * enable them. Use at own risk!
5268 if (rtl_chip_supports_csum_v2(tp)) {
5269 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5270 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5271 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5273 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5274 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5275 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5278 dev->hw_features |= NETIF_F_RXALL;
5279 dev->hw_features |= NETIF_F_RXFCS;
5281 /* configure chip for default features */
5282 rtl8169_set_features(dev, dev->features);
5284 if (tp->dash_type == RTL_DASH_NONE) {
5285 rtl_set_d3_pll_down(tp, true);
5287 rtl_set_d3_pll_down(tp, false);
5288 dev->wol_enabled = 1;
5291 jumbo_max = rtl_jumbo_max(tp);
5293 dev->max_mtu = jumbo_max;
5295 rtl_set_irq_mask(tp);
5297 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5299 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5300 &tp->counters_phys_addr,
5305 pci_set_drvdata(pdev, tp);
5307 rc = r8169_mdio_register(tp);
5311 rc = register_netdev(dev);
5315 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5316 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5319 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5320 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5323 if (tp->dash_type != RTL_DASH_NONE) {
5324 netdev_info(dev, "DASH enabled\n");
5325 rtl8168_driver_start(tp);
5328 if (pci_dev_run_wake(pdev))
5329 pm_runtime_put_sync(&pdev->dev);
5334 static struct pci_driver rtl8169_pci_driver = {
5335 .name = KBUILD_MODNAME,
5336 .id_table = rtl8169_pci_tbl,
5337 .probe = rtl_init_one,
5338 .remove = rtl_remove_one,
5339 .shutdown = rtl_shutdown,
5340 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5343 module_pci_driver(rtl8169_pci_driver);