2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/phy.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/prefetch.h>
29 #include <linux/ipv6.h>
30 #include <net/ip6_checksum.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58 #define R8169_MSG_DEFAULT \
59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61 #define TX_SLOTS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
64 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
65 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
66 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
72 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
73 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75 #define R8169_REGS_SIZE 256
76 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
77 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
78 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
79 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
80 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
82 #define RTL8169_TX_TIMEOUT (6*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
86 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
87 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
88 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
89 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
90 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
93 RTL_GIGA_MAC_VER_01 = 0,
144 RTL_GIGA_MAC_NONE = 0xff,
147 enum rtl_tx_desc_version {
152 #define JUMBO_1K ETH_DATA_LEN
153 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
154 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
155 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
156 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
158 #define _R(NAME,TD,FW,SZ) { \
165 static const struct {
167 enum rtl_tx_desc_version txd_version;
170 } rtl_chip_infos[] = {
172 [RTL_GIGA_MAC_VER_01] =
173 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K),
174 [RTL_GIGA_MAC_VER_02] =
175 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K),
176 [RTL_GIGA_MAC_VER_03] =
177 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K),
178 [RTL_GIGA_MAC_VER_04] =
179 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K),
180 [RTL_GIGA_MAC_VER_05] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
182 [RTL_GIGA_MAC_VER_06] =
183 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
185 [RTL_GIGA_MAC_VER_07] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
187 [RTL_GIGA_MAC_VER_08] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
189 [RTL_GIGA_MAC_VER_09] =
190 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
191 [RTL_GIGA_MAC_VER_10] =
192 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
193 [RTL_GIGA_MAC_VER_11] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
195 [RTL_GIGA_MAC_VER_12] =
196 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
197 [RTL_GIGA_MAC_VER_13] =
198 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
199 [RTL_GIGA_MAC_VER_14] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
201 [RTL_GIGA_MAC_VER_15] =
202 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
203 [RTL_GIGA_MAC_VER_16] =
204 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
205 [RTL_GIGA_MAC_VER_17] =
206 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
207 [RTL_GIGA_MAC_VER_18] =
208 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
209 [RTL_GIGA_MAC_VER_19] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
211 [RTL_GIGA_MAC_VER_20] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
213 [RTL_GIGA_MAC_VER_21] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
215 [RTL_GIGA_MAC_VER_22] =
216 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
217 [RTL_GIGA_MAC_VER_23] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
219 [RTL_GIGA_MAC_VER_24] =
220 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
221 [RTL_GIGA_MAC_VER_25] =
222 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
223 [RTL_GIGA_MAC_VER_26] =
224 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
231 [RTL_GIGA_MAC_VER_30] =
232 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
233 [RTL_GIGA_MAC_VER_31] =
234 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
235 [RTL_GIGA_MAC_VER_32] =
236 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
237 [RTL_GIGA_MAC_VER_33] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
239 [RTL_GIGA_MAC_VER_34] =
240 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
241 [RTL_GIGA_MAC_VER_35] =
242 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
243 [RTL_GIGA_MAC_VER_36] =
244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
245 [RTL_GIGA_MAC_VER_37] =
246 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K),
247 [RTL_GIGA_MAC_VER_38] =
248 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K),
249 [RTL_GIGA_MAC_VER_39] =
250 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
251 [RTL_GIGA_MAC_VER_40] =
252 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
253 [RTL_GIGA_MAC_VER_41] =
254 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K),
255 [RTL_GIGA_MAC_VER_42] =
256 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
257 [RTL_GIGA_MAC_VER_43] =
258 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
259 [RTL_GIGA_MAC_VER_44] =
260 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K),
261 [RTL_GIGA_MAC_VER_45] =
262 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
263 [RTL_GIGA_MAC_VER_46] =
264 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
265 [RTL_GIGA_MAC_VER_47] =
266 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
267 [RTL_GIGA_MAC_VER_48] =
268 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
269 [RTL_GIGA_MAC_VER_49] =
270 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
271 [RTL_GIGA_MAC_VER_50] =
272 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
273 [RTL_GIGA_MAC_VER_51] =
274 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
284 static const struct pci_device_id rtl8169_pci_tbl[] = {
285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
290 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
291 { PCI_VENDOR_ID_DLINK, 0x4300,
292 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
293 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
294 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
295 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
296 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
297 { PCI_VENDOR_ID_LINKSYS, 0x1032,
298 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
300 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
304 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
306 static int use_dac = -1;
312 MAC0 = 0, /* Ethernet hardware address. */
314 MAR0 = 8, /* Multicast filter. */
315 CounterAddrLow = 0x10,
316 CounterAddrHigh = 0x14,
317 TxDescStartAddrLow = 0x20,
318 TxDescStartAddrHigh = 0x24,
319 TxHDescStartAddrLow = 0x28,
320 TxHDescStartAddrHigh = 0x2c,
329 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
330 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
333 #define RX128_INT_EN (1 << 15) /* 8111c and later */
334 #define RX_MULTI_EN (1 << 14) /* 8111c only */
335 #define RXCFG_FIFO_SHIFT 13
336 /* No threshold before first PCI xfer */
337 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
338 #define RX_EARLY_OFF (1 << 11)
339 #define RXCFG_DMA_SHIFT 8
340 /* Unlimited maximum PCI burst. */
341 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
348 #define PME_SIGNAL (1 << 5) /* 8168c and later */
360 #define RTL_COALESCE_MASK 0x0f
361 #define RTL_COALESCE_SHIFT 4
362 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
363 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
365 RxDescAddrLow = 0xe4,
366 RxDescAddrHigh = 0xe8,
367 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
369 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
371 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
373 #define TxPacketMax (8064 >> 7)
374 #define EarlySize 0x27
377 FuncEventMask = 0xf4,
378 FuncPresetState = 0xf8,
383 FuncForceEvent = 0xfc,
386 enum rtl8168_8101_registers {
389 #define CSIAR_FLAG 0x80000000
390 #define CSIAR_WRITE_CMD 0x80000000
391 #define CSIAR_BYTE_ENABLE 0x0000f000
392 #define CSIAR_ADDR_MASK 0x00000fff
395 #define EPHYAR_FLAG 0x80000000
396 #define EPHYAR_WRITE_CMD 0x80000000
397 #define EPHYAR_REG_MASK 0x1f
398 #define EPHYAR_REG_SHIFT 16
399 #define EPHYAR_DATA_MASK 0xffff
401 #define PFM_EN (1 << 6)
402 #define TX_10M_PS_EN (1 << 7)
404 #define FIX_NAK_1 (1 << 4)
405 #define FIX_NAK_2 (1 << 3)
408 #define NOW_IS_OOB (1 << 7)
409 #define TX_EMPTY (1 << 5)
410 #define RX_EMPTY (1 << 4)
411 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
412 #define EN_NDP (1 << 3)
413 #define EN_OOB_RESET (1 << 2)
414 #define LINK_LIST_RDY (1 << 1)
416 #define EFUSEAR_FLAG 0x80000000
417 #define EFUSEAR_WRITE_CMD 0x80000000
418 #define EFUSEAR_READ_CMD 0x00000000
419 #define EFUSEAR_REG_MASK 0x03ff
420 #define EFUSEAR_REG_SHIFT 8
421 #define EFUSEAR_DATA_MASK 0xff
423 #define PFM_D3COLD_EN (1 << 6)
426 enum rtl8168_registers {
431 #define ERIAR_FLAG 0x80000000
432 #define ERIAR_WRITE_CMD 0x80000000
433 #define ERIAR_READ_CMD 0x00000000
434 #define ERIAR_ADDR_BYTE_ALIGN 4
435 #define ERIAR_TYPE_SHIFT 16
436 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
437 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
438 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
439 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
440 #define ERIAR_MASK_SHIFT 12
441 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
442 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
443 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
444 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
445 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
446 EPHY_RXER_NUM = 0x7c,
447 OCPDR = 0xb0, /* OCP GPHY access */
448 #define OCPDR_WRITE_CMD 0x80000000
449 #define OCPDR_READ_CMD 0x00000000
450 #define OCPDR_REG_MASK 0x7f
451 #define OCPDR_GPHY_REG_SHIFT 16
452 #define OCPDR_DATA_MASK 0xffff
454 #define OCPAR_FLAG 0x80000000
455 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
456 #define OCPAR_GPHY_READ_CMD 0x0000f060
458 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
459 MISC = 0xf0, /* 8168e only. */
460 #define TXPLA_RST (1 << 29)
461 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
462 #define PWM_EN (1 << 22)
463 #define RXDV_GATED_EN (1 << 19)
464 #define EARLY_TALLY_EN (1 << 16)
467 enum rtl_register_content {
468 /* InterruptStatusBits */
472 TxDescUnavail = 0x0080,
496 /* TXPoll register p.5 */
497 HPQ = 0x80, /* Poll cmd on the high prio queue */
498 NPQ = 0x40, /* Poll cmd on the low prio queue */
499 FSWInt = 0x01, /* Forced software interrupt */
503 Cfg9346_Unlock = 0xc0,
508 AcceptBroadcast = 0x08,
509 AcceptMulticast = 0x04,
511 AcceptAllPhys = 0x01,
512 #define RX_CONFIG_ACCEPT_MASK 0x3f
515 TxInterFrameGapShift = 24,
516 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
518 /* Config1 register p.24 */
521 Speed_down = (1 << 4),
525 PMEnable = (1 << 0), /* Power Management Enable */
527 /* Config2 register p. 25 */
528 ClkReqEn = (1 << 7), /* Clock Request Enable */
529 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
530 PCI_Clock_66MHz = 0x01,
531 PCI_Clock_33MHz = 0x00,
533 /* Config3 register p.25 */
534 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
535 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
536 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
537 Rdy_to_L23 = (1 << 1), /* L23 Enable */
538 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
540 /* Config4 register */
541 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
543 /* Config5 register p.27 */
544 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
545 MWF = (1 << 5), /* Accept Multicast wakeup frame */
546 UWF = (1 << 4), /* Accept Unicast wakeup frame */
548 LanWake = (1 << 1), /* LanWake enable/disable */
549 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
550 ASPM_en = (1 << 0), /* ASPM enable */
553 EnableBist = (1 << 15), // 8168 8101
554 Mac_dbgo_oe = (1 << 14), // 8168 8101
555 Normal_mode = (1 << 13), // unused
556 Force_half_dup = (1 << 12), // 8168 8101
557 Force_rxflow_en = (1 << 11), // 8168 8101
558 Force_txflow_en = (1 << 10), // 8168 8101
559 Cxpl_dbg_sel = (1 << 9), // 8168 8101
560 ASF = (1 << 8), // 8168 8101
561 PktCntrDisable = (1 << 7), // 8168 8101
562 Mac_dbgo_sel = 0x001c, // 8168
567 #define INTT_MASK GENMASK(1, 0)
568 INTT_0 = 0x0000, // 8168
569 INTT_1 = 0x0001, // 8168
570 INTT_2 = 0x0002, // 8168
571 INTT_3 = 0x0003, // 8168
573 /* rtl8169_PHYstatus */
584 TBILinkOK = 0x02000000,
586 /* ResetCounterCommand */
589 /* DumpCounterCommand */
592 /* magic enable v2 */
593 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
597 /* First doubleword. */
598 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
599 RingEnd = (1 << 30), /* End of descriptor ring */
600 FirstFrag = (1 << 29), /* First segment of a packet */
601 LastFrag = (1 << 28), /* Final segment of a packet */
605 enum rtl_tx_desc_bit {
606 /* First doubleword. */
607 TD_LSO = (1 << 27), /* Large Send Offload */
608 #define TD_MSS_MAX 0x07ffu /* MSS value */
610 /* Second doubleword. */
611 TxVlanTag = (1 << 17), /* Add VLAN tag */
614 /* 8169, 8168b and 810x except 8102e. */
615 enum rtl_tx_desc_bit_0 {
616 /* First doubleword. */
617 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
618 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
619 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
620 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
623 /* 8102e, 8168c and beyond. */
624 enum rtl_tx_desc_bit_1 {
625 /* First doubleword. */
626 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
627 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
628 #define GTTCPHO_SHIFT 18
629 #define GTTCPHO_MAX 0x7fU
631 /* Second doubleword. */
632 #define TCPHO_SHIFT 18
633 #define TCPHO_MAX 0x3ffU
634 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
635 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
636 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
637 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
638 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
641 enum rtl_rx_desc_bit {
643 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
644 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
646 #define RxProtoUDP (PID1)
647 #define RxProtoTCP (PID0)
648 #define RxProtoIP (PID1 | PID0)
649 #define RxProtoMask RxProtoIP
651 IPFail = (1 << 16), /* IP checksum failed */
652 UDPFail = (1 << 15), /* UDP/IP checksum failed */
653 TCPFail = (1 << 14), /* TCP/IP checksum failed */
654 RxVlanTag = (1 << 16), /* VLAN tag available */
657 #define RsvdMask 0x3fffc000
658 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
675 u8 __pad[sizeof(void *) - sizeof(u32)];
678 struct rtl8169_counters {
685 __le32 tx_one_collision;
686 __le32 tx_multi_collision;
694 struct rtl8169_tc_offsets {
697 __le32 tx_multi_collision;
702 RTL_FLAG_TASK_ENABLED,
703 RTL_FLAG_TASK_SLOW_PENDING,
704 RTL_FLAG_TASK_RESET_PENDING,
708 struct rtl8169_stats {
711 struct u64_stats_sync syncp;
714 struct rtl8169_private {
715 void __iomem *mmio_addr; /* memory map physical address */
716 struct pci_dev *pci_dev;
717 struct net_device *dev;
718 struct napi_struct napi;
721 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
722 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
724 struct rtl8169_stats rx_stats;
725 struct rtl8169_stats tx_stats;
726 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
727 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
728 dma_addr_t TxPhyAddr;
729 dma_addr_t RxPhyAddr;
730 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
731 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
735 const struct rtl_coalesce_info *coalesce_info;
738 void (*write)(struct rtl8169_private *, int, int);
739 int (*read)(struct rtl8169_private *, int);
743 void (*enable)(struct rtl8169_private *);
744 void (*disable)(struct rtl8169_private *);
747 void (*hw_start)(struct rtl8169_private *tp);
748 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
751 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
753 struct work_struct work;
756 unsigned supports_gmii:1;
757 struct mii_bus *mii_bus;
758 dma_addr_t counters_phys_addr;
759 struct rtl8169_counters *counters;
760 struct rtl8169_tc_offsets tc_offset;
764 const struct firmware *fw;
766 #define RTL_VER_SIZE 32
768 char version[RTL_VER_SIZE];
770 struct rtl_fw_phy_action {
775 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
780 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
781 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
782 module_param(use_dac, int, 0);
783 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
784 module_param_named(debug, debug.msg_enable, int, 0);
785 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
786 MODULE_LICENSE("GPL");
787 MODULE_VERSION(RTL8169_VERSION);
788 MODULE_FIRMWARE(FIRMWARE_8168D_1);
789 MODULE_FIRMWARE(FIRMWARE_8168D_2);
790 MODULE_FIRMWARE(FIRMWARE_8168E_1);
791 MODULE_FIRMWARE(FIRMWARE_8168E_2);
792 MODULE_FIRMWARE(FIRMWARE_8168E_3);
793 MODULE_FIRMWARE(FIRMWARE_8105E_1);
794 MODULE_FIRMWARE(FIRMWARE_8168F_1);
795 MODULE_FIRMWARE(FIRMWARE_8168F_2);
796 MODULE_FIRMWARE(FIRMWARE_8402_1);
797 MODULE_FIRMWARE(FIRMWARE_8411_1);
798 MODULE_FIRMWARE(FIRMWARE_8411_2);
799 MODULE_FIRMWARE(FIRMWARE_8106E_1);
800 MODULE_FIRMWARE(FIRMWARE_8106E_2);
801 MODULE_FIRMWARE(FIRMWARE_8168G_2);
802 MODULE_FIRMWARE(FIRMWARE_8168G_3);
803 MODULE_FIRMWARE(FIRMWARE_8168H_1);
804 MODULE_FIRMWARE(FIRMWARE_8168H_2);
805 MODULE_FIRMWARE(FIRMWARE_8107E_1);
806 MODULE_FIRMWARE(FIRMWARE_8107E_2);
808 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
810 return &tp->pci_dev->dev;
813 static void rtl_lock_work(struct rtl8169_private *tp)
815 mutex_lock(&tp->wk.mutex);
818 static void rtl_unlock_work(struct rtl8169_private *tp)
820 mutex_unlock(&tp->wk.mutex);
823 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
825 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
826 PCI_EXP_DEVCTL_READRQ, force);
830 bool (*check)(struct rtl8169_private *);
834 static void rtl_udelay(unsigned int d)
839 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
840 void (*delay)(unsigned int), unsigned int d, int n,
845 for (i = 0; i < n; i++) {
847 if (c->check(tp) == high)
850 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
851 c->msg, !high, n, d);
855 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
856 const struct rtl_cond *c,
857 unsigned int d, int n)
859 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
862 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
863 const struct rtl_cond *c,
864 unsigned int d, int n)
866 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
869 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
870 const struct rtl_cond *c,
871 unsigned int d, int n)
873 return rtl_loop_wait(tp, c, msleep, d, n, true);
876 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
877 const struct rtl_cond *c,
878 unsigned int d, int n)
880 return rtl_loop_wait(tp, c, msleep, d, n, false);
883 #define DECLARE_RTL_COND(name) \
884 static bool name ## _check(struct rtl8169_private *); \
886 static const struct rtl_cond name = { \
887 .check = name ## _check, \
891 static bool name ## _check(struct rtl8169_private *tp)
893 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
895 if (reg & 0xffff0001) {
896 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
902 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
904 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
907 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
909 if (rtl_ocp_reg_failure(tp, reg))
912 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
914 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
917 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
919 if (rtl_ocp_reg_failure(tp, reg))
922 RTL_W32(tp, GPHY_OCP, reg << 15);
924 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
925 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
928 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
930 if (rtl_ocp_reg_failure(tp, reg))
933 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
936 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
938 if (rtl_ocp_reg_failure(tp, reg))
941 RTL_W32(tp, OCPDR, reg << 15);
943 return RTL_R32(tp, OCPDR);
946 #define OCP_STD_PHY_BASE 0xa400
948 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
951 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
955 if (tp->ocp_base != OCP_STD_PHY_BASE)
958 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
961 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
963 if (tp->ocp_base != OCP_STD_PHY_BASE)
966 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
969 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
972 tp->ocp_base = value << 4;
976 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
979 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
981 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
984 DECLARE_RTL_COND(rtl_phyar_cond)
986 return RTL_R32(tp, PHYAR) & 0x80000000;
989 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
991 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
993 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
995 * According to hardware specs a 20us delay is required after write
996 * complete indication, but before sending next command.
1001 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1005 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1007 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1008 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1011 * According to hardware specs a 20us delay is required after read
1012 * complete indication, but before sending next command.
1019 DECLARE_RTL_COND(rtl_ocpar_cond)
1021 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1024 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1026 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1027 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1028 RTL_W32(tp, EPHY_RXER_NUM, 0);
1030 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1033 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1035 r8168dp_1_mdio_access(tp, reg,
1036 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1039 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1041 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1044 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1045 RTL_W32(tp, EPHY_RXER_NUM, 0);
1047 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1048 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1051 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1053 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1055 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1058 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1060 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1063 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 r8168dp_2_mdio_start(tp);
1067 r8169_mdio_write(tp, reg, value);
1069 r8168dp_2_mdio_stop(tp);
1072 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1076 r8168dp_2_mdio_start(tp);
1078 value = r8169_mdio_read(tp, reg);
1080 r8168dp_2_mdio_stop(tp);
1085 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1087 tp->mdio_ops.write(tp, location, val);
1090 static int rtl_readphy(struct rtl8169_private *tp, int location)
1092 return tp->mdio_ops.read(tp, location);
1095 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1097 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1100 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1104 val = rtl_readphy(tp, reg_addr);
1105 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1108 DECLARE_RTL_COND(rtl_ephyar_cond)
1110 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1113 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1115 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1116 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1118 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1123 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1125 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1127 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1128 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1131 DECLARE_RTL_COND(rtl_eriar_cond)
1133 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1136 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1139 BUG_ON((addr & 3) || (mask == 0));
1140 RTL_W32(tp, ERIDR, val);
1141 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1143 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1146 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1148 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1150 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1151 RTL_R32(tp, ERIDR) : ~0;
1154 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1159 val = rtl_eri_read(tp, addr, type);
1160 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1163 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1165 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1166 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1167 RTL_R32(tp, OCPDR) : ~0;
1170 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1172 return rtl_eri_read(tp, reg, ERIAR_OOB);
1175 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1177 switch (tp->mac_version) {
1178 case RTL_GIGA_MAC_VER_27:
1179 case RTL_GIGA_MAC_VER_28:
1180 case RTL_GIGA_MAC_VER_31:
1181 return r8168dp_ocp_read(tp, mask, reg);
1182 case RTL_GIGA_MAC_VER_49:
1183 case RTL_GIGA_MAC_VER_50:
1184 case RTL_GIGA_MAC_VER_51:
1185 return r8168ep_ocp_read(tp, mask, reg);
1192 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1195 RTL_W32(tp, OCPDR, data);
1196 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1197 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1200 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1203 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1207 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1209 switch (tp->mac_version) {
1210 case RTL_GIGA_MAC_VER_27:
1211 case RTL_GIGA_MAC_VER_28:
1212 case RTL_GIGA_MAC_VER_31:
1213 r8168dp_ocp_write(tp, mask, reg, data);
1215 case RTL_GIGA_MAC_VER_49:
1216 case RTL_GIGA_MAC_VER_50:
1217 case RTL_GIGA_MAC_VER_51:
1218 r8168ep_ocp_write(tp, mask, reg, data);
1226 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1228 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1230 ocp_write(tp, 0x1, 0x30, 0x00000001);
1233 #define OOB_CMD_RESET 0x00
1234 #define OOB_CMD_DRIVER_START 0x05
1235 #define OOB_CMD_DRIVER_STOP 0x06
1237 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1239 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1242 DECLARE_RTL_COND(rtl_ocp_read_cond)
1246 reg = rtl8168_get_ocp_reg(tp);
1248 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1251 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1253 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1256 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1258 return RTL_R8(tp, IBISR0) & 0x20;
1261 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1263 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1264 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1265 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1266 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1269 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1271 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1272 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1275 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1277 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1278 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1279 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1282 static void rtl8168_driver_start(struct rtl8169_private *tp)
1284 switch (tp->mac_version) {
1285 case RTL_GIGA_MAC_VER_27:
1286 case RTL_GIGA_MAC_VER_28:
1287 case RTL_GIGA_MAC_VER_31:
1288 rtl8168dp_driver_start(tp);
1290 case RTL_GIGA_MAC_VER_49:
1291 case RTL_GIGA_MAC_VER_50:
1292 case RTL_GIGA_MAC_VER_51:
1293 rtl8168ep_driver_start(tp);
1301 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1303 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1304 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1307 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1309 rtl8168ep_stop_cmac(tp);
1310 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1311 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1312 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1315 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1317 switch (tp->mac_version) {
1318 case RTL_GIGA_MAC_VER_27:
1319 case RTL_GIGA_MAC_VER_28:
1320 case RTL_GIGA_MAC_VER_31:
1321 rtl8168dp_driver_stop(tp);
1323 case RTL_GIGA_MAC_VER_49:
1324 case RTL_GIGA_MAC_VER_50:
1325 case RTL_GIGA_MAC_VER_51:
1326 rtl8168ep_driver_stop(tp);
1334 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1336 u16 reg = rtl8168_get_ocp_reg(tp);
1338 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1341 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1343 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1346 static bool r8168_check_dash(struct rtl8169_private *tp)
1348 switch (tp->mac_version) {
1349 case RTL_GIGA_MAC_VER_27:
1350 case RTL_GIGA_MAC_VER_28:
1351 case RTL_GIGA_MAC_VER_31:
1352 return r8168dp_check_dash(tp);
1353 case RTL_GIGA_MAC_VER_49:
1354 case RTL_GIGA_MAC_VER_50:
1355 case RTL_GIGA_MAC_VER_51:
1356 return r8168ep_check_dash(tp);
1368 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1369 const struct exgmac_reg *r, int len)
1372 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1377 DECLARE_RTL_COND(rtl_efusear_cond)
1379 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1382 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1384 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1386 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1387 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1390 static u16 rtl_get_events(struct rtl8169_private *tp)
1392 return RTL_R16(tp, IntrStatus);
1395 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1397 RTL_W16(tp, IntrStatus, bits);
1401 static void rtl_irq_disable(struct rtl8169_private *tp)
1403 RTL_W16(tp, IntrMask, 0);
1407 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1409 RTL_W16(tp, IntrMask, bits);
1412 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1413 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1414 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1416 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1418 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1421 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1423 rtl_irq_disable(tp);
1424 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1425 RTL_R8(tp, ChipCmd);
1428 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1430 struct net_device *dev = tp->dev;
1431 struct phy_device *phydev = dev->phydev;
1433 if (!netif_running(dev))
1436 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1437 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1438 if (phydev->speed == SPEED_1000) {
1439 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1443 } else if (phydev->speed == SPEED_100) {
1444 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1446 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1449 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1451 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1454 /* Reset packet filter */
1455 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1457 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1459 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1460 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1461 if (phydev->speed == SPEED_1000) {
1462 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1464 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1467 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1469 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1472 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1473 if (phydev->speed == SPEED_10) {
1474 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1476 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1479 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1485 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1487 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1492 options = RTL_R8(tp, Config1);
1493 if (!(options & PMEnable))
1496 options = RTL_R8(tp, Config3);
1497 if (options & LinkUp)
1498 wolopts |= WAKE_PHY;
1499 switch (tp->mac_version) {
1500 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1501 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1502 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1503 wolopts |= WAKE_MAGIC;
1506 if (options & MagicPacket)
1507 wolopts |= WAKE_MAGIC;
1511 options = RTL_R8(tp, Config5);
1513 wolopts |= WAKE_UCAST;
1515 wolopts |= WAKE_BCAST;
1517 wolopts |= WAKE_MCAST;
1522 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1524 struct rtl8169_private *tp = netdev_priv(dev);
1527 wol->supported = WAKE_ANY;
1528 wol->wolopts = tp->saved_wolopts;
1529 rtl_unlock_work(tp);
1532 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1534 unsigned int i, tmp;
1535 static const struct {
1540 { WAKE_PHY, Config3, LinkUp },
1541 { WAKE_UCAST, Config5, UWF },
1542 { WAKE_BCAST, Config5, BWF },
1543 { WAKE_MCAST, Config5, MWF },
1544 { WAKE_ANY, Config5, LanWake },
1545 { WAKE_MAGIC, Config3, MagicPacket }
1549 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1551 switch (tp->mac_version) {
1552 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1553 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1554 tmp = ARRAY_SIZE(cfg) - 1;
1555 if (wolopts & WAKE_MAGIC)
1571 tmp = ARRAY_SIZE(cfg);
1575 for (i = 0; i < tmp; i++) {
1576 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1577 if (wolopts & cfg[i].opt)
1578 options |= cfg[i].mask;
1579 RTL_W8(tp, cfg[i].reg, options);
1582 switch (tp->mac_version) {
1583 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1584 options = RTL_R8(tp, Config1) & ~PMEnable;
1586 options |= PMEnable;
1587 RTL_W8(tp, Config1, options);
1590 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1592 options |= PME_SIGNAL;
1593 RTL_W8(tp, Config2, options);
1597 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1600 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1602 struct rtl8169_private *tp = netdev_priv(dev);
1603 struct device *d = tp_to_dev(tp);
1605 if (wol->wolopts & ~WAKE_ANY)
1608 pm_runtime_get_noresume(d);
1612 tp->saved_wolopts = wol->wolopts;
1614 if (pm_runtime_active(d))
1615 __rtl8169_set_wol(tp, tp->saved_wolopts);
1617 rtl_unlock_work(tp);
1619 device_set_wakeup_enable(d, tp->saved_wolopts);
1621 pm_runtime_put_noidle(d);
1626 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1628 return rtl_chip_infos[tp->mac_version].fw_name;
1631 static void rtl8169_get_drvinfo(struct net_device *dev,
1632 struct ethtool_drvinfo *info)
1634 struct rtl8169_private *tp = netdev_priv(dev);
1635 struct rtl_fw *rtl_fw = tp->rtl_fw;
1637 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1638 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1639 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1640 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1641 if (!IS_ERR_OR_NULL(rtl_fw))
1642 strlcpy(info->fw_version, rtl_fw->version,
1643 sizeof(info->fw_version));
1646 static int rtl8169_get_regs_len(struct net_device *dev)
1648 return R8169_REGS_SIZE;
1651 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1652 netdev_features_t features)
1654 struct rtl8169_private *tp = netdev_priv(dev);
1656 if (dev->mtu > TD_MSS_MAX)
1657 features &= ~NETIF_F_ALL_TSO;
1659 if (dev->mtu > JUMBO_1K &&
1660 tp->mac_version > RTL_GIGA_MAC_VER_06)
1661 features &= ~NETIF_F_IP_CSUM;
1666 static int rtl8169_set_features(struct net_device *dev,
1667 netdev_features_t features)
1669 struct rtl8169_private *tp = netdev_priv(dev);
1674 rx_config = RTL_R32(tp, RxConfig);
1675 if (features & NETIF_F_RXALL)
1676 rx_config |= (AcceptErr | AcceptRunt);
1678 rx_config &= ~(AcceptErr | AcceptRunt);
1680 RTL_W32(tp, RxConfig, rx_config);
1682 if (features & NETIF_F_RXCSUM)
1683 tp->cp_cmd |= RxChkSum;
1685 tp->cp_cmd &= ~RxChkSum;
1687 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1688 tp->cp_cmd |= RxVlan;
1690 tp->cp_cmd &= ~RxVlan;
1692 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1693 RTL_R16(tp, CPlusCmd);
1695 rtl_unlock_work(tp);
1700 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1702 return (skb_vlan_tag_present(skb)) ?
1703 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1706 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1708 u32 opts2 = le32_to_cpu(desc->opts2);
1710 if (opts2 & RxVlanTag)
1711 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1714 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1717 struct rtl8169_private *tp = netdev_priv(dev);
1718 u32 __iomem *data = tp->mmio_addr;
1723 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1724 memcpy_fromio(dw++, data++, 4);
1725 rtl_unlock_work(tp);
1728 static u32 rtl8169_get_msglevel(struct net_device *dev)
1730 struct rtl8169_private *tp = netdev_priv(dev);
1732 return tp->msg_enable;
1735 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1737 struct rtl8169_private *tp = netdev_priv(dev);
1739 tp->msg_enable = value;
1742 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1749 "tx_single_collisions",
1750 "tx_multi_collisions",
1758 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1762 return ARRAY_SIZE(rtl8169_gstrings);
1768 DECLARE_RTL_COND(rtl_counters_cond)
1770 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1773 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1775 dma_addr_t paddr = tp->counters_phys_addr;
1778 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1779 RTL_R32(tp, CounterAddrHigh);
1780 cmd = (u64)paddr & DMA_BIT_MASK(32);
1781 RTL_W32(tp, CounterAddrLow, cmd);
1782 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1784 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1787 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1790 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1793 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1796 return rtl8169_do_counters(tp, CounterReset);
1799 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1802 * Some chips are unable to dump tally counters when the receiver
1805 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1808 return rtl8169_do_counters(tp, CounterDump);
1811 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1813 struct rtl8169_counters *counters = tp->counters;
1817 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1818 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1819 * reset by a power cycle, while the counter values collected by the
1820 * driver are reset at every driver unload/load cycle.
1822 * To make sure the HW values returned by @get_stats64 match the SW
1823 * values, we collect the initial values at first open(*) and use them
1824 * as offsets to normalize the values returned by @get_stats64.
1826 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1827 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1828 * set at open time by rtl_hw_start.
1831 if (tp->tc_offset.inited)
1834 /* If both, reset and update fail, propagate to caller. */
1835 if (rtl8169_reset_counters(tp))
1838 if (rtl8169_update_counters(tp))
1841 tp->tc_offset.tx_errors = counters->tx_errors;
1842 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1843 tp->tc_offset.tx_aborted = counters->tx_aborted;
1844 tp->tc_offset.inited = true;
1849 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1850 struct ethtool_stats *stats, u64 *data)
1852 struct rtl8169_private *tp = netdev_priv(dev);
1853 struct device *d = tp_to_dev(tp);
1854 struct rtl8169_counters *counters = tp->counters;
1858 pm_runtime_get_noresume(d);
1860 if (pm_runtime_active(d))
1861 rtl8169_update_counters(tp);
1863 pm_runtime_put_noidle(d);
1865 data[0] = le64_to_cpu(counters->tx_packets);
1866 data[1] = le64_to_cpu(counters->rx_packets);
1867 data[2] = le64_to_cpu(counters->tx_errors);
1868 data[3] = le32_to_cpu(counters->rx_errors);
1869 data[4] = le16_to_cpu(counters->rx_missed);
1870 data[5] = le16_to_cpu(counters->align_errors);
1871 data[6] = le32_to_cpu(counters->tx_one_collision);
1872 data[7] = le32_to_cpu(counters->tx_multi_collision);
1873 data[8] = le64_to_cpu(counters->rx_unicast);
1874 data[9] = le64_to_cpu(counters->rx_broadcast);
1875 data[10] = le32_to_cpu(counters->rx_multicast);
1876 data[11] = le16_to_cpu(counters->tx_aborted);
1877 data[12] = le16_to_cpu(counters->tx_underun);
1880 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1884 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1890 * Interrupt coalescing
1892 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1893 * > 8169, 8168 and 810x line of chipsets
1895 * 8169, 8168, and 8136(810x) serial chipsets support it.
1897 * > 2 - the Tx timer unit at gigabit speed
1899 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1900 * (0xe0) bit 1 and bit 0.
1903 * bit[1:0] \ speed 1000M 100M 10M
1904 * 0 0 320ns 2.56us 40.96us
1905 * 0 1 2.56us 20.48us 327.7us
1906 * 1 0 5.12us 40.96us 655.4us
1907 * 1 1 10.24us 81.92us 1.31ms
1910 * bit[1:0] \ speed 1000M 100M 10M
1911 * 0 0 5us 2.56us 40.96us
1912 * 0 1 40us 20.48us 327.7us
1913 * 1 0 80us 40.96us 655.4us
1914 * 1 1 160us 81.92us 1.31ms
1917 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1918 struct rtl_coalesce_scale {
1923 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1924 struct rtl_coalesce_info {
1926 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1929 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1930 #define rxtx_x1822(r, t) { \
1933 {{(r)*8*2, (t)*8*2}}, \
1934 {{(r)*8*2*2, (t)*8*2*2}}, \
1936 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1937 /* speed delays: rx00 tx00 */
1938 { SPEED_10, rxtx_x1822(40960, 40960) },
1939 { SPEED_100, rxtx_x1822( 2560, 2560) },
1940 { SPEED_1000, rxtx_x1822( 320, 320) },
1944 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1945 /* speed delays: rx00 tx00 */
1946 { SPEED_10, rxtx_x1822(40960, 40960) },
1947 { SPEED_100, rxtx_x1822( 2560, 2560) },
1948 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1953 /* get rx/tx scale vector corresponding to current speed */
1954 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1956 struct rtl8169_private *tp = netdev_priv(dev);
1957 struct ethtool_link_ksettings ecmd;
1958 const struct rtl_coalesce_info *ci;
1961 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1965 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1966 if (ecmd.base.speed == ci->speed) {
1971 return ERR_PTR(-ELNRNG);
1974 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1976 struct rtl8169_private *tp = netdev_priv(dev);
1977 const struct rtl_coalesce_info *ci;
1978 const struct rtl_coalesce_scale *scale;
1982 } coal_settings [] = {
1983 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1984 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1985 }, *p = coal_settings;
1989 memset(ec, 0, sizeof(*ec));
1991 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1992 ci = rtl_coalesce_info(dev);
1996 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1998 /* read IntrMitigate and adjust according to scale */
1999 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2000 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2001 w >>= RTL_COALESCE_SHIFT;
2002 *p->usecs = w & RTL_COALESCE_MASK;
2005 for (i = 0; i < 2; i++) {
2006 p = coal_settings + i;
2007 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2010 * ethtool_coalesce says it is illegal to set both usecs and
2013 if (!*p->usecs && !*p->max_frames)
2020 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2021 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2022 struct net_device *dev, u32 nsec, u16 *cp01)
2024 const struct rtl_coalesce_info *ci;
2027 ci = rtl_coalesce_info(dev);
2029 return ERR_CAST(ci);
2031 for (i = 0; i < 4; i++) {
2032 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2033 ci->scalev[i].nsecs[1]);
2034 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2036 return &ci->scalev[i];
2040 return ERR_PTR(-EINVAL);
2043 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2045 struct rtl8169_private *tp = netdev_priv(dev);
2046 const struct rtl_coalesce_scale *scale;
2050 } coal_settings [] = {
2051 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2052 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2053 }, *p = coal_settings;
2057 scale = rtl_coalesce_choose_scale(dev,
2058 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2060 return PTR_ERR(scale);
2062 for (i = 0; i < 2; i++, p++) {
2066 * accept max_frames=1 we returned in rtl_get_coalesce.
2067 * accept it not only when usecs=0 because of e.g. the following scenario:
2069 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2070 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2071 * - then user does `ethtool -C eth0 rx-usecs 100`
2073 * since ethtool sends to kernel whole ethtool_coalesce
2074 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2075 * we'll reject it below in `frames % 4 != 0`.
2077 if (p->frames == 1) {
2081 units = p->usecs * 1000 / scale->nsecs[i];
2082 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2085 w <<= RTL_COALESCE_SHIFT;
2087 w <<= RTL_COALESCE_SHIFT;
2088 w |= p->frames >> 2;
2093 RTL_W16(tp, IntrMitigate, swab16(w));
2095 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2096 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2097 RTL_R16(tp, CPlusCmd);
2099 rtl_unlock_work(tp);
2104 static const struct ethtool_ops rtl8169_ethtool_ops = {
2105 .get_drvinfo = rtl8169_get_drvinfo,
2106 .get_regs_len = rtl8169_get_regs_len,
2107 .get_link = ethtool_op_get_link,
2108 .get_coalesce = rtl_get_coalesce,
2109 .set_coalesce = rtl_set_coalesce,
2110 .get_msglevel = rtl8169_get_msglevel,
2111 .set_msglevel = rtl8169_set_msglevel,
2112 .get_regs = rtl8169_get_regs,
2113 .get_wol = rtl8169_get_wol,
2114 .set_wol = rtl8169_set_wol,
2115 .get_strings = rtl8169_get_strings,
2116 .get_sset_count = rtl8169_get_sset_count,
2117 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2118 .get_ts_info = ethtool_op_get_ts_info,
2119 .nway_reset = phy_ethtool_nway_reset,
2120 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2121 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2124 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2128 * The driver currently handles the 8168Bf and the 8168Be identically
2129 * but they can be identified more specifically through the test below
2132 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2134 * Same thing for the 8101Eb and the 8101Ec:
2136 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2138 static const struct rtl_mac_info {
2143 /* 8168EP family. */
2144 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2145 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2146 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2149 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2150 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2153 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2154 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2155 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2156 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2159 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2160 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2161 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2164 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2165 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2166 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2169 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2170 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2172 /* 8168DP family. */
2173 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2174 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2175 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2178 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2179 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2180 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2181 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2182 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2183 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2184 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2187 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2188 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2189 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2192 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2193 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2194 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2195 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2196 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2197 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2198 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2199 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2200 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2201 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2202 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2203 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2204 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2205 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2206 /* FIXME: where did these entries come from ? -- FR */
2207 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2208 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2211 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2212 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2213 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2214 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2215 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2216 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2219 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2221 const struct rtl_mac_info *p = mac_info;
2224 reg = RTL_R32(tp, TxConfig);
2225 while ((reg & p->mask) != p->val)
2227 tp->mac_version = p->mac_version;
2229 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2230 dev_notice(tp_to_dev(tp),
2231 "unknown MAC, using family default\n");
2232 tp->mac_version = default_version;
2233 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2234 tp->mac_version = tp->supports_gmii ?
2235 RTL_GIGA_MAC_VER_42 :
2236 RTL_GIGA_MAC_VER_43;
2237 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2238 tp->mac_version = tp->supports_gmii ?
2239 RTL_GIGA_MAC_VER_45 :
2240 RTL_GIGA_MAC_VER_47;
2241 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2242 tp->mac_version = tp->supports_gmii ?
2243 RTL_GIGA_MAC_VER_46 :
2244 RTL_GIGA_MAC_VER_48;
2248 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2250 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2258 static void rtl_writephy_batch(struct rtl8169_private *tp,
2259 const struct phy_reg *regs, int len)
2262 rtl_writephy(tp, regs->reg, regs->val);
2267 #define PHY_READ 0x00000000
2268 #define PHY_DATA_OR 0x10000000
2269 #define PHY_DATA_AND 0x20000000
2270 #define PHY_BJMPN 0x30000000
2271 #define PHY_MDIO_CHG 0x40000000
2272 #define PHY_CLEAR_READCOUNT 0x70000000
2273 #define PHY_WRITE 0x80000000
2274 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2275 #define PHY_COMP_EQ_SKIPN 0xa0000000
2276 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2277 #define PHY_WRITE_PREVIOUS 0xc0000000
2278 #define PHY_SKIPN 0xd0000000
2279 #define PHY_DELAY_MS 0xe0000000
2283 char version[RTL_VER_SIZE];
2289 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2291 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2293 const struct firmware *fw = rtl_fw->fw;
2294 struct fw_info *fw_info = (struct fw_info *)fw->data;
2295 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2296 char *version = rtl_fw->version;
2299 if (fw->size < FW_OPCODE_SIZE)
2302 if (!fw_info->magic) {
2303 size_t i, size, start;
2306 if (fw->size < sizeof(*fw_info))
2309 for (i = 0; i < fw->size; i++)
2310 checksum += fw->data[i];
2314 start = le32_to_cpu(fw_info->fw_start);
2315 if (start > fw->size)
2318 size = le32_to_cpu(fw_info->fw_len);
2319 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2322 memcpy(version, fw_info->version, RTL_VER_SIZE);
2324 pa->code = (__le32 *)(fw->data + start);
2327 if (fw->size % FW_OPCODE_SIZE)
2330 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2332 pa->code = (__le32 *)fw->data;
2333 pa->size = fw->size / FW_OPCODE_SIZE;
2335 version[RTL_VER_SIZE - 1] = 0;
2342 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2343 struct rtl_fw_phy_action *pa)
2348 for (index = 0; index < pa->size; index++) {
2349 u32 action = le32_to_cpu(pa->code[index]);
2350 u32 regno = (action & 0x0fff0000) >> 16;
2352 switch(action & 0xf0000000) {
2357 case PHY_CLEAR_READCOUNT:
2359 case PHY_WRITE_PREVIOUS:
2364 if (regno > index) {
2365 netif_err(tp, ifup, tp->dev,
2366 "Out of range of firmware\n");
2370 case PHY_READCOUNT_EQ_SKIP:
2371 if (index + 2 >= pa->size) {
2372 netif_err(tp, ifup, tp->dev,
2373 "Out of range of firmware\n");
2377 case PHY_COMP_EQ_SKIPN:
2378 case PHY_COMP_NEQ_SKIPN:
2380 if (index + 1 + regno >= pa->size) {
2381 netif_err(tp, ifup, tp->dev,
2382 "Out of range of firmware\n");
2388 netif_err(tp, ifup, tp->dev,
2389 "Invalid action 0x%08x\n", action);
2398 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2400 struct net_device *dev = tp->dev;
2403 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2404 netif_err(tp, ifup, dev, "invalid firmware\n");
2408 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2414 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2416 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2417 struct mdio_ops org, *ops = &tp->mdio_ops;
2421 predata = count = 0;
2422 org.write = ops->write;
2423 org.read = ops->read;
2425 for (index = 0; index < pa->size; ) {
2426 u32 action = le32_to_cpu(pa->code[index]);
2427 u32 data = action & 0x0000ffff;
2428 u32 regno = (action & 0x0fff0000) >> 16;
2433 switch(action & 0xf0000000) {
2435 predata = rtl_readphy(tp, regno);
2452 ops->write = org.write;
2453 ops->read = org.read;
2454 } else if (data == 1) {
2455 ops->write = mac_mcu_write;
2456 ops->read = mac_mcu_read;
2461 case PHY_CLEAR_READCOUNT:
2466 rtl_writephy(tp, regno, data);
2469 case PHY_READCOUNT_EQ_SKIP:
2470 index += (count == data) ? 2 : 1;
2472 case PHY_COMP_EQ_SKIPN:
2473 if (predata == data)
2477 case PHY_COMP_NEQ_SKIPN:
2478 if (predata != data)
2482 case PHY_WRITE_PREVIOUS:
2483 rtl_writephy(tp, regno, predata);
2499 ops->write = org.write;
2500 ops->read = org.read;
2503 static void rtl_release_firmware(struct rtl8169_private *tp)
2505 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2506 release_firmware(tp->rtl_fw->fw);
2509 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2512 static void rtl_apply_firmware(struct rtl8169_private *tp)
2514 struct rtl_fw *rtl_fw = tp->rtl_fw;
2516 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2517 if (!IS_ERR_OR_NULL(rtl_fw))
2518 rtl_phy_write_fw(tp, rtl_fw);
2521 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2523 if (rtl_readphy(tp, reg) != val)
2524 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2526 rtl_apply_firmware(tp);
2529 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2531 static const struct phy_reg phy_reg_init[] = {
2593 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2596 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2598 static const struct phy_reg phy_reg_init[] = {
2604 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2607 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2609 struct pci_dev *pdev = tp->pci_dev;
2611 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2612 (pdev->subsystem_device != 0xe000))
2615 rtl_writephy(tp, 0x1f, 0x0001);
2616 rtl_writephy(tp, 0x10, 0xf01b);
2617 rtl_writephy(tp, 0x1f, 0x0000);
2620 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2622 static const struct phy_reg phy_reg_init[] = {
2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2664 rtl8169scd_hw_phy_config_quirk(tp);
2667 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2669 static const struct phy_reg phy_reg_init[] = {
2717 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2720 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2722 static const struct phy_reg phy_reg_init[] = {
2727 rtl_writephy(tp, 0x1f, 0x0001);
2728 rtl_patchphy(tp, 0x16, 1 << 0);
2730 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2733 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2735 static const struct phy_reg phy_reg_init[] = {
2741 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2744 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2746 static const struct phy_reg phy_reg_init[] = {
2754 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2757 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2759 static const struct phy_reg phy_reg_init[] = {
2765 rtl_writephy(tp, 0x1f, 0x0000);
2766 rtl_patchphy(tp, 0x14, 1 << 5);
2767 rtl_patchphy(tp, 0x0d, 1 << 5);
2769 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2772 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2774 static const struct phy_reg phy_reg_init[] = {
2794 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2796 rtl_patchphy(tp, 0x14, 1 << 5);
2797 rtl_patchphy(tp, 0x0d, 1 << 5);
2798 rtl_writephy(tp, 0x1f, 0x0000);
2801 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2803 static const struct phy_reg phy_reg_init[] = {
2821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823 rtl_patchphy(tp, 0x16, 1 << 0);
2824 rtl_patchphy(tp, 0x14, 1 << 5);
2825 rtl_patchphy(tp, 0x0d, 1 << 5);
2826 rtl_writephy(tp, 0x1f, 0x0000);
2829 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2831 static const struct phy_reg phy_reg_init[] = {
2843 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2845 rtl_patchphy(tp, 0x16, 1 << 0);
2846 rtl_patchphy(tp, 0x14, 1 << 5);
2847 rtl_patchphy(tp, 0x0d, 1 << 5);
2848 rtl_writephy(tp, 0x1f, 0x0000);
2851 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2853 rtl8168c_3_hw_phy_config(tp);
2856 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2858 static const struct phy_reg phy_reg_init_0[] = {
2859 /* Channel Estimation */
2880 * Enhance line driver power
2889 * Can not link to 1Gbps with bad cable
2890 * Decrease SNR threshold form 21.07dB to 19.04dB
2899 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2903 * Fine Tune Switching regulator parameter
2905 rtl_writephy(tp, 0x1f, 0x0002);
2906 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2907 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2909 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2910 static const struct phy_reg phy_reg_init[] = {
2920 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2922 val = rtl_readphy(tp, 0x0d);
2924 if ((val & 0x00ff) != 0x006c) {
2925 static const u32 set[] = {
2926 0x0065, 0x0066, 0x0067, 0x0068,
2927 0x0069, 0x006a, 0x006b, 0x006c
2931 rtl_writephy(tp, 0x1f, 0x0002);
2934 for (i = 0; i < ARRAY_SIZE(set); i++)
2935 rtl_writephy(tp, 0x0d, val | set[i]);
2938 static const struct phy_reg phy_reg_init[] = {
2946 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2949 /* RSET couple improve */
2950 rtl_writephy(tp, 0x1f, 0x0002);
2951 rtl_patchphy(tp, 0x0d, 0x0300);
2952 rtl_patchphy(tp, 0x0f, 0x0010);
2954 /* Fine tune PLL performance */
2955 rtl_writephy(tp, 0x1f, 0x0002);
2956 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2957 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2959 rtl_writephy(tp, 0x1f, 0x0005);
2960 rtl_writephy(tp, 0x05, 0x001b);
2962 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2964 rtl_writephy(tp, 0x1f, 0x0000);
2967 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2969 static const struct phy_reg phy_reg_init_0[] = {
2970 /* Channel Estimation */
2991 * Enhance line driver power
3000 * Can not link to 1Gbps with bad cable
3001 * Decrease SNR threshold form 21.07dB to 19.04dB
3010 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3012 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3013 static const struct phy_reg phy_reg_init[] = {
3024 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3026 val = rtl_readphy(tp, 0x0d);
3027 if ((val & 0x00ff) != 0x006c) {
3028 static const u32 set[] = {
3029 0x0065, 0x0066, 0x0067, 0x0068,
3030 0x0069, 0x006a, 0x006b, 0x006c
3034 rtl_writephy(tp, 0x1f, 0x0002);
3037 for (i = 0; i < ARRAY_SIZE(set); i++)
3038 rtl_writephy(tp, 0x0d, val | set[i]);
3041 static const struct phy_reg phy_reg_init[] = {
3049 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3052 /* Fine tune PLL performance */
3053 rtl_writephy(tp, 0x1f, 0x0002);
3054 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3055 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3057 /* Switching regulator Slew rate */
3058 rtl_writephy(tp, 0x1f, 0x0002);
3059 rtl_patchphy(tp, 0x0f, 0x0017);
3061 rtl_writephy(tp, 0x1f, 0x0005);
3062 rtl_writephy(tp, 0x05, 0x001b);
3064 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3066 rtl_writephy(tp, 0x1f, 0x0000);
3069 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3071 static const struct phy_reg phy_reg_init[] = {
3127 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3130 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3132 static const struct phy_reg phy_reg_init[] = {
3142 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3143 rtl_patchphy(tp, 0x0d, 1 << 5);
3146 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3148 static const struct phy_reg phy_reg_init[] = {
3149 /* Enable Delay cap */
3155 /* Channel estimation fine tune */
3164 /* Update PFM & 10M TX idle timer */
3176 rtl_apply_firmware(tp);
3178 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3180 /* DCO enable for 10M IDLE Power */
3181 rtl_writephy(tp, 0x1f, 0x0007);
3182 rtl_writephy(tp, 0x1e, 0x0023);
3183 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3184 rtl_writephy(tp, 0x1f, 0x0000);
3186 /* For impedance matching */
3187 rtl_writephy(tp, 0x1f, 0x0002);
3188 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3189 rtl_writephy(tp, 0x1f, 0x0000);
3191 /* PHY auto speed down */
3192 rtl_writephy(tp, 0x1f, 0x0007);
3193 rtl_writephy(tp, 0x1e, 0x002d);
3194 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3195 rtl_writephy(tp, 0x1f, 0x0000);
3196 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3198 rtl_writephy(tp, 0x1f, 0x0005);
3199 rtl_writephy(tp, 0x05, 0x8b86);
3200 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3201 rtl_writephy(tp, 0x1f, 0x0000);
3203 rtl_writephy(tp, 0x1f, 0x0005);
3204 rtl_writephy(tp, 0x05, 0x8b85);
3205 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3206 rtl_writephy(tp, 0x1f, 0x0007);
3207 rtl_writephy(tp, 0x1e, 0x0020);
3208 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3209 rtl_writephy(tp, 0x1f, 0x0006);
3210 rtl_writephy(tp, 0x00, 0x5a00);
3211 rtl_writephy(tp, 0x1f, 0x0000);
3212 rtl_writephy(tp, 0x0d, 0x0007);
3213 rtl_writephy(tp, 0x0e, 0x003c);
3214 rtl_writephy(tp, 0x0d, 0x4007);
3215 rtl_writephy(tp, 0x0e, 0x0000);
3216 rtl_writephy(tp, 0x0d, 0x0000);
3219 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3222 addr[0] | (addr[1] << 8),
3223 addr[2] | (addr[3] << 8),
3224 addr[4] | (addr[5] << 8)
3226 const struct exgmac_reg e[] = {
3227 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3228 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3229 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3230 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3233 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3236 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3238 static const struct phy_reg phy_reg_init[] = {
3239 /* Enable Delay cap */
3248 /* Channel estimation fine tune */
3265 rtl_apply_firmware(tp);
3267 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3269 /* For 4-corner performance improve */
3270 rtl_writephy(tp, 0x1f, 0x0005);
3271 rtl_writephy(tp, 0x05, 0x8b80);
3272 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3273 rtl_writephy(tp, 0x1f, 0x0000);
3275 /* PHY auto speed down */
3276 rtl_writephy(tp, 0x1f, 0x0004);
3277 rtl_writephy(tp, 0x1f, 0x0007);
3278 rtl_writephy(tp, 0x1e, 0x002d);
3279 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3280 rtl_writephy(tp, 0x1f, 0x0002);
3281 rtl_writephy(tp, 0x1f, 0x0000);
3282 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3284 /* improve 10M EEE waveform */
3285 rtl_writephy(tp, 0x1f, 0x0005);
3286 rtl_writephy(tp, 0x05, 0x8b86);
3287 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3288 rtl_writephy(tp, 0x1f, 0x0000);
3290 /* Improve 2-pair detection performance */
3291 rtl_writephy(tp, 0x1f, 0x0005);
3292 rtl_writephy(tp, 0x05, 0x8b85);
3293 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3294 rtl_writephy(tp, 0x1f, 0x0000);
3297 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3298 rtl_writephy(tp, 0x1f, 0x0005);
3299 rtl_writephy(tp, 0x05, 0x8b85);
3300 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3301 rtl_writephy(tp, 0x1f, 0x0004);
3302 rtl_writephy(tp, 0x1f, 0x0007);
3303 rtl_writephy(tp, 0x1e, 0x0020);
3304 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3305 rtl_writephy(tp, 0x1f, 0x0002);
3306 rtl_writephy(tp, 0x1f, 0x0000);
3307 rtl_writephy(tp, 0x0d, 0x0007);
3308 rtl_writephy(tp, 0x0e, 0x003c);
3309 rtl_writephy(tp, 0x0d, 0x4007);
3310 rtl_writephy(tp, 0x0e, 0x0006);
3311 rtl_writephy(tp, 0x0d, 0x0000);
3314 rtl_writephy(tp, 0x1f, 0x0003);
3315 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3316 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3317 rtl_writephy(tp, 0x1f, 0x0000);
3318 rtl_writephy(tp, 0x1f, 0x0005);
3319 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3320 rtl_writephy(tp, 0x1f, 0x0000);
3322 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3323 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3326 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3328 /* For 4-corner performance improve */
3329 rtl_writephy(tp, 0x1f, 0x0005);
3330 rtl_writephy(tp, 0x05, 0x8b80);
3331 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3332 rtl_writephy(tp, 0x1f, 0x0000);
3334 /* PHY auto speed down */
3335 rtl_writephy(tp, 0x1f, 0x0007);
3336 rtl_writephy(tp, 0x1e, 0x002d);
3337 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3338 rtl_writephy(tp, 0x1f, 0x0000);
3339 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3341 /* Improve 10M EEE waveform */
3342 rtl_writephy(tp, 0x1f, 0x0005);
3343 rtl_writephy(tp, 0x05, 0x8b86);
3344 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3345 rtl_writephy(tp, 0x1f, 0x0000);
3348 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3350 static const struct phy_reg phy_reg_init[] = {
3351 /* Channel estimation fine tune */
3356 /* Modify green table for giga & fnet */
3373 /* Modify green table for 10M */
3379 /* Disable hiimpedance detection (RTCT) */
3385 rtl_apply_firmware(tp);
3387 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3389 rtl8168f_hw_phy_config(tp);
3391 /* Improve 2-pair detection performance */
3392 rtl_writephy(tp, 0x1f, 0x0005);
3393 rtl_writephy(tp, 0x05, 0x8b85);
3394 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3395 rtl_writephy(tp, 0x1f, 0x0000);
3398 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3400 rtl_apply_firmware(tp);
3402 rtl8168f_hw_phy_config(tp);
3405 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3407 static const struct phy_reg phy_reg_init[] = {
3408 /* Channel estimation fine tune */
3413 /* Modify green table for giga & fnet */
3430 /* Modify green table for 10M */
3436 /* Disable hiimpedance detection (RTCT) */
3443 rtl_apply_firmware(tp);
3445 rtl8168f_hw_phy_config(tp);
3447 /* Improve 2-pair detection performance */
3448 rtl_writephy(tp, 0x1f, 0x0005);
3449 rtl_writephy(tp, 0x05, 0x8b85);
3450 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3451 rtl_writephy(tp, 0x1f, 0x0000);
3453 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3455 /* Modify green table for giga */
3456 rtl_writephy(tp, 0x1f, 0x0005);
3457 rtl_writephy(tp, 0x05, 0x8b54);
3458 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3459 rtl_writephy(tp, 0x05, 0x8b5d);
3460 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3461 rtl_writephy(tp, 0x05, 0x8a7c);
3462 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3463 rtl_writephy(tp, 0x05, 0x8a7f);
3464 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3465 rtl_writephy(tp, 0x05, 0x8a82);
3466 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3467 rtl_writephy(tp, 0x05, 0x8a85);
3468 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3469 rtl_writephy(tp, 0x05, 0x8a88);
3470 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3471 rtl_writephy(tp, 0x1f, 0x0000);
3473 /* uc same-seed solution */
3474 rtl_writephy(tp, 0x1f, 0x0005);
3475 rtl_writephy(tp, 0x05, 0x8b85);
3476 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3477 rtl_writephy(tp, 0x1f, 0x0000);
3480 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3481 rtl_writephy(tp, 0x1f, 0x0005);
3482 rtl_writephy(tp, 0x05, 0x8b85);
3483 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3484 rtl_writephy(tp, 0x1f, 0x0004);
3485 rtl_writephy(tp, 0x1f, 0x0007);
3486 rtl_writephy(tp, 0x1e, 0x0020);
3487 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3488 rtl_writephy(tp, 0x1f, 0x0000);
3489 rtl_writephy(tp, 0x0d, 0x0007);
3490 rtl_writephy(tp, 0x0e, 0x003c);
3491 rtl_writephy(tp, 0x0d, 0x4007);
3492 rtl_writephy(tp, 0x0e, 0x0000);
3493 rtl_writephy(tp, 0x0d, 0x0000);
3496 rtl_writephy(tp, 0x1f, 0x0003);
3497 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3498 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3499 rtl_writephy(tp, 0x1f, 0x0000);
3502 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3504 rtl_apply_firmware(tp);
3506 rtl_writephy(tp, 0x1f, 0x0a46);
3507 if (rtl_readphy(tp, 0x10) & 0x0100) {
3508 rtl_writephy(tp, 0x1f, 0x0bcc);
3509 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3511 rtl_writephy(tp, 0x1f, 0x0bcc);
3512 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3515 rtl_writephy(tp, 0x1f, 0x0a46);
3516 if (rtl_readphy(tp, 0x13) & 0x0100) {
3517 rtl_writephy(tp, 0x1f, 0x0c41);
3518 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3520 rtl_writephy(tp, 0x1f, 0x0c41);
3521 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3524 /* Enable PHY auto speed down */
3525 rtl_writephy(tp, 0x1f, 0x0a44);
3526 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3528 rtl_writephy(tp, 0x1f, 0x0bcc);
3529 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3530 rtl_writephy(tp, 0x1f, 0x0a44);
3531 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3532 rtl_writephy(tp, 0x1f, 0x0a43);
3533 rtl_writephy(tp, 0x13, 0x8084);
3534 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3535 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3537 /* EEE auto-fallback function */
3538 rtl_writephy(tp, 0x1f, 0x0a4b);
3539 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3541 /* Enable UC LPF tune function */
3542 rtl_writephy(tp, 0x1f, 0x0a43);
3543 rtl_writephy(tp, 0x13, 0x8012);
3544 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3546 rtl_writephy(tp, 0x1f, 0x0c42);
3547 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3549 /* Improve SWR Efficiency */
3550 rtl_writephy(tp, 0x1f, 0x0bcd);
3551 rtl_writephy(tp, 0x14, 0x5065);
3552 rtl_writephy(tp, 0x14, 0xd065);
3553 rtl_writephy(tp, 0x1f, 0x0bc8);
3554 rtl_writephy(tp, 0x11, 0x5655);
3555 rtl_writephy(tp, 0x1f, 0x0bcd);
3556 rtl_writephy(tp, 0x14, 0x1065);
3557 rtl_writephy(tp, 0x14, 0x9065);
3558 rtl_writephy(tp, 0x14, 0x1065);
3560 /* Check ALDPS bit, disable it if enabled */
3561 rtl_writephy(tp, 0x1f, 0x0a43);
3562 if (rtl_readphy(tp, 0x10) & 0x0004)
3563 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3565 rtl_writephy(tp, 0x1f, 0x0000);
3568 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3570 rtl_apply_firmware(tp);
3573 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3578 rtl_apply_firmware(tp);
3580 /* CHN EST parameters adjust - giga master */
3581 rtl_writephy(tp, 0x1f, 0x0a43);
3582 rtl_writephy(tp, 0x13, 0x809b);
3583 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3584 rtl_writephy(tp, 0x13, 0x80a2);
3585 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3586 rtl_writephy(tp, 0x13, 0x80a4);
3587 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3588 rtl_writephy(tp, 0x13, 0x809c);
3589 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3590 rtl_writephy(tp, 0x1f, 0x0000);
3592 /* CHN EST parameters adjust - giga slave */
3593 rtl_writephy(tp, 0x1f, 0x0a43);
3594 rtl_writephy(tp, 0x13, 0x80ad);
3595 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3596 rtl_writephy(tp, 0x13, 0x80b4);
3597 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3598 rtl_writephy(tp, 0x13, 0x80ac);
3599 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3602 /* CHN EST parameters adjust - fnet */
3603 rtl_writephy(tp, 0x1f, 0x0a43);
3604 rtl_writephy(tp, 0x13, 0x808e);
3605 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3606 rtl_writephy(tp, 0x13, 0x8090);
3607 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3608 rtl_writephy(tp, 0x13, 0x8092);
3609 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3610 rtl_writephy(tp, 0x1f, 0x0000);
3612 /* enable R-tune & PGA-retune function */
3614 rtl_writephy(tp, 0x1f, 0x0a46);
3615 data = rtl_readphy(tp, 0x13);
3618 dout_tapbin |= data;
3619 data = rtl_readphy(tp, 0x12);
3622 dout_tapbin |= data;
3623 dout_tapbin = ~(dout_tapbin^0x08);
3625 dout_tapbin &= 0xf000;
3626 rtl_writephy(tp, 0x1f, 0x0a43);
3627 rtl_writephy(tp, 0x13, 0x827a);
3628 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3629 rtl_writephy(tp, 0x13, 0x827b);
3630 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3631 rtl_writephy(tp, 0x13, 0x827c);
3632 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3633 rtl_writephy(tp, 0x13, 0x827d);
3634 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3636 rtl_writephy(tp, 0x1f, 0x0a43);
3637 rtl_writephy(tp, 0x13, 0x0811);
3638 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3639 rtl_writephy(tp, 0x1f, 0x0a42);
3640 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3641 rtl_writephy(tp, 0x1f, 0x0000);
3643 /* enable GPHY 10M */
3644 rtl_writephy(tp, 0x1f, 0x0a44);
3645 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3646 rtl_writephy(tp, 0x1f, 0x0000);
3648 /* SAR ADC performance */
3649 rtl_writephy(tp, 0x1f, 0x0bca);
3650 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3651 rtl_writephy(tp, 0x1f, 0x0000);
3653 rtl_writephy(tp, 0x1f, 0x0a43);
3654 rtl_writephy(tp, 0x13, 0x803f);
3655 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3656 rtl_writephy(tp, 0x13, 0x8047);
3657 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3658 rtl_writephy(tp, 0x13, 0x804f);
3659 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3660 rtl_writephy(tp, 0x13, 0x8057);
3661 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3662 rtl_writephy(tp, 0x13, 0x805f);
3663 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3664 rtl_writephy(tp, 0x13, 0x8067);
3665 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3666 rtl_writephy(tp, 0x13, 0x806f);
3667 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3668 rtl_writephy(tp, 0x1f, 0x0000);
3670 /* disable phy pfm mode */
3671 rtl_writephy(tp, 0x1f, 0x0a44);
3672 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3673 rtl_writephy(tp, 0x1f, 0x0000);
3675 /* Check ALDPS bit, disable it if enabled */
3676 rtl_writephy(tp, 0x1f, 0x0a43);
3677 if (rtl_readphy(tp, 0x10) & 0x0004)
3678 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3680 rtl_writephy(tp, 0x1f, 0x0000);
3683 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3685 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3689 rtl_apply_firmware(tp);
3691 /* CHIN EST parameter update */
3692 rtl_writephy(tp, 0x1f, 0x0a43);
3693 rtl_writephy(tp, 0x13, 0x808a);
3694 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3695 rtl_writephy(tp, 0x1f, 0x0000);
3697 /* enable R-tune & PGA-retune function */
3698 rtl_writephy(tp, 0x1f, 0x0a43);
3699 rtl_writephy(tp, 0x13, 0x0811);
3700 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3701 rtl_writephy(tp, 0x1f, 0x0a42);
3702 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3703 rtl_writephy(tp, 0x1f, 0x0000);
3705 /* enable GPHY 10M */
3706 rtl_writephy(tp, 0x1f, 0x0a44);
3707 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3708 rtl_writephy(tp, 0x1f, 0x0000);
3710 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3711 data = r8168_mac_ocp_read(tp, 0xdd02);
3712 ioffset_p3 = ((data & 0x80)>>7);
3715 data = r8168_mac_ocp_read(tp, 0xdd00);
3716 ioffset_p3 |= ((data & (0xe000))>>13);
3717 ioffset_p2 = ((data & (0x1e00))>>9);
3718 ioffset_p1 = ((data & (0x01e0))>>5);
3719 ioffset_p0 = ((data & 0x0010)>>4);
3721 ioffset_p0 |= (data & (0x07));
3722 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3724 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3725 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3726 rtl_writephy(tp, 0x1f, 0x0bcf);
3727 rtl_writephy(tp, 0x16, data);
3728 rtl_writephy(tp, 0x1f, 0x0000);
3731 /* Modify rlen (TX LPF corner frequency) level */
3732 rtl_writephy(tp, 0x1f, 0x0bcd);
3733 data = rtl_readphy(tp, 0x16);
3738 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3739 rtl_writephy(tp, 0x17, data);
3740 rtl_writephy(tp, 0x1f, 0x0bcd);
3741 rtl_writephy(tp, 0x1f, 0x0000);
3743 /* disable phy pfm mode */
3744 rtl_writephy(tp, 0x1f, 0x0a44);
3745 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3746 rtl_writephy(tp, 0x1f, 0x0000);
3748 /* Check ALDPS bit, disable it if enabled */
3749 rtl_writephy(tp, 0x1f, 0x0a43);
3750 if (rtl_readphy(tp, 0x10) & 0x0004)
3751 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3753 rtl_writephy(tp, 0x1f, 0x0000);
3756 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3758 /* Enable PHY auto speed down */
3759 rtl_writephy(tp, 0x1f, 0x0a44);
3760 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3761 rtl_writephy(tp, 0x1f, 0x0000);
3763 /* patch 10M & ALDPS */
3764 rtl_writephy(tp, 0x1f, 0x0bcc);
3765 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3766 rtl_writephy(tp, 0x1f, 0x0a44);
3767 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3768 rtl_writephy(tp, 0x1f, 0x0a43);
3769 rtl_writephy(tp, 0x13, 0x8084);
3770 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3771 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3772 rtl_writephy(tp, 0x1f, 0x0000);
3774 /* Enable EEE auto-fallback function */
3775 rtl_writephy(tp, 0x1f, 0x0a4b);
3776 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3777 rtl_writephy(tp, 0x1f, 0x0000);
3779 /* Enable UC LPF tune function */
3780 rtl_writephy(tp, 0x1f, 0x0a43);
3781 rtl_writephy(tp, 0x13, 0x8012);
3782 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3783 rtl_writephy(tp, 0x1f, 0x0000);
3785 /* set rg_sel_sdm_rate */
3786 rtl_writephy(tp, 0x1f, 0x0c42);
3787 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3788 rtl_writephy(tp, 0x1f, 0x0000);
3790 /* Check ALDPS bit, disable it if enabled */
3791 rtl_writephy(tp, 0x1f, 0x0a43);
3792 if (rtl_readphy(tp, 0x10) & 0x0004)
3793 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3795 rtl_writephy(tp, 0x1f, 0x0000);
3798 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3800 /* patch 10M & ALDPS */
3801 rtl_writephy(tp, 0x1f, 0x0bcc);
3802 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3803 rtl_writephy(tp, 0x1f, 0x0a44);
3804 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3805 rtl_writephy(tp, 0x1f, 0x0a43);
3806 rtl_writephy(tp, 0x13, 0x8084);
3807 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3808 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3809 rtl_writephy(tp, 0x1f, 0x0000);
3811 /* Enable UC LPF tune function */
3812 rtl_writephy(tp, 0x1f, 0x0a43);
3813 rtl_writephy(tp, 0x13, 0x8012);
3814 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3815 rtl_writephy(tp, 0x1f, 0x0000);
3817 /* Set rg_sel_sdm_rate */
3818 rtl_writephy(tp, 0x1f, 0x0c42);
3819 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3820 rtl_writephy(tp, 0x1f, 0x0000);
3822 /* Channel estimation parameters */
3823 rtl_writephy(tp, 0x1f, 0x0a43);
3824 rtl_writephy(tp, 0x13, 0x80f3);
3825 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3826 rtl_writephy(tp, 0x13, 0x80f0);
3827 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3828 rtl_writephy(tp, 0x13, 0x80ef);
3829 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3830 rtl_writephy(tp, 0x13, 0x80f6);
3831 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3832 rtl_writephy(tp, 0x13, 0x80ec);
3833 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3834 rtl_writephy(tp, 0x13, 0x80ed);
3835 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3836 rtl_writephy(tp, 0x13, 0x80f2);
3837 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3838 rtl_writephy(tp, 0x13, 0x80f4);
3839 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3840 rtl_writephy(tp, 0x1f, 0x0a43);
3841 rtl_writephy(tp, 0x13, 0x8110);
3842 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3843 rtl_writephy(tp, 0x13, 0x810f);
3844 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3845 rtl_writephy(tp, 0x13, 0x8111);
3846 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3847 rtl_writephy(tp, 0x13, 0x8113);
3848 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3849 rtl_writephy(tp, 0x13, 0x8115);
3850 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3851 rtl_writephy(tp, 0x13, 0x810e);
3852 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3853 rtl_writephy(tp, 0x13, 0x810c);
3854 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3855 rtl_writephy(tp, 0x13, 0x810b);
3856 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3857 rtl_writephy(tp, 0x1f, 0x0a43);
3858 rtl_writephy(tp, 0x13, 0x80d1);
3859 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3860 rtl_writephy(tp, 0x13, 0x80cd);
3861 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3862 rtl_writephy(tp, 0x13, 0x80d3);
3863 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3864 rtl_writephy(tp, 0x13, 0x80d5);
3865 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3866 rtl_writephy(tp, 0x13, 0x80d7);
3867 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3869 /* Force PWM-mode */
3870 rtl_writephy(tp, 0x1f, 0x0bcd);
3871 rtl_writephy(tp, 0x14, 0x5065);
3872 rtl_writephy(tp, 0x14, 0xd065);
3873 rtl_writephy(tp, 0x1f, 0x0bc8);
3874 rtl_writephy(tp, 0x12, 0x00ed);
3875 rtl_writephy(tp, 0x1f, 0x0bcd);
3876 rtl_writephy(tp, 0x14, 0x1065);
3877 rtl_writephy(tp, 0x14, 0x9065);
3878 rtl_writephy(tp, 0x14, 0x1065);
3879 rtl_writephy(tp, 0x1f, 0x0000);
3881 /* Check ALDPS bit, disable it if enabled */
3882 rtl_writephy(tp, 0x1f, 0x0a43);
3883 if (rtl_readphy(tp, 0x10) & 0x0004)
3884 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3886 rtl_writephy(tp, 0x1f, 0x0000);
3889 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3891 static const struct phy_reg phy_reg_init[] = {
3898 rtl_writephy(tp, 0x1f, 0x0000);
3899 rtl_patchphy(tp, 0x11, 1 << 12);
3900 rtl_patchphy(tp, 0x19, 1 << 13);
3901 rtl_patchphy(tp, 0x10, 1 << 15);
3903 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3906 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3908 static const struct phy_reg phy_reg_init[] = {
3922 /* Disable ALDPS before ram code */
3923 rtl_writephy(tp, 0x1f, 0x0000);
3924 rtl_writephy(tp, 0x18, 0x0310);
3927 rtl_apply_firmware(tp);
3929 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3932 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3934 /* Disable ALDPS before setting firmware */
3935 rtl_writephy(tp, 0x1f, 0x0000);
3936 rtl_writephy(tp, 0x18, 0x0310);
3939 rtl_apply_firmware(tp);
3942 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3943 rtl_writephy(tp, 0x1f, 0x0004);
3944 rtl_writephy(tp, 0x10, 0x401f);
3945 rtl_writephy(tp, 0x19, 0x7030);
3946 rtl_writephy(tp, 0x1f, 0x0000);
3949 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3951 static const struct phy_reg phy_reg_init[] = {
3958 /* Disable ALDPS before ram code */
3959 rtl_writephy(tp, 0x1f, 0x0000);
3960 rtl_writephy(tp, 0x18, 0x0310);
3963 rtl_apply_firmware(tp);
3965 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3968 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3971 static void rtl_hw_phy_config(struct net_device *dev)
3973 struct rtl8169_private *tp = netdev_priv(dev);
3975 rtl8169_print_mac_version(tp);
3977 switch (tp->mac_version) {
3978 case RTL_GIGA_MAC_VER_01:
3980 case RTL_GIGA_MAC_VER_02:
3981 case RTL_GIGA_MAC_VER_03:
3982 rtl8169s_hw_phy_config(tp);
3984 case RTL_GIGA_MAC_VER_04:
3985 rtl8169sb_hw_phy_config(tp);
3987 case RTL_GIGA_MAC_VER_05:
3988 rtl8169scd_hw_phy_config(tp);
3990 case RTL_GIGA_MAC_VER_06:
3991 rtl8169sce_hw_phy_config(tp);
3993 case RTL_GIGA_MAC_VER_07:
3994 case RTL_GIGA_MAC_VER_08:
3995 case RTL_GIGA_MAC_VER_09:
3996 rtl8102e_hw_phy_config(tp);
3998 case RTL_GIGA_MAC_VER_11:
3999 rtl8168bb_hw_phy_config(tp);
4001 case RTL_GIGA_MAC_VER_12:
4002 rtl8168bef_hw_phy_config(tp);
4004 case RTL_GIGA_MAC_VER_17:
4005 rtl8168bef_hw_phy_config(tp);
4007 case RTL_GIGA_MAC_VER_18:
4008 rtl8168cp_1_hw_phy_config(tp);
4010 case RTL_GIGA_MAC_VER_19:
4011 rtl8168c_1_hw_phy_config(tp);
4013 case RTL_GIGA_MAC_VER_20:
4014 rtl8168c_2_hw_phy_config(tp);
4016 case RTL_GIGA_MAC_VER_21:
4017 rtl8168c_3_hw_phy_config(tp);
4019 case RTL_GIGA_MAC_VER_22:
4020 rtl8168c_4_hw_phy_config(tp);
4022 case RTL_GIGA_MAC_VER_23:
4023 case RTL_GIGA_MAC_VER_24:
4024 rtl8168cp_2_hw_phy_config(tp);
4026 case RTL_GIGA_MAC_VER_25:
4027 rtl8168d_1_hw_phy_config(tp);
4029 case RTL_GIGA_MAC_VER_26:
4030 rtl8168d_2_hw_phy_config(tp);
4032 case RTL_GIGA_MAC_VER_27:
4033 rtl8168d_3_hw_phy_config(tp);
4035 case RTL_GIGA_MAC_VER_28:
4036 rtl8168d_4_hw_phy_config(tp);
4038 case RTL_GIGA_MAC_VER_29:
4039 case RTL_GIGA_MAC_VER_30:
4040 rtl8105e_hw_phy_config(tp);
4042 case RTL_GIGA_MAC_VER_31:
4045 case RTL_GIGA_MAC_VER_32:
4046 case RTL_GIGA_MAC_VER_33:
4047 rtl8168e_1_hw_phy_config(tp);
4049 case RTL_GIGA_MAC_VER_34:
4050 rtl8168e_2_hw_phy_config(tp);
4052 case RTL_GIGA_MAC_VER_35:
4053 rtl8168f_1_hw_phy_config(tp);
4055 case RTL_GIGA_MAC_VER_36:
4056 rtl8168f_2_hw_phy_config(tp);
4059 case RTL_GIGA_MAC_VER_37:
4060 rtl8402_hw_phy_config(tp);
4063 case RTL_GIGA_MAC_VER_38:
4064 rtl8411_hw_phy_config(tp);
4067 case RTL_GIGA_MAC_VER_39:
4068 rtl8106e_hw_phy_config(tp);
4071 case RTL_GIGA_MAC_VER_40:
4072 rtl8168g_1_hw_phy_config(tp);
4074 case RTL_GIGA_MAC_VER_42:
4075 case RTL_GIGA_MAC_VER_43:
4076 case RTL_GIGA_MAC_VER_44:
4077 rtl8168g_2_hw_phy_config(tp);
4079 case RTL_GIGA_MAC_VER_45:
4080 case RTL_GIGA_MAC_VER_47:
4081 rtl8168h_1_hw_phy_config(tp);
4083 case RTL_GIGA_MAC_VER_46:
4084 case RTL_GIGA_MAC_VER_48:
4085 rtl8168h_2_hw_phy_config(tp);
4088 case RTL_GIGA_MAC_VER_49:
4089 rtl8168ep_1_hw_phy_config(tp);
4091 case RTL_GIGA_MAC_VER_50:
4092 case RTL_GIGA_MAC_VER_51:
4093 rtl8168ep_2_hw_phy_config(tp);
4096 case RTL_GIGA_MAC_VER_41:
4102 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4104 if (!test_and_set_bit(flag, tp->wk.flags))
4105 schedule_work(&tp->wk.work);
4108 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4110 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4111 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4114 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4116 rtl_hw_phy_config(dev);
4118 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4119 netif_dbg(tp, drv, dev,
4120 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4121 RTL_W8(tp, 0x82, 0x01);
4124 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4126 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4127 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4129 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4130 netif_dbg(tp, drv, dev,
4131 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4132 RTL_W8(tp, 0x82, 0x01);
4133 netif_dbg(tp, drv, dev,
4134 "Set PHY Reg 0x0bh = 0x00h\n");
4135 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4138 /* We may have called phy_speed_down before */
4139 phy_speed_up(dev->phydev);
4141 genphy_soft_reset(dev->phydev);
4144 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4148 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4150 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4153 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4156 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4157 rtl_rar_exgmac_set(tp, addr);
4159 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4161 rtl_unlock_work(tp);
4164 static int rtl_set_mac_address(struct net_device *dev, void *p)
4166 struct rtl8169_private *tp = netdev_priv(dev);
4167 struct device *d = tp_to_dev(tp);
4170 ret = eth_mac_addr(dev, p);
4174 pm_runtime_get_noresume(d);
4176 if (pm_runtime_active(d))
4177 rtl_rar_set(tp, dev->dev_addr);
4179 pm_runtime_put_noidle(d);
4184 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4186 if (!netif_running(dev))
4189 return phy_mii_ioctl(dev->phydev, ifr, cmd);
4192 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4194 struct mdio_ops *ops = &tp->mdio_ops;
4196 switch (tp->mac_version) {
4197 case RTL_GIGA_MAC_VER_27:
4198 ops->write = r8168dp_1_mdio_write;
4199 ops->read = r8168dp_1_mdio_read;
4201 case RTL_GIGA_MAC_VER_28:
4202 case RTL_GIGA_MAC_VER_31:
4203 ops->write = r8168dp_2_mdio_write;
4204 ops->read = r8168dp_2_mdio_read;
4206 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4207 ops->write = r8168g_mdio_write;
4208 ops->read = r8168g_mdio_read;
4211 ops->write = r8169_mdio_write;
4212 ops->read = r8169_mdio_read;
4217 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4219 switch (tp->mac_version) {
4220 case RTL_GIGA_MAC_VER_25:
4221 case RTL_GIGA_MAC_VER_26:
4222 case RTL_GIGA_MAC_VER_29:
4223 case RTL_GIGA_MAC_VER_30:
4224 case RTL_GIGA_MAC_VER_32:
4225 case RTL_GIGA_MAC_VER_33:
4226 case RTL_GIGA_MAC_VER_34:
4227 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4228 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4229 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4236 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4238 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4241 phy_speed_down(tp->dev->phydev, false);
4242 rtl_wol_suspend_quirk(tp);
4247 static void r8168_pll_power_down(struct rtl8169_private *tp)
4249 if (r8168_check_dash(tp))
4252 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4253 tp->mac_version == RTL_GIGA_MAC_VER_33)
4254 rtl_ephy_write(tp, 0x19, 0xff64);
4256 if (rtl_wol_pll_power_down(tp))
4259 switch (tp->mac_version) {
4260 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4261 case RTL_GIGA_MAC_VER_37:
4262 case RTL_GIGA_MAC_VER_39:
4263 case RTL_GIGA_MAC_VER_43:
4264 case RTL_GIGA_MAC_VER_44:
4265 case RTL_GIGA_MAC_VER_45:
4266 case RTL_GIGA_MAC_VER_46:
4267 case RTL_GIGA_MAC_VER_47:
4268 case RTL_GIGA_MAC_VER_48:
4269 case RTL_GIGA_MAC_VER_50:
4270 case RTL_GIGA_MAC_VER_51:
4271 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4273 case RTL_GIGA_MAC_VER_40:
4274 case RTL_GIGA_MAC_VER_41:
4275 case RTL_GIGA_MAC_VER_49:
4276 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4277 0xfc000000, ERIAR_EXGMAC);
4278 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4283 static void r8168_pll_power_up(struct rtl8169_private *tp)
4285 switch (tp->mac_version) {
4286 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4287 case RTL_GIGA_MAC_VER_37:
4288 case RTL_GIGA_MAC_VER_39:
4289 case RTL_GIGA_MAC_VER_43:
4290 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4292 case RTL_GIGA_MAC_VER_44:
4293 case RTL_GIGA_MAC_VER_45:
4294 case RTL_GIGA_MAC_VER_46:
4295 case RTL_GIGA_MAC_VER_47:
4296 case RTL_GIGA_MAC_VER_48:
4297 case RTL_GIGA_MAC_VER_50:
4298 case RTL_GIGA_MAC_VER_51:
4299 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4301 case RTL_GIGA_MAC_VER_40:
4302 case RTL_GIGA_MAC_VER_41:
4303 case RTL_GIGA_MAC_VER_49:
4304 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4305 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4306 0x00000000, ERIAR_EXGMAC);
4310 phy_resume(tp->dev->phydev);
4311 /* give MAC/PHY some time to resume */
4315 static void rtl_pll_power_down(struct rtl8169_private *tp)
4317 switch (tp->mac_version) {
4318 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4319 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4322 r8168_pll_power_down(tp);
4326 static void rtl_pll_power_up(struct rtl8169_private *tp)
4328 switch (tp->mac_version) {
4329 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4330 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4333 r8168_pll_power_up(tp);
4337 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4339 switch (tp->mac_version) {
4340 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4341 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4342 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4344 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4345 case RTL_GIGA_MAC_VER_34:
4346 case RTL_GIGA_MAC_VER_35:
4347 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4349 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4350 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4353 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4358 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4360 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4363 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4365 if (tp->jumbo_ops.enable) {
4366 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4367 tp->jumbo_ops.enable(tp);
4368 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4372 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4374 if (tp->jumbo_ops.disable) {
4375 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4376 tp->jumbo_ops.disable(tp);
4377 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4381 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4383 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4384 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4385 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4388 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4390 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4391 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4392 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4395 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4397 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4400 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4402 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4405 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4407 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4408 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4409 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4410 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4413 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4415 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4416 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4417 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4418 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4421 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4423 rtl_tx_performance_tweak(tp,
4424 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4427 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4429 rtl_tx_performance_tweak(tp,
4430 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4433 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4435 r8168b_0_hw_jumbo_enable(tp);
4437 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4440 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4442 r8168b_0_hw_jumbo_disable(tp);
4444 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4447 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4449 struct jumbo_ops *ops = &tp->jumbo_ops;
4451 switch (tp->mac_version) {
4452 case RTL_GIGA_MAC_VER_11:
4453 ops->disable = r8168b_0_hw_jumbo_disable;
4454 ops->enable = r8168b_0_hw_jumbo_enable;
4456 case RTL_GIGA_MAC_VER_12:
4457 case RTL_GIGA_MAC_VER_17:
4458 ops->disable = r8168b_1_hw_jumbo_disable;
4459 ops->enable = r8168b_1_hw_jumbo_enable;
4461 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4462 case RTL_GIGA_MAC_VER_19:
4463 case RTL_GIGA_MAC_VER_20:
4464 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4465 case RTL_GIGA_MAC_VER_22:
4466 case RTL_GIGA_MAC_VER_23:
4467 case RTL_GIGA_MAC_VER_24:
4468 case RTL_GIGA_MAC_VER_25:
4469 case RTL_GIGA_MAC_VER_26:
4470 ops->disable = r8168c_hw_jumbo_disable;
4471 ops->enable = r8168c_hw_jumbo_enable;
4473 case RTL_GIGA_MAC_VER_27:
4474 case RTL_GIGA_MAC_VER_28:
4475 ops->disable = r8168dp_hw_jumbo_disable;
4476 ops->enable = r8168dp_hw_jumbo_enable;
4478 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4479 case RTL_GIGA_MAC_VER_32:
4480 case RTL_GIGA_MAC_VER_33:
4481 case RTL_GIGA_MAC_VER_34:
4482 ops->disable = r8168e_hw_jumbo_disable;
4483 ops->enable = r8168e_hw_jumbo_enable;
4487 * No action needed for jumbo frames with 8169.
4488 * No jumbo for 810x at all.
4490 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4492 ops->disable = NULL;
4498 DECLARE_RTL_COND(rtl_chipcmd_cond)
4500 return RTL_R8(tp, ChipCmd) & CmdReset;
4503 static void rtl_hw_reset(struct rtl8169_private *tp)
4505 RTL_W8(tp, ChipCmd, CmdReset);
4507 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4510 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4512 struct rtl_fw *rtl_fw;
4516 name = rtl_lookup_firmware_name(tp);
4518 goto out_no_firmware;
4520 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4524 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4528 rc = rtl_check_firmware(tp, rtl_fw);
4530 goto err_release_firmware;
4532 tp->rtl_fw = rtl_fw;
4536 err_release_firmware:
4537 release_firmware(rtl_fw->fw);
4541 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4548 static void rtl_request_firmware(struct rtl8169_private *tp)
4550 if (IS_ERR(tp->rtl_fw))
4551 rtl_request_uncached_firmware(tp);
4554 static void rtl_rx_close(struct rtl8169_private *tp)
4556 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4559 DECLARE_RTL_COND(rtl_npq_cond)
4561 return RTL_R8(tp, TxPoll) & NPQ;
4564 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4566 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4569 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4571 /* Disable interrupts */
4572 rtl8169_irq_mask_and_ack(tp);
4576 switch (tp->mac_version) {
4577 case RTL_GIGA_MAC_VER_27:
4578 case RTL_GIGA_MAC_VER_28:
4579 case RTL_GIGA_MAC_VER_31:
4580 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4582 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4583 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4584 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4585 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4588 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4596 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4598 /* Set DMA burst size and Interframe Gap Time */
4599 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4600 (InterFrameGap << TxInterFrameGapShift));
4603 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4605 /* Low hurts. Let's disable the filtering. */
4606 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4609 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4612 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4613 * register to be written before TxDescAddrLow to work.
4614 * Switching from MMIO to I/O access fixes the issue as well.
4616 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4617 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4618 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4619 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4622 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4624 static const struct rtl_cfg2_info {
4629 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4630 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4631 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4632 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4634 const struct rtl_cfg2_info *p = cfg2_info;
4638 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4639 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4640 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4641 RTL_W32(tp, 0x7c, p->val);
4647 static void rtl_set_rx_mode(struct net_device *dev)
4649 struct rtl8169_private *tp = netdev_priv(dev);
4650 u32 mc_filter[2]; /* Multicast hash filter */
4654 if (dev->flags & IFF_PROMISC) {
4655 /* Unconditionally log net taps. */
4656 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4658 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4660 mc_filter[1] = mc_filter[0] = 0xffffffff;
4661 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4662 (dev->flags & IFF_ALLMULTI)) {
4663 /* Too many to filter perfectly -- accept all multicasts. */
4664 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4665 mc_filter[1] = mc_filter[0] = 0xffffffff;
4667 struct netdev_hw_addr *ha;
4669 rx_mode = AcceptBroadcast | AcceptMyPhys;
4670 mc_filter[1] = mc_filter[0] = 0;
4671 netdev_for_each_mc_addr(ha, dev) {
4672 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4673 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4674 rx_mode |= AcceptMulticast;
4678 if (dev->features & NETIF_F_RXALL)
4679 rx_mode |= (AcceptErr | AcceptRunt);
4681 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4683 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4684 u32 data = mc_filter[0];
4686 mc_filter[0] = swab32(mc_filter[1]);
4687 mc_filter[1] = swab32(data);
4690 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4691 mc_filter[1] = mc_filter[0] = 0xffffffff;
4693 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4694 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4696 RTL_W32(tp, RxConfig, tmp);
4699 static void rtl_hw_start(struct rtl8169_private *tp)
4701 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4705 rtl_set_rx_max_size(tp);
4706 rtl_set_rx_tx_desc_registers(tp);
4707 rtl_set_rx_tx_config_registers(tp);
4708 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4710 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4711 RTL_R8(tp, IntrMask);
4712 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4713 rtl_set_rx_mode(tp->dev);
4714 /* no early-rx interrupts */
4715 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4716 rtl_irq_enable_all(tp);
4719 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4721 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4722 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4724 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4726 tp->cp_cmd |= PCIMulRW;
4728 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4729 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4730 netif_dbg(tp, drv, tp->dev,
4731 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4732 tp->cp_cmd |= (1 << 14);
4735 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4737 rtl8169_set_magic_reg(tp, tp->mac_version);
4740 * Undocumented corner. Supposedly:
4741 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4743 RTL_W16(tp, IntrMitigate, 0x0000);
4745 RTL_W32(tp, RxMissed, 0);
4748 DECLARE_RTL_COND(rtl_csiar_cond)
4750 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4753 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4755 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4757 RTL_W32(tp, CSIDR, value);
4758 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4759 CSIAR_BYTE_ENABLE | func << 16);
4761 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4764 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4766 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4768 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4771 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4772 RTL_R32(tp, CSIDR) : ~0;
4775 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4777 struct pci_dev *pdev = tp->pci_dev;
4780 /* According to Realtek the value at config space address 0x070f
4781 * controls the L0s/L1 entrance latency. We try standard ECAM access
4782 * first and if it fails fall back to CSI.
4784 if (pdev->cfg_size > 0x070f &&
4785 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4788 netdev_notice_once(tp->dev,
4789 "No native access to PCI extended config space, falling back to CSI\n");
4790 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4791 rtl_csi_write(tp, 0x070c, csi | val << 24);
4794 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4796 rtl_csi_access_enable(tp, 0x27);
4800 unsigned int offset;
4805 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4811 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4812 rtl_ephy_write(tp, e->offset, w);
4817 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4819 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4820 PCI_EXP_LNKCTL_CLKREQ_EN);
4823 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4825 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4826 PCI_EXP_LNKCTL_CLKREQ_EN);
4829 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4833 data = RTL_R8(tp, Config3);
4838 data &= ~Rdy_to_L23;
4840 RTL_W8(tp, Config3, data);
4843 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4846 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4847 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4849 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4850 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4854 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4856 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4858 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4859 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4861 if (tp->dev->mtu <= ETH_DATA_LEN) {
4862 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4863 PCI_EXP_DEVCTL_NOSNOOP_EN);
4867 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4869 rtl_hw_start_8168bb(tp);
4871 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4873 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4876 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4878 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4880 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4882 if (tp->dev->mtu <= ETH_DATA_LEN)
4883 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4885 rtl_disable_clock_request(tp);
4887 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4888 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4891 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4893 static const struct ephy_info e_info_8168cp[] = {
4894 { 0x01, 0, 0x0001 },
4895 { 0x02, 0x0800, 0x1000 },
4896 { 0x03, 0, 0x0042 },
4897 { 0x06, 0x0080, 0x0000 },
4901 rtl_set_def_aspm_entry_latency(tp);
4903 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4905 __rtl_hw_start_8168cp(tp);
4908 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4910 rtl_set_def_aspm_entry_latency(tp);
4912 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4914 if (tp->dev->mtu <= ETH_DATA_LEN)
4915 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4917 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4918 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4921 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4923 rtl_set_def_aspm_entry_latency(tp);
4925 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4928 RTL_W8(tp, DBG_REG, 0x20);
4930 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4932 if (tp->dev->mtu <= ETH_DATA_LEN)
4933 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4935 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4936 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4939 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4941 static const struct ephy_info e_info_8168c_1[] = {
4942 { 0x02, 0x0800, 0x1000 },
4943 { 0x03, 0, 0x0002 },
4944 { 0x06, 0x0080, 0x0000 }
4947 rtl_set_def_aspm_entry_latency(tp);
4949 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4951 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4953 __rtl_hw_start_8168cp(tp);
4956 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4958 static const struct ephy_info e_info_8168c_2[] = {
4959 { 0x01, 0, 0x0001 },
4960 { 0x03, 0x0400, 0x0220 }
4963 rtl_set_def_aspm_entry_latency(tp);
4965 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4967 __rtl_hw_start_8168cp(tp);
4970 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4972 rtl_hw_start_8168c_2(tp);
4975 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4977 rtl_set_def_aspm_entry_latency(tp);
4979 __rtl_hw_start_8168cp(tp);
4982 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4984 rtl_set_def_aspm_entry_latency(tp);
4986 rtl_disable_clock_request(tp);
4988 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4990 if (tp->dev->mtu <= ETH_DATA_LEN)
4991 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4993 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4994 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4997 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4999 rtl_set_def_aspm_entry_latency(tp);
5001 if (tp->dev->mtu <= ETH_DATA_LEN)
5002 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5004 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5006 rtl_disable_clock_request(tp);
5009 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5011 static const struct ephy_info e_info_8168d_4[] = {
5012 { 0x0b, 0x0000, 0x0048 },
5013 { 0x19, 0x0020, 0x0050 },
5014 { 0x0c, 0x0100, 0x0020 }
5017 rtl_set_def_aspm_entry_latency(tp);
5019 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5021 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5023 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5025 rtl_enable_clock_request(tp);
5028 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5030 static const struct ephy_info e_info_8168e_1[] = {
5031 { 0x00, 0x0200, 0x0100 },
5032 { 0x00, 0x0000, 0x0004 },
5033 { 0x06, 0x0002, 0x0001 },
5034 { 0x06, 0x0000, 0x0030 },
5035 { 0x07, 0x0000, 0x2000 },
5036 { 0x00, 0x0000, 0x0020 },
5037 { 0x03, 0x5800, 0x2000 },
5038 { 0x03, 0x0000, 0x0001 },
5039 { 0x01, 0x0800, 0x1000 },
5040 { 0x07, 0x0000, 0x4000 },
5041 { 0x1e, 0x0000, 0x2000 },
5042 { 0x19, 0xffff, 0xfe6c },
5043 { 0x0a, 0x0000, 0x0040 }
5046 rtl_set_def_aspm_entry_latency(tp);
5048 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5050 if (tp->dev->mtu <= ETH_DATA_LEN)
5051 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5053 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5055 rtl_disable_clock_request(tp);
5057 /* Reset tx FIFO pointer */
5058 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5059 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5061 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5064 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5066 static const struct ephy_info e_info_8168e_2[] = {
5067 { 0x09, 0x0000, 0x0080 },
5068 { 0x19, 0x0000, 0x0224 }
5071 rtl_set_def_aspm_entry_latency(tp);
5073 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5075 if (tp->dev->mtu <= ETH_DATA_LEN)
5076 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5078 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5079 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5080 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5081 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5082 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5083 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5084 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5085 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5087 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5089 rtl_disable_clock_request(tp);
5091 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5092 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5094 /* Adjust EEE LED frequency */
5095 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5097 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5098 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5099 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5101 rtl_hw_aspm_clkreq_enable(tp, true);
5104 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5106 rtl_set_def_aspm_entry_latency(tp);
5108 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5110 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5111 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5112 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5113 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5114 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5115 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5116 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5117 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5118 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5119 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5121 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5123 rtl_disable_clock_request(tp);
5125 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5126 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5127 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5128 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5129 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5132 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5134 static const struct ephy_info e_info_8168f_1[] = {
5135 { 0x06, 0x00c0, 0x0020 },
5136 { 0x08, 0x0001, 0x0002 },
5137 { 0x09, 0x0000, 0x0080 },
5138 { 0x19, 0x0000, 0x0224 }
5141 rtl_hw_start_8168f(tp);
5143 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5145 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5147 /* Adjust EEE LED frequency */
5148 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5151 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5153 static const struct ephy_info e_info_8168f_1[] = {
5154 { 0x06, 0x00c0, 0x0020 },
5155 { 0x0f, 0xffff, 0x5200 },
5156 { 0x1e, 0x0000, 0x4000 },
5157 { 0x19, 0x0000, 0x0224 }
5160 rtl_hw_start_8168f(tp);
5161 rtl_pcie_state_l2l3_enable(tp, false);
5163 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5165 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5168 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5170 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5172 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5173 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5174 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5175 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5177 rtl_set_def_aspm_entry_latency(tp);
5179 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5181 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5182 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5183 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5185 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5186 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5188 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5189 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5191 /* Adjust EEE LED frequency */
5192 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5194 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5195 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5197 rtl_pcie_state_l2l3_enable(tp, false);
5200 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5202 static const struct ephy_info e_info_8168g_1[] = {
5203 { 0x00, 0x0000, 0x0008 },
5204 { 0x0c, 0x37d0, 0x0820 },
5205 { 0x1e, 0x0000, 0x0001 },
5206 { 0x19, 0x8000, 0x0000 }
5209 rtl_hw_start_8168g(tp);
5211 /* disable aspm and clock request before access ephy */
5212 rtl_hw_aspm_clkreq_enable(tp, false);
5213 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5214 rtl_hw_aspm_clkreq_enable(tp, true);
5217 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5219 static const struct ephy_info e_info_8168g_2[] = {
5220 { 0x00, 0x0000, 0x0008 },
5221 { 0x0c, 0x3df0, 0x0200 },
5222 { 0x19, 0xffff, 0xfc00 },
5223 { 0x1e, 0xffff, 0x20eb }
5226 rtl_hw_start_8168g(tp);
5228 /* disable aspm and clock request before access ephy */
5229 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5230 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5231 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5234 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5236 static const struct ephy_info e_info_8411_2[] = {
5237 { 0x00, 0x0000, 0x0008 },
5238 { 0x0c, 0x3df0, 0x0200 },
5239 { 0x0f, 0xffff, 0x5200 },
5240 { 0x19, 0x0020, 0x0000 },
5241 { 0x1e, 0x0000, 0x2000 }
5244 rtl_hw_start_8168g(tp);
5246 /* disable aspm and clock request before access ephy */
5247 rtl_hw_aspm_clkreq_enable(tp, false);
5248 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5249 rtl_hw_aspm_clkreq_enable(tp, true);
5252 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5256 static const struct ephy_info e_info_8168h_1[] = {
5257 { 0x1e, 0x0800, 0x0001 },
5258 { 0x1d, 0x0000, 0x0800 },
5259 { 0x05, 0xffff, 0x2089 },
5260 { 0x06, 0xffff, 0x5881 },
5261 { 0x04, 0xffff, 0x154a },
5262 { 0x01, 0xffff, 0x068b }
5265 /* disable aspm and clock request before access ephy */
5266 rtl_hw_aspm_clkreq_enable(tp, false);
5267 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5269 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5271 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5272 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5273 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5274 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5276 rtl_set_def_aspm_entry_latency(tp);
5278 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5280 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5281 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5283 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5285 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5287 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5289 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5290 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5292 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5293 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5295 /* Adjust EEE LED frequency */
5296 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5298 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5299 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5301 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5303 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5305 rtl_pcie_state_l2l3_enable(tp, false);
5307 rtl_writephy(tp, 0x1f, 0x0c42);
5308 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5309 rtl_writephy(tp, 0x1f, 0x0000);
5310 if (rg_saw_cnt > 0) {
5313 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5314 sw_cnt_1ms_ini &= 0x0fff;
5315 data = r8168_mac_ocp_read(tp, 0xd412);
5317 data |= sw_cnt_1ms_ini;
5318 r8168_mac_ocp_write(tp, 0xd412, data);
5321 data = r8168_mac_ocp_read(tp, 0xe056);
5324 r8168_mac_ocp_write(tp, 0xe056, data);
5326 data = r8168_mac_ocp_read(tp, 0xe052);
5329 r8168_mac_ocp_write(tp, 0xe052, data);
5331 data = r8168_mac_ocp_read(tp, 0xe0d6);
5334 r8168_mac_ocp_write(tp, 0xe0d6, data);
5336 data = r8168_mac_ocp_read(tp, 0xd420);
5339 r8168_mac_ocp_write(tp, 0xd420, data);
5341 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5342 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5343 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5344 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5346 rtl_hw_aspm_clkreq_enable(tp, true);
5349 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5351 rtl8168ep_stop_cmac(tp);
5353 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5355 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5356 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5357 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5358 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5360 rtl_set_def_aspm_entry_latency(tp);
5362 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5364 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5365 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5367 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5369 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5371 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5372 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5374 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5375 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5377 /* Adjust EEE LED frequency */
5378 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5380 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5382 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5384 rtl_pcie_state_l2l3_enable(tp, false);
5387 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5389 static const struct ephy_info e_info_8168ep_1[] = {
5390 { 0x00, 0xffff, 0x10ab },
5391 { 0x06, 0xffff, 0xf030 },
5392 { 0x08, 0xffff, 0x2006 },
5393 { 0x0d, 0xffff, 0x1666 },
5394 { 0x0c, 0x3ff0, 0x0000 }
5397 /* disable aspm and clock request before access ephy */
5398 rtl_hw_aspm_clkreq_enable(tp, false);
5399 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5401 rtl_hw_start_8168ep(tp);
5403 rtl_hw_aspm_clkreq_enable(tp, true);
5406 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5408 static const struct ephy_info e_info_8168ep_2[] = {
5409 { 0x00, 0xffff, 0x10a3 },
5410 { 0x19, 0xffff, 0xfc00 },
5411 { 0x1e, 0xffff, 0x20ea }
5414 /* disable aspm and clock request before access ephy */
5415 rtl_hw_aspm_clkreq_enable(tp, false);
5416 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5418 rtl_hw_start_8168ep(tp);
5420 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5421 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5423 rtl_hw_aspm_clkreq_enable(tp, true);
5426 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5429 static const struct ephy_info e_info_8168ep_3[] = {
5430 { 0x00, 0xffff, 0x10a3 },
5431 { 0x19, 0xffff, 0x7c00 },
5432 { 0x1e, 0xffff, 0x20eb },
5433 { 0x0d, 0xffff, 0x1666 }
5436 /* disable aspm and clock request before access ephy */
5437 rtl_hw_aspm_clkreq_enable(tp, false);
5438 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5440 rtl_hw_start_8168ep(tp);
5442 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5443 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5445 data = r8168_mac_ocp_read(tp, 0xd3e2);
5448 r8168_mac_ocp_write(tp, 0xd3e2, data);
5450 data = r8168_mac_ocp_read(tp, 0xd3e4);
5452 r8168_mac_ocp_write(tp, 0xd3e4, data);
5454 data = r8168_mac_ocp_read(tp, 0xe860);
5456 r8168_mac_ocp_write(tp, 0xe860, data);
5458 rtl_hw_aspm_clkreq_enable(tp, true);
5461 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5463 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5465 tp->cp_cmd &= ~INTT_MASK;
5466 tp->cp_cmd |= PktCntrDisable | INTT_1;
5467 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5469 RTL_W16(tp, IntrMitigate, 0x5151);
5471 /* Work around for RxFIFO overflow. */
5472 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5473 tp->event_slow |= RxFIFOOver | PCSTimeout;
5474 tp->event_slow &= ~RxOverflow;
5477 switch (tp->mac_version) {
5478 case RTL_GIGA_MAC_VER_11:
5479 rtl_hw_start_8168bb(tp);
5482 case RTL_GIGA_MAC_VER_12:
5483 case RTL_GIGA_MAC_VER_17:
5484 rtl_hw_start_8168bef(tp);
5487 case RTL_GIGA_MAC_VER_18:
5488 rtl_hw_start_8168cp_1(tp);
5491 case RTL_GIGA_MAC_VER_19:
5492 rtl_hw_start_8168c_1(tp);
5495 case RTL_GIGA_MAC_VER_20:
5496 rtl_hw_start_8168c_2(tp);
5499 case RTL_GIGA_MAC_VER_21:
5500 rtl_hw_start_8168c_3(tp);
5503 case RTL_GIGA_MAC_VER_22:
5504 rtl_hw_start_8168c_4(tp);
5507 case RTL_GIGA_MAC_VER_23:
5508 rtl_hw_start_8168cp_2(tp);
5511 case RTL_GIGA_MAC_VER_24:
5512 rtl_hw_start_8168cp_3(tp);
5515 case RTL_GIGA_MAC_VER_25:
5516 case RTL_GIGA_MAC_VER_26:
5517 case RTL_GIGA_MAC_VER_27:
5518 rtl_hw_start_8168d(tp);
5521 case RTL_GIGA_MAC_VER_28:
5522 rtl_hw_start_8168d_4(tp);
5525 case RTL_GIGA_MAC_VER_31:
5526 rtl_hw_start_8168dp(tp);
5529 case RTL_GIGA_MAC_VER_32:
5530 case RTL_GIGA_MAC_VER_33:
5531 rtl_hw_start_8168e_1(tp);
5533 case RTL_GIGA_MAC_VER_34:
5534 rtl_hw_start_8168e_2(tp);
5537 case RTL_GIGA_MAC_VER_35:
5538 case RTL_GIGA_MAC_VER_36:
5539 rtl_hw_start_8168f_1(tp);
5542 case RTL_GIGA_MAC_VER_38:
5543 rtl_hw_start_8411(tp);
5546 case RTL_GIGA_MAC_VER_40:
5547 case RTL_GIGA_MAC_VER_41:
5548 rtl_hw_start_8168g_1(tp);
5550 case RTL_GIGA_MAC_VER_42:
5551 rtl_hw_start_8168g_2(tp);
5554 case RTL_GIGA_MAC_VER_44:
5555 rtl_hw_start_8411_2(tp);
5558 case RTL_GIGA_MAC_VER_45:
5559 case RTL_GIGA_MAC_VER_46:
5560 rtl_hw_start_8168h_1(tp);
5563 case RTL_GIGA_MAC_VER_49:
5564 rtl_hw_start_8168ep_1(tp);
5567 case RTL_GIGA_MAC_VER_50:
5568 rtl_hw_start_8168ep_2(tp);
5571 case RTL_GIGA_MAC_VER_51:
5572 rtl_hw_start_8168ep_3(tp);
5576 netif_err(tp, drv, tp->dev,
5577 "unknown chipset (mac_version = %d)\n",
5583 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5585 static const struct ephy_info e_info_8102e_1[] = {
5586 { 0x01, 0, 0x6e65 },
5587 { 0x02, 0, 0x091f },
5588 { 0x03, 0, 0xc2f9 },
5589 { 0x06, 0, 0xafb5 },
5590 { 0x07, 0, 0x0e00 },
5591 { 0x19, 0, 0xec80 },
5592 { 0x01, 0, 0x2e65 },
5597 rtl_set_def_aspm_entry_latency(tp);
5599 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5601 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5604 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5605 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5607 cfg1 = RTL_R8(tp, Config1);
5608 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5609 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5611 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5614 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5616 rtl_set_def_aspm_entry_latency(tp);
5618 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5620 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5621 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5624 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5626 rtl_hw_start_8102e_2(tp);
5628 rtl_ephy_write(tp, 0x03, 0xc2f9);
5631 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5633 static const struct ephy_info e_info_8105e_1[] = {
5634 { 0x07, 0, 0x4000 },
5635 { 0x19, 0, 0x0200 },
5636 { 0x19, 0, 0x0020 },
5637 { 0x1e, 0, 0x2000 },
5638 { 0x03, 0, 0x0001 },
5639 { 0x19, 0, 0x0100 },
5640 { 0x19, 0, 0x0004 },
5644 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5645 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5647 /* Disable Early Tally Counter */
5648 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5650 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5651 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5653 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5655 rtl_pcie_state_l2l3_enable(tp, false);
5658 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5660 rtl_hw_start_8105e_1(tp);
5661 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5664 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5666 static const struct ephy_info e_info_8402[] = {
5667 { 0x19, 0xffff, 0xff64 },
5671 rtl_set_def_aspm_entry_latency(tp);
5673 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5674 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5676 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5677 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5679 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5681 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5683 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5684 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5685 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5686 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5687 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5688 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5689 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5691 rtl_pcie_state_l2l3_enable(tp, false);
5694 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5696 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5697 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5699 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5700 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5701 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5703 rtl_pcie_state_l2l3_enable(tp, false);
5706 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5708 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5709 tp->event_slow &= ~RxFIFOOver;
5711 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5712 tp->mac_version == RTL_GIGA_MAC_VER_16)
5713 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5714 PCI_EXP_DEVCTL_NOSNOOP_EN);
5716 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5718 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5719 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5721 switch (tp->mac_version) {
5722 case RTL_GIGA_MAC_VER_07:
5723 rtl_hw_start_8102e_1(tp);
5726 case RTL_GIGA_MAC_VER_08:
5727 rtl_hw_start_8102e_3(tp);
5730 case RTL_GIGA_MAC_VER_09:
5731 rtl_hw_start_8102e_2(tp);
5734 case RTL_GIGA_MAC_VER_29:
5735 rtl_hw_start_8105e_1(tp);
5737 case RTL_GIGA_MAC_VER_30:
5738 rtl_hw_start_8105e_2(tp);
5741 case RTL_GIGA_MAC_VER_37:
5742 rtl_hw_start_8402(tp);
5745 case RTL_GIGA_MAC_VER_39:
5746 rtl_hw_start_8106(tp);
5748 case RTL_GIGA_MAC_VER_43:
5749 rtl_hw_start_8168g_2(tp);
5751 case RTL_GIGA_MAC_VER_47:
5752 case RTL_GIGA_MAC_VER_48:
5753 rtl_hw_start_8168h_1(tp);
5757 RTL_W16(tp, IntrMitigate, 0x0000);
5760 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5762 struct rtl8169_private *tp = netdev_priv(dev);
5764 if (new_mtu > ETH_DATA_LEN)
5765 rtl_hw_jumbo_enable(tp);
5767 rtl_hw_jumbo_disable(tp);
5770 netdev_update_features(dev);
5775 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5777 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5778 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5781 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5782 void **data_buff, struct RxDesc *desc)
5784 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5785 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5789 rtl8169_make_unusable_by_asic(desc);
5792 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5794 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5796 /* Force memory writes to complete before releasing descriptor */
5799 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5802 static inline void *rtl8169_align(void *data)
5804 return (void *)ALIGN((long)data, 16);
5807 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5808 struct RxDesc *desc)
5812 struct device *d = tp_to_dev(tp);
5813 int node = dev_to_node(d);
5815 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5819 if (rtl8169_align(data) != data) {
5821 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5826 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5828 if (unlikely(dma_mapping_error(d, mapping))) {
5829 if (net_ratelimit())
5830 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5834 desc->addr = cpu_to_le64(mapping);
5835 rtl8169_mark_to_asic(desc);
5843 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5847 for (i = 0; i < NUM_RX_DESC; i++) {
5848 if (tp->Rx_databuff[i]) {
5849 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5850 tp->RxDescArray + i);
5855 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5857 desc->opts1 |= cpu_to_le32(RingEnd);
5860 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5864 for (i = 0; i < NUM_RX_DESC; i++) {
5867 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5869 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5872 tp->Rx_databuff[i] = data;
5875 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5879 rtl8169_rx_clear(tp);
5883 static int rtl8169_init_ring(struct rtl8169_private *tp)
5885 rtl8169_init_ring_indexes(tp);
5887 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5888 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5890 return rtl8169_rx_fill(tp);
5893 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5894 struct TxDesc *desc)
5896 unsigned int len = tx_skb->len;
5898 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5906 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5911 for (i = 0; i < n; i++) {
5912 unsigned int entry = (start + i) % NUM_TX_DESC;
5913 struct ring_info *tx_skb = tp->tx_skb + entry;
5914 unsigned int len = tx_skb->len;
5917 struct sk_buff *skb = tx_skb->skb;
5919 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5920 tp->TxDescArray + entry);
5922 dev_consume_skb_any(skb);
5929 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5931 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5932 tp->cur_tx = tp->dirty_tx = 0;
5935 static void rtl_reset_work(struct rtl8169_private *tp)
5937 struct net_device *dev = tp->dev;
5940 napi_disable(&tp->napi);
5941 netif_stop_queue(dev);
5942 synchronize_sched();
5944 rtl8169_hw_reset(tp);
5946 for (i = 0; i < NUM_RX_DESC; i++)
5947 rtl8169_mark_to_asic(tp->RxDescArray + i);
5949 rtl8169_tx_clear(tp);
5950 rtl8169_init_ring_indexes(tp);
5952 napi_enable(&tp->napi);
5954 netif_wake_queue(dev);
5957 static void rtl8169_tx_timeout(struct net_device *dev)
5959 struct rtl8169_private *tp = netdev_priv(dev);
5961 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5964 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5967 struct skb_shared_info *info = skb_shinfo(skb);
5968 unsigned int cur_frag, entry;
5969 struct TxDesc *uninitialized_var(txd);
5970 struct device *d = tp_to_dev(tp);
5973 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5974 const skb_frag_t *frag = info->frags + cur_frag;
5979 entry = (entry + 1) % NUM_TX_DESC;
5981 txd = tp->TxDescArray + entry;
5982 len = skb_frag_size(frag);
5983 addr = skb_frag_address(frag);
5984 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5985 if (unlikely(dma_mapping_error(d, mapping))) {
5986 if (net_ratelimit())
5987 netif_err(tp, drv, tp->dev,
5988 "Failed to map TX fragments DMA!\n");
5992 /* Anti gcc 2.95.3 bugware (sic) */
5993 status = opts[0] | len |
5994 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5996 txd->opts1 = cpu_to_le32(status);
5997 txd->opts2 = cpu_to_le32(opts[1]);
5998 txd->addr = cpu_to_le64(mapping);
6000 tp->tx_skb[entry].len = len;
6004 tp->tx_skb[entry].skb = skb;
6005 txd->opts1 |= cpu_to_le32(LastFrag);
6011 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6015 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6017 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6020 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6021 struct net_device *dev);
6022 /* r8169_csum_workaround()
6023 * The hw limites the value the transport offset. When the offset is out of the
6024 * range, calculate the checksum by sw.
6026 static void r8169_csum_workaround(struct rtl8169_private *tp,
6027 struct sk_buff *skb)
6029 if (skb_shinfo(skb)->gso_size) {
6030 netdev_features_t features = tp->dev->features;
6031 struct sk_buff *segs, *nskb;
6033 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6034 segs = skb_gso_segment(skb, features);
6035 if (IS_ERR(segs) || !segs)
6042 rtl8169_start_xmit(nskb, tp->dev);
6045 dev_consume_skb_any(skb);
6046 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6047 if (skb_checksum_help(skb) < 0)
6050 rtl8169_start_xmit(skb, tp->dev);
6052 struct net_device_stats *stats;
6055 stats = &tp->dev->stats;
6056 stats->tx_dropped++;
6057 dev_kfree_skb_any(skb);
6061 /* msdn_giant_send_check()
6062 * According to the document of microsoft, the TCP Pseudo Header excludes the
6063 * packet length for IPv6 TCP large packets.
6065 static int msdn_giant_send_check(struct sk_buff *skb)
6067 const struct ipv6hdr *ipv6h;
6071 ret = skb_cow_head(skb, 0);
6075 ipv6h = ipv6_hdr(skb);
6079 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6084 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6085 struct sk_buff *skb, u32 *opts)
6087 u32 mss = skb_shinfo(skb)->gso_size;
6091 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6092 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6093 const struct iphdr *ip = ip_hdr(skb);
6095 if (ip->protocol == IPPROTO_TCP)
6096 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6097 else if (ip->protocol == IPPROTO_UDP)
6098 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6106 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6107 struct sk_buff *skb, u32 *opts)
6109 u32 transport_offset = (u32)skb_transport_offset(skb);
6110 u32 mss = skb_shinfo(skb)->gso_size;
6113 if (transport_offset > GTTCPHO_MAX) {
6114 netif_warn(tp, tx_err, tp->dev,
6115 "Invalid transport offset 0x%x for TSO\n",
6120 switch (vlan_get_protocol(skb)) {
6121 case htons(ETH_P_IP):
6122 opts[0] |= TD1_GTSENV4;
6125 case htons(ETH_P_IPV6):
6126 if (msdn_giant_send_check(skb))
6129 opts[0] |= TD1_GTSENV6;
6137 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6138 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6139 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6142 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6143 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6145 if (transport_offset > TCPHO_MAX) {
6146 netif_warn(tp, tx_err, tp->dev,
6147 "Invalid transport offset 0x%x\n",
6152 switch (vlan_get_protocol(skb)) {
6153 case htons(ETH_P_IP):
6154 opts[1] |= TD1_IPv4_CS;
6155 ip_protocol = ip_hdr(skb)->protocol;
6158 case htons(ETH_P_IPV6):
6159 opts[1] |= TD1_IPv6_CS;
6160 ip_protocol = ipv6_hdr(skb)->nexthdr;
6164 ip_protocol = IPPROTO_RAW;
6168 if (ip_protocol == IPPROTO_TCP)
6169 opts[1] |= TD1_TCP_CS;
6170 else if (ip_protocol == IPPROTO_UDP)
6171 opts[1] |= TD1_UDP_CS;
6175 opts[1] |= transport_offset << TCPHO_SHIFT;
6177 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6178 return !eth_skb_pad(skb);
6184 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6185 struct net_device *dev)
6187 struct rtl8169_private *tp = netdev_priv(dev);
6188 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6189 struct TxDesc *txd = tp->TxDescArray + entry;
6190 struct device *d = tp_to_dev(tp);
6196 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6197 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6201 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6204 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6207 if (!tp->tso_csum(tp, skb, opts)) {
6208 r8169_csum_workaround(tp, skb);
6209 return NETDEV_TX_OK;
6212 len = skb_headlen(skb);
6213 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6214 if (unlikely(dma_mapping_error(d, mapping))) {
6215 if (net_ratelimit())
6216 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6220 tp->tx_skb[entry].len = len;
6221 txd->addr = cpu_to_le64(mapping);
6223 frags = rtl8169_xmit_frags(tp, skb, opts);
6227 opts[0] |= FirstFrag;
6229 opts[0] |= FirstFrag | LastFrag;
6230 tp->tx_skb[entry].skb = skb;
6233 txd->opts2 = cpu_to_le32(opts[1]);
6235 skb_tx_timestamp(skb);
6237 /* Force memory writes to complete before releasing descriptor */
6240 /* Anti gcc 2.95.3 bugware (sic) */
6241 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6242 txd->opts1 = cpu_to_le32(status);
6244 /* Force all memory writes to complete before notifying device */
6247 tp->cur_tx += frags + 1;
6249 RTL_W8(tp, TxPoll, NPQ);
6253 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6254 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6255 * not miss a ring update when it notices a stopped queue.
6258 netif_stop_queue(dev);
6259 /* Sync with rtl_tx:
6260 * - publish queue status and cur_tx ring index (write barrier)
6261 * - refresh dirty_tx ring index (read barrier).
6262 * May the current thread have a pessimistic view of the ring
6263 * status and forget to wake up queue, a racing rtl_tx thread
6267 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6268 netif_wake_queue(dev);
6271 return NETDEV_TX_OK;
6274 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6276 dev_kfree_skb_any(skb);
6277 dev->stats.tx_dropped++;
6278 return NETDEV_TX_OK;
6281 netif_stop_queue(dev);
6282 dev->stats.tx_dropped++;
6283 return NETDEV_TX_BUSY;
6286 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6288 struct rtl8169_private *tp = netdev_priv(dev);
6289 struct pci_dev *pdev = tp->pci_dev;
6290 u16 pci_status, pci_cmd;
6292 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6293 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6295 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6296 pci_cmd, pci_status);
6299 * The recovery sequence below admits a very elaborated explanation:
6300 * - it seems to work;
6301 * - I did not see what else could be done;
6302 * - it makes iop3xx happy.
6304 * Feel free to adjust to your needs.
6306 if (pdev->broken_parity_status)
6307 pci_cmd &= ~PCI_COMMAND_PARITY;
6309 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6311 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6313 pci_write_config_word(pdev, PCI_STATUS,
6314 pci_status & (PCI_STATUS_DETECTED_PARITY |
6315 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6316 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6318 /* The infamous DAC f*ckup only happens at boot time */
6319 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6320 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6321 tp->cp_cmd &= ~PCIDAC;
6322 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6323 dev->features &= ~NETIF_F_HIGHDMA;
6326 rtl8169_hw_reset(tp);
6328 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6331 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6333 unsigned int dirty_tx, tx_left;
6335 dirty_tx = tp->dirty_tx;
6337 tx_left = tp->cur_tx - dirty_tx;
6339 while (tx_left > 0) {
6340 unsigned int entry = dirty_tx % NUM_TX_DESC;
6341 struct ring_info *tx_skb = tp->tx_skb + entry;
6344 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6345 if (status & DescOwn)
6348 /* This barrier is needed to keep us from reading
6349 * any other fields out of the Tx descriptor until
6350 * we know the status of DescOwn
6354 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6355 tp->TxDescArray + entry);
6356 if (status & LastFrag) {
6357 u64_stats_update_begin(&tp->tx_stats.syncp);
6358 tp->tx_stats.packets++;
6359 tp->tx_stats.bytes += tx_skb->skb->len;
6360 u64_stats_update_end(&tp->tx_stats.syncp);
6361 dev_consume_skb_any(tx_skb->skb);
6368 if (tp->dirty_tx != dirty_tx) {
6369 tp->dirty_tx = dirty_tx;
6370 /* Sync with rtl8169_start_xmit:
6371 * - publish dirty_tx ring index (write barrier)
6372 * - refresh cur_tx ring index and queue status (read barrier)
6373 * May the current thread miss the stopped queue condition,
6374 * a racing xmit thread can only have a right view of the
6378 if (netif_queue_stopped(dev) &&
6379 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6380 netif_wake_queue(dev);
6383 * 8168 hack: TxPoll requests are lost when the Tx packets are
6384 * too close. Let's kick an extra TxPoll request when a burst
6385 * of start_xmit activity is detected (if it is not detected,
6386 * it is slow enough). -- FR
6388 if (tp->cur_tx != dirty_tx)
6389 RTL_W8(tp, TxPoll, NPQ);
6393 static inline int rtl8169_fragmented_frame(u32 status)
6395 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6398 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6400 u32 status = opts1 & RxProtoMask;
6402 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6403 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6404 skb->ip_summed = CHECKSUM_UNNECESSARY;
6406 skb_checksum_none_assert(skb);
6409 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6410 struct rtl8169_private *tp,
6414 struct sk_buff *skb;
6415 struct device *d = tp_to_dev(tp);
6417 data = rtl8169_align(data);
6418 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6420 skb = napi_alloc_skb(&tp->napi, pkt_size);
6422 skb_copy_to_linear_data(skb, data, pkt_size);
6423 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6428 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6430 unsigned int cur_rx, rx_left;
6433 cur_rx = tp->cur_rx;
6435 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6436 unsigned int entry = cur_rx % NUM_RX_DESC;
6437 struct RxDesc *desc = tp->RxDescArray + entry;
6440 status = le32_to_cpu(desc->opts1);
6441 if (status & DescOwn)
6444 /* This barrier is needed to keep us from reading
6445 * any other fields out of the Rx descriptor until
6446 * we know the status of DescOwn
6450 if (unlikely(status & RxRES)) {
6451 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6453 dev->stats.rx_errors++;
6454 if (status & (RxRWT | RxRUNT))
6455 dev->stats.rx_length_errors++;
6457 dev->stats.rx_crc_errors++;
6458 /* RxFOVF is a reserved bit on later chip versions */
6459 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6461 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6462 dev->stats.rx_fifo_errors++;
6463 } else if (status & (RxRUNT | RxCRC) &&
6464 !(status & RxRWT) &&
6465 dev->features & NETIF_F_RXALL) {
6469 struct sk_buff *skb;
6474 addr = le64_to_cpu(desc->addr);
6475 if (likely(!(dev->features & NETIF_F_RXFCS)))
6476 pkt_size = (status & 0x00003fff) - 4;
6478 pkt_size = status & 0x00003fff;
6481 * The driver does not support incoming fragmented
6482 * frames. They are seen as a symptom of over-mtu
6485 if (unlikely(rtl8169_fragmented_frame(status))) {
6486 dev->stats.rx_dropped++;
6487 dev->stats.rx_length_errors++;
6488 goto release_descriptor;
6491 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6492 tp, pkt_size, addr);
6494 dev->stats.rx_dropped++;
6495 goto release_descriptor;
6498 rtl8169_rx_csum(skb, status);
6499 skb_put(skb, pkt_size);
6500 skb->protocol = eth_type_trans(skb, dev);
6502 rtl8169_rx_vlan_tag(desc, skb);
6504 if (skb->pkt_type == PACKET_MULTICAST)
6505 dev->stats.multicast++;
6507 napi_gro_receive(&tp->napi, skb);
6509 u64_stats_update_begin(&tp->rx_stats.syncp);
6510 tp->rx_stats.packets++;
6511 tp->rx_stats.bytes += pkt_size;
6512 u64_stats_update_end(&tp->rx_stats.syncp);
6516 rtl8169_mark_to_asic(desc);
6519 count = cur_rx - tp->cur_rx;
6520 tp->cur_rx = cur_rx;
6525 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6527 struct rtl8169_private *tp = dev_instance;
6531 status = rtl_get_events(tp);
6532 if (status && status != 0xffff) {
6533 status &= RTL_EVENT_NAPI | tp->event_slow;
6537 rtl_irq_disable(tp);
6538 napi_schedule_irqoff(&tp->napi);
6541 return IRQ_RETVAL(handled);
6545 * Workqueue context.
6547 static void rtl_slow_event_work(struct rtl8169_private *tp)
6549 struct net_device *dev = tp->dev;
6552 status = rtl_get_events(tp) & tp->event_slow;
6553 rtl_ack_events(tp, status);
6555 if (unlikely(status & RxFIFOOver)) {
6556 switch (tp->mac_version) {
6557 /* Work around for rx fifo overflow */
6558 case RTL_GIGA_MAC_VER_11:
6559 netif_stop_queue(dev);
6560 /* XXX - Hack alert. See rtl_task(). */
6561 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6567 if (unlikely(status & SYSErr))
6568 rtl8169_pcierr_interrupt(dev);
6570 if (status & LinkChg)
6571 phy_mac_interrupt(dev->phydev);
6573 rtl_irq_enable_all(tp);
6576 static void rtl_task(struct work_struct *work)
6578 static const struct {
6580 void (*action)(struct rtl8169_private *);
6582 /* XXX - keep rtl_slow_event_work() as first element. */
6583 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6584 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6586 struct rtl8169_private *tp =
6587 container_of(work, struct rtl8169_private, wk.work);
6588 struct net_device *dev = tp->dev;
6593 if (!netif_running(dev) ||
6594 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6597 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6600 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6602 rtl_work[i].action(tp);
6606 rtl_unlock_work(tp);
6609 static int rtl8169_poll(struct napi_struct *napi, int budget)
6611 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6612 struct net_device *dev = tp->dev;
6613 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6617 status = rtl_get_events(tp);
6618 rtl_ack_events(tp, status & ~tp->event_slow);
6620 if (status & RTL_EVENT_NAPI_RX)
6621 work_done = rtl_rx(dev, tp, (u32) budget);
6623 if (status & RTL_EVENT_NAPI_TX)
6626 if (status & tp->event_slow) {
6627 enable_mask &= ~tp->event_slow;
6629 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6632 if (work_done < budget) {
6633 napi_complete_done(napi, work_done);
6635 rtl_irq_enable(tp, enable_mask);
6642 static void rtl8169_rx_missed(struct net_device *dev)
6644 struct rtl8169_private *tp = netdev_priv(dev);
6646 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6649 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6650 RTL_W32(tp, RxMissed, 0);
6653 static void r8169_phylink_handler(struct net_device *ndev)
6655 struct rtl8169_private *tp = netdev_priv(ndev);
6657 if (netif_carrier_ok(ndev)) {
6658 rtl_link_chg_patch(tp);
6659 pm_request_resume(&tp->pci_dev->dev);
6661 pm_runtime_idle(&tp->pci_dev->dev);
6664 if (net_ratelimit())
6665 phy_print_status(ndev->phydev);
6668 static int r8169_phy_connect(struct rtl8169_private *tp)
6670 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6671 phy_interface_t phy_mode;
6674 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6675 PHY_INTERFACE_MODE_MII;
6677 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6682 if (!tp->supports_gmii)
6683 phy_set_max_speed(phydev, SPEED_100);
6685 /* Ensure to advertise everything, incl. pause */
6686 phydev->advertising = phydev->supported;
6688 phy_attached_info(phydev);
6693 static void rtl8169_down(struct net_device *dev)
6695 struct rtl8169_private *tp = netdev_priv(dev);
6697 phy_stop(dev->phydev);
6699 napi_disable(&tp->napi);
6700 netif_stop_queue(dev);
6702 rtl8169_hw_reset(tp);
6704 * At this point device interrupts can not be enabled in any function,
6705 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6706 * and napi is disabled (rtl8169_poll).
6708 rtl8169_rx_missed(dev);
6710 /* Give a racing hard_start_xmit a few cycles to complete. */
6711 synchronize_sched();
6713 rtl8169_tx_clear(tp);
6715 rtl8169_rx_clear(tp);
6717 rtl_pll_power_down(tp);
6720 static int rtl8169_close(struct net_device *dev)
6722 struct rtl8169_private *tp = netdev_priv(dev);
6723 struct pci_dev *pdev = tp->pci_dev;
6725 pm_runtime_get_sync(&pdev->dev);
6727 /* Update counters before going down */
6728 rtl8169_update_counters(tp);
6731 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6734 rtl_unlock_work(tp);
6736 cancel_work_sync(&tp->wk.work);
6738 phy_disconnect(dev->phydev);
6740 pci_free_irq(pdev, 0, tp);
6742 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6744 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6746 tp->TxDescArray = NULL;
6747 tp->RxDescArray = NULL;
6749 pm_runtime_put_sync(&pdev->dev);
6754 #ifdef CONFIG_NET_POLL_CONTROLLER
6755 static void rtl8169_netpoll(struct net_device *dev)
6757 struct rtl8169_private *tp = netdev_priv(dev);
6759 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6763 static int rtl_open(struct net_device *dev)
6765 struct rtl8169_private *tp = netdev_priv(dev);
6766 struct pci_dev *pdev = tp->pci_dev;
6767 int retval = -ENOMEM;
6769 pm_runtime_get_sync(&pdev->dev);
6772 * Rx and Tx descriptors needs 256 bytes alignment.
6773 * dma_alloc_coherent provides more.
6775 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6776 &tp->TxPhyAddr, GFP_KERNEL);
6777 if (!tp->TxDescArray)
6778 goto err_pm_runtime_put;
6780 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6781 &tp->RxPhyAddr, GFP_KERNEL);
6782 if (!tp->RxDescArray)
6785 retval = rtl8169_init_ring(tp);
6789 INIT_WORK(&tp->wk.work, rtl_task);
6793 rtl_request_firmware(tp);
6795 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6798 goto err_release_fw_2;
6800 retval = r8169_phy_connect(tp);
6806 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6808 napi_enable(&tp->napi);
6810 rtl8169_init_phy(dev, tp);
6812 rtl_pll_power_up(tp);
6816 if (!rtl8169_init_counter_offsets(tp))
6817 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6819 phy_start(dev->phydev);
6820 netif_start_queue(dev);
6822 rtl_unlock_work(tp);
6824 pm_runtime_put_sync(&pdev->dev);
6829 pci_free_irq(pdev, 0, tp);
6831 rtl_release_firmware(tp);
6832 rtl8169_rx_clear(tp);
6834 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6836 tp->RxDescArray = NULL;
6838 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6840 tp->TxDescArray = NULL;
6842 pm_runtime_put_noidle(&pdev->dev);
6847 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6849 struct rtl8169_private *tp = netdev_priv(dev);
6850 struct pci_dev *pdev = tp->pci_dev;
6851 struct rtl8169_counters *counters = tp->counters;
6854 pm_runtime_get_noresume(&pdev->dev);
6856 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6857 rtl8169_rx_missed(dev);
6860 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6861 stats->rx_packets = tp->rx_stats.packets;
6862 stats->rx_bytes = tp->rx_stats.bytes;
6863 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6866 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6867 stats->tx_packets = tp->tx_stats.packets;
6868 stats->tx_bytes = tp->tx_stats.bytes;
6869 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6871 stats->rx_dropped = dev->stats.rx_dropped;
6872 stats->tx_dropped = dev->stats.tx_dropped;
6873 stats->rx_length_errors = dev->stats.rx_length_errors;
6874 stats->rx_errors = dev->stats.rx_errors;
6875 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6876 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6877 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6878 stats->multicast = dev->stats.multicast;
6881 * Fetch additonal counter values missing in stats collected by driver
6882 * from tally counters.
6884 if (pm_runtime_active(&pdev->dev))
6885 rtl8169_update_counters(tp);
6888 * Subtract values fetched during initalization.
6889 * See rtl8169_init_counter_offsets for a description why we do that.
6891 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6892 le64_to_cpu(tp->tc_offset.tx_errors);
6893 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6894 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6895 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6896 le16_to_cpu(tp->tc_offset.tx_aborted);
6898 pm_runtime_put_noidle(&pdev->dev);
6901 static void rtl8169_net_suspend(struct net_device *dev)
6903 struct rtl8169_private *tp = netdev_priv(dev);
6905 if (!netif_running(dev))
6908 phy_stop(dev->phydev);
6909 netif_device_detach(dev);
6910 netif_stop_queue(dev);
6913 napi_disable(&tp->napi);
6914 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6915 rtl_unlock_work(tp);
6917 rtl_pll_power_down(tp);
6922 static int rtl8169_suspend(struct device *device)
6924 struct pci_dev *pdev = to_pci_dev(device);
6925 struct net_device *dev = pci_get_drvdata(pdev);
6927 rtl8169_net_suspend(dev);
6932 static void __rtl8169_resume(struct net_device *dev)
6934 struct rtl8169_private *tp = netdev_priv(dev);
6936 netif_device_attach(dev);
6938 rtl_pll_power_up(tp);
6939 rtl8169_init_phy(dev, tp);
6941 phy_start(tp->dev->phydev);
6944 napi_enable(&tp->napi);
6945 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6946 rtl_unlock_work(tp);
6948 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6951 static int rtl8169_resume(struct device *device)
6953 struct pci_dev *pdev = to_pci_dev(device);
6954 struct net_device *dev = pci_get_drvdata(pdev);
6956 if (netif_running(dev))
6957 __rtl8169_resume(dev);
6962 static int rtl8169_runtime_suspend(struct device *device)
6964 struct pci_dev *pdev = to_pci_dev(device);
6965 struct net_device *dev = pci_get_drvdata(pdev);
6966 struct rtl8169_private *tp = netdev_priv(dev);
6968 if (!tp->TxDescArray)
6972 __rtl8169_set_wol(tp, WAKE_ANY);
6973 rtl_unlock_work(tp);
6975 rtl8169_net_suspend(dev);
6977 /* Update counters before going runtime suspend */
6978 rtl8169_rx_missed(dev);
6979 rtl8169_update_counters(tp);
6984 static int rtl8169_runtime_resume(struct device *device)
6986 struct pci_dev *pdev = to_pci_dev(device);
6987 struct net_device *dev = pci_get_drvdata(pdev);
6988 struct rtl8169_private *tp = netdev_priv(dev);
6989 rtl_rar_set(tp, dev->dev_addr);
6991 if (!tp->TxDescArray)
6995 __rtl8169_set_wol(tp, tp->saved_wolopts);
6996 rtl_unlock_work(tp);
6998 __rtl8169_resume(dev);
7003 static int rtl8169_runtime_idle(struct device *device)
7005 struct pci_dev *pdev = to_pci_dev(device);
7006 struct net_device *dev = pci_get_drvdata(pdev);
7008 if (!netif_running(dev) || !netif_carrier_ok(dev))
7009 pm_schedule_suspend(device, 10000);
7014 static const struct dev_pm_ops rtl8169_pm_ops = {
7015 .suspend = rtl8169_suspend,
7016 .resume = rtl8169_resume,
7017 .freeze = rtl8169_suspend,
7018 .thaw = rtl8169_resume,
7019 .poweroff = rtl8169_suspend,
7020 .restore = rtl8169_resume,
7021 .runtime_suspend = rtl8169_runtime_suspend,
7022 .runtime_resume = rtl8169_runtime_resume,
7023 .runtime_idle = rtl8169_runtime_idle,
7026 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7028 #else /* !CONFIG_PM */
7030 #define RTL8169_PM_OPS NULL
7032 #endif /* !CONFIG_PM */
7034 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7036 /* WoL fails with 8168b when the receiver is disabled. */
7037 switch (tp->mac_version) {
7038 case RTL_GIGA_MAC_VER_11:
7039 case RTL_GIGA_MAC_VER_12:
7040 case RTL_GIGA_MAC_VER_17:
7041 pci_clear_master(tp->pci_dev);
7043 RTL_W8(tp, ChipCmd, CmdRxEnb);
7045 RTL_R8(tp, ChipCmd);
7052 static void rtl_shutdown(struct pci_dev *pdev)
7054 struct net_device *dev = pci_get_drvdata(pdev);
7055 struct rtl8169_private *tp = netdev_priv(dev);
7057 rtl8169_net_suspend(dev);
7059 /* Restore original MAC address */
7060 rtl_rar_set(tp, dev->perm_addr);
7062 rtl8169_hw_reset(tp);
7064 if (system_state == SYSTEM_POWER_OFF) {
7065 if (tp->saved_wolopts) {
7066 rtl_wol_suspend_quirk(tp);
7067 rtl_wol_shutdown_quirk(tp);
7070 pci_wake_from_d3(pdev, true);
7071 pci_set_power_state(pdev, PCI_D3hot);
7075 static void rtl_remove_one(struct pci_dev *pdev)
7077 struct net_device *dev = pci_get_drvdata(pdev);
7078 struct rtl8169_private *tp = netdev_priv(dev);
7080 if (r8168_check_dash(tp))
7081 rtl8168_driver_stop(tp);
7083 netif_napi_del(&tp->napi);
7085 unregister_netdev(dev);
7086 mdiobus_unregister(tp->mii_bus);
7088 rtl_release_firmware(tp);
7090 if (pci_dev_run_wake(pdev))
7091 pm_runtime_get_noresume(&pdev->dev);
7093 /* restore original MAC address */
7094 rtl_rar_set(tp, dev->perm_addr);
7097 static const struct net_device_ops rtl_netdev_ops = {
7098 .ndo_open = rtl_open,
7099 .ndo_stop = rtl8169_close,
7100 .ndo_get_stats64 = rtl8169_get_stats64,
7101 .ndo_start_xmit = rtl8169_start_xmit,
7102 .ndo_tx_timeout = rtl8169_tx_timeout,
7103 .ndo_validate_addr = eth_validate_addr,
7104 .ndo_change_mtu = rtl8169_change_mtu,
7105 .ndo_fix_features = rtl8169_fix_features,
7106 .ndo_set_features = rtl8169_set_features,
7107 .ndo_set_mac_address = rtl_set_mac_address,
7108 .ndo_do_ioctl = rtl8169_ioctl,
7109 .ndo_set_rx_mode = rtl_set_rx_mode,
7110 #ifdef CONFIG_NET_POLL_CONTROLLER
7111 .ndo_poll_controller = rtl8169_netpoll,
7116 static const struct rtl_cfg_info {
7117 void (*hw_start)(struct rtl8169_private *tp);
7119 unsigned int has_gmii:1;
7120 const struct rtl_coalesce_info *coalesce_info;
7122 } rtl_cfg_infos [] = {
7124 .hw_start = rtl_hw_start_8169,
7125 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7127 .coalesce_info = rtl_coalesce_info_8169,
7128 .default_ver = RTL_GIGA_MAC_VER_01,
7131 .hw_start = rtl_hw_start_8168,
7132 .event_slow = SYSErr | LinkChg | RxOverflow,
7134 .coalesce_info = rtl_coalesce_info_8168_8136,
7135 .default_ver = RTL_GIGA_MAC_VER_11,
7138 .hw_start = rtl_hw_start_8101,
7139 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7141 .coalesce_info = rtl_coalesce_info_8168_8136,
7142 .default_ver = RTL_GIGA_MAC_VER_13,
7146 static int rtl_alloc_irq(struct rtl8169_private *tp)
7150 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7151 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7152 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7153 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7154 flags = PCI_IRQ_LEGACY;
7156 flags = PCI_IRQ_ALL_TYPES;
7159 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7162 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7164 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7167 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7169 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7172 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7174 struct rtl8169_private *tp = mii_bus->priv;
7179 return rtl_readphy(tp, phyreg);
7182 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7183 int phyreg, u16 val)
7185 struct rtl8169_private *tp = mii_bus->priv;
7190 rtl_writephy(tp, phyreg, val);
7195 static int r8169_mdio_register(struct rtl8169_private *tp)
7197 struct pci_dev *pdev = tp->pci_dev;
7198 struct phy_device *phydev;
7199 struct mii_bus *new_bus;
7202 new_bus = devm_mdiobus_alloc(&pdev->dev);
7206 new_bus->name = "r8169";
7208 new_bus->parent = &pdev->dev;
7209 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7210 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7211 PCI_DEVID(pdev->bus->number, pdev->devfn));
7213 new_bus->read = r8169_mdio_read_reg;
7214 new_bus->write = r8169_mdio_write_reg;
7216 ret = mdiobus_register(new_bus);
7220 phydev = mdiobus_get_phy(new_bus, 0);
7222 mdiobus_unregister(new_bus);
7226 /* PHY will be woken up in rtl_open() */
7227 phy_suspend(phydev);
7229 tp->mii_bus = new_bus;
7234 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7238 tp->ocp_base = OCP_STD_PHY_BASE;
7240 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7242 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7245 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7248 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7250 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7252 data = r8168_mac_ocp_read(tp, 0xe8de);
7254 r8168_mac_ocp_write(tp, 0xe8de, data);
7256 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7259 data = r8168_mac_ocp_read(tp, 0xe8de);
7261 r8168_mac_ocp_write(tp, 0xe8de, data);
7263 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7267 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7269 rtl8168ep_stop_cmac(tp);
7270 rtl_hw_init_8168g(tp);
7273 static void rtl_hw_initialize(struct rtl8169_private *tp)
7275 switch (tp->mac_version) {
7276 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7277 rtl_hw_init_8168g(tp);
7279 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7280 rtl_hw_init_8168ep(tp);
7287 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7289 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7290 struct rtl8169_private *tp;
7291 struct net_device *dev;
7292 int chipset, region, i;
7295 if (netif_msg_drv(&debug)) {
7296 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7297 MODULENAME, RTL8169_VERSION);
7300 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7304 SET_NETDEV_DEV(dev, &pdev->dev);
7305 dev->netdev_ops = &rtl_netdev_ops;
7306 tp = netdev_priv(dev);
7309 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7310 tp->supports_gmii = cfg->has_gmii;
7312 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7313 rc = pcim_enable_device(pdev);
7315 dev_err(&pdev->dev, "enable failure\n");
7319 if (pcim_set_mwi(pdev) < 0)
7320 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7322 /* use first MMIO region */
7323 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7325 dev_err(&pdev->dev, "no MMIO resource found\n");
7329 /* check for weird/broken PCI region reporting */
7330 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7331 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7335 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7337 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7341 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7343 if (!pci_is_pcie(pdev))
7344 dev_info(&pdev->dev, "not PCI Express\n");
7346 /* Identify chip attached to board */
7347 rtl8169_get_mac_version(tp, cfg->default_ver);
7349 if (rtl_tbi_enabled(tp)) {
7350 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7354 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7356 if ((sizeof(dma_addr_t) > 4) &&
7357 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7358 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7359 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7360 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7362 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7363 if (!pci_is_pcie(pdev))
7364 tp->cp_cmd |= PCIDAC;
7365 dev->features |= NETIF_F_HIGHDMA;
7367 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7369 dev_err(&pdev->dev, "DMA configuration failed\n");
7376 rtl_irq_disable(tp);
7378 rtl_hw_initialize(tp);
7382 rtl_ack_events(tp, 0xffff);
7384 pci_set_master(pdev);
7386 rtl_init_mdio_ops(tp);
7387 rtl_init_jumbo_ops(tp);
7389 rtl8169_print_mac_version(tp);
7391 chipset = tp->mac_version;
7393 rc = rtl_alloc_irq(tp);
7395 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7399 tp->saved_wolopts = __rtl8169_get_wol(tp);
7401 mutex_init(&tp->wk.mutex);
7402 u64_stats_init(&tp->rx_stats.syncp);
7403 u64_stats_init(&tp->tx_stats.syncp);
7405 /* Get MAC address */
7406 switch (tp->mac_version) {
7407 u8 mac_addr[ETH_ALEN] __aligned(4);
7408 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7409 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7410 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7411 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7413 if (is_valid_ether_addr(mac_addr))
7414 rtl_rar_set(tp, mac_addr);
7419 for (i = 0; i < ETH_ALEN; i++)
7420 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7422 dev->ethtool_ops = &rtl8169_ethtool_ops;
7423 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7425 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7427 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7428 * properly for all devices */
7429 dev->features |= NETIF_F_RXCSUM |
7430 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7432 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7433 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7434 NETIF_F_HW_VLAN_CTAG_RX;
7435 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7437 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7439 tp->cp_cmd |= RxChkSum | RxVlan;
7442 * Pretend we are using VLANs; This bypasses a nasty bug where
7443 * Interrupts stop flowing on high load on 8110SCd controllers.
7445 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7446 /* Disallow toggling */
7447 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7449 switch (rtl_chip_infos[chipset].txd_version) {
7451 tp->tso_csum = rtl8169_tso_csum_v1;
7454 tp->tso_csum = rtl8169_tso_csum_v2;
7455 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7461 dev->hw_features |= NETIF_F_RXALL;
7462 dev->hw_features |= NETIF_F_RXFCS;
7464 /* MTU range: 60 - hw-specific max */
7465 dev->min_mtu = ETH_ZLEN;
7466 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7468 tp->hw_start = cfg->hw_start;
7469 tp->event_slow = cfg->event_slow;
7470 tp->coalesce_info = cfg->coalesce_info;
7472 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7474 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7475 &tp->counters_phys_addr,
7480 pci_set_drvdata(pdev, dev);
7482 rc = r8169_mdio_register(tp);
7486 /* chip gets powered up in rtl_open() */
7487 rtl_pll_power_down(tp);
7489 rc = register_netdev(dev);
7491 goto err_mdio_unregister;
7493 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7494 rtl_chip_infos[chipset].name, dev->dev_addr,
7495 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7496 pci_irq_vector(pdev, 0));
7497 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7498 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7499 "tx checksumming: %s]\n",
7500 rtl_chip_infos[chipset].jumbo_max,
7501 tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7504 if (r8168_check_dash(tp))
7505 rtl8168_driver_start(tp);
7507 if (pci_dev_run_wake(pdev))
7508 pm_runtime_put_sync(&pdev->dev);
7512 err_mdio_unregister:
7513 mdiobus_unregister(tp->mii_bus);
7517 static struct pci_driver rtl8169_pci_driver = {
7519 .id_table = rtl8169_pci_tbl,
7520 .probe = rtl_init_one,
7521 .remove = rtl_remove_one,
7522 .shutdown = rtl_shutdown,
7523 .driver.pm = RTL8169_PM_OPS,
7526 module_pci_driver(rtl8169_pci_driver);