drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         RTL_GIGA_MAC_VER_01 = 0,
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE   = 0xff,
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 150         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 151         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 152         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 153         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 154         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 155         /* PCI-E devices. */
 156         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 159         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 160         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 162         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 163         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 165         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 166         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 167         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 168         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 172         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 174         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 175         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 176         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 178         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 180         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 181         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 182         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 183         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 184         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 185         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 186         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 187         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 188         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 189         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 190         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 191         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 192         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 193         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 194         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 195         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 196         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 197         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 198         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 200         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 201 };
 202
 203 enum cfg_version {
 204         RTL_CFG_0 = 0x00,
 205         RTL_CFG_1,
 206         RTL_CFG_2
 207 };
 208
 209 static const struct pci_device_id rtl8169_pci_tbl[] = {
 210         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 212         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 213         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 214         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 215         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 216         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 218         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 219         { PCI_VENDOR_ID_DLINK,  0x4300,
 220                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 221         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 222         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 223         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 224         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 225         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 226                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 227         { 0x0001,                               0x8168,
 228                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 229         {}
 230 };
 231
 232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 233
 234 static struct {
 235         u32 msg_enable;
 236 } debug = { -1 };
 237
 238 enum rtl_registers {
 239         MAC0            = 0,    /* Ethernet hardware address. */
 240         MAC4            = 4,
 241         MAR0            = 8,    /* Multicast filter. */
 242         CounterAddrLow          = 0x10,
 243         CounterAddrHigh         = 0x14,
 244         TxDescStartAddrLow      = 0x20,
 245         TxDescStartAddrHigh     = 0x24,
 246         TxHDescStartAddrLow     = 0x28,
 247         TxHDescStartAddrHigh    = 0x2c,
 248         FLASH           = 0x30,
 249         ERSR            = 0x36,
 250         ChipCmd         = 0x37,
 251         TxPoll          = 0x38,
 252         IntrMask        = 0x3c,
 253         IntrStatus      = 0x3e,
 254
 255         TxConfig        = 0x40,
 256 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 257 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 258
 259         RxConfig        = 0x44,
 260 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 261 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 262 #define RXCFG_FIFO_SHIFT                13
 263                                         /* No threshold before first PCI xfer */
 264 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 265 #define RX_EARLY_OFF                    (1 << 11)
 266 #define RXCFG_DMA_SHIFT                 8
 267                                         /* Unlimited maximum PCI burst. */
 268 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 269
 270         RxMissed        = 0x4c,
 271         Cfg9346         = 0x50,
 272         Config0         = 0x51,
 273         Config1         = 0x52,
 274         Config2         = 0x53,
 275 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 276
 277         Config3         = 0x54,
 278         Config4         = 0x55,
 279         Config5         = 0x56,
 280         MultiIntr       = 0x5c,
 281         PHYAR           = 0x60,
 282         PHYstatus       = 0x6c,
 283         RxMaxSize       = 0xda,
 284         CPlusCmd        = 0xe0,
 285         IntrMitigate    = 0xe2,
 286
 287 #define RTL_COALESCE_MASK       0x0f
 288 #define RTL_COALESCE_SHIFT      4
 289 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 290 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 291
 292         RxDescAddrLow   = 0xe4,
 293         RxDescAddrHigh  = 0xe8,
 294         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 295
 296 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 297
 298         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 299
 300 #define TxPacketMax     (8064 >> 7)
 301 #define EarlySize       0x27
 302
 303         FuncEvent       = 0xf0,
 304         FuncEventMask   = 0xf4,
 305         FuncPresetState = 0xf8,
 306         IBCR0           = 0xf8,
 307         IBCR2           = 0xf9,
 308         IBIMR0          = 0xfa,
 309         IBISR0          = 0xfb,
 310         FuncForceEvent  = 0xfc,
 311 };
 312
 313 enum rtl8168_8101_registers {
 314         CSIDR                   = 0x64,
 315         CSIAR                   = 0x68,
 316 #define CSIAR_FLAG                      0x80000000
 317 #define CSIAR_WRITE_CMD                 0x80000000
 318 #define CSIAR_BYTE_ENABLE               0x0000f000
 319 #define CSIAR_ADDR_MASK                 0x00000fff
 320         PMCH                    = 0x6f,
 321         EPHYAR                  = 0x80,
 322 #define EPHYAR_FLAG                     0x80000000
 323 #define EPHYAR_WRITE_CMD                0x80000000
 324 #define EPHYAR_REG_MASK                 0x1f
 325 #define EPHYAR_REG_SHIFT                16
 326 #define EPHYAR_DATA_MASK                0xffff
 327         DLLPR                   = 0xd0,
 328 #define PFM_EN                          (1 << 6)
 329 #define TX_10M_PS_EN                    (1 << 7)
 330         DBG_REG                 = 0xd1,
 331 #define FIX_NAK_1                       (1 << 4)
 332 #define FIX_NAK_2                       (1 << 3)
 333         TWSI                    = 0xd2,
 334         MCU                     = 0xd3,
 335 #define NOW_IS_OOB                      (1 << 7)
 336 #define TX_EMPTY                        (1 << 5)
 337 #define RX_EMPTY                        (1 << 4)
 338 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 339 #define EN_NDP                          (1 << 3)
 340 #define EN_OOB_RESET                    (1 << 2)
 341 #define LINK_LIST_RDY                   (1 << 1)
 342         EFUSEAR                 = 0xdc,
 343 #define EFUSEAR_FLAG                    0x80000000
 344 #define EFUSEAR_WRITE_CMD               0x80000000
 345 #define EFUSEAR_READ_CMD                0x00000000
 346 #define EFUSEAR_REG_MASK                0x03ff
 347 #define EFUSEAR_REG_SHIFT               8
 348 #define EFUSEAR_DATA_MASK               0xff
 349         MISC_1                  = 0xf2,
 350 #define PFM_D3COLD_EN                   (1 << 6)
 351 };
 352
 353 enum rtl8168_registers {
 354         LED_FREQ                = 0x1a,
 355         EEE_LED                 = 0x1b,
 356         ERIDR                   = 0x70,
 357         ERIAR                   = 0x74,
 358 #define ERIAR_FLAG                      0x80000000
 359 #define ERIAR_WRITE_CMD                 0x80000000
 360 #define ERIAR_READ_CMD                  0x00000000
 361 #define ERIAR_ADDR_BYTE_ALIGN           4
 362 #define ERIAR_TYPE_SHIFT                16
 363 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 367 #define ERIAR_MASK_SHIFT                12
 368 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 372 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 373         EPHY_RXER_NUM           = 0x7c,
 374         OCPDR                   = 0xb0, /* OCP GPHY access */
 375 #define OCPDR_WRITE_CMD                 0x80000000
 376 #define OCPDR_READ_CMD                  0x00000000
 377 #define OCPDR_REG_MASK                  0x7f
 378 #define OCPDR_GPHY_REG_SHIFT            16
 379 #define OCPDR_DATA_MASK                 0xffff
 380         OCPAR                   = 0xb4,
 381 #define OCPAR_FLAG                      0x80000000
 382 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 383 #define OCPAR_GPHY_READ_CMD             0x0000f060
 384         GPHY_OCP                = 0xb8,
 385         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 386         MISC                    = 0xf0, /* 8168e only. */
 387 #define TXPLA_RST                       (1 << 29)
 388 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 389 #define PWM_EN                          (1 << 22)
 390 #define RXDV_GATED_EN                   (1 << 19)
 391 #define EARLY_TALLY_EN                  (1 << 16)
 392 };
 393
 394 enum rtl_register_content {
 395         /* InterruptStatusBits */
 396         SYSErr          = 0x8000,
 397         PCSTimeout      = 0x4000,
 398         SWInt           = 0x0100,
 399         TxDescUnavail   = 0x0080,
 400         RxFIFOOver      = 0x0040,
 401         LinkChg         = 0x0020,
 402         RxOverflow      = 0x0010,
 403         TxErr           = 0x0008,
 404         TxOK            = 0x0004,
 405         RxErr           = 0x0002,
 406         RxOK            = 0x0001,
 407
 408         /* RxStatusDesc */
 409         RxBOVF  = (1 << 24),
 410         RxFOVF  = (1 << 23),
 411         RxRWT   = (1 << 22),
 412         RxRES   = (1 << 21),
 413         RxRUNT  = (1 << 20),
 414         RxCRC   = (1 << 19),
 415
 416         /* ChipCmdBits */
 417         StopReq         = 0x80,
 418         CmdReset        = 0x10,
 419         CmdRxEnb        = 0x08,
 420         CmdTxEnb        = 0x04,
 421         RxBufEmpty      = 0x01,
 422
 423         /* TXPoll register p.5 */
 424         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 425         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 426         FSWInt          = 0x01,         /* Forced software interrupt */
 427
 428         /* Cfg9346Bits */
 429         Cfg9346_Lock    = 0x00,
 430         Cfg9346_Unlock  = 0xc0,
 431
 432         /* rx_mode_bits */
 433         AcceptErr       = 0x20,
 434         AcceptRunt      = 0x10,
 435         AcceptBroadcast = 0x08,
 436         AcceptMulticast = 0x04,
 437         AcceptMyPhys    = 0x02,
 438         AcceptAllPhys   = 0x01,
 439 #define RX_CONFIG_ACCEPT_MASK           0x3f
 440
 441         /* TxConfigBits */
 442         TxInterFrameGapShift = 24,
 443         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 444
 445         /* Config1 register p.24 */
 446         LEDS1           = (1 << 7),
 447         LEDS0           = (1 << 6),
 448         Speed_down      = (1 << 4),
 449         MEMMAP          = (1 << 3),
 450         IOMAP           = (1 << 2),
 451         VPD             = (1 << 1),
 452         PMEnable        = (1 << 0),     /* Power Management Enable */
 453
 454         /* Config2 register p. 25 */
 455         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 456         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 457         PCI_Clock_66MHz = 0x01,
 458         PCI_Clock_33MHz = 0x00,
 459
 460         /* Config3 register p.25 */
 461         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 462         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 463         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 464         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 465         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config4 register */
 468         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 469
 470         /* Config5 register p.27 */
 471         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 472         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 473         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 474         Spi_en          = (1 << 3),
 475         LanWake         = (1 << 1),     /* LanWake enable/disable */
 476         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 477         ASPM_en         = (1 << 0),     /* ASPM enable */
 478
 479         /* CPlusCmd p.31 */
 480         EnableBist      = (1 << 15),    // 8168 8101
 481         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 482         Normal_mode     = (1 << 13),    // unused
 483         Force_half_dup  = (1 << 12),    // 8168 8101
 484         Force_rxflow_en = (1 << 11),    // 8168 8101
 485         Force_txflow_en = (1 << 10),    // 8168 8101
 486         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 487         ASF             = (1 << 8),     // 8168 8101
 488         PktCntrDisable  = (1 << 7),     // 8168 8101
 489         Mac_dbgo_sel    = 0x001c,       // 8168
 490         RxVlan          = (1 << 6),
 491         RxChkSum        = (1 << 5),
 492         PCIDAC          = (1 << 4),
 493         PCIMulRW        = (1 << 3),
 494 #define INTT_MASK       GENMASK(1, 0)
 495
 496         /* rtl8169_PHYstatus */
 497         TBI_Enable      = 0x80,
 498         TxFlowCtrl      = 0x40,
 499         RxFlowCtrl      = 0x20,
 500         _1000bpsF       = 0x10,
 501         _100bps         = 0x08,
 502         _10bps          = 0x04,
 503         LinkStatus      = 0x02,
 504         FullDup         = 0x01,
 505
 506         /* _TBICSRBit */
 507         TBILinkOK       = 0x02000000,
 508
 509         /* ResetCounterCommand */
 510         CounterReset    = 0x1,
 511
 512         /* DumpCounterCommand */
 513         CounterDump     = 0x8,
 514
 515         /* magic enable v2 */
 516         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 517 };
 518
 519 enum rtl_desc_bit {
 520         /* First doubleword. */
 521         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 522         RingEnd         = (1 << 30), /* End of descriptor ring */
 523         FirstFrag       = (1 << 29), /* First segment of a packet */
 524         LastFrag        = (1 << 28), /* Final segment of a packet */
 525 };
 526
 527 /* Generic case. */
 528 enum rtl_tx_desc_bit {
 529         /* First doubleword. */
 530         TD_LSO          = (1 << 27),            /* Large Send Offload */
 531 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 532
 533         /* Second doubleword. */
 534         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 535 };
 536
 537 /* 8169, 8168b and 810x except 8102e. */
 538 enum rtl_tx_desc_bit_0 {
 539         /* First doubleword. */
 540 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 541         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 542         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 543         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 544 };
 545
 546 /* 8102e, 8168c and beyond. */
 547 enum rtl_tx_desc_bit_1 {
 548         /* First doubleword. */
 549         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 550         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 551 #define GTTCPHO_SHIFT                   18
 552 #define GTTCPHO_MAX                     0x7fU
 553
 554         /* Second doubleword. */
 555 #define TCPHO_SHIFT                     18
 556 #define TCPHO_MAX                       0x3ffU
 557 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 558         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 559         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 560         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 561         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 562 };
 563
 564 enum rtl_rx_desc_bit {
 565         /* Rx private */
 566         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 567         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 568
 569 #define RxProtoUDP      (PID1)
 570 #define RxProtoTCP      (PID0)
 571 #define RxProtoIP       (PID1 | PID0)
 572 #define RxProtoMask     RxProtoIP
 573
 574         IPFail          = (1 << 16), /* IP checksum failed */
 575         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 576         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 577         RxVlanTag       = (1 << 16), /* VLAN tag available */
 578 };
 579
 580 #define RsvdMask        0x3fffc000
 581 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 582
 583 struct TxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct RxDesc {
 590         __le32 opts1;
 591         __le32 opts2;
 592         __le64 addr;
 593 };
 594
 595 struct ring_info {
 596         struct sk_buff  *skb;
 597         u32             len;
 598 };
 599
 600 struct rtl8169_counters {
 601         __le64  tx_packets;
 602         __le64  rx_packets;
 603         __le64  tx_errors;
 604         __le32  rx_errors;
 605         __le16  rx_missed;
 606         __le16  align_errors;
 607         __le32  tx_one_collision;
 608         __le32  tx_multi_collision;
 609         __le64  rx_unicast;
 610         __le64  rx_broadcast;
 611         __le32  rx_multicast;
 612         __le16  tx_aborted;
 613         __le16  tx_underun;
 614 };
 615
 616 struct rtl8169_tc_offsets {
 617         bool    inited;
 618         __le64  tx_errors;
 619         __le32  tx_multi_collision;
 620         __le16  tx_aborted;
 621 };
 622
 623 enum rtl_flag {
 624         RTL_FLAG_TASK_ENABLED = 0,
 625         RTL_FLAG_TASK_RESET_PENDING,
 626         RTL_FLAG_MAX
 627 };
 628
 629 struct rtl8169_stats {
 630         u64                     packets;
 631         u64                     bytes;
 632         struct u64_stats_sync   syncp;
 633 };
 634
 635 struct rtl8169_private {
 636         void __iomem *mmio_addr;        /* memory map physical address */
 637         struct pci_dev *pci_dev;
 638         struct net_device *dev;
 639         struct phy_device *phydev;
 640         struct napi_struct napi;
 641         u32 msg_enable;
 642         u16 mac_version;
 643         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 644         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 645         u32 dirty_tx;
 646         struct rtl8169_stats rx_stats;
 647         struct rtl8169_stats tx_stats;
 648         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 649         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 650         dma_addr_t TxPhyAddr;
 651         dma_addr_t RxPhyAddr;
 652         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 653         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 654         u16 cp_cmd;
 655
 656         u16 irq_mask;
 657         const struct rtl_coalesce_info *coalesce_info;
 658         struct clk *clk;
 659
 660         struct mdio_ops {
 661                 void (*write)(struct rtl8169_private *, int, int);
 662                 int (*read)(struct rtl8169_private *, int);
 663         } mdio_ops;
 664
 665         struct jumbo_ops {
 666                 void (*enable)(struct rtl8169_private *);
 667                 void (*disable)(struct rtl8169_private *);
 668         } jumbo_ops;
 669
 670         void (*hw_start)(struct rtl8169_private *tp);
 671         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 672
 673         struct {
 674                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 675                 struct mutex mutex;
 676                 struct work_struct work;
 677         } wk;
 678
 679         unsigned irq_enabled:1;
 680         unsigned supports_gmii:1;
 681         dma_addr_t counters_phys_addr;
 682         struct rtl8169_counters *counters;
 683         struct rtl8169_tc_offsets tc_offset;
 684         u32 saved_wolopts;
 685
 686         const char *fw_name;
 687         struct rtl_fw {
 688                 const struct firmware *fw;
 689
 690 #define RTL_VER_SIZE            32
 691
 692                 char version[RTL_VER_SIZE];
 693
 694                 struct rtl_fw_phy_action {
 695                         __le32 *code;
 696                         size_t size;
 697                 } phy_action;
 698         } *rtl_fw;
 699
 700         u32 ocp_base;
 701 };
 702
 703 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 704
 705 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 706 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 707 module_param_named(debug, debug.msg_enable, int, 0);
 708 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 709 MODULE_SOFTDEP("pre: realtek");
 710 MODULE_LICENSE("GPL");
 711 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 712 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 717 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 719 MODULE_FIRMWARE(FIRMWARE_8402_1);
 720 MODULE_FIRMWARE(FIRMWARE_8411_1);
 721 MODULE_FIRMWARE(FIRMWARE_8411_2);
 722 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 723 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 725 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 726 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 727 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 728 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 729 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 730
 731 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 732 {
 733         return &tp->pci_dev->dev;
 734 }
 735
 736 static void rtl_lock_work(struct rtl8169_private *tp)
 737 {
 738         mutex_lock(&tp->wk.mutex);
 739 }
 740
 741 static void rtl_unlock_work(struct rtl8169_private *tp)
 742 {
 743         mutex_unlock(&tp->wk.mutex);
 744 }
 745
 746 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 747 {
 748         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 749 }
 750
 751 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 752 {
 753         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 754 }
 755
 756 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 757 {
 758         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 759                                            PCI_EXP_DEVCTL_READRQ, force);
 760 }
 761
 762 struct rtl_cond {
 763         bool (*check)(struct rtl8169_private *);
 764         const char *msg;
 765 };
 766
 767 static void rtl_udelay(unsigned int d)
 768 {
 769         udelay(d);
 770 }
 771
 772 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 773                           void (*delay)(unsigned int), unsigned int d, int n,
 774                           bool high)
 775 {
 776         int i;
 777
 778         for (i = 0; i < n; i++) {
 779                 if (c->check(tp) == high)
 780                         return true;
 781                 delay(d);
 782         }
 783         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 784                   c->msg, !high, n, d);
 785         return false;
 786 }
 787
 788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 789                                       const struct rtl_cond *c,
 790                                       unsigned int d, int n)
 791 {
 792         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 793 }
 794
 795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 796                                      const struct rtl_cond *c,
 797                                      unsigned int d, int n)
 798 {
 799         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 800 }
 801
 802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 803                                       const struct rtl_cond *c,
 804                                       unsigned int d, int n)
 805 {
 806         return rtl_loop_wait(tp, c, msleep, d, n, true);
 807 }
 808
 809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 810                                      const struct rtl_cond *c,
 811                                      unsigned int d, int n)
 812 {
 813         return rtl_loop_wait(tp, c, msleep, d, n, false);
 814 }
 815
 816 #define DECLARE_RTL_COND(name)                          \
 817 static bool name ## _check(struct rtl8169_private *);   \
 818                                                         \
 819 static const struct rtl_cond name = {                   \
 820         .check  = name ## _check,                       \
 821         .msg    = #name                                 \
 822 };                                                      \
 823                                                         \
 824 static bool name ## _check(struct rtl8169_private *tp)
 825
 826 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 827 {
 828         if (reg & 0xffff0001) {
 829                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 830                 return true;
 831         }
 832         return false;
 833 }
 834
 835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 836 {
 837         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 838 }
 839
 840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 841 {
 842         if (rtl_ocp_reg_failure(tp, reg))
 843                 return;
 844
 845         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 846
 847         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 848 }
 849
 850 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 851 {
 852         if (rtl_ocp_reg_failure(tp, reg))
 853                 return 0;
 854
 855         RTL_W32(tp, GPHY_OCP, reg << 15);
 856
 857         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 858                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 859 }
 860
 861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 862 {
 863         if (rtl_ocp_reg_failure(tp, reg))
 864                 return;
 865
 866         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 867 }
 868
 869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 870 {
 871         if (rtl_ocp_reg_failure(tp, reg))
 872                 return 0;
 873
 874         RTL_W32(tp, OCPDR, reg << 15);
 875
 876         return RTL_R32(tp, OCPDR);
 877 }
 878
 879 #define OCP_STD_PHY_BASE        0xa400
 880
 881 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 882 {
 883         if (reg == 0x1f) {
 884                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 885                 return;
 886         }
 887
 888         if (tp->ocp_base != OCP_STD_PHY_BASE)
 889                 reg -= 0x10;
 890
 891         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 892 }
 893
 894 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 895 {
 896         if (tp->ocp_base != OCP_STD_PHY_BASE)
 897                 reg -= 0x10;
 898
 899         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 900 }
 901
 902 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 903 {
 904         if (reg == 0x1f) {
 905                 tp->ocp_base = value << 4;
 906                 return;
 907         }
 908
 909         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 910 }
 911
 912 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 913 {
 914         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 915 }
 916
 917 DECLARE_RTL_COND(rtl_phyar_cond)
 918 {
 919         return RTL_R32(tp, PHYAR) & 0x80000000;
 920 }
 921
 922 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 923 {
 924         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 925
 926         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 927         /*
 928          * According to hardware specs a 20us delay is required after write
 929          * complete indication, but before sending next command.
 930          */
 931         udelay(20);
 932 }
 933
 934 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 935 {
 936         int value;
 937
 938         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 939
 940         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 941                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 942
 943         /*
 944          * According to hardware specs a 20us delay is required after read
 945          * complete indication, but before sending next command.
 946          */
 947         udelay(20);
 948
 949         return value;
 950 }
 951
 952 DECLARE_RTL_COND(rtl_ocpar_cond)
 953 {
 954         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 955 }
 956
 957 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 958 {
 959         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 960         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 961         RTL_W32(tp, EPHY_RXER_NUM, 0);
 962
 963         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 964 }
 965
 966 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 967 {
 968         r8168dp_1_mdio_access(tp, reg,
 969                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 970 }
 971
 972 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 973 {
 974         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 975
 976         mdelay(1);
 977         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 978         RTL_W32(tp, EPHY_RXER_NUM, 0);
 979
 980         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 981                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 982 }
 983
 984 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 985
 986 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 987 {
 988         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 989 }
 990
 991 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 992 {
 993         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 994 }
 995
 996 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 997 {
 998         r8168dp_2_mdio_start(tp);
 999
1000         r8169_mdio_write(tp, reg, value);
1001
1002         r8168dp_2_mdio_stop(tp);
1003 }
1004
1005 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006 {
1007         int value;
1008
1009         r8168dp_2_mdio_start(tp);
1010
1011         value = r8169_mdio_read(tp, reg);
1012
1013         r8168dp_2_mdio_stop(tp);
1014
1015         return value;
1016 }
1017
1018 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1019 {
1020         tp->mdio_ops.write(tp, location, val);
1021 }
1022
1023 static int rtl_readphy(struct rtl8169_private *tp, int location)
1024 {
1025         return tp->mdio_ops.read(tp, location);
1026 }
1027
1028 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1029 {
1030         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1031 }
1032
1033 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 {
1035         int val;
1036
1037         val = rtl_readphy(tp, reg_addr);
1038         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1039 }
1040
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1042 {
1043         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044 }
1045
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047 {
1048         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053         udelay(10);
1054 }
1055
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057 {
1058         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062 }
1063
1064 DECLARE_RTL_COND(rtl_eriar_cond)
1065 {
1066         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1067 }
1068
1069 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1070                            u32 val, int type)
1071 {
1072         BUG_ON((addr & 3) || (mask == 0));
1073         RTL_W32(tp, ERIDR, val);
1074         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1075
1076         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1077 }
1078
1079 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1080                           u32 val)
1081 {
1082         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1083 }
1084
1085 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1086 {
1087         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1088
1089         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1090                 RTL_R32(tp, ERIDR) : ~0;
1091 }
1092
1093 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1094 {
1095         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1096 }
1097
1098 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1099                          u32 m)
1100 {
1101         u32 val;
1102
1103         val = rtl_eri_read(tp, addr);
1104         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1105 }
1106
1107 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1108                              u32 p)
1109 {
1110         rtl_w0w1_eri(tp, addr, mask, p, 0);
1111 }
1112
1113 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1114                                u32 m)
1115 {
1116         rtl_w0w1_eri(tp, addr, mask, 0, m);
1117 }
1118
1119 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1120 {
1121         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1122         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1123                 RTL_R32(tp, OCPDR) : ~0;
1124 }
1125
1126 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1127 {
1128         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1129 }
1130
1131 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1132                               u32 data)
1133 {
1134         RTL_W32(tp, OCPDR, data);
1135         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1136         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1137 }
1138
1139 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1140                               u32 data)
1141 {
1142         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1143                        data, ERIAR_OOB);
1144 }
1145
1146 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1147 {
1148         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1149
1150         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1151 }
1152
1153 #define OOB_CMD_RESET           0x00
1154 #define OOB_CMD_DRIVER_START    0x05
1155 #define OOB_CMD_DRIVER_STOP     0x06
1156
1157 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1158 {
1159         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1160 }
1161
1162 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1163 {
1164         u16 reg;
1165
1166         reg = rtl8168_get_ocp_reg(tp);
1167
1168         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1169 }
1170
1171 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1172 {
1173         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1174 }
1175
1176 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1177 {
1178         return RTL_R8(tp, IBISR0) & 0x20;
1179 }
1180
1181 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1182 {
1183         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1184         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1185         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1186         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1187 }
1188
1189 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1190 {
1191         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1192         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1193 }
1194
1195 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1196 {
1197         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1198         r8168ep_ocp_write(tp, 0x01, 0x30,
1199                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1200         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1201 }
1202
1203 static void rtl8168_driver_start(struct rtl8169_private *tp)
1204 {
1205         switch (tp->mac_version) {
1206         case RTL_GIGA_MAC_VER_27:
1207         case RTL_GIGA_MAC_VER_28:
1208         case RTL_GIGA_MAC_VER_31:
1209                 rtl8168dp_driver_start(tp);
1210                 break;
1211         case RTL_GIGA_MAC_VER_49:
1212         case RTL_GIGA_MAC_VER_50:
1213         case RTL_GIGA_MAC_VER_51:
1214                 rtl8168ep_driver_start(tp);
1215                 break;
1216         default:
1217                 BUG();
1218                 break;
1219         }
1220 }
1221
1222 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1223 {
1224         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1225         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1226 }
1227
1228 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1229 {
1230         rtl8168ep_stop_cmac(tp);
1231         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1232         r8168ep_ocp_write(tp, 0x01, 0x30,
1233                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1234         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1235 }
1236
1237 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1238 {
1239         switch (tp->mac_version) {
1240         case RTL_GIGA_MAC_VER_27:
1241         case RTL_GIGA_MAC_VER_28:
1242         case RTL_GIGA_MAC_VER_31:
1243                 rtl8168dp_driver_stop(tp);
1244                 break;
1245         case RTL_GIGA_MAC_VER_49:
1246         case RTL_GIGA_MAC_VER_50:
1247         case RTL_GIGA_MAC_VER_51:
1248                 rtl8168ep_driver_stop(tp);
1249                 break;
1250         default:
1251                 BUG();
1252                 break;
1253         }
1254 }
1255
1256 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1257 {
1258         u16 reg = rtl8168_get_ocp_reg(tp);
1259
1260         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1261 }
1262
1263 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1264 {
1265         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1266 }
1267
1268 static bool r8168_check_dash(struct rtl8169_private *tp)
1269 {
1270         switch (tp->mac_version) {
1271         case RTL_GIGA_MAC_VER_27:
1272         case RTL_GIGA_MAC_VER_28:
1273         case RTL_GIGA_MAC_VER_31:
1274                 return r8168dp_check_dash(tp);
1275         case RTL_GIGA_MAC_VER_49:
1276         case RTL_GIGA_MAC_VER_50:
1277         case RTL_GIGA_MAC_VER_51:
1278                 return r8168ep_check_dash(tp);
1279         default:
1280                 return false;
1281         }
1282 }
1283
1284 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1285 {
1286         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1287         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1288 }
1289
1290 DECLARE_RTL_COND(rtl_efusear_cond)
1291 {
1292         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1293 }
1294
1295 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1296 {
1297         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1298
1299         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1300                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1301 }
1302
1303 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1304 {
1305         RTL_W16(tp, IntrStatus, bits);
1306 }
1307
1308 static void rtl_irq_disable(struct rtl8169_private *tp)
1309 {
1310         RTL_W16(tp, IntrMask, 0);
1311         tp->irq_enabled = 0;
1312 }
1313
1314 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1315 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1316 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1317
1318 static void rtl_irq_enable(struct rtl8169_private *tp)
1319 {
1320         tp->irq_enabled = 1;
1321         RTL_W16(tp, IntrMask, tp->irq_mask);
1322 }
1323
1324 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1325 {
1326         rtl_irq_disable(tp);
1327         rtl_ack_events(tp, 0xffff);
1328         /* PCI commit */
1329         RTL_R8(tp, ChipCmd);
1330 }
1331
1332 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1333 {
1334         struct net_device *dev = tp->dev;
1335         struct phy_device *phydev = tp->phydev;
1336
1337         if (!netif_running(dev))
1338                 return;
1339
1340         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1341             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1342                 if (phydev->speed == SPEED_1000) {
1343                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1344                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1345                 } else if (phydev->speed == SPEED_100) {
1346                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1347                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1348                 } else {
1349                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1350                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1351                 }
1352                 rtl_reset_packet_filter(tp);
1353         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1354                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1355                 if (phydev->speed == SPEED_1000) {
1356                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1357                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1358                 } else {
1359                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1360                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1361                 }
1362         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1363                 if (phydev->speed == SPEED_10) {
1364                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1366                 } else {
1367                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1368                 }
1369         }
1370 }
1371
1372 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1373
1374 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1375 {
1376         struct rtl8169_private *tp = netdev_priv(dev);
1377
1378         rtl_lock_work(tp);
1379         wol->supported = WAKE_ANY;
1380         wol->wolopts = tp->saved_wolopts;
1381         rtl_unlock_work(tp);
1382 }
1383
1384 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1385 {
1386         unsigned int i, tmp;
1387         static const struct {
1388                 u32 opt;
1389                 u16 reg;
1390                 u8  mask;
1391         } cfg[] = {
1392                 { WAKE_PHY,   Config3, LinkUp },
1393                 { WAKE_UCAST, Config5, UWF },
1394                 { WAKE_BCAST, Config5, BWF },
1395                 { WAKE_MCAST, Config5, MWF },
1396                 { WAKE_ANY,   Config5, LanWake },
1397                 { WAKE_MAGIC, Config3, MagicPacket }
1398         };
1399         u8 options;
1400
1401         rtl_unlock_config_regs(tp);
1402
1403         switch (tp->mac_version) {
1404         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1405         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1406                 tmp = ARRAY_SIZE(cfg) - 1;
1407                 if (wolopts & WAKE_MAGIC)
1408                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1409                                          MagicPacket_v2);
1410                 else
1411                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1412                                            MagicPacket_v2);
1413                 break;
1414         default:
1415                 tmp = ARRAY_SIZE(cfg);
1416                 break;
1417         }
1418
1419         for (i = 0; i < tmp; i++) {
1420                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1421                 if (wolopts & cfg[i].opt)
1422                         options |= cfg[i].mask;
1423                 RTL_W8(tp, cfg[i].reg, options);
1424         }
1425
1426         switch (tp->mac_version) {
1427         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1428                 options = RTL_R8(tp, Config1) & ~PMEnable;
1429                 if (wolopts)
1430                         options |= PMEnable;
1431                 RTL_W8(tp, Config1, options);
1432                 break;
1433         default:
1434                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1435                 if (wolopts)
1436                         options |= PME_SIGNAL;
1437                 RTL_W8(tp, Config2, options);
1438                 break;
1439         }
1440
1441         rtl_lock_config_regs(tp);
1442
1443         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1444 }
1445
1446 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1447 {
1448         struct rtl8169_private *tp = netdev_priv(dev);
1449         struct device *d = tp_to_dev(tp);
1450
1451         if (wol->wolopts & ~WAKE_ANY)
1452                 return -EINVAL;
1453
1454         pm_runtime_get_noresume(d);
1455
1456         rtl_lock_work(tp);
1457
1458         tp->saved_wolopts = wol->wolopts;
1459
1460         if (pm_runtime_active(d))
1461                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1462
1463         rtl_unlock_work(tp);
1464
1465         pm_runtime_put_noidle(d);
1466
1467         return 0;
1468 }
1469
1470 static void rtl8169_get_drvinfo(struct net_device *dev,
1471                                 struct ethtool_drvinfo *info)
1472 {
1473         struct rtl8169_private *tp = netdev_priv(dev);
1474         struct rtl_fw *rtl_fw = tp->rtl_fw;
1475
1476         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1477         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1478         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1479         if (rtl_fw)
1480                 strlcpy(info->fw_version, rtl_fw->version,
1481                         sizeof(info->fw_version));
1482 }
1483
1484 static int rtl8169_get_regs_len(struct net_device *dev)
1485 {
1486         return R8169_REGS_SIZE;
1487 }
1488
1489 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1490         netdev_features_t features)
1491 {
1492         struct rtl8169_private *tp = netdev_priv(dev);
1493
1494         if (dev->mtu > TD_MSS_MAX)
1495                 features &= ~NETIF_F_ALL_TSO;
1496
1497         if (dev->mtu > JUMBO_1K &&
1498             tp->mac_version > RTL_GIGA_MAC_VER_06)
1499                 features &= ~NETIF_F_IP_CSUM;
1500
1501         return features;
1502 }
1503
1504 static int rtl8169_set_features(struct net_device *dev,
1505                                 netdev_features_t features)
1506 {
1507         struct rtl8169_private *tp = netdev_priv(dev);
1508         u32 rx_config;
1509
1510         rtl_lock_work(tp);
1511
1512         rx_config = RTL_R32(tp, RxConfig);
1513         if (features & NETIF_F_RXALL)
1514                 rx_config |= (AcceptErr | AcceptRunt);
1515         else
1516                 rx_config &= ~(AcceptErr | AcceptRunt);
1517
1518         RTL_W32(tp, RxConfig, rx_config);
1519
1520         if (features & NETIF_F_RXCSUM)
1521                 tp->cp_cmd |= RxChkSum;
1522         else
1523                 tp->cp_cmd &= ~RxChkSum;
1524
1525         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1526                 tp->cp_cmd |= RxVlan;
1527         else
1528                 tp->cp_cmd &= ~RxVlan;
1529
1530         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1531         RTL_R16(tp, CPlusCmd);
1532
1533         rtl_unlock_work(tp);
1534
1535         return 0;
1536 }
1537
1538 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1539 {
1540         return (skb_vlan_tag_present(skb)) ?
1541                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1542 }
1543
1544 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1545 {
1546         u32 opts2 = le32_to_cpu(desc->opts2);
1547
1548         if (opts2 & RxVlanTag)
1549                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1550 }
1551
1552 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1553                              void *p)
1554 {
1555         struct rtl8169_private *tp = netdev_priv(dev);
1556         u32 __iomem *data = tp->mmio_addr;
1557         u32 *dw = p;
1558         int i;
1559
1560         rtl_lock_work(tp);
1561         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1562                 memcpy_fromio(dw++, data++, 4);
1563         rtl_unlock_work(tp);
1564 }
1565
1566 static u32 rtl8169_get_msglevel(struct net_device *dev)
1567 {
1568         struct rtl8169_private *tp = netdev_priv(dev);
1569
1570         return tp->msg_enable;
1571 }
1572
1573 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1574 {
1575         struct rtl8169_private *tp = netdev_priv(dev);
1576
1577         tp->msg_enable = value;
1578 }
1579
1580 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1581         "tx_packets",
1582         "rx_packets",
1583         "tx_errors",
1584         "rx_errors",
1585         "rx_missed",
1586         "align_errors",
1587         "tx_single_collisions",
1588         "tx_multi_collisions",
1589         "unicast",
1590         "broadcast",
1591         "multicast",
1592         "tx_aborted",
1593         "tx_underrun",
1594 };
1595
1596 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1597 {
1598         switch (sset) {
1599         case ETH_SS_STATS:
1600                 return ARRAY_SIZE(rtl8169_gstrings);
1601         default:
1602                 return -EOPNOTSUPP;
1603         }
1604 }
1605
1606 DECLARE_RTL_COND(rtl_counters_cond)
1607 {
1608         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1609 }
1610
1611 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1612 {
1613         dma_addr_t paddr = tp->counters_phys_addr;
1614         u32 cmd;
1615
1616         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1617         RTL_R32(tp, CounterAddrHigh);
1618         cmd = (u64)paddr & DMA_BIT_MASK(32);
1619         RTL_W32(tp, CounterAddrLow, cmd);
1620         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1621
1622         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1623 }
1624
1625 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1626 {
1627         /*
1628          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1629          * tally counters.
1630          */
1631         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1632                 return true;
1633
1634         return rtl8169_do_counters(tp, CounterReset);
1635 }
1636
1637 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1638 {
1639         u8 val = RTL_R8(tp, ChipCmd);
1640
1641         /*
1642          * Some chips are unable to dump tally counters when the receiver
1643          * is disabled. If 0xff chip may be in a PCI power-save state.
1644          */
1645         if (!(val & CmdRxEnb) || val == 0xff)
1646                 return true;
1647
1648         return rtl8169_do_counters(tp, CounterDump);
1649 }
1650
1651 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1652 {
1653         struct rtl8169_counters *counters = tp->counters;
1654         bool ret = false;
1655
1656         /*
1657          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1658          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1659          * reset by a power cycle, while the counter values collected by the
1660          * driver are reset at every driver unload/load cycle.
1661          *
1662          * To make sure the HW values returned by @get_stats64 match the SW
1663          * values, we collect the initial values at first open(*) and use them
1664          * as offsets to normalize the values returned by @get_stats64.
1665          *
1666          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1667          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1668          * set at open time by rtl_hw_start.
1669          */
1670
1671         if (tp->tc_offset.inited)
1672                 return true;
1673
1674         /* If both, reset and update fail, propagate to caller. */
1675         if (rtl8169_reset_counters(tp))
1676                 ret = true;
1677
1678         if (rtl8169_update_counters(tp))
1679                 ret = true;
1680
1681         tp->tc_offset.tx_errors = counters->tx_errors;
1682         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1683         tp->tc_offset.tx_aborted = counters->tx_aborted;
1684         tp->tc_offset.inited = true;
1685
1686         return ret;
1687 }
1688
1689 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1690                                       struct ethtool_stats *stats, u64 *data)
1691 {
1692         struct rtl8169_private *tp = netdev_priv(dev);
1693         struct device *d = tp_to_dev(tp);
1694         struct rtl8169_counters *counters = tp->counters;
1695
1696         ASSERT_RTNL();
1697
1698         pm_runtime_get_noresume(d);
1699
1700         if (pm_runtime_active(d))
1701                 rtl8169_update_counters(tp);
1702
1703         pm_runtime_put_noidle(d);
1704
1705         data[0] = le64_to_cpu(counters->tx_packets);
1706         data[1] = le64_to_cpu(counters->rx_packets);
1707         data[2] = le64_to_cpu(counters->tx_errors);
1708         data[3] = le32_to_cpu(counters->rx_errors);
1709         data[4] = le16_to_cpu(counters->rx_missed);
1710         data[5] = le16_to_cpu(counters->align_errors);
1711         data[6] = le32_to_cpu(counters->tx_one_collision);
1712         data[7] = le32_to_cpu(counters->tx_multi_collision);
1713         data[8] = le64_to_cpu(counters->rx_unicast);
1714         data[9] = le64_to_cpu(counters->rx_broadcast);
1715         data[10] = le32_to_cpu(counters->rx_multicast);
1716         data[11] = le16_to_cpu(counters->tx_aborted);
1717         data[12] = le16_to_cpu(counters->tx_underun);
1718 }
1719
1720 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1721 {
1722         switch(stringset) {
1723         case ETH_SS_STATS:
1724                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1725                 break;
1726         }
1727 }
1728
1729 /*
1730  * Interrupt coalescing
1731  *
1732  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1733  * >     8169, 8168 and 810x line of chipsets
1734  *
1735  * 8169, 8168, and 8136(810x) serial chipsets support it.
1736  *
1737  * > 2 - the Tx timer unit at gigabit speed
1738  *
1739  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1740  * (0xe0) bit 1 and bit 0.
1741  *
1742  * For 8169
1743  * bit[1:0] \ speed        1000M           100M            10M
1744  * 0 0                     320ns           2.56us          40.96us
1745  * 0 1                     2.56us          20.48us         327.7us
1746  * 1 0                     5.12us          40.96us         655.4us
1747  * 1 1                     10.24us         81.92us         1.31ms
1748  *
1749  * For the other
1750  * bit[1:0] \ speed        1000M           100M            10M
1751  * 0 0                     5us             2.56us          40.96us
1752  * 0 1                     40us            20.48us         327.7us
1753  * 1 0                     80us            40.96us         655.4us
1754  * 1 1                     160us           81.92us         1.31ms
1755  */
1756
1757 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1758 struct rtl_coalesce_scale {
1759         /* Rx / Tx */
1760         u32 nsecs[2];
1761 };
1762
1763 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1764 struct rtl_coalesce_info {
1765         u32 speed;
1766         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1767 };
1768
1769 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1770 #define rxtx_x1822(r, t) {              \
1771         {{(r),          (t)}},          \
1772         {{(r)*8,        (t)*8}},        \
1773         {{(r)*8*2,      (t)*8*2}},      \
1774         {{(r)*8*2*2,    (t)*8*2*2}},    \
1775 }
1776 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1777         /* speed        delays:     rx00   tx00 */
1778         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1779         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1780         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1781         { 0 },
1782 };
1783
1784 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1785         /* speed        delays:     rx00   tx00 */
1786         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1787         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1788         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1789         { 0 },
1790 };
1791 #undef rxtx_x1822
1792
1793 /* get rx/tx scale vector corresponding to current speed */
1794 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1795 {
1796         struct rtl8169_private *tp = netdev_priv(dev);
1797         struct ethtool_link_ksettings ecmd;
1798         const struct rtl_coalesce_info *ci;
1799         int rc;
1800
1801         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1802         if (rc < 0)
1803                 return ERR_PTR(rc);
1804
1805         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1806                 if (ecmd.base.speed == ci->speed) {
1807                         return ci;
1808                 }
1809         }
1810
1811         return ERR_PTR(-ELNRNG);
1812 }
1813
1814 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1815 {
1816         struct rtl8169_private *tp = netdev_priv(dev);
1817         const struct rtl_coalesce_info *ci;
1818         const struct rtl_coalesce_scale *scale;
1819         struct {
1820                 u32 *max_frames;
1821                 u32 *usecs;
1822         } coal_settings [] = {
1823                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1824                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1825         }, *p = coal_settings;
1826         int i;
1827         u16 w;
1828
1829         memset(ec, 0, sizeof(*ec));
1830
1831         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1832         ci = rtl_coalesce_info(dev);
1833         if (IS_ERR(ci))
1834                 return PTR_ERR(ci);
1835
1836         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1837
1838         /* read IntrMitigate and adjust according to scale */
1839         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1840                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1841                 w >>= RTL_COALESCE_SHIFT;
1842                 *p->usecs = w & RTL_COALESCE_MASK;
1843         }
1844
1845         for (i = 0; i < 2; i++) {
1846                 p = coal_settings + i;
1847                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1848
1849                 /*
1850                  * ethtool_coalesce says it is illegal to set both usecs and
1851                  * max_frames to 0.
1852                  */
1853                 if (!*p->usecs && !*p->max_frames)
1854                         *p->max_frames = 1;
1855         }
1856
1857         return 0;
1858 }
1859
1860 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1861 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1862                         struct net_device *dev, u32 nsec, u16 *cp01)
1863 {
1864         const struct rtl_coalesce_info *ci;
1865         u16 i;
1866
1867         ci = rtl_coalesce_info(dev);
1868         if (IS_ERR(ci))
1869                 return ERR_CAST(ci);
1870
1871         for (i = 0; i < 4; i++) {
1872                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1873                                         ci->scalev[i].nsecs[1]);
1874                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1875                         *cp01 = i;
1876                         return &ci->scalev[i];
1877                 }
1878         }
1879
1880         return ERR_PTR(-EINVAL);
1881 }
1882
1883 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1884 {
1885         struct rtl8169_private *tp = netdev_priv(dev);
1886         const struct rtl_coalesce_scale *scale;
1887         struct {
1888                 u32 frames;
1889                 u32 usecs;
1890         } coal_settings [] = {
1891                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1892                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1893         }, *p = coal_settings;
1894         u16 w = 0, cp01;
1895         int i;
1896
1897         scale = rtl_coalesce_choose_scale(dev,
1898                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1899         if (IS_ERR(scale))
1900                 return PTR_ERR(scale);
1901
1902         for (i = 0; i < 2; i++, p++) {
1903                 u32 units;
1904
1905                 /*
1906                  * accept max_frames=1 we returned in rtl_get_coalesce.
1907                  * accept it not only when usecs=0 because of e.g. the following scenario:
1908                  *
1909                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1910                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1911                  * - then user does `ethtool -C eth0 rx-usecs 100`
1912                  *
1913                  * since ethtool sends to kernel whole ethtool_coalesce
1914                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1915                  * we'll reject it below in `frames % 4 != 0`.
1916                  */
1917                 if (p->frames == 1) {
1918                         p->frames = 0;
1919                 }
1920
1921                 units = p->usecs * 1000 / scale->nsecs[i];
1922                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1923                         return -EINVAL;
1924
1925                 w <<= RTL_COALESCE_SHIFT;
1926                 w |= units;
1927                 w <<= RTL_COALESCE_SHIFT;
1928                 w |= p->frames >> 2;
1929         }
1930
1931         rtl_lock_work(tp);
1932
1933         RTL_W16(tp, IntrMitigate, swab16(w));
1934
1935         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1936         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1937         RTL_R16(tp, CPlusCmd);
1938
1939         rtl_unlock_work(tp);
1940
1941         return 0;
1942 }
1943
1944 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1945 {
1946         struct phy_device *phydev = tp->phydev;
1947         int ret;
1948
1949         switch (tp->mac_version) {
1950         case RTL_GIGA_MAC_VER_34:
1951         case RTL_GIGA_MAC_VER_35:
1952         case RTL_GIGA_MAC_VER_36:
1953         case RTL_GIGA_MAC_VER_38:
1954                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1955                 break;
1956         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1957                 phy_write(phydev, 0x1f, 0x0a5c);
1958                 ret = phy_read(phydev, 0x12);
1959                 phy_write(phydev, 0x1f, 0x0000);
1960                 break;
1961         default:
1962                 ret = -EPROTONOSUPPORT;
1963                 break;
1964         }
1965
1966         return ret;
1967 }
1968
1969 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1970 {
1971         struct phy_device *phydev = tp->phydev;
1972         int ret;
1973
1974         switch (tp->mac_version) {
1975         case RTL_GIGA_MAC_VER_34:
1976         case RTL_GIGA_MAC_VER_35:
1977         case RTL_GIGA_MAC_VER_36:
1978         case RTL_GIGA_MAC_VER_38:
1979                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1980                 break;
1981         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1982                 phy_write(phydev, 0x1f, 0x0a5d);
1983                 ret = phy_read(phydev, 0x11);
1984                 phy_write(phydev, 0x1f, 0x0000);
1985                 break;
1986         default:
1987                 ret = -EPROTONOSUPPORT;
1988                 break;
1989         }
1990
1991         return ret;
1992 }
1993
1994 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1995 {
1996         struct phy_device *phydev = tp->phydev;
1997         int ret;
1998
1999         switch (tp->mac_version) {
2000         case RTL_GIGA_MAC_VER_34:
2001         case RTL_GIGA_MAC_VER_35:
2002         case RTL_GIGA_MAC_VER_36:
2003         case RTL_GIGA_MAC_VER_38:
2004                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2005                 break;
2006         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2007                 phy_write(phydev, 0x1f, 0x0a5d);
2008                 ret = phy_read(phydev, 0x10);
2009                 phy_write(phydev, 0x1f, 0x0000);
2010                 break;
2011         default:
2012                 ret = -EPROTONOSUPPORT;
2013                 break;
2014         }
2015
2016         return ret;
2017 }
2018
2019 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2020 {
2021         struct phy_device *phydev = tp->phydev;
2022         int ret = 0;
2023
2024         switch (tp->mac_version) {
2025         case RTL_GIGA_MAC_VER_34:
2026         case RTL_GIGA_MAC_VER_35:
2027         case RTL_GIGA_MAC_VER_36:
2028         case RTL_GIGA_MAC_VER_38:
2029                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2030                 break;
2031         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2032                 phy_write(phydev, 0x1f, 0x0a5d);
2033                 phy_write(phydev, 0x10, val);
2034                 phy_write(phydev, 0x1f, 0x0000);
2035                 break;
2036         default:
2037                 ret = -EPROTONOSUPPORT;
2038                 break;
2039         }
2040
2041         return ret;
2042 }
2043
2044 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2045 {
2046         struct rtl8169_private *tp = netdev_priv(dev);
2047         struct device *d = tp_to_dev(tp);
2048         int ret;
2049
2050         pm_runtime_get_noresume(d);
2051
2052         if (!pm_runtime_active(d)) {
2053                 ret = -EOPNOTSUPP;
2054                 goto out;
2055         }
2056
2057         /* Get Supported EEE */
2058         ret = rtl_get_eee_supp(tp);
2059         if (ret < 0)
2060                 goto out;
2061         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2062
2063         /* Get advertisement EEE */
2064         ret = rtl_get_eee_adv(tp);
2065         if (ret < 0)
2066                 goto out;
2067         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2068         data->eee_enabled = !!data->advertised;
2069
2070         /* Get LP advertisement EEE */
2071         ret = rtl_get_eee_lpadv(tp);
2072         if (ret < 0)
2073                 goto out;
2074         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2075         data->eee_active = !!(data->advertised & data->lp_advertised);
2076 out:
2077         pm_runtime_put_noidle(d);
2078         return ret < 0 ? ret : 0;
2079 }
2080
2081 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2082 {
2083         struct rtl8169_private *tp = netdev_priv(dev);
2084         struct device *d = tp_to_dev(tp);
2085         int old_adv, adv = 0, cap, ret;
2086
2087         pm_runtime_get_noresume(d);
2088
2089         if (!dev->phydev || !pm_runtime_active(d)) {
2090                 ret = -EOPNOTSUPP;
2091                 goto out;
2092         }
2093
2094         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2095             dev->phydev->duplex != DUPLEX_FULL) {
2096                 ret = -EPROTONOSUPPORT;
2097                 goto out;
2098         }
2099
2100         /* Get Supported EEE */
2101         ret = rtl_get_eee_supp(tp);
2102         if (ret < 0)
2103                 goto out;
2104         cap = ret;
2105
2106         ret = rtl_get_eee_adv(tp);
2107         if (ret < 0)
2108                 goto out;
2109         old_adv = ret;
2110
2111         if (data->eee_enabled) {
2112                 adv = !data->advertised ? cap :
2113                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2114                 /* Mask prohibited EEE modes */
2115                 adv &= ~dev->phydev->eee_broken_modes;
2116         }
2117
2118         if (old_adv != adv) {
2119                 ret = rtl_set_eee_adv(tp, adv);
2120                 if (ret < 0)
2121                         goto out;
2122
2123                 /* Restart autonegotiation so the new modes get sent to the
2124                  * link partner.
2125                  */
2126                 ret = phy_restart_aneg(dev->phydev);
2127         }
2128
2129 out:
2130         pm_runtime_put_noidle(d);
2131         return ret < 0 ? ret : 0;
2132 }
2133
2134 static const struct ethtool_ops rtl8169_ethtool_ops = {
2135         .get_drvinfo            = rtl8169_get_drvinfo,
2136         .get_regs_len           = rtl8169_get_regs_len,
2137         .get_link               = ethtool_op_get_link,
2138         .get_coalesce           = rtl_get_coalesce,
2139         .set_coalesce           = rtl_set_coalesce,
2140         .get_msglevel           = rtl8169_get_msglevel,
2141         .set_msglevel           = rtl8169_set_msglevel,
2142         .get_regs               = rtl8169_get_regs,
2143         .get_wol                = rtl8169_get_wol,
2144         .set_wol                = rtl8169_set_wol,
2145         .get_strings            = rtl8169_get_strings,
2146         .get_sset_count         = rtl8169_get_sset_count,
2147         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2148         .get_ts_info            = ethtool_op_get_ts_info,
2149         .nway_reset             = phy_ethtool_nway_reset,
2150         .get_eee                = rtl8169_get_eee,
2151         .set_eee                = rtl8169_set_eee,
2152         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2153         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2154 };
2155
2156 static void rtl_enable_eee(struct rtl8169_private *tp)
2157 {
2158         int supported = rtl_get_eee_supp(tp);
2159
2160         if (supported > 0)
2161                 rtl_set_eee_adv(tp, supported);
2162 }
2163
2164 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2165 {
2166         /*
2167          * The driver currently handles the 8168Bf and the 8168Be identically
2168          * but they can be identified more specifically through the test below
2169          * if needed:
2170          *
2171          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2172          *
2173          * Same thing for the 8101Eb and the 8101Ec:
2174          *
2175          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2176          */
2177         static const struct rtl_mac_info {
2178                 u16 mask;
2179                 u16 val;
2180                 u16 mac_version;
2181         } mac_info[] = {
2182                 /* 8168EP family. */
2183                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2184                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2185                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2186
2187                 /* 8168H family. */
2188                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2189                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2190
2191                 /* 8168G family. */
2192                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2193                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2194                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2195                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2196
2197                 /* 8168F family. */
2198                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2199                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2200                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2201
2202                 /* 8168E family. */
2203                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2204                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2205                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2206
2207                 /* 8168D family. */
2208                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2209                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2210
2211                 /* 8168DP family. */
2212                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2213                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2214                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2215
2216                 /* 8168C family. */
2217                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2218                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2219                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2220                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2221                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2222                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2223                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2224
2225                 /* 8168B family. */
2226                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2227                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2228                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2229
2230                 /* 8101 family. */
2231                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2232                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2233                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2234                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2235                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2236                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2237                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2238                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2239                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2240                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2241                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2242                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2243                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2244                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2245                 /* FIXME: where did these entries come from ? -- FR */
2246                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2247                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2248
2249                 /* 8110 family. */
2250                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2251                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2252                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2253                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2254                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2255                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2256
2257                 /* Catch-all */
2258                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2259         };
2260         const struct rtl_mac_info *p = mac_info;
2261         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2262
2263         while ((reg & p->mask) != p->val)
2264                 p++;
2265         tp->mac_version = p->mac_version;
2266
2267         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2268                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2269         } else if (!tp->supports_gmii) {
2270                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2271                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2272                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2273                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2274                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2275                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2276         }
2277 }
2278
2279 struct phy_reg {
2280         u16 reg;
2281         u16 val;
2282 };
2283
2284 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2285                                  const struct phy_reg *regs, int len)
2286 {
2287         while (len-- > 0) {
2288                 rtl_writephy(tp, regs->reg, regs->val);
2289                 regs++;
2290         }
2291 }
2292
2293 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2294
2295 #define PHY_READ                0x00000000
2296 #define PHY_DATA_OR             0x10000000
2297 #define PHY_DATA_AND            0x20000000
2298 #define PHY_BJMPN               0x30000000
2299 #define PHY_MDIO_CHG            0x40000000
2300 #define PHY_CLEAR_READCOUNT     0x70000000
2301 #define PHY_WRITE               0x80000000
2302 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2303 #define PHY_COMP_EQ_SKIPN       0xa0000000
2304 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2305 #define PHY_WRITE_PREVIOUS      0xc0000000
2306 #define PHY_SKIPN               0xd0000000
2307 #define PHY_DELAY_MS            0xe0000000
2308
2309 struct fw_info {
2310         u32     magic;
2311         char    version[RTL_VER_SIZE];
2312         __le32  fw_start;
2313         __le32  fw_len;
2314         u8      chksum;
2315 } __packed;
2316
2317 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2318
2319 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2320 {
2321         const struct firmware *fw = rtl_fw->fw;
2322         struct fw_info *fw_info = (struct fw_info *)fw->data;
2323         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2324         char *version = rtl_fw->version;
2325         bool rc = false;
2326
2327         if (fw->size < FW_OPCODE_SIZE)
2328                 goto out;
2329
2330         if (!fw_info->magic) {
2331                 size_t i, size, start;
2332                 u8 checksum = 0;
2333
2334                 if (fw->size < sizeof(*fw_info))
2335                         goto out;
2336
2337                 for (i = 0; i < fw->size; i++)
2338                         checksum += fw->data[i];
2339                 if (checksum != 0)
2340                         goto out;
2341
2342                 start = le32_to_cpu(fw_info->fw_start);
2343                 if (start > fw->size)
2344                         goto out;
2345
2346                 size = le32_to_cpu(fw_info->fw_len);
2347                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2348                         goto out;
2349
2350                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2351
2352                 pa->code = (__le32 *)(fw->data + start);
2353                 pa->size = size;
2354         } else {
2355                 if (fw->size % FW_OPCODE_SIZE)
2356                         goto out;
2357
2358                 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2359
2360                 pa->code = (__le32 *)fw->data;
2361                 pa->size = fw->size / FW_OPCODE_SIZE;
2362         }
2363         version[RTL_VER_SIZE - 1] = 0;
2364
2365         rc = true;
2366 out:
2367         return rc;
2368 }
2369
2370 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2371                            struct rtl_fw_phy_action *pa)
2372 {
2373         bool rc = false;
2374         size_t index;
2375
2376         for (index = 0; index < pa->size; index++) {
2377                 u32 action = le32_to_cpu(pa->code[index]);
2378                 u32 regno = (action & 0x0fff0000) >> 16;
2379
2380                 switch(action & 0xf0000000) {
2381                 case PHY_READ:
2382                 case PHY_DATA_OR:
2383                 case PHY_DATA_AND:
2384                 case PHY_MDIO_CHG:
2385                 case PHY_CLEAR_READCOUNT:
2386                 case PHY_WRITE:
2387                 case PHY_WRITE_PREVIOUS:
2388                 case PHY_DELAY_MS:
2389                         break;
2390
2391                 case PHY_BJMPN:
2392                         if (regno > index) {
2393                                 netif_err(tp, ifup, tp->dev,
2394                                           "Out of range of firmware\n");
2395                                 goto out;
2396                         }
2397                         break;
2398                 case PHY_READCOUNT_EQ_SKIP:
2399                         if (index + 2 >= pa->size) {
2400                                 netif_err(tp, ifup, tp->dev,
2401                                           "Out of range of firmware\n");
2402                                 goto out;
2403                         }
2404                         break;
2405                 case PHY_COMP_EQ_SKIPN:
2406                 case PHY_COMP_NEQ_SKIPN:
2407                 case PHY_SKIPN:
2408                         if (index + 1 + regno >= pa->size) {
2409                                 netif_err(tp, ifup, tp->dev,
2410                                           "Out of range of firmware\n");
2411                                 goto out;
2412                         }
2413                         break;
2414
2415                 default:
2416                         netif_err(tp, ifup, tp->dev,
2417                                   "Invalid action 0x%08x\n", action);
2418                         goto out;
2419                 }
2420         }
2421         rc = true;
2422 out:
2423         return rc;
2424 }
2425
2426 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2427 {
2428         struct net_device *dev = tp->dev;
2429         int rc = -EINVAL;
2430
2431         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2432                 netif_err(tp, ifup, dev, "invalid firmware\n");
2433                 goto out;
2434         }
2435
2436         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2437                 rc = 0;
2438 out:
2439         return rc;
2440 }
2441
2442 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2443 {
2444         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2445         struct mdio_ops org, *ops = &tp->mdio_ops;
2446         u32 predata, count;
2447         size_t index;
2448
2449         predata = count = 0;
2450         org.write = ops->write;
2451         org.read = ops->read;
2452
2453         for (index = 0; index < pa->size; ) {
2454                 u32 action = le32_to_cpu(pa->code[index]);
2455                 u32 data = action & 0x0000ffff;
2456                 u32 regno = (action & 0x0fff0000) >> 16;
2457
2458                 if (!action)
2459                         break;
2460
2461                 switch(action & 0xf0000000) {
2462                 case PHY_READ:
2463                         predata = rtl_readphy(tp, regno);
2464                         count++;
2465                         index++;
2466                         break;
2467                 case PHY_DATA_OR:
2468                         predata |= data;
2469                         index++;
2470                         break;
2471                 case PHY_DATA_AND:
2472                         predata &= data;
2473                         index++;
2474                         break;
2475                 case PHY_BJMPN:
2476                         index -= regno;
2477                         break;
2478                 case PHY_MDIO_CHG:
2479                         if (data == 0) {
2480                                 ops->write = org.write;
2481                                 ops->read = org.read;
2482                         } else if (data == 1) {
2483                                 ops->write = mac_mcu_write;
2484                                 ops->read = mac_mcu_read;
2485                         }
2486
2487                         index++;
2488                         break;
2489                 case PHY_CLEAR_READCOUNT:
2490                         count = 0;
2491                         index++;
2492                         break;
2493                 case PHY_WRITE:
2494                         rtl_writephy(tp, regno, data);
2495                         index++;
2496                         break;
2497                 case PHY_READCOUNT_EQ_SKIP:
2498                         index += (count == data) ? 2 : 1;
2499                         break;
2500                 case PHY_COMP_EQ_SKIPN:
2501                         if (predata == data)
2502                                 index += regno;
2503                         index++;
2504                         break;
2505                 case PHY_COMP_NEQ_SKIPN:
2506                         if (predata != data)
2507                                 index += regno;
2508                         index++;
2509                         break;
2510                 case PHY_WRITE_PREVIOUS:
2511                         rtl_writephy(tp, regno, predata);
2512                         index++;
2513                         break;
2514                 case PHY_SKIPN:
2515                         index += regno + 1;
2516                         break;
2517                 case PHY_DELAY_MS:
2518                         mdelay(data);
2519                         index++;
2520                         break;
2521
2522                 default:
2523                         BUG();
2524                 }
2525         }
2526
2527         ops->write = org.write;
2528         ops->read = org.read;
2529 }
2530
2531 static void rtl_release_firmware(struct rtl8169_private *tp)
2532 {
2533         if (tp->rtl_fw) {
2534                 release_firmware(tp->rtl_fw->fw);
2535                 kfree(tp->rtl_fw);
2536                 tp->rtl_fw = NULL;
2537         }
2538 }
2539
2540 static void rtl_apply_firmware(struct rtl8169_private *tp)
2541 {
2542         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2543         if (tp->rtl_fw)
2544                 rtl_phy_write_fw(tp, tp->rtl_fw);
2545 }
2546
2547 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2548 {
2549         if (rtl_readphy(tp, reg) != val)
2550                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2551         else
2552                 rtl_apply_firmware(tp);
2553 }
2554
2555 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2556 {
2557         /* Adjust EEE LED frequency */
2558         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2559                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2560
2561         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2562 }
2563
2564 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2565 {
2566         struct phy_device *phydev = tp->phydev;
2567
2568         phy_write(phydev, 0x1f, 0x0007);
2569         phy_write(phydev, 0x1e, 0x0020);
2570         phy_set_bits(phydev, 0x15, BIT(8));
2571
2572         phy_write(phydev, 0x1f, 0x0005);
2573         phy_write(phydev, 0x05, 0x8b85);
2574         phy_set_bits(phydev, 0x06, BIT(13));
2575
2576         phy_write(phydev, 0x1f, 0x0000);
2577 }
2578
2579 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2580 {
2581         phy_write(tp->phydev, 0x1f, 0x0a43);
2582         phy_set_bits(tp->phydev, 0x11, BIT(4));
2583         phy_write(tp->phydev, 0x1f, 0x0000);
2584 }
2585
2586 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2587 {
2588         static const struct phy_reg phy_reg_init[] = {
2589                 { 0x1f, 0x0001 },
2590                 { 0x06, 0x006e },
2591                 { 0x08, 0x0708 },
2592                 { 0x15, 0x4000 },
2593                 { 0x18, 0x65c7 },
2594
2595                 { 0x1f, 0x0001 },
2596                 { 0x03, 0x00a1 },
2597                 { 0x02, 0x0008 },
2598                 { 0x01, 0x0120 },
2599                 { 0x00, 0x1000 },
2600                 { 0x04, 0x0800 },
2601                 { 0x04, 0x0000 },
2602
2603                 { 0x03, 0xff41 },
2604                 { 0x02, 0xdf60 },
2605                 { 0x01, 0x0140 },
2606                 { 0x00, 0x0077 },
2607                 { 0x04, 0x7800 },
2608                 { 0x04, 0x7000 },
2609
2610                 { 0x03, 0x802f },
2611                 { 0x02, 0x4f02 },
2612                 { 0x01, 0x0409 },
2613                 { 0x00, 0xf0f9 },
2614                 { 0x04, 0x9800 },
2615                 { 0x04, 0x9000 },
2616
2617                 { 0x03, 0xdf01 },
2618                 { 0x02, 0xdf20 },
2619                 { 0x01, 0xff95 },
2620                 { 0x00, 0xba00 },
2621                 { 0x04, 0xa800 },
2622                 { 0x04, 0xa000 },
2623
2624                 { 0x03, 0xff41 },
2625                 { 0x02, 0xdf20 },
2626                 { 0x01, 0x0140 },
2627                 { 0x00, 0x00bb },
2628                 { 0x04, 0xb800 },
2629                 { 0x04, 0xb000 },
2630
2631                 { 0x03, 0xdf41 },
2632                 { 0x02, 0xdc60 },
2633                 { 0x01, 0x6340 },
2634                 { 0x00, 0x007d },
2635                 { 0x04, 0xd800 },
2636                 { 0x04, 0xd000 },
2637
2638                 { 0x03, 0xdf01 },
2639                 { 0x02, 0xdf20 },
2640                 { 0x01, 0x100a },
2641                 { 0x00, 0xa0ff },
2642                 { 0x04, 0xf800 },
2643                 { 0x04, 0xf000 },
2644
2645                 { 0x1f, 0x0000 },
2646                 { 0x0b, 0x0000 },
2647                 { 0x00, 0x9200 }
2648         };
2649
2650         rtl_writephy_batch(tp, phy_reg_init);
2651 }
2652
2653 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2654 {
2655         static const struct phy_reg phy_reg_init[] = {
2656                 { 0x1f, 0x0002 },
2657                 { 0x01, 0x90d0 },
2658                 { 0x1f, 0x0000 }
2659         };
2660
2661         rtl_writephy_batch(tp, phy_reg_init);
2662 }
2663
2664 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2665 {
2666         struct pci_dev *pdev = tp->pci_dev;
2667
2668         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2669             (pdev->subsystem_device != 0xe000))
2670                 return;
2671
2672         rtl_writephy(tp, 0x1f, 0x0001);
2673         rtl_writephy(tp, 0x10, 0xf01b);
2674         rtl_writephy(tp, 0x1f, 0x0000);
2675 }
2676
2677 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2678 {
2679         static const struct phy_reg phy_reg_init[] = {
2680                 { 0x1f, 0x0001 },
2681                 { 0x04, 0x0000 },
2682                 { 0x03, 0x00a1 },
2683                 { 0x02, 0x0008 },
2684                 { 0x01, 0x0120 },
2685                 { 0x00, 0x1000 },
2686                 { 0x04, 0x0800 },
2687                 { 0x04, 0x9000 },
2688                 { 0x03, 0x802f },
2689                 { 0x02, 0x4f02 },
2690                 { 0x01, 0x0409 },
2691                 { 0x00, 0xf099 },
2692                 { 0x04, 0x9800 },
2693                 { 0x04, 0xa000 },
2694                 { 0x03, 0xdf01 },
2695                 { 0x02, 0xdf20 },
2696                 { 0x01, 0xff95 },
2697                 { 0x00, 0xba00 },
2698                 { 0x04, 0xa800 },
2699                 { 0x04, 0xf000 },
2700                 { 0x03, 0xdf01 },
2701                 { 0x02, 0xdf20 },
2702                 { 0x01, 0x101a },
2703                 { 0x00, 0xa0ff },
2704                 { 0x04, 0xf800 },
2705                 { 0x04, 0x0000 },
2706                 { 0x1f, 0x0000 },
2707
2708                 { 0x1f, 0x0001 },
2709                 { 0x10, 0xf41b },
2710                 { 0x14, 0xfb54 },
2711                 { 0x18, 0xf5c7 },
2712                 { 0x1f, 0x0000 },
2713
2714                 { 0x1f, 0x0001 },
2715                 { 0x17, 0x0cc0 },
2716                 { 0x1f, 0x0000 }
2717         };
2718
2719         rtl_writephy_batch(tp, phy_reg_init);
2720
2721         rtl8169scd_hw_phy_config_quirk(tp);
2722 }
2723
2724 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2725 {
2726         static const struct phy_reg phy_reg_init[] = {
2727                 { 0x1f, 0x0001 },
2728                 { 0x04, 0x0000 },
2729                 { 0x03, 0x00a1 },
2730                 { 0x02, 0x0008 },
2731                 { 0x01, 0x0120 },
2732                 { 0x00, 0x1000 },
2733                 { 0x04, 0x0800 },
2734                 { 0x04, 0x9000 },
2735                 { 0x03, 0x802f },
2736                 { 0x02, 0x4f02 },
2737                 { 0x01, 0x0409 },
2738                 { 0x00, 0xf099 },
2739                 { 0x04, 0x9800 },
2740                 { 0x04, 0xa000 },
2741                 { 0x03, 0xdf01 },
2742                 { 0x02, 0xdf20 },
2743                 { 0x01, 0xff95 },
2744                 { 0x00, 0xba00 },
2745                 { 0x04, 0xa800 },
2746                 { 0x04, 0xf000 },
2747                 { 0x03, 0xdf01 },
2748                 { 0x02, 0xdf20 },
2749                 { 0x01, 0x101a },
2750                 { 0x00, 0xa0ff },
2751                 { 0x04, 0xf800 },
2752                 { 0x04, 0x0000 },
2753                 { 0x1f, 0x0000 },
2754
2755                 { 0x1f, 0x0001 },
2756                 { 0x0b, 0x8480 },
2757                 { 0x1f, 0x0000 },
2758
2759                 { 0x1f, 0x0001 },
2760                 { 0x18, 0x67c7 },
2761                 { 0x04, 0x2000 },
2762                 { 0x03, 0x002f },
2763                 { 0x02, 0x4360 },
2764                 { 0x01, 0x0109 },
2765                 { 0x00, 0x3022 },
2766                 { 0x04, 0x2800 },
2767                 { 0x1f, 0x0000 },
2768
2769                 { 0x1f, 0x0001 },
2770                 { 0x17, 0x0cc0 },
2771                 { 0x1f, 0x0000 }
2772         };
2773
2774         rtl_writephy_batch(tp, phy_reg_init);
2775 }
2776
2777 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2778 {
2779         static const struct phy_reg phy_reg_init[] = {
2780                 { 0x10, 0xf41b },
2781                 { 0x1f, 0x0000 }
2782         };
2783
2784         rtl_writephy(tp, 0x1f, 0x0001);
2785         rtl_patchphy(tp, 0x16, 1 << 0);
2786
2787         rtl_writephy_batch(tp, phy_reg_init);
2788 }
2789
2790 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2791 {
2792         static const struct phy_reg phy_reg_init[] = {
2793                 { 0x1f, 0x0001 },
2794                 { 0x10, 0xf41b },
2795                 { 0x1f, 0x0000 }
2796         };
2797
2798         rtl_writephy_batch(tp, phy_reg_init);
2799 }
2800
2801 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2802 {
2803         static const struct phy_reg phy_reg_init[] = {
2804                 { 0x1f, 0x0000 },
2805                 { 0x1d, 0x0f00 },
2806                 { 0x1f, 0x0002 },
2807                 { 0x0c, 0x1ec8 },
2808                 { 0x1f, 0x0000 }
2809         };
2810
2811         rtl_writephy_batch(tp, phy_reg_init);
2812 }
2813
2814 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2815 {
2816         static const struct phy_reg phy_reg_init[] = {
2817                 { 0x1f, 0x0001 },
2818                 { 0x1d, 0x3d98 },
2819                 { 0x1f, 0x0000 }
2820         };
2821
2822         rtl_writephy(tp, 0x1f, 0x0000);
2823         rtl_patchphy(tp, 0x14, 1 << 5);
2824         rtl_patchphy(tp, 0x0d, 1 << 5);
2825
2826         rtl_writephy_batch(tp, phy_reg_init);
2827 }
2828
2829 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2830 {
2831         static const struct phy_reg phy_reg_init[] = {
2832                 { 0x1f, 0x0001 },
2833                 { 0x12, 0x2300 },
2834                 { 0x1f, 0x0002 },
2835                 { 0x00, 0x88d4 },
2836                 { 0x01, 0x82b1 },
2837                 { 0x03, 0x7002 },
2838                 { 0x08, 0x9e30 },
2839                 { 0x09, 0x01f0 },
2840                 { 0x0a, 0x5500 },
2841                 { 0x0c, 0x00c8 },
2842                 { 0x1f, 0x0003 },
2843                 { 0x12, 0xc096 },
2844                 { 0x16, 0x000a },
2845                 { 0x1f, 0x0000 },
2846                 { 0x1f, 0x0000 },
2847                 { 0x09, 0x2000 },
2848                 { 0x09, 0x0000 }
2849         };
2850
2851         rtl_writephy_batch(tp, phy_reg_init);
2852
2853         rtl_patchphy(tp, 0x14, 1 << 5);
2854         rtl_patchphy(tp, 0x0d, 1 << 5);
2855         rtl_writephy(tp, 0x1f, 0x0000);
2856 }
2857
2858 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2859 {
2860         static const struct phy_reg phy_reg_init[] = {
2861                 { 0x1f, 0x0001 },
2862                 { 0x12, 0x2300 },
2863                 { 0x03, 0x802f },
2864                 { 0x02, 0x4f02 },
2865                 { 0x01, 0x0409 },
2866                 { 0x00, 0xf099 },
2867                 { 0x04, 0x9800 },
2868                 { 0x04, 0x9000 },
2869                 { 0x1d, 0x3d98 },
2870                 { 0x1f, 0x0002 },
2871                 { 0x0c, 0x7eb8 },
2872                 { 0x06, 0x0761 },
2873                 { 0x1f, 0x0003 },
2874                 { 0x16, 0x0f0a },
2875                 { 0x1f, 0x0000 }
2876         };
2877
2878         rtl_writephy_batch(tp, phy_reg_init);
2879
2880         rtl_patchphy(tp, 0x16, 1 << 0);
2881         rtl_patchphy(tp, 0x14, 1 << 5);
2882         rtl_patchphy(tp, 0x0d, 1 << 5);
2883         rtl_writephy(tp, 0x1f, 0x0000);
2884 }
2885
2886 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2887 {
2888         static const struct phy_reg phy_reg_init[] = {
2889                 { 0x1f, 0x0001 },
2890                 { 0x12, 0x2300 },
2891                 { 0x1d, 0x3d98 },
2892                 { 0x1f, 0x0002 },
2893                 { 0x0c, 0x7eb8 },
2894                 { 0x06, 0x5461 },
2895                 { 0x1f, 0x0003 },
2896                 { 0x16, 0x0f0a },
2897                 { 0x1f, 0x0000 }
2898         };
2899
2900         rtl_writephy_batch(tp, phy_reg_init);
2901
2902         rtl_patchphy(tp, 0x16, 1 << 0);
2903         rtl_patchphy(tp, 0x14, 1 << 5);
2904         rtl_patchphy(tp, 0x0d, 1 << 5);
2905         rtl_writephy(tp, 0x1f, 0x0000);
2906 }
2907
2908 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2909 {
2910         rtl8168c_3_hw_phy_config(tp);
2911 }
2912
2913 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2914 {
2915         static const struct phy_reg phy_reg_init_0[] = {
2916                 /* Channel Estimation */
2917                 { 0x1f, 0x0001 },
2918                 { 0x06, 0x4064 },
2919                 { 0x07, 0x2863 },
2920                 { 0x08, 0x059c },
2921                 { 0x09, 0x26b4 },
2922                 { 0x0a, 0x6a19 },
2923                 { 0x0b, 0xdcc8 },
2924                 { 0x10, 0xf06d },
2925                 { 0x14, 0x7f68 },
2926                 { 0x18, 0x7fd9 },
2927                 { 0x1c, 0xf0ff },
2928                 { 0x1d, 0x3d9c },
2929                 { 0x1f, 0x0003 },
2930                 { 0x12, 0xf49f },
2931                 { 0x13, 0x070b },
2932                 { 0x1a, 0x05ad },
2933                 { 0x14, 0x94c0 },
2934
2935                 /*
2936                  * Tx Error Issue
2937                  * Enhance line driver power
2938                  */
2939                 { 0x1f, 0x0002 },
2940                 { 0x06, 0x5561 },
2941                 { 0x1f, 0x0005 },
2942                 { 0x05, 0x8332 },
2943                 { 0x06, 0x5561 },
2944
2945                 /*
2946                  * Can not link to 1Gbps with bad cable
2947                  * Decrease SNR threshold form 21.07dB to 19.04dB
2948                  */
2949                 { 0x1f, 0x0001 },
2950                 { 0x17, 0x0cc0 },
2951
2952                 { 0x1f, 0x0000 },
2953                 { 0x0d, 0xf880 }
2954         };
2955
2956         rtl_writephy_batch(tp, phy_reg_init_0);
2957
2958         /*
2959          * Rx Error Issue
2960          * Fine Tune Switching regulator parameter
2961          */
2962         rtl_writephy(tp, 0x1f, 0x0002);
2963         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2964         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2965
2966         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2967                 static const struct phy_reg phy_reg_init[] = {
2968                         { 0x1f, 0x0002 },
2969                         { 0x05, 0x669a },
2970                         { 0x1f, 0x0005 },
2971                         { 0x05, 0x8330 },
2972                         { 0x06, 0x669a },
2973                         { 0x1f, 0x0002 }
2974                 };
2975                 int val;
2976
2977                 rtl_writephy_batch(tp, phy_reg_init);
2978
2979                 val = rtl_readphy(tp, 0x0d);
2980
2981                 if ((val & 0x00ff) != 0x006c) {
2982                         static const u32 set[] = {
2983                                 0x0065, 0x0066, 0x0067, 0x0068,
2984                                 0x0069, 0x006a, 0x006b, 0x006c
2985                         };
2986                         int i;
2987
2988                         rtl_writephy(tp, 0x1f, 0x0002);
2989
2990                         val &= 0xff00;
2991                         for (i = 0; i < ARRAY_SIZE(set); i++)
2992                                 rtl_writephy(tp, 0x0d, val | set[i]);
2993                 }
2994         } else {
2995                 static const struct phy_reg phy_reg_init[] = {
2996                         { 0x1f, 0x0002 },
2997                         { 0x05, 0x6662 },
2998                         { 0x1f, 0x0005 },
2999                         { 0x05, 0x8330 },
3000                         { 0x06, 0x6662 }
3001                 };
3002
3003                 rtl_writephy_batch(tp, phy_reg_init);
3004         }
3005
3006         /* RSET couple improve */
3007         rtl_writephy(tp, 0x1f, 0x0002);
3008         rtl_patchphy(tp, 0x0d, 0x0300);
3009         rtl_patchphy(tp, 0x0f, 0x0010);
3010
3011         /* Fine tune PLL performance */
3012         rtl_writephy(tp, 0x1f, 0x0002);
3013         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3014         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3015
3016         rtl_writephy(tp, 0x1f, 0x0005);
3017         rtl_writephy(tp, 0x05, 0x001b);
3018
3019         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3020
3021         rtl_writephy(tp, 0x1f, 0x0000);
3022 }
3023
3024 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3025 {
3026         static const struct phy_reg phy_reg_init_0[] = {
3027                 /* Channel Estimation */
3028                 { 0x1f, 0x0001 },
3029                 { 0x06, 0x4064 },
3030                 { 0x07, 0x2863 },
3031                 { 0x08, 0x059c },
3032                 { 0x09, 0x26b4 },
3033                 { 0x0a, 0x6a19 },
3034                 { 0x0b, 0xdcc8 },
3035                 { 0x10, 0xf06d },
3036                 { 0x14, 0x7f68 },
3037                 { 0x18, 0x7fd9 },
3038                 { 0x1c, 0xf0ff },
3039                 { 0x1d, 0x3d9c },
3040                 { 0x1f, 0x0003 },
3041                 { 0x12, 0xf49f },
3042                 { 0x13, 0x070b },
3043                 { 0x1a, 0x05ad },
3044                 { 0x14, 0x94c0 },
3045
3046                 /*
3047                  * Tx Error Issue
3048                  * Enhance line driver power
3049                  */
3050                 { 0x1f, 0x0002 },
3051                 { 0x06, 0x5561 },
3052                 { 0x1f, 0x0005 },
3053                 { 0x05, 0x8332 },
3054                 { 0x06, 0x5561 },
3055
3056                 /*
3057                  * Can not link to 1Gbps with bad cable
3058                  * Decrease SNR threshold form 21.07dB to 19.04dB
3059                  */
3060                 { 0x1f, 0x0001 },
3061                 { 0x17, 0x0cc0 },
3062
3063                 { 0x1f, 0x0000 },
3064                 { 0x0d, 0xf880 }
3065         };
3066
3067         rtl_writephy_batch(tp, phy_reg_init_0);
3068
3069         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3070                 static const struct phy_reg phy_reg_init[] = {
3071                         { 0x1f, 0x0002 },
3072                         { 0x05, 0x669a },
3073                         { 0x1f, 0x0005 },
3074                         { 0x05, 0x8330 },
3075                         { 0x06, 0x669a },
3076
3077                         { 0x1f, 0x0002 }
3078                 };
3079                 int val;
3080
3081                 rtl_writephy_batch(tp, phy_reg_init);
3082
3083                 val = rtl_readphy(tp, 0x0d);
3084                 if ((val & 0x00ff) != 0x006c) {
3085                         static const u32 set[] = {
3086                                 0x0065, 0x0066, 0x0067, 0x0068,
3087                                 0x0069, 0x006a, 0x006b, 0x006c
3088                         };
3089                         int i;
3090
3091                         rtl_writephy(tp, 0x1f, 0x0002);
3092
3093                         val &= 0xff00;
3094                         for (i = 0; i < ARRAY_SIZE(set); i++)
3095                                 rtl_writephy(tp, 0x0d, val | set[i]);
3096                 }
3097         } else {
3098                 static const struct phy_reg phy_reg_init[] = {
3099                         { 0x1f, 0x0002 },
3100                         { 0x05, 0x2642 },
3101                         { 0x1f, 0x0005 },
3102                         { 0x05, 0x8330 },
3103                         { 0x06, 0x2642 }
3104                 };
3105
3106                 rtl_writephy_batch(tp, phy_reg_init);
3107         }
3108
3109         /* Fine tune PLL performance */
3110         rtl_writephy(tp, 0x1f, 0x0002);
3111         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3112         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3113
3114         /* Switching regulator Slew rate */
3115         rtl_writephy(tp, 0x1f, 0x0002);
3116         rtl_patchphy(tp, 0x0f, 0x0017);
3117
3118         rtl_writephy(tp, 0x1f, 0x0005);
3119         rtl_writephy(tp, 0x05, 0x001b);
3120
3121         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3122
3123         rtl_writephy(tp, 0x1f, 0x0000);
3124 }
3125
3126 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3127 {
3128         static const struct phy_reg phy_reg_init[] = {
3129                 { 0x1f, 0x0002 },
3130                 { 0x10, 0x0008 },
3131                 { 0x0d, 0x006c },
3132
3133                 { 0x1f, 0x0000 },
3134                 { 0x0d, 0xf880 },
3135
3136                 { 0x1f, 0x0001 },
3137                 { 0x17, 0x0cc0 },
3138
3139                 { 0x1f, 0x0001 },
3140                 { 0x0b, 0xa4d8 },
3141                 { 0x09, 0x281c },
3142                 { 0x07, 0x2883 },
3143                 { 0x0a, 0x6b35 },
3144                 { 0x1d, 0x3da4 },
3145                 { 0x1c, 0xeffd },
3146                 { 0x14, 0x7f52 },
3147                 { 0x18, 0x7fc6 },
3148                 { 0x08, 0x0601 },
3149                 { 0x06, 0x4063 },
3150                 { 0x10, 0xf074 },
3151                 { 0x1f, 0x0003 },
3152                 { 0x13, 0x0789 },
3153                 { 0x12, 0xf4bd },
3154                 { 0x1a, 0x04fd },
3155                 { 0x14, 0x84b0 },
3156                 { 0x1f, 0x0000 },
3157                 { 0x00, 0x9200 },
3158
3159                 { 0x1f, 0x0005 },
3160                 { 0x01, 0x0340 },
3161                 { 0x1f, 0x0001 },
3162                 { 0x04, 0x4000 },
3163                 { 0x03, 0x1d21 },
3164                 { 0x02, 0x0c32 },
3165                 { 0x01, 0x0200 },
3166                 { 0x00, 0x5554 },
3167                 { 0x04, 0x4800 },
3168                 { 0x04, 0x4000 },
3169                 { 0x04, 0xf000 },
3170                 { 0x03, 0xdf01 },
3171                 { 0x02, 0xdf20 },
3172                 { 0x01, 0x101a },
3173                 { 0x00, 0xa0ff },
3174                 { 0x04, 0xf800 },
3175                 { 0x04, 0xf000 },
3176                 { 0x1f, 0x0000 },
3177
3178                 { 0x1f, 0x0007 },
3179                 { 0x1e, 0x0023 },
3180                 { 0x16, 0x0000 },
3181                 { 0x1f, 0x0000 }
3182         };
3183
3184         rtl_writephy_batch(tp, phy_reg_init);
3185 }
3186
3187 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3188 {
3189         static const struct phy_reg phy_reg_init[] = {
3190                 { 0x1f, 0x0001 },
3191                 { 0x17, 0x0cc0 },
3192
3193                 { 0x1f, 0x0007 },
3194                 { 0x1e, 0x002d },
3195                 { 0x18, 0x0040 },
3196                 { 0x1f, 0x0000 }
3197         };
3198
3199         rtl_writephy_batch(tp, phy_reg_init);
3200         rtl_patchphy(tp, 0x0d, 1 << 5);
3201 }
3202
3203 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3204 {
3205         static const struct phy_reg phy_reg_init[] = {
3206                 /* Enable Delay cap */
3207                 { 0x1f, 0x0005 },
3208                 { 0x05, 0x8b80 },
3209                 { 0x06, 0xc896 },
3210                 { 0x1f, 0x0000 },
3211
3212                 /* Channel estimation fine tune */
3213                 { 0x1f, 0x0001 },
3214                 { 0x0b, 0x6c20 },
3215                 { 0x07, 0x2872 },
3216                 { 0x1c, 0xefff },
3217                 { 0x1f, 0x0003 },
3218                 { 0x14, 0x6420 },
3219                 { 0x1f, 0x0000 },
3220
3221                 /* Update PFM & 10M TX idle timer */
3222                 { 0x1f, 0x0007 },
3223                 { 0x1e, 0x002f },
3224                 { 0x15, 0x1919 },
3225                 { 0x1f, 0x0000 },
3226
3227                 { 0x1f, 0x0007 },
3228                 { 0x1e, 0x00ac },
3229                 { 0x18, 0x0006 },
3230                 { 0x1f, 0x0000 }
3231         };
3232
3233         rtl_apply_firmware(tp);
3234
3235         rtl_writephy_batch(tp, phy_reg_init);
3236
3237         /* DCO enable for 10M IDLE Power */
3238         rtl_writephy(tp, 0x1f, 0x0007);
3239         rtl_writephy(tp, 0x1e, 0x0023);
3240         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3241         rtl_writephy(tp, 0x1f, 0x0000);
3242
3243         /* For impedance matching */
3244         rtl_writephy(tp, 0x1f, 0x0002);
3245         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3246         rtl_writephy(tp, 0x1f, 0x0000);
3247
3248         /* PHY auto speed down */
3249         rtl_writephy(tp, 0x1f, 0x0007);
3250         rtl_writephy(tp, 0x1e, 0x002d);
3251         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3252         rtl_writephy(tp, 0x1f, 0x0000);
3253         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3254
3255         rtl_writephy(tp, 0x1f, 0x0005);
3256         rtl_writephy(tp, 0x05, 0x8b86);
3257         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3258         rtl_writephy(tp, 0x1f, 0x0000);
3259
3260         rtl_writephy(tp, 0x1f, 0x0005);
3261         rtl_writephy(tp, 0x05, 0x8b85);
3262         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3263         rtl_writephy(tp, 0x1f, 0x0007);
3264         rtl_writephy(tp, 0x1e, 0x0020);
3265         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3266         rtl_writephy(tp, 0x1f, 0x0006);
3267         rtl_writephy(tp, 0x00, 0x5a00);
3268         rtl_writephy(tp, 0x1f, 0x0000);
3269         rtl_writephy(tp, 0x0d, 0x0007);
3270         rtl_writephy(tp, 0x0e, 0x003c);
3271         rtl_writephy(tp, 0x0d, 0x4007);
3272         rtl_writephy(tp, 0x0e, 0x0000);
3273         rtl_writephy(tp, 0x0d, 0x0000);
3274 }
3275
3276 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3277 {
3278         const u16 w[] = {
3279                 addr[0] | (addr[1] << 8),
3280                 addr[2] | (addr[3] << 8),
3281                 addr[4] | (addr[5] << 8)
3282         };
3283
3284         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3285         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3286         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3287         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3288 }
3289
3290 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3291 {
3292         static const struct phy_reg phy_reg_init[] = {
3293                 /* Enable Delay cap */
3294                 { 0x1f, 0x0004 },
3295                 { 0x1f, 0x0007 },
3296                 { 0x1e, 0x00ac },
3297                 { 0x18, 0x0006 },
3298                 { 0x1f, 0x0002 },
3299                 { 0x1f, 0x0000 },
3300                 { 0x1f, 0x0000 },
3301
3302                 /* Channel estimation fine tune */
3303                 { 0x1f, 0x0003 },
3304                 { 0x09, 0xa20f },
3305                 { 0x1f, 0x0000 },
3306                 { 0x1f, 0x0000 },
3307
3308                 /* Green Setting */
3309                 { 0x1f, 0x0005 },
3310                 { 0x05, 0x8b5b },
3311                 { 0x06, 0x9222 },
3312                 { 0x05, 0x8b6d },
3313                 { 0x06, 0x8000 },
3314                 { 0x05, 0x8b76 },
3315                 { 0x06, 0x8000 },
3316                 { 0x1f, 0x0000 }
3317         };
3318
3319         rtl_apply_firmware(tp);
3320
3321         rtl_writephy_batch(tp, phy_reg_init);
3322
3323         /* For 4-corner performance improve */
3324         rtl_writephy(tp, 0x1f, 0x0005);
3325         rtl_writephy(tp, 0x05, 0x8b80);
3326         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3327         rtl_writephy(tp, 0x1f, 0x0000);
3328
3329         /* PHY auto speed down */
3330         rtl_writephy(tp, 0x1f, 0x0004);
3331         rtl_writephy(tp, 0x1f, 0x0007);
3332         rtl_writephy(tp, 0x1e, 0x002d);
3333         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3334         rtl_writephy(tp, 0x1f, 0x0002);
3335         rtl_writephy(tp, 0x1f, 0x0000);
3336         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3337
3338         /* improve 10M EEE waveform */
3339         rtl_writephy(tp, 0x1f, 0x0005);
3340         rtl_writephy(tp, 0x05, 0x8b86);
3341         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3342         rtl_writephy(tp, 0x1f, 0x0000);
3343
3344         /* Improve 2-pair detection performance */
3345         rtl_writephy(tp, 0x1f, 0x0005);
3346         rtl_writephy(tp, 0x05, 0x8b85);
3347         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3348         rtl_writephy(tp, 0x1f, 0x0000);
3349
3350         rtl8168f_config_eee_phy(tp);
3351         rtl_enable_eee(tp);
3352
3353         /* Green feature */
3354         rtl_writephy(tp, 0x1f, 0x0003);
3355         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3356         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3357         rtl_writephy(tp, 0x1f, 0x0000);
3358         rtl_writephy(tp, 0x1f, 0x0005);
3359         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3360         rtl_writephy(tp, 0x1f, 0x0000);
3361
3362         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3363         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3364 }
3365
3366 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3367 {
3368         /* For 4-corner performance improve */
3369         rtl_writephy(tp, 0x1f, 0x0005);
3370         rtl_writephy(tp, 0x05, 0x8b80);
3371         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3372         rtl_writephy(tp, 0x1f, 0x0000);
3373
3374         /* PHY auto speed down */
3375         rtl_writephy(tp, 0x1f, 0x0007);
3376         rtl_writephy(tp, 0x1e, 0x002d);
3377         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3378         rtl_writephy(tp, 0x1f, 0x0000);
3379         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3380
3381         /* Improve 10M EEE waveform */
3382         rtl_writephy(tp, 0x1f, 0x0005);
3383         rtl_writephy(tp, 0x05, 0x8b86);
3384         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3385         rtl_writephy(tp, 0x1f, 0x0000);
3386
3387         rtl8168f_config_eee_phy(tp);
3388         rtl_enable_eee(tp);
3389 }
3390
3391 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3392 {
3393         static const struct phy_reg phy_reg_init[] = {
3394                 /* Channel estimation fine tune */
3395                 { 0x1f, 0x0003 },
3396                 { 0x09, 0xa20f },
3397                 { 0x1f, 0x0000 },
3398
3399                 /* Modify green table for giga & fnet */
3400                 { 0x1f, 0x0005 },
3401                 { 0x05, 0x8b55 },
3402                 { 0x06, 0x0000 },
3403                 { 0x05, 0x8b5e },
3404                 { 0x06, 0x0000 },
3405                 { 0x05, 0x8b67 },
3406                 { 0x06, 0x0000 },
3407                 { 0x05, 0x8b70 },
3408                 { 0x06, 0x0000 },
3409                 { 0x1f, 0x0000 },
3410                 { 0x1f, 0x0007 },
3411                 { 0x1e, 0x0078 },
3412                 { 0x17, 0x0000 },
3413                 { 0x19, 0x00fb },
3414                 { 0x1f, 0x0000 },
3415
3416                 /* Modify green table for 10M */
3417                 { 0x1f, 0x0005 },
3418                 { 0x05, 0x8b79 },
3419                 { 0x06, 0xaa00 },
3420                 { 0x1f, 0x0000 },
3421
3422                 /* Disable hiimpedance detection (RTCT) */
3423                 { 0x1f, 0x0003 },
3424                 { 0x01, 0x328a },
3425                 { 0x1f, 0x0000 }
3426         };
3427
3428         rtl_apply_firmware(tp);
3429
3430         rtl_writephy_batch(tp, phy_reg_init);
3431
3432         rtl8168f_hw_phy_config(tp);
3433
3434         /* Improve 2-pair detection performance */
3435         rtl_writephy(tp, 0x1f, 0x0005);
3436         rtl_writephy(tp, 0x05, 0x8b85);
3437         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3438         rtl_writephy(tp, 0x1f, 0x0000);
3439 }
3440
3441 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3442 {
3443         rtl_apply_firmware(tp);
3444
3445         rtl8168f_hw_phy_config(tp);
3446 }
3447
3448 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3449 {
3450         static const struct phy_reg phy_reg_init[] = {
3451                 /* Channel estimation fine tune */
3452                 { 0x1f, 0x0003 },
3453                 { 0x09, 0xa20f },
3454                 { 0x1f, 0x0000 },
3455
3456                 /* Modify green table for giga & fnet */
3457                 { 0x1f, 0x0005 },
3458                 { 0x05, 0x8b55 },
3459                 { 0x06, 0x0000 },
3460                 { 0x05, 0x8b5e },
3461                 { 0x06, 0x0000 },
3462                 { 0x05, 0x8b67 },
3463                 { 0x06, 0x0000 },
3464                 { 0x05, 0x8b70 },
3465                 { 0x06, 0x0000 },
3466                 { 0x1f, 0x0000 },
3467                 { 0x1f, 0x0007 },
3468                 { 0x1e, 0x0078 },
3469                 { 0x17, 0x0000 },
3470                 { 0x19, 0x00aa },
3471                 { 0x1f, 0x0000 },
3472
3473                 /* Modify green table for 10M */
3474                 { 0x1f, 0x0005 },
3475                 { 0x05, 0x8b79 },
3476                 { 0x06, 0xaa00 },
3477                 { 0x1f, 0x0000 },
3478
3479                 /* Disable hiimpedance detection (RTCT) */
3480                 { 0x1f, 0x0003 },
3481                 { 0x01, 0x328a },
3482                 { 0x1f, 0x0000 }
3483         };
3484
3485
3486         rtl_apply_firmware(tp);
3487
3488         rtl8168f_hw_phy_config(tp);
3489
3490         /* Improve 2-pair detection performance */
3491         rtl_writephy(tp, 0x1f, 0x0005);
3492         rtl_writephy(tp, 0x05, 0x8b85);
3493         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3494         rtl_writephy(tp, 0x1f, 0x0000);
3495
3496         rtl_writephy_batch(tp, phy_reg_init);
3497
3498         /* Modify green table for giga */
3499         rtl_writephy(tp, 0x1f, 0x0005);
3500         rtl_writephy(tp, 0x05, 0x8b54);
3501         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3502         rtl_writephy(tp, 0x05, 0x8b5d);
3503         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3504         rtl_writephy(tp, 0x05, 0x8a7c);
3505         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3506         rtl_writephy(tp, 0x05, 0x8a7f);
3507         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3508         rtl_writephy(tp, 0x05, 0x8a82);
3509         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3510         rtl_writephy(tp, 0x05, 0x8a85);
3511         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3512         rtl_writephy(tp, 0x05, 0x8a88);
3513         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3514         rtl_writephy(tp, 0x1f, 0x0000);
3515
3516         /* uc same-seed solution */
3517         rtl_writephy(tp, 0x1f, 0x0005);
3518         rtl_writephy(tp, 0x05, 0x8b85);
3519         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3520         rtl_writephy(tp, 0x1f, 0x0000);
3521
3522         /* Green feature */
3523         rtl_writephy(tp, 0x1f, 0x0003);
3524         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3525         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3526         rtl_writephy(tp, 0x1f, 0x0000);
3527 }
3528
3529 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3530 {
3531         phy_write(tp->phydev, 0x1f, 0x0a43);
3532         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3533 }
3534
3535 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3536 {
3537         struct phy_device *phydev = tp->phydev;
3538
3539         phy_write(phydev, 0x1f, 0x0bcc);
3540         phy_clear_bits(phydev, 0x14, BIT(8));
3541
3542         phy_write(phydev, 0x1f, 0x0a44);
3543         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3544
3545         phy_write(phydev, 0x1f, 0x0a43);
3546         phy_write(phydev, 0x13, 0x8084);
3547         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3548         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3549
3550         phy_write(phydev, 0x1f, 0x0000);
3551 }
3552
3553 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3554 {
3555         rtl_apply_firmware(tp);
3556
3557         rtl_writephy(tp, 0x1f, 0x0a46);
3558         if (rtl_readphy(tp, 0x10) & 0x0100) {
3559                 rtl_writephy(tp, 0x1f, 0x0bcc);
3560                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3561         } else {
3562                 rtl_writephy(tp, 0x1f, 0x0bcc);
3563                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3564         }
3565
3566         rtl_writephy(tp, 0x1f, 0x0a46);
3567         if (rtl_readphy(tp, 0x13) & 0x0100) {
3568                 rtl_writephy(tp, 0x1f, 0x0c41);
3569                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3570         } else {
3571                 rtl_writephy(tp, 0x1f, 0x0c41);
3572                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3573         }
3574
3575         /* Enable PHY auto speed down */
3576         rtl_writephy(tp, 0x1f, 0x0a44);
3577         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3578
3579         rtl8168g_phy_adjust_10m_aldps(tp);
3580
3581         /* EEE auto-fallback function */
3582         rtl_writephy(tp, 0x1f, 0x0a4b);
3583         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3584
3585         /* Enable UC LPF tune function */
3586         rtl_writephy(tp, 0x1f, 0x0a43);
3587         rtl_writephy(tp, 0x13, 0x8012);
3588         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3589
3590         rtl_writephy(tp, 0x1f, 0x0c42);
3591         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3592
3593         /* Improve SWR Efficiency */
3594         rtl_writephy(tp, 0x1f, 0x0bcd);
3595         rtl_writephy(tp, 0x14, 0x5065);
3596         rtl_writephy(tp, 0x14, 0xd065);
3597         rtl_writephy(tp, 0x1f, 0x0bc8);
3598         rtl_writephy(tp, 0x11, 0x5655);
3599         rtl_writephy(tp, 0x1f, 0x0bcd);
3600         rtl_writephy(tp, 0x14, 0x1065);
3601         rtl_writephy(tp, 0x14, 0x9065);
3602         rtl_writephy(tp, 0x14, 0x1065);
3603
3604         rtl8168g_disable_aldps(tp);
3605         rtl8168g_config_eee_phy(tp);
3606         rtl_enable_eee(tp);
3607 }
3608
3609 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3610 {
3611         rtl_apply_firmware(tp);
3612         rtl8168g_config_eee_phy(tp);
3613         rtl_enable_eee(tp);
3614 }
3615
3616 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3617 {
3618         u16 dout_tapbin;
3619         u32 data;
3620
3621         rtl_apply_firmware(tp);
3622
3623         /* CHN EST parameters adjust - giga master */
3624         rtl_writephy(tp, 0x1f, 0x0a43);
3625         rtl_writephy(tp, 0x13, 0x809b);
3626         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3627         rtl_writephy(tp, 0x13, 0x80a2);
3628         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3629         rtl_writephy(tp, 0x13, 0x80a4);
3630         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3631         rtl_writephy(tp, 0x13, 0x809c);
3632         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3633         rtl_writephy(tp, 0x1f, 0x0000);
3634
3635         /* CHN EST parameters adjust - giga slave */
3636         rtl_writephy(tp, 0x1f, 0x0a43);
3637         rtl_writephy(tp, 0x13, 0x80ad);
3638         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3639         rtl_writephy(tp, 0x13, 0x80b4);
3640         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3641         rtl_writephy(tp, 0x13, 0x80ac);
3642         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3643         rtl_writephy(tp, 0x1f, 0x0000);
3644
3645         /* CHN EST parameters adjust - fnet */
3646         rtl_writephy(tp, 0x1f, 0x0a43);
3647         rtl_writephy(tp, 0x13, 0x808e);
3648         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3649         rtl_writephy(tp, 0x13, 0x8090);
3650         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3651         rtl_writephy(tp, 0x13, 0x8092);
3652         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3653         rtl_writephy(tp, 0x1f, 0x0000);
3654
3655         /* enable R-tune & PGA-retune function */
3656         dout_tapbin = 0;
3657         rtl_writephy(tp, 0x1f, 0x0a46);
3658         data = rtl_readphy(tp, 0x13);
3659         data &= 3;
3660         data <<= 2;
3661         dout_tapbin |= data;
3662         data = rtl_readphy(tp, 0x12);
3663         data &= 0xc000;
3664         data >>= 14;
3665         dout_tapbin |= data;
3666         dout_tapbin = ~(dout_tapbin^0x08);
3667         dout_tapbin <<= 12;
3668         dout_tapbin &= 0xf000;
3669         rtl_writephy(tp, 0x1f, 0x0a43);
3670         rtl_writephy(tp, 0x13, 0x827a);
3671         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3672         rtl_writephy(tp, 0x13, 0x827b);
3673         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3674         rtl_writephy(tp, 0x13, 0x827c);
3675         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3676         rtl_writephy(tp, 0x13, 0x827d);
3677         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3678
3679         rtl_writephy(tp, 0x1f, 0x0a43);
3680         rtl_writephy(tp, 0x13, 0x0811);
3681         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3682         rtl_writephy(tp, 0x1f, 0x0a42);
3683         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3684         rtl_writephy(tp, 0x1f, 0x0000);
3685
3686         /* enable GPHY 10M */
3687         rtl_writephy(tp, 0x1f, 0x0a44);
3688         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3689         rtl_writephy(tp, 0x1f, 0x0000);
3690
3691         /* SAR ADC performance */
3692         rtl_writephy(tp, 0x1f, 0x0bca);
3693         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3694         rtl_writephy(tp, 0x1f, 0x0000);
3695
3696         rtl_writephy(tp, 0x1f, 0x0a43);
3697         rtl_writephy(tp, 0x13, 0x803f);
3698         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3699         rtl_writephy(tp, 0x13, 0x8047);
3700         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3701         rtl_writephy(tp, 0x13, 0x804f);
3702         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3703         rtl_writephy(tp, 0x13, 0x8057);
3704         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3705         rtl_writephy(tp, 0x13, 0x805f);
3706         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3707         rtl_writephy(tp, 0x13, 0x8067);
3708         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3709         rtl_writephy(tp, 0x13, 0x806f);
3710         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3711         rtl_writephy(tp, 0x1f, 0x0000);
3712
3713         /* disable phy pfm mode */
3714         rtl_writephy(tp, 0x1f, 0x0a44);
3715         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3716         rtl_writephy(tp, 0x1f, 0x0000);
3717
3718         rtl8168g_disable_aldps(tp);
3719         rtl8168g_config_eee_phy(tp);
3720         rtl_enable_eee(tp);
3721 }
3722
3723 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3724 {
3725         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3726         u16 rlen;
3727         u32 data;
3728
3729         rtl_apply_firmware(tp);
3730
3731         /* CHIN EST parameter update */
3732         rtl_writephy(tp, 0x1f, 0x0a43);
3733         rtl_writephy(tp, 0x13, 0x808a);
3734         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3735         rtl_writephy(tp, 0x1f, 0x0000);
3736
3737         /* enable R-tune & PGA-retune function */
3738         rtl_writephy(tp, 0x1f, 0x0a43);
3739         rtl_writephy(tp, 0x13, 0x0811);
3740         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3741         rtl_writephy(tp, 0x1f, 0x0a42);
3742         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3743         rtl_writephy(tp, 0x1f, 0x0000);
3744
3745         /* enable GPHY 10M */
3746         rtl_writephy(tp, 0x1f, 0x0a44);
3747         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3748         rtl_writephy(tp, 0x1f, 0x0000);
3749
3750         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3751         data = r8168_mac_ocp_read(tp, 0xdd02);
3752         ioffset_p3 = ((data & 0x80)>>7);
3753         ioffset_p3 <<= 3;
3754
3755         data = r8168_mac_ocp_read(tp, 0xdd00);
3756         ioffset_p3 |= ((data & (0xe000))>>13);
3757         ioffset_p2 = ((data & (0x1e00))>>9);
3758         ioffset_p1 = ((data & (0x01e0))>>5);
3759         ioffset_p0 = ((data & 0x0010)>>4);
3760         ioffset_p0 <<= 3;
3761         ioffset_p0 |= (data & (0x07));
3762         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3763
3764         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3765             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3766                 rtl_writephy(tp, 0x1f, 0x0bcf);
3767                 rtl_writephy(tp, 0x16, data);
3768                 rtl_writephy(tp, 0x1f, 0x0000);
3769         }
3770
3771         /* Modify rlen (TX LPF corner frequency) level */
3772         rtl_writephy(tp, 0x1f, 0x0bcd);
3773         data = rtl_readphy(tp, 0x16);
3774         data &= 0x000f;
3775         rlen = 0;
3776         if (data > 3)
3777                 rlen = data - 3;
3778         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3779         rtl_writephy(tp, 0x17, data);
3780         rtl_writephy(tp, 0x1f, 0x0bcd);
3781         rtl_writephy(tp, 0x1f, 0x0000);
3782
3783         /* disable phy pfm mode */
3784         rtl_writephy(tp, 0x1f, 0x0a44);
3785         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3786         rtl_writephy(tp, 0x1f, 0x0000);
3787
3788         rtl8168g_disable_aldps(tp);
3789         rtl8168g_config_eee_phy(tp);
3790         rtl_enable_eee(tp);
3791 }
3792
3793 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3794 {
3795         /* Enable PHY auto speed down */
3796         rtl_writephy(tp, 0x1f, 0x0a44);
3797         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3798         rtl_writephy(tp, 0x1f, 0x0000);
3799
3800         rtl8168g_phy_adjust_10m_aldps(tp);
3801
3802         /* Enable EEE auto-fallback function */
3803         rtl_writephy(tp, 0x1f, 0x0a4b);
3804         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3805         rtl_writephy(tp, 0x1f, 0x0000);
3806
3807         /* Enable UC LPF tune function */
3808         rtl_writephy(tp, 0x1f, 0x0a43);
3809         rtl_writephy(tp, 0x13, 0x8012);
3810         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3811         rtl_writephy(tp, 0x1f, 0x0000);
3812
3813         /* set rg_sel_sdm_rate */
3814         rtl_writephy(tp, 0x1f, 0x0c42);
3815         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3816         rtl_writephy(tp, 0x1f, 0x0000);
3817
3818         rtl8168g_disable_aldps(tp);
3819         rtl8168g_config_eee_phy(tp);
3820         rtl_enable_eee(tp);
3821 }
3822
3823 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3824 {
3825         rtl8168g_phy_adjust_10m_aldps(tp);
3826
3827         /* Enable UC LPF tune function */
3828         rtl_writephy(tp, 0x1f, 0x0a43);
3829         rtl_writephy(tp, 0x13, 0x8012);
3830         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3831         rtl_writephy(tp, 0x1f, 0x0000);
3832
3833         /* Set rg_sel_sdm_rate */
3834         rtl_writephy(tp, 0x1f, 0x0c42);
3835         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3836         rtl_writephy(tp, 0x1f, 0x0000);
3837
3838         /* Channel estimation parameters */
3839         rtl_writephy(tp, 0x1f, 0x0a43);
3840         rtl_writephy(tp, 0x13, 0x80f3);
3841         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3842         rtl_writephy(tp, 0x13, 0x80f0);
3843         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3844         rtl_writephy(tp, 0x13, 0x80ef);
3845         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3846         rtl_writephy(tp, 0x13, 0x80f6);
3847         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3848         rtl_writephy(tp, 0x13, 0x80ec);
3849         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3850         rtl_writephy(tp, 0x13, 0x80ed);
3851         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3852         rtl_writephy(tp, 0x13, 0x80f2);
3853         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3854         rtl_writephy(tp, 0x13, 0x80f4);
3855         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3856         rtl_writephy(tp, 0x1f, 0x0a43);
3857         rtl_writephy(tp, 0x13, 0x8110);
3858         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3859         rtl_writephy(tp, 0x13, 0x810f);
3860         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3861         rtl_writephy(tp, 0x13, 0x8111);
3862         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3863         rtl_writephy(tp, 0x13, 0x8113);
3864         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3865         rtl_writephy(tp, 0x13, 0x8115);
3866         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3867         rtl_writephy(tp, 0x13, 0x810e);
3868         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3869         rtl_writephy(tp, 0x13, 0x810c);
3870         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3871         rtl_writephy(tp, 0x13, 0x810b);
3872         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3873         rtl_writephy(tp, 0x1f, 0x0a43);
3874         rtl_writephy(tp, 0x13, 0x80d1);
3875         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3876         rtl_writephy(tp, 0x13, 0x80cd);
3877         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3878         rtl_writephy(tp, 0x13, 0x80d3);
3879         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3880         rtl_writephy(tp, 0x13, 0x80d5);
3881         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3882         rtl_writephy(tp, 0x13, 0x80d7);
3883         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3884
3885         /* Force PWM-mode */
3886         rtl_writephy(tp, 0x1f, 0x0bcd);
3887         rtl_writephy(tp, 0x14, 0x5065);
3888         rtl_writephy(tp, 0x14, 0xd065);
3889         rtl_writephy(tp, 0x1f, 0x0bc8);
3890         rtl_writephy(tp, 0x12, 0x00ed);
3891         rtl_writephy(tp, 0x1f, 0x0bcd);
3892         rtl_writephy(tp, 0x14, 0x1065);
3893         rtl_writephy(tp, 0x14, 0x9065);
3894         rtl_writephy(tp, 0x14, 0x1065);
3895         rtl_writephy(tp, 0x1f, 0x0000);
3896
3897         rtl8168g_disable_aldps(tp);
3898         rtl8168g_config_eee_phy(tp);
3899         rtl_enable_eee(tp);
3900 }
3901
3902 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3903 {
3904         static const struct phy_reg phy_reg_init[] = {
3905                 { 0x1f, 0x0003 },
3906                 { 0x08, 0x441d },
3907                 { 0x01, 0x9100 },
3908                 { 0x1f, 0x0000 }
3909         };
3910
3911         rtl_writephy(tp, 0x1f, 0x0000);
3912         rtl_patchphy(tp, 0x11, 1 << 12);
3913         rtl_patchphy(tp, 0x19, 1 << 13);
3914         rtl_patchphy(tp, 0x10, 1 << 15);
3915
3916         rtl_writephy_batch(tp, phy_reg_init);
3917 }
3918
3919 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3920 {
3921         static const struct phy_reg phy_reg_init[] = {
3922                 { 0x1f, 0x0005 },
3923                 { 0x1a, 0x0000 },
3924                 { 0x1f, 0x0000 },
3925
3926                 { 0x1f, 0x0004 },
3927                 { 0x1c, 0x0000 },
3928                 { 0x1f, 0x0000 },
3929
3930                 { 0x1f, 0x0001 },
3931                 { 0x15, 0x7701 },
3932                 { 0x1f, 0x0000 }
3933         };
3934
3935         /* Disable ALDPS before ram code */
3936         rtl_writephy(tp, 0x1f, 0x0000);
3937         rtl_writephy(tp, 0x18, 0x0310);
3938         msleep(100);
3939
3940         rtl_apply_firmware(tp);
3941
3942         rtl_writephy_batch(tp, phy_reg_init);
3943 }
3944
3945 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3946 {
3947         /* Disable ALDPS before setting firmware */
3948         rtl_writephy(tp, 0x1f, 0x0000);
3949         rtl_writephy(tp, 0x18, 0x0310);
3950         msleep(20);
3951
3952         rtl_apply_firmware(tp);
3953
3954         /* EEE setting */
3955         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3956         rtl_writephy(tp, 0x1f, 0x0004);
3957         rtl_writephy(tp, 0x10, 0x401f);
3958         rtl_writephy(tp, 0x19, 0x7030);
3959         rtl_writephy(tp, 0x1f, 0x0000);
3960 }
3961
3962 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3963 {
3964         static const struct phy_reg phy_reg_init[] = {
3965                 { 0x1f, 0x0004 },
3966                 { 0x10, 0xc07f },
3967                 { 0x19, 0x7030 },
3968                 { 0x1f, 0x0000 }
3969         };
3970
3971         /* Disable ALDPS before ram code */
3972         rtl_writephy(tp, 0x1f, 0x0000);
3973         rtl_writephy(tp, 0x18, 0x0310);
3974         msleep(100);
3975
3976         rtl_apply_firmware(tp);
3977
3978         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3979         rtl_writephy_batch(tp, phy_reg_init);
3980
3981         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3982 }
3983
3984 static void rtl_hw_phy_config(struct net_device *dev)
3985 {
3986         static const rtl_generic_fct phy_configs[] = {
3987                 /* PCI devices. */
3988                 [RTL_GIGA_MAC_VER_01] = NULL,
3989                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3990                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3991                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3992                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3993                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3994                 /* PCI-E devices. */
3995                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3996                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3997                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3998                 [RTL_GIGA_MAC_VER_10] = NULL,
3999                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
4000                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
4001                 [RTL_GIGA_MAC_VER_13] = NULL,
4002                 [RTL_GIGA_MAC_VER_14] = NULL,
4003                 [RTL_GIGA_MAC_VER_15] = NULL,
4004                 [RTL_GIGA_MAC_VER_16] = NULL,
4005                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
4006                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
4007                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
4008                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
4009                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
4010                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
4011                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
4012                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
4013                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
4014                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
4015                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
4016                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
4017                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
4018                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
4019                 [RTL_GIGA_MAC_VER_31] = NULL,
4020                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
4021                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
4022                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
4023                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
4024                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
4025                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
4026                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
4027                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
4028                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
4029                 [RTL_GIGA_MAC_VER_41] = NULL,
4030                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
4031                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
4032                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
4033                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
4034                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
4035                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
4036                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
4037                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
4038                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
4039                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
4040         };
4041         struct rtl8169_private *tp = netdev_priv(dev);
4042
4043         if (phy_configs[tp->mac_version])
4044                 phy_configs[tp->mac_version](tp);
4045 }
4046
4047 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4048 {
4049         if (!test_and_set_bit(flag, tp->wk.flags))
4050                 schedule_work(&tp->wk.work);
4051 }
4052
4053 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4054 {
4055         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4056                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4057 }
4058
4059 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4060 {
4061         rtl_hw_phy_config(dev);
4062
4063         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4064                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4065                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4066                 netif_dbg(tp, drv, dev,
4067                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4068                 RTL_W8(tp, 0x82, 0x01);
4069         }
4070
4071         /* We may have called phy_speed_down before */
4072         phy_speed_up(tp->phydev);
4073
4074         genphy_soft_reset(tp->phydev);
4075 }
4076
4077 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4078 {
4079         rtl_lock_work(tp);
4080
4081         rtl_unlock_config_regs(tp);
4082
4083         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4084         RTL_R32(tp, MAC4);
4085
4086         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4087         RTL_R32(tp, MAC0);
4088
4089         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4090                 rtl_rar_exgmac_set(tp, addr);
4091
4092         rtl_lock_config_regs(tp);
4093
4094         rtl_unlock_work(tp);
4095 }
4096
4097 static int rtl_set_mac_address(struct net_device *dev, void *p)
4098 {
4099         struct rtl8169_private *tp = netdev_priv(dev);
4100         struct device *d = tp_to_dev(tp);
4101         int ret;
4102
4103         ret = eth_mac_addr(dev, p);
4104         if (ret)
4105                 return ret;
4106
4107         pm_runtime_get_noresume(d);
4108
4109         if (pm_runtime_active(d))
4110                 rtl_rar_set(tp, dev->dev_addr);
4111
4112         pm_runtime_put_noidle(d);
4113
4114         return 0;
4115 }
4116
4117 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4118 {
4119         struct rtl8169_private *tp = netdev_priv(dev);
4120
4121         if (!netif_running(dev))
4122                 return -ENODEV;
4123
4124         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4125 }
4126
4127 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4128 {
4129         struct mdio_ops *ops = &tp->mdio_ops;
4130
4131         switch (tp->mac_version) {
4132         case RTL_GIGA_MAC_VER_27:
4133                 ops->write      = r8168dp_1_mdio_write;
4134                 ops->read       = r8168dp_1_mdio_read;
4135                 break;
4136         case RTL_GIGA_MAC_VER_28:
4137         case RTL_GIGA_MAC_VER_31:
4138                 ops->write      = r8168dp_2_mdio_write;
4139                 ops->read       = r8168dp_2_mdio_read;
4140                 break;
4141         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4142                 ops->write      = r8168g_mdio_write;
4143                 ops->read       = r8168g_mdio_read;
4144                 break;
4145         default:
4146                 ops->write      = r8169_mdio_write;
4147                 ops->read       = r8169_mdio_read;
4148                 break;
4149         }
4150 }
4151
4152 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4153 {
4154         switch (tp->mac_version) {
4155         case RTL_GIGA_MAC_VER_25:
4156         case RTL_GIGA_MAC_VER_26:
4157         case RTL_GIGA_MAC_VER_29:
4158         case RTL_GIGA_MAC_VER_30:
4159         case RTL_GIGA_MAC_VER_32:
4160         case RTL_GIGA_MAC_VER_33:
4161         case RTL_GIGA_MAC_VER_34:
4162         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4163                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4164                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4165                 break;
4166         default:
4167                 break;
4168         }
4169 }
4170
4171 static void r8168_pll_power_down(struct rtl8169_private *tp)
4172 {
4173         if (r8168_check_dash(tp))
4174                 return;
4175
4176         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4177             tp->mac_version == RTL_GIGA_MAC_VER_33)
4178                 rtl_ephy_write(tp, 0x19, 0xff64);
4179
4180         if (device_may_wakeup(tp_to_dev(tp))) {
4181                 phy_speed_down(tp->phydev, false);
4182                 rtl_wol_suspend_quirk(tp);
4183                 return;
4184         }
4185
4186         switch (tp->mac_version) {
4187         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4188         case RTL_GIGA_MAC_VER_37:
4189         case RTL_GIGA_MAC_VER_39:
4190         case RTL_GIGA_MAC_VER_43:
4191         case RTL_GIGA_MAC_VER_44:
4192         case RTL_GIGA_MAC_VER_45:
4193         case RTL_GIGA_MAC_VER_46:
4194         case RTL_GIGA_MAC_VER_47:
4195         case RTL_GIGA_MAC_VER_48:
4196         case RTL_GIGA_MAC_VER_50:
4197         case RTL_GIGA_MAC_VER_51:
4198                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4199                 break;
4200         case RTL_GIGA_MAC_VER_40:
4201         case RTL_GIGA_MAC_VER_41:
4202         case RTL_GIGA_MAC_VER_49:
4203                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4204                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4205                 break;
4206         }
4207 }
4208
4209 static void r8168_pll_power_up(struct rtl8169_private *tp)
4210 {
4211         switch (tp->mac_version) {
4212         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4213         case RTL_GIGA_MAC_VER_37:
4214         case RTL_GIGA_MAC_VER_39:
4215         case RTL_GIGA_MAC_VER_43:
4216                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4217                 break;
4218         case RTL_GIGA_MAC_VER_44:
4219         case RTL_GIGA_MAC_VER_45:
4220         case RTL_GIGA_MAC_VER_46:
4221         case RTL_GIGA_MAC_VER_47:
4222         case RTL_GIGA_MAC_VER_48:
4223         case RTL_GIGA_MAC_VER_50:
4224         case RTL_GIGA_MAC_VER_51:
4225                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4226                 break;
4227         case RTL_GIGA_MAC_VER_40:
4228         case RTL_GIGA_MAC_VER_41:
4229         case RTL_GIGA_MAC_VER_49:
4230                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4231                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4232                 break;
4233         }
4234
4235         phy_resume(tp->phydev);
4236         /* give MAC/PHY some time to resume */
4237         msleep(20);
4238 }
4239
4240 static void rtl_pll_power_down(struct rtl8169_private *tp)
4241 {
4242         switch (tp->mac_version) {
4243         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4244         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4245                 break;
4246         default:
4247                 r8168_pll_power_down(tp);
4248         }
4249 }
4250
4251 static void rtl_pll_power_up(struct rtl8169_private *tp)
4252 {
4253         switch (tp->mac_version) {
4254         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4255         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4256                 break;
4257         default:
4258                 r8168_pll_power_up(tp);
4259         }
4260 }
4261
4262 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4263 {
4264         switch (tp->mac_version) {
4265         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4266         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4267                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4268                 break;
4269         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4270         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4271         case RTL_GIGA_MAC_VER_38:
4272                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4273                 break;
4274         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4275                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4276                 break;
4277         default:
4278                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4279                 break;
4280         }
4281 }
4282
4283 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4284 {
4285         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4286 }
4287
4288 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4289 {
4290         if (tp->jumbo_ops.enable) {
4291                 rtl_unlock_config_regs(tp);
4292                 tp->jumbo_ops.enable(tp);
4293                 rtl_lock_config_regs(tp);
4294         }
4295 }
4296
4297 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4298 {
4299         if (tp->jumbo_ops.disable) {
4300                 rtl_unlock_config_regs(tp);
4301                 tp->jumbo_ops.disable(tp);
4302                 rtl_lock_config_regs(tp);
4303         }
4304 }
4305
4306 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4307 {
4308         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4309         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4310         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4311 }
4312
4313 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4314 {
4315         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4316         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4317         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4318 }
4319
4320 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4321 {
4322         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4323 }
4324
4325 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4326 {
4327         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4328 }
4329
4330 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4331 {
4332         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4333         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4334         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4335         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4336 }
4337
4338 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4339 {
4340         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4341         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4342         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4343         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4344 }
4345
4346 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4347 {
4348         rtl_tx_performance_tweak(tp,
4349                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4350 }
4351
4352 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4353 {
4354         rtl_tx_performance_tweak(tp,
4355                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4356 }
4357
4358 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4359 {
4360         r8168b_0_hw_jumbo_enable(tp);
4361
4362         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4363 }
4364
4365 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4366 {
4367         r8168b_0_hw_jumbo_disable(tp);
4368
4369         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4370 }
4371
4372 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4373 {
4374         struct jumbo_ops *ops = &tp->jumbo_ops;
4375
4376         switch (tp->mac_version) {
4377         case RTL_GIGA_MAC_VER_11:
4378                 ops->disable    = r8168b_0_hw_jumbo_disable;
4379                 ops->enable     = r8168b_0_hw_jumbo_enable;
4380                 break;
4381         case RTL_GIGA_MAC_VER_12:
4382         case RTL_GIGA_MAC_VER_17:
4383                 ops->disable    = r8168b_1_hw_jumbo_disable;
4384                 ops->enable     = r8168b_1_hw_jumbo_enable;
4385                 break;
4386         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4387         case RTL_GIGA_MAC_VER_19:
4388         case RTL_GIGA_MAC_VER_20:
4389         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4390         case RTL_GIGA_MAC_VER_22:
4391         case RTL_GIGA_MAC_VER_23:
4392         case RTL_GIGA_MAC_VER_24:
4393         case RTL_GIGA_MAC_VER_25:
4394         case RTL_GIGA_MAC_VER_26:
4395                 ops->disable    = r8168c_hw_jumbo_disable;
4396                 ops->enable     = r8168c_hw_jumbo_enable;
4397                 break;
4398         case RTL_GIGA_MAC_VER_27:
4399         case RTL_GIGA_MAC_VER_28:
4400                 ops->disable    = r8168dp_hw_jumbo_disable;
4401                 ops->enable     = r8168dp_hw_jumbo_enable;
4402                 break;
4403         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4404         case RTL_GIGA_MAC_VER_32:
4405         case RTL_GIGA_MAC_VER_33:
4406         case RTL_GIGA_MAC_VER_34:
4407                 ops->disable    = r8168e_hw_jumbo_disable;
4408                 ops->enable     = r8168e_hw_jumbo_enable;
4409                 break;
4410
4411         /*
4412          * No action needed for jumbo frames with 8169.
4413          * No jumbo for 810x at all.
4414          */
4415         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4416         default:
4417                 ops->disable    = NULL;
4418                 ops->enable     = NULL;
4419                 break;
4420         }
4421 }
4422
4423 DECLARE_RTL_COND(rtl_chipcmd_cond)
4424 {
4425         return RTL_R8(tp, ChipCmd) & CmdReset;
4426 }
4427
4428 static void rtl_hw_reset(struct rtl8169_private *tp)
4429 {
4430         RTL_W8(tp, ChipCmd, CmdReset);
4431
4432         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4433 }
4434
4435 static void rtl_request_firmware(struct rtl8169_private *tp)
4436 {
4437         struct rtl_fw *rtl_fw;
4438         int rc = -ENOMEM;
4439
4440         /* firmware loaded already or no firmware available */
4441         if (tp->rtl_fw || !tp->fw_name)
4442                 return;
4443
4444         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4445         if (!rtl_fw)
4446                 goto err_warn;
4447
4448         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4449         if (rc < 0)
4450                 goto err_free;
4451
4452         rc = rtl_check_firmware(tp, rtl_fw);
4453         if (rc < 0)
4454                 goto err_release_firmware;
4455
4456         tp->rtl_fw = rtl_fw;
4457
4458         return;
4459
4460 err_release_firmware:
4461         release_firmware(rtl_fw->fw);
4462 err_free:
4463         kfree(rtl_fw);
4464 err_warn:
4465         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4466                    tp->fw_name, rc);
4467 }
4468
4469 static void rtl_rx_close(struct rtl8169_private *tp)
4470 {
4471         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4472 }
4473
4474 DECLARE_RTL_COND(rtl_npq_cond)
4475 {
4476         return RTL_R8(tp, TxPoll) & NPQ;
4477 }
4478
4479 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4480 {
4481         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4482 }
4483
4484 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4485 {
4486         /* Disable interrupts */
4487         rtl8169_irq_mask_and_ack(tp);
4488
4489         rtl_rx_close(tp);
4490
4491         switch (tp->mac_version) {
4492         case RTL_GIGA_MAC_VER_27:
4493         case RTL_GIGA_MAC_VER_28:
4494         case RTL_GIGA_MAC_VER_31:
4495                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4496                 break;
4497         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4498         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4499                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4500                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4501                 break;
4502         default:
4503                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4504                 udelay(100);
4505                 break;
4506         }
4507
4508         rtl_hw_reset(tp);
4509 }
4510
4511 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4512 {
4513         u32 val = TX_DMA_BURST << TxDMAShift |
4514                   InterFrameGap << TxInterFrameGapShift;
4515
4516         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4517             tp->mac_version != RTL_GIGA_MAC_VER_39)
4518                 val |= TXCFG_AUTO_FIFO;
4519
4520         RTL_W32(tp, TxConfig, val);
4521 }
4522
4523 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4524 {
4525         /* Low hurts. Let's disable the filtering. */
4526         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4527 }
4528
4529 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4530 {
4531         /*
4532          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4533          * register to be written before TxDescAddrLow to work.
4534          * Switching from MMIO to I/O access fixes the issue as well.
4535          */
4536         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4537         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4538         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4539         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4540 }
4541
4542 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4543 {
4544         u32 val;
4545
4546         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4547                 val = 0x000fff00;
4548         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4549                 val = 0x00ffff00;
4550         else
4551                 return;
4552
4553         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4554                 val |= 0xff;
4555
4556         RTL_W32(tp, 0x7c, val);
4557 }
4558
4559 static void rtl_set_rx_mode(struct net_device *dev)
4560 {
4561         struct rtl8169_private *tp = netdev_priv(dev);
4562         u32 mc_filter[2];       /* Multicast hash filter */
4563         int rx_mode;
4564         u32 tmp = 0;
4565
4566         if (dev->flags & IFF_PROMISC) {
4567                 /* Unconditionally log net taps. */
4568                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4569                 rx_mode =
4570                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4571                     AcceptAllPhys;
4572                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4573         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4574                    (dev->flags & IFF_ALLMULTI)) {
4575                 /* Too many to filter perfectly -- accept all multicasts. */
4576                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4577                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4578         } else {
4579                 struct netdev_hw_addr *ha;
4580
4581                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4582                 mc_filter[1] = mc_filter[0] = 0;
4583                 netdev_for_each_mc_addr(ha, dev) {
4584                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4585                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4586                         rx_mode |= AcceptMulticast;
4587                 }
4588         }
4589
4590         if (dev->features & NETIF_F_RXALL)
4591                 rx_mode |= (AcceptErr | AcceptRunt);
4592
4593         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4594
4595         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4596                 u32 data = mc_filter[0];
4597
4598                 mc_filter[0] = swab32(mc_filter[1]);
4599                 mc_filter[1] = swab32(data);
4600         }
4601
4602         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4603                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4604
4605         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4606         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4607
4608         RTL_W32(tp, RxConfig, tmp);
4609 }
4610
4611 static void rtl_hw_start(struct  rtl8169_private *tp)
4612 {
4613         rtl_unlock_config_regs(tp);
4614
4615         tp->hw_start(tp);
4616
4617         rtl_set_rx_max_size(tp);
4618         rtl_set_rx_tx_desc_registers(tp);
4619         rtl_lock_config_regs(tp);
4620
4621         /* disable interrupt coalescing */
4622         RTL_W16(tp, IntrMitigate, 0x0000);
4623         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4624         RTL_R8(tp, IntrMask);
4625         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4626         rtl_init_rxcfg(tp);
4627         rtl_set_tx_config_registers(tp);
4628
4629         rtl_set_rx_mode(tp->dev);
4630         /* no early-rx interrupts */
4631         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4632         rtl_irq_enable(tp);
4633 }
4634
4635 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4636 {
4637         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4638                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4639
4640         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4641
4642         tp->cp_cmd |= PCIMulRW;
4643
4644         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4645             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4646                 netif_dbg(tp, drv, tp->dev,
4647                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4648                 tp->cp_cmd |= (1 << 14);
4649         }
4650
4651         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4652
4653         rtl8169_set_magic_reg(tp, tp->mac_version);
4654
4655         RTL_W32(tp, RxMissed, 0);
4656 }
4657
4658 DECLARE_RTL_COND(rtl_csiar_cond)
4659 {
4660         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4661 }
4662
4663 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4664 {
4665         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4666
4667         RTL_W32(tp, CSIDR, value);
4668         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4669                 CSIAR_BYTE_ENABLE | func << 16);
4670
4671         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4672 }
4673
4674 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4675 {
4676         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4677
4678         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4679                 CSIAR_BYTE_ENABLE);
4680
4681         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4682                 RTL_R32(tp, CSIDR) : ~0;
4683 }
4684
4685 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4686 {
4687         struct pci_dev *pdev = tp->pci_dev;
4688         u32 csi;
4689
4690         /* According to Realtek the value at config space address 0x070f
4691          * controls the L0s/L1 entrance latency. We try standard ECAM access
4692          * first and if it fails fall back to CSI.
4693          */
4694         if (pdev->cfg_size > 0x070f &&
4695             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4696                 return;
4697
4698         netdev_notice_once(tp->dev,
4699                 "No native access to PCI extended config space, falling back to CSI\n");
4700         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4701         rtl_csi_write(tp, 0x070c, csi | val << 24);
4702 }
4703
4704 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4705 {
4706         rtl_csi_access_enable(tp, 0x27);
4707 }
4708
4709 struct ephy_info {
4710         unsigned int offset;
4711         u16 mask;
4712         u16 bits;
4713 };
4714
4715 static void __rtl_ephy_init(struct rtl8169_private *tp,
4716                             const struct ephy_info *e, int len)
4717 {
4718         u16 w;
4719
4720         while (len-- > 0) {
4721                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4722                 rtl_ephy_write(tp, e->offset, w);
4723                 e++;
4724         }
4725 }
4726
4727 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4728
4729 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4730 {
4731         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4732                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4733 }
4734
4735 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4736 {
4737         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4738                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4739 }
4740
4741 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4742 {
4743         /* work around an issue when PCI reset occurs during L2/L3 state */
4744         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4745 }
4746
4747 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4748 {
4749         if (enable) {
4750                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4751                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4752         } else {
4753                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4754                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4755         }
4756
4757         udelay(10);
4758 }
4759
4760 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4761                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4762 {
4763         /* Usage of dynamic vs. static FIFO is controlled by bit
4764          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4765          */
4766         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4767         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4768 }
4769
4770 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4771                                           u8 low, u8 high)
4772 {
4773         /* FIFO thresholds for pause flow control */
4774         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4775         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4776 }
4777
4778 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4779 {
4780         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4781
4782         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4783         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4784
4785         if (tp->dev->mtu <= ETH_DATA_LEN) {
4786                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4787                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4788         }
4789 }
4790
4791 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4792 {
4793         rtl_hw_start_8168bb(tp);
4794
4795         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4796
4797         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4798 }
4799
4800 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4801 {
4802         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4803
4804         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4805
4806         if (tp->dev->mtu <= ETH_DATA_LEN)
4807                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4808
4809         rtl_disable_clock_request(tp);
4810
4811         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4812         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4813 }
4814
4815 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4816 {
4817         static const struct ephy_info e_info_8168cp[] = {
4818                 { 0x01, 0,      0x0001 },
4819                 { 0x02, 0x0800, 0x1000 },
4820                 { 0x03, 0,      0x0042 },
4821                 { 0x06, 0x0080, 0x0000 },
4822                 { 0x07, 0,      0x2000 }
4823         };
4824
4825         rtl_set_def_aspm_entry_latency(tp);
4826
4827         rtl_ephy_init(tp, e_info_8168cp);
4828
4829         __rtl_hw_start_8168cp(tp);
4830 }
4831
4832 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4833 {
4834         rtl_set_def_aspm_entry_latency(tp);
4835
4836         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4837
4838         if (tp->dev->mtu <= ETH_DATA_LEN)
4839                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4840
4841         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4842         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4843 }
4844
4845 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4846 {
4847         rtl_set_def_aspm_entry_latency(tp);
4848
4849         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4850
4851         /* Magic. */
4852         RTL_W8(tp, DBG_REG, 0x20);
4853
4854         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4855
4856         if (tp->dev->mtu <= ETH_DATA_LEN)
4857                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4858
4859         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4860         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4861 }
4862
4863 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4864 {
4865         static const struct ephy_info e_info_8168c_1[] = {
4866                 { 0x02, 0x0800, 0x1000 },
4867                 { 0x03, 0,      0x0002 },
4868                 { 0x06, 0x0080, 0x0000 }
4869         };
4870
4871         rtl_set_def_aspm_entry_latency(tp);
4872
4873         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4874
4875         rtl_ephy_init(tp, e_info_8168c_1);
4876
4877         __rtl_hw_start_8168cp(tp);
4878 }
4879
4880 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4881 {
4882         static const struct ephy_info e_info_8168c_2[] = {
4883                 { 0x01, 0,      0x0001 },
4884                 { 0x03, 0x0400, 0x0220 }
4885         };
4886
4887         rtl_set_def_aspm_entry_latency(tp);
4888
4889         rtl_ephy_init(tp, e_info_8168c_2);
4890
4891         __rtl_hw_start_8168cp(tp);
4892 }
4893
4894 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4895 {
4896         rtl_hw_start_8168c_2(tp);
4897 }
4898
4899 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4900 {
4901         rtl_set_def_aspm_entry_latency(tp);
4902
4903         __rtl_hw_start_8168cp(tp);
4904 }
4905
4906 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4907 {
4908         rtl_set_def_aspm_entry_latency(tp);
4909
4910         rtl_disable_clock_request(tp);
4911
4912         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4913
4914         if (tp->dev->mtu <= ETH_DATA_LEN)
4915                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4916
4917         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4918         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4919 }
4920
4921 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4922 {
4923         rtl_set_def_aspm_entry_latency(tp);
4924
4925         if (tp->dev->mtu <= ETH_DATA_LEN)
4926                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4927
4928         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4929
4930         rtl_disable_clock_request(tp);
4931 }
4932
4933 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4934 {
4935         static const struct ephy_info e_info_8168d_4[] = {
4936                 { 0x0b, 0x0000, 0x0048 },
4937                 { 0x19, 0x0020, 0x0050 },
4938                 { 0x0c, 0x0100, 0x0020 }
4939         };
4940
4941         rtl_set_def_aspm_entry_latency(tp);
4942
4943         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4944
4945         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4946
4947         rtl_ephy_init(tp, e_info_8168d_4);
4948
4949         rtl_enable_clock_request(tp);
4950 }
4951
4952 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4953 {
4954         static const struct ephy_info e_info_8168e_1[] = {
4955                 { 0x00, 0x0200, 0x0100 },
4956                 { 0x00, 0x0000, 0x0004 },
4957                 { 0x06, 0x0002, 0x0001 },
4958                 { 0x06, 0x0000, 0x0030 },
4959                 { 0x07, 0x0000, 0x2000 },
4960                 { 0x00, 0x0000, 0x0020 },
4961                 { 0x03, 0x5800, 0x2000 },
4962                 { 0x03, 0x0000, 0x0001 },
4963                 { 0x01, 0x0800, 0x1000 },
4964                 { 0x07, 0x0000, 0x4000 },
4965                 { 0x1e, 0x0000, 0x2000 },
4966                 { 0x19, 0xffff, 0xfe6c },
4967                 { 0x0a, 0x0000, 0x0040 }
4968         };
4969
4970         rtl_set_def_aspm_entry_latency(tp);
4971
4972         rtl_ephy_init(tp, e_info_8168e_1);
4973
4974         if (tp->dev->mtu <= ETH_DATA_LEN)
4975                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4976
4977         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4978
4979         rtl_disable_clock_request(tp);
4980
4981         /* Reset tx FIFO pointer */
4982         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4983         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4984
4985         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4986 }
4987
4988 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4989 {
4990         static const struct ephy_info e_info_8168e_2[] = {
4991                 { 0x09, 0x0000, 0x0080 },
4992                 { 0x19, 0x0000, 0x0224 }
4993         };
4994
4995         rtl_set_def_aspm_entry_latency(tp);
4996
4997         rtl_ephy_init(tp, e_info_8168e_2);
4998
4999         if (tp->dev->mtu <= ETH_DATA_LEN)
5000                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5001
5002         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5003         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5004         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
5005         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
5006         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
5007         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
5008         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5009
5010         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5011
5012         rtl_disable_clock_request(tp);
5013
5014         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5015
5016         rtl8168_config_eee_mac(tp);
5017
5018         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5019         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5020         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5021
5022         rtl_hw_aspm_clkreq_enable(tp, true);
5023 }
5024
5025 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5026 {
5027         rtl_set_def_aspm_entry_latency(tp);
5028
5029         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5030
5031         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5032         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5033         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
5034         rtl_reset_packet_filter(tp);
5035         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
5036         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
5037         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
5038         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
5039
5040         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5041
5042         rtl_disable_clock_request(tp);
5043
5044         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5045         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5046         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5047         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5048
5049         rtl8168_config_eee_mac(tp);
5050 }
5051
5052 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5053 {
5054         static const struct ephy_info e_info_8168f_1[] = {
5055                 { 0x06, 0x00c0, 0x0020 },
5056                 { 0x08, 0x0001, 0x0002 },
5057                 { 0x09, 0x0000, 0x0080 },
5058                 { 0x19, 0x0000, 0x0224 }
5059         };
5060
5061         rtl_hw_start_8168f(tp);
5062
5063         rtl_ephy_init(tp, e_info_8168f_1);
5064
5065         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5066 }
5067
5068 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5069 {
5070         static const struct ephy_info e_info_8168f_1[] = {
5071                 { 0x06, 0x00c0, 0x0020 },
5072                 { 0x0f, 0xffff, 0x5200 },
5073                 { 0x1e, 0x0000, 0x4000 },
5074                 { 0x19, 0x0000, 0x0224 }
5075         };
5076
5077         rtl_hw_start_8168f(tp);
5078         rtl_pcie_state_l2l3_disable(tp);
5079
5080         rtl_ephy_init(tp, e_info_8168f_1);
5081
5082         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
5083 }
5084
5085 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5086 {
5087         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5088         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5089
5090         rtl_set_def_aspm_entry_latency(tp);
5091
5092         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5093
5094         rtl_reset_packet_filter(tp);
5095         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5096
5097         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5098         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5099
5100         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5101         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5102
5103         rtl8168_config_eee_mac(tp);
5104
5105         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5106         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5107
5108         rtl_pcie_state_l2l3_disable(tp);
5109 }
5110
5111 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5112 {
5113         static const struct ephy_info e_info_8168g_1[] = {
5114                 { 0x00, 0x0000, 0x0008 },
5115                 { 0x0c, 0x37d0, 0x0820 },
5116                 { 0x1e, 0x0000, 0x0001 },
5117                 { 0x19, 0x8000, 0x0000 }
5118         };
5119
5120         rtl_hw_start_8168g(tp);
5121
5122         /* disable aspm and clock request before access ephy */
5123         rtl_hw_aspm_clkreq_enable(tp, false);
5124         rtl_ephy_init(tp, e_info_8168g_1);
5125         rtl_hw_aspm_clkreq_enable(tp, true);
5126 }
5127
5128 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5129 {
5130         static const struct ephy_info e_info_8168g_2[] = {
5131                 { 0x00, 0x0000, 0x0008 },
5132                 { 0x0c, 0x3df0, 0x0200 },
5133                 { 0x19, 0xffff, 0xfc00 },
5134                 { 0x1e, 0xffff, 0x20eb }
5135         };
5136
5137         rtl_hw_start_8168g(tp);
5138
5139         /* disable aspm and clock request before access ephy */
5140         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5141         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5142         rtl_ephy_init(tp, e_info_8168g_2);
5143 }
5144
5145 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5146 {
5147         static const struct ephy_info e_info_8411_2[] = {
5148                 { 0x00, 0x0000, 0x0008 },
5149                 { 0x0c, 0x3df0, 0x0200 },
5150                 { 0x0f, 0xffff, 0x5200 },
5151                 { 0x19, 0x0020, 0x0000 },
5152                 { 0x1e, 0x0000, 0x2000 }
5153         };
5154
5155         rtl_hw_start_8168g(tp);
5156
5157         /* disable aspm and clock request before access ephy */
5158         rtl_hw_aspm_clkreq_enable(tp, false);
5159         rtl_ephy_init(tp, e_info_8411_2);
5160         rtl_hw_aspm_clkreq_enable(tp, true);
5161 }
5162
5163 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5164 {
5165         int rg_saw_cnt;
5166         u32 data;
5167         static const struct ephy_info e_info_8168h_1[] = {
5168                 { 0x1e, 0x0800, 0x0001 },
5169                 { 0x1d, 0x0000, 0x0800 },
5170                 { 0x05, 0xffff, 0x2089 },
5171                 { 0x06, 0xffff, 0x5881 },
5172                 { 0x04, 0xffff, 0x154a },
5173                 { 0x01, 0xffff, 0x068b }
5174         };
5175
5176         /* disable aspm and clock request before access ephy */
5177         rtl_hw_aspm_clkreq_enable(tp, false);
5178         rtl_ephy_init(tp, e_info_8168h_1);
5179
5180         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5181         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5182
5183         rtl_set_def_aspm_entry_latency(tp);
5184
5185         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5186
5187         rtl_reset_packet_filter(tp);
5188
5189         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5190
5191         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5192
5193         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5194
5195         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5196         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5197
5198         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5199         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5200
5201         rtl8168_config_eee_mac(tp);
5202
5203         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5204         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5205
5206         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5207
5208         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5209
5210         rtl_pcie_state_l2l3_disable(tp);
5211
5212         rtl_writephy(tp, 0x1f, 0x0c42);
5213         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5214         rtl_writephy(tp, 0x1f, 0x0000);
5215         if (rg_saw_cnt > 0) {
5216                 u16 sw_cnt_1ms_ini;
5217
5218                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5219                 sw_cnt_1ms_ini &= 0x0fff;
5220                 data = r8168_mac_ocp_read(tp, 0xd412);
5221                 data &= ~0x0fff;
5222                 data |= sw_cnt_1ms_ini;
5223                 r8168_mac_ocp_write(tp, 0xd412, data);
5224         }
5225
5226         data = r8168_mac_ocp_read(tp, 0xe056);
5227         data &= ~0xf0;
5228         data |= 0x70;
5229         r8168_mac_ocp_write(tp, 0xe056, data);
5230
5231         data = r8168_mac_ocp_read(tp, 0xe052);
5232         data &= ~0x6000;
5233         data |= 0x8008;
5234         r8168_mac_ocp_write(tp, 0xe052, data);
5235
5236         data = r8168_mac_ocp_read(tp, 0xe0d6);
5237         data &= ~0x01ff;
5238         data |= 0x017f;
5239         r8168_mac_ocp_write(tp, 0xe0d6, data);
5240
5241         data = r8168_mac_ocp_read(tp, 0xd420);
5242         data &= ~0x0fff;
5243         data |= 0x047f;
5244         r8168_mac_ocp_write(tp, 0xd420, data);
5245
5246         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5247         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5248         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5249         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5250
5251         rtl_hw_aspm_clkreq_enable(tp, true);
5252 }
5253
5254 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5255 {
5256         rtl8168ep_stop_cmac(tp);
5257
5258         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5259         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5260
5261         rtl_set_def_aspm_entry_latency(tp);
5262
5263         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5264
5265         rtl_reset_packet_filter(tp);
5266
5267         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5268
5269         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5270
5271         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5272         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5273
5274         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5275         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5276
5277         rtl8168_config_eee_mac(tp);
5278
5279         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5280
5281         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5282
5283         rtl_pcie_state_l2l3_disable(tp);
5284 }
5285
5286 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5287 {
5288         static const struct ephy_info e_info_8168ep_1[] = {
5289                 { 0x00, 0xffff, 0x10ab },
5290                 { 0x06, 0xffff, 0xf030 },
5291                 { 0x08, 0xffff, 0x2006 },
5292                 { 0x0d, 0xffff, 0x1666 },
5293                 { 0x0c, 0x3ff0, 0x0000 }
5294         };
5295
5296         /* disable aspm and clock request before access ephy */
5297         rtl_hw_aspm_clkreq_enable(tp, false);
5298         rtl_ephy_init(tp, e_info_8168ep_1);
5299
5300         rtl_hw_start_8168ep(tp);
5301
5302         rtl_hw_aspm_clkreq_enable(tp, true);
5303 }
5304
5305 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5306 {
5307         static const struct ephy_info e_info_8168ep_2[] = {
5308                 { 0x00, 0xffff, 0x10a3 },
5309                 { 0x19, 0xffff, 0xfc00 },
5310                 { 0x1e, 0xffff, 0x20ea }
5311         };
5312
5313         /* disable aspm and clock request before access ephy */
5314         rtl_hw_aspm_clkreq_enable(tp, false);
5315         rtl_ephy_init(tp, e_info_8168ep_2);
5316
5317         rtl_hw_start_8168ep(tp);
5318
5319         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5320         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5321
5322         rtl_hw_aspm_clkreq_enable(tp, true);
5323 }
5324
5325 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5326 {
5327         u32 data;
5328         static const struct ephy_info e_info_8168ep_3[] = {
5329                 { 0x00, 0xffff, 0x10a3 },
5330                 { 0x19, 0xffff, 0x7c00 },
5331                 { 0x1e, 0xffff, 0x20eb },
5332                 { 0x0d, 0xffff, 0x1666 }
5333         };
5334
5335         /* disable aspm and clock request before access ephy */
5336         rtl_hw_aspm_clkreq_enable(tp, false);
5337         rtl_ephy_init(tp, e_info_8168ep_3);
5338
5339         rtl_hw_start_8168ep(tp);
5340
5341         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5342         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5343
5344         data = r8168_mac_ocp_read(tp, 0xd3e2);
5345         data &= 0xf000;
5346         data |= 0x0271;
5347         r8168_mac_ocp_write(tp, 0xd3e2, data);
5348
5349         data = r8168_mac_ocp_read(tp, 0xd3e4);
5350         data &= 0xff00;
5351         r8168_mac_ocp_write(tp, 0xd3e4, data);
5352
5353         data = r8168_mac_ocp_read(tp, 0xe860);
5354         data |= 0x0080;
5355         r8168_mac_ocp_write(tp, 0xe860, data);
5356
5357         rtl_hw_aspm_clkreq_enable(tp, true);
5358 }
5359
5360 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5361 {
5362         static const struct ephy_info e_info_8102e_1[] = {
5363                 { 0x01, 0, 0x6e65 },
5364                 { 0x02, 0, 0x091f },
5365                 { 0x03, 0, 0xc2f9 },
5366                 { 0x06, 0, 0xafb5 },
5367                 { 0x07, 0, 0x0e00 },
5368                 { 0x19, 0, 0xec80 },
5369                 { 0x01, 0, 0x2e65 },
5370                 { 0x01, 0, 0x6e65 }
5371         };
5372         u8 cfg1;
5373
5374         rtl_set_def_aspm_entry_latency(tp);
5375
5376         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5377
5378         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5379
5380         RTL_W8(tp, Config1,
5381                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5382         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5383
5384         cfg1 = RTL_R8(tp, Config1);
5385         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5386                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5387
5388         rtl_ephy_init(tp, e_info_8102e_1);
5389 }
5390
5391 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5392 {
5393         rtl_set_def_aspm_entry_latency(tp);
5394
5395         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5396
5397         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5398         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5399 }
5400
5401 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5402 {
5403         rtl_hw_start_8102e_2(tp);
5404
5405         rtl_ephy_write(tp, 0x03, 0xc2f9);
5406 }
5407
5408 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5409 {
5410         static const struct ephy_info e_info_8105e_1[] = {
5411                 { 0x07, 0, 0x4000 },
5412                 { 0x19, 0, 0x0200 },
5413                 { 0x19, 0, 0x0020 },
5414                 { 0x1e, 0, 0x2000 },
5415                 { 0x03, 0, 0x0001 },
5416                 { 0x19, 0, 0x0100 },
5417                 { 0x19, 0, 0x0004 },
5418                 { 0x0a, 0, 0x0020 }
5419         };
5420
5421         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5422         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5423
5424         /* Disable Early Tally Counter */
5425         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5426
5427         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5428         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5429
5430         rtl_ephy_init(tp, e_info_8105e_1);
5431
5432         rtl_pcie_state_l2l3_disable(tp);
5433 }
5434
5435 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5436 {
5437         rtl_hw_start_8105e_1(tp);
5438         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5439 }
5440
5441 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5442 {
5443         static const struct ephy_info e_info_8402[] = {
5444                 { 0x19, 0xffff, 0xff64 },
5445                 { 0x1e, 0, 0x4000 }
5446         };
5447
5448         rtl_set_def_aspm_entry_latency(tp);
5449
5450         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5451         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5452
5453         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5454
5455         rtl_ephy_init(tp, e_info_8402);
5456
5457         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5458
5459         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5460         rtl_reset_packet_filter(tp);
5461         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5462         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5463         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5464
5465         rtl_pcie_state_l2l3_disable(tp);
5466 }
5467
5468 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5469 {
5470         rtl_hw_aspm_clkreq_enable(tp, false);
5471
5472         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5473         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5474
5475         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5476         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5477         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5478
5479         rtl_pcie_state_l2l3_disable(tp);
5480         rtl_hw_aspm_clkreq_enable(tp, true);
5481 }
5482
5483 static void rtl_hw_config(struct rtl8169_private *tp)
5484 {
5485         static const rtl_generic_fct hw_configs[] = {
5486                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5487                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5488                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5489                 [RTL_GIGA_MAC_VER_10] = NULL,
5490                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5491                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5492                 [RTL_GIGA_MAC_VER_13] = NULL,
5493                 [RTL_GIGA_MAC_VER_14] = NULL,
5494                 [RTL_GIGA_MAC_VER_15] = NULL,
5495                 [RTL_GIGA_MAC_VER_16] = NULL,
5496                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5497                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5498                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5499                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5500                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5501                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5502                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5503                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5504                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5505                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5506                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5507                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5508                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5509                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5510                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5511                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5512                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5513                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5514                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5515                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5516                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5517                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5518                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5519                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5520                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5521                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5522                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5523                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5524                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5525                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5526                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5527                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5528                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5529                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5530                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5531         };
5532
5533         if (hw_configs[tp->mac_version])
5534                 hw_configs[tp->mac_version](tp);
5535 }
5536
5537 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5538 {
5539         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5540
5541         /* Workaround for RxFIFO overflow. */
5542         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5543                 tp->irq_mask |= RxFIFOOver;
5544                 tp->irq_mask &= ~RxOverflow;
5545         }
5546
5547         rtl_hw_config(tp);
5548 }
5549
5550 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5551 {
5552         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5553                 tp->irq_mask &= ~RxFIFOOver;
5554
5555         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5556             tp->mac_version == RTL_GIGA_MAC_VER_16)
5557                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5558                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5559
5560         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5561
5562         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5563         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5564
5565         rtl_hw_config(tp);
5566 }
5567
5568 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5569 {
5570         struct rtl8169_private *tp = netdev_priv(dev);
5571
5572         if (new_mtu > ETH_DATA_LEN)
5573                 rtl_hw_jumbo_enable(tp);
5574         else
5575                 rtl_hw_jumbo_disable(tp);
5576
5577         dev->mtu = new_mtu;
5578         netdev_update_features(dev);
5579
5580         return 0;
5581 }
5582
5583 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5584 {
5585         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5586         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5587 }
5588
5589 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5590                                      void **data_buff, struct RxDesc *desc)
5591 {
5592         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5593                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5594
5595         kfree(*data_buff);
5596         *data_buff = NULL;
5597         rtl8169_make_unusable_by_asic(desc);
5598 }
5599
5600 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5601 {
5602         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5603
5604         /* Force memory writes to complete before releasing descriptor */
5605         dma_wmb();
5606
5607         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5608 }
5609
5610 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5611                                              struct RxDesc *desc)
5612 {
5613         void *data;
5614         dma_addr_t mapping;
5615         struct device *d = tp_to_dev(tp);
5616         int node = dev_to_node(d);
5617
5618         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5619         if (!data)
5620                 return NULL;
5621
5622         /* Memory should be properly aligned, but better check. */
5623         if (!IS_ALIGNED((unsigned long)data, 8)) {
5624                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5625                 goto err_out;
5626         }
5627
5628         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5629         if (unlikely(dma_mapping_error(d, mapping))) {
5630                 if (net_ratelimit())
5631                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5632                 goto err_out;
5633         }
5634
5635         desc->addr = cpu_to_le64(mapping);
5636         rtl8169_mark_to_asic(desc);
5637         return data;
5638
5639 err_out:
5640         kfree(data);
5641         return NULL;
5642 }
5643
5644 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5645 {
5646         unsigned int i;
5647
5648         for (i = 0; i < NUM_RX_DESC; i++) {
5649                 if (tp->Rx_databuff[i]) {
5650                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5651                                             tp->RxDescArray + i);
5652                 }
5653         }
5654 }
5655
5656 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5657 {
5658         desc->opts1 |= cpu_to_le32(RingEnd);
5659 }
5660
5661 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5662 {
5663         unsigned int i;
5664
5665         for (i = 0; i < NUM_RX_DESC; i++) {
5666                 void *data;
5667
5668                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5669                 if (!data) {
5670                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5671                         goto err_out;
5672                 }
5673                 tp->Rx_databuff[i] = data;
5674         }
5675
5676         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5677         return 0;
5678
5679 err_out:
5680         rtl8169_rx_clear(tp);
5681         return -ENOMEM;
5682 }
5683
5684 static int rtl8169_init_ring(struct rtl8169_private *tp)
5685 {
5686         rtl8169_init_ring_indexes(tp);
5687
5688         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5689         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5690
5691         return rtl8169_rx_fill(tp);
5692 }
5693
5694 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5695                                  struct TxDesc *desc)
5696 {
5697         unsigned int len = tx_skb->len;
5698
5699         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5700
5701         desc->opts1 = 0x00;
5702         desc->opts2 = 0x00;
5703         desc->addr = 0x00;
5704         tx_skb->len = 0;
5705 }
5706
5707 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5708                                    unsigned int n)
5709 {
5710         unsigned int i;
5711
5712         for (i = 0; i < n; i++) {
5713                 unsigned int entry = (start + i) % NUM_TX_DESC;
5714                 struct ring_info *tx_skb = tp->tx_skb + entry;
5715                 unsigned int len = tx_skb->len;
5716
5717                 if (len) {
5718                         struct sk_buff *skb = tx_skb->skb;
5719
5720                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5721                                              tp->TxDescArray + entry);
5722                         if (skb) {
5723                                 dev_consume_skb_any(skb);
5724                                 tx_skb->skb = NULL;
5725                         }
5726                 }
5727         }
5728 }
5729
5730 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5731 {
5732         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5733         tp->cur_tx = tp->dirty_tx = 0;
5734         netdev_reset_queue(tp->dev);
5735 }
5736
5737 static void rtl_reset_work(struct rtl8169_private *tp)
5738 {
5739         struct net_device *dev = tp->dev;
5740         int i;
5741
5742         napi_disable(&tp->napi);
5743         netif_stop_queue(dev);
5744         synchronize_rcu();
5745
5746         rtl8169_hw_reset(tp);
5747
5748         for (i = 0; i < NUM_RX_DESC; i++)
5749                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5750
5751         rtl8169_tx_clear(tp);
5752         rtl8169_init_ring_indexes(tp);
5753
5754         napi_enable(&tp->napi);
5755         rtl_hw_start(tp);
5756         netif_wake_queue(dev);
5757 }
5758
5759 static void rtl8169_tx_timeout(struct net_device *dev)
5760 {
5761         struct rtl8169_private *tp = netdev_priv(dev);
5762
5763         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5764 }
5765
5766 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5767 {
5768         u32 status = opts0 | len;
5769
5770         if (entry == NUM_TX_DESC - 1)
5771                 status |= RingEnd;
5772
5773         return cpu_to_le32(status);
5774 }
5775
5776 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5777                               u32 *opts)
5778 {
5779         struct skb_shared_info *info = skb_shinfo(skb);
5780         unsigned int cur_frag, entry;
5781         struct TxDesc *uninitialized_var(txd);
5782         struct device *d = tp_to_dev(tp);
5783
5784         entry = tp->cur_tx;
5785         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5786                 const skb_frag_t *frag = info->frags + cur_frag;
5787                 dma_addr_t mapping;
5788                 u32 len;
5789                 void *addr;
5790
5791                 entry = (entry + 1) % NUM_TX_DESC;
5792
5793                 txd = tp->TxDescArray + entry;
5794                 len = skb_frag_size(frag);
5795                 addr = skb_frag_address(frag);
5796                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5797                 if (unlikely(dma_mapping_error(d, mapping))) {
5798                         if (net_ratelimit())
5799                                 netif_err(tp, drv, tp->dev,
5800                                           "Failed to map TX fragments DMA!\n");
5801                         goto err_out;
5802                 }
5803
5804                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5805                 txd->opts2 = cpu_to_le32(opts[1]);
5806                 txd->addr = cpu_to_le64(mapping);
5807
5808                 tp->tx_skb[entry].len = len;
5809         }
5810
5811         if (cur_frag) {
5812                 tp->tx_skb[entry].skb = skb;
5813                 txd->opts1 |= cpu_to_le32(LastFrag);
5814         }
5815
5816         return cur_frag;
5817
5818 err_out:
5819         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5820         return -EIO;
5821 }
5822
5823 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5824 {
5825         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5826 }
5827
5828 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5829                                       struct net_device *dev);
5830 /* r8169_csum_workaround()
5831  * The hw limites the value the transport offset. When the offset is out of the
5832  * range, calculate the checksum by sw.
5833  */
5834 static void r8169_csum_workaround(struct rtl8169_private *tp,
5835                                   struct sk_buff *skb)
5836 {
5837         if (skb_shinfo(skb)->gso_size) {
5838                 netdev_features_t features = tp->dev->features;
5839                 struct sk_buff *segs, *nskb;
5840
5841                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5842                 segs = skb_gso_segment(skb, features);
5843                 if (IS_ERR(segs) || !segs)
5844                         goto drop;
5845
5846                 do {
5847                         nskb = segs;
5848                         segs = segs->next;
5849                         nskb->next = NULL;
5850                         rtl8169_start_xmit(nskb, tp->dev);
5851                 } while (segs);
5852
5853                 dev_consume_skb_any(skb);
5854         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5855                 if (skb_checksum_help(skb) < 0)
5856                         goto drop;
5857
5858                 rtl8169_start_xmit(skb, tp->dev);
5859         } else {
5860                 struct net_device_stats *stats;
5861
5862 drop:
5863                 stats = &tp->dev->stats;
5864                 stats->tx_dropped++;
5865                 dev_kfree_skb_any(skb);
5866         }
5867 }
5868
5869 /* msdn_giant_send_check()
5870  * According to the document of microsoft, the TCP Pseudo Header excludes the
5871  * packet length for IPv6 TCP large packets.
5872  */
5873 static int msdn_giant_send_check(struct sk_buff *skb)
5874 {
5875         const struct ipv6hdr *ipv6h;
5876         struct tcphdr *th;
5877         int ret;
5878
5879         ret = skb_cow_head(skb, 0);
5880         if (ret)
5881                 return ret;
5882
5883         ipv6h = ipv6_hdr(skb);
5884         th = tcp_hdr(skb);
5885
5886         th->check = 0;
5887         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5888
5889         return ret;
5890 }
5891
5892 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5893                                 struct sk_buff *skb, u32 *opts)
5894 {
5895         u32 mss = skb_shinfo(skb)->gso_size;
5896
5897         if (mss) {
5898                 opts[0] |= TD_LSO;
5899                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5900         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5901                 const struct iphdr *ip = ip_hdr(skb);
5902
5903                 if (ip->protocol == IPPROTO_TCP)
5904                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5905                 else if (ip->protocol == IPPROTO_UDP)
5906                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5907                 else
5908                         WARN_ON_ONCE(1);
5909         }
5910
5911         return true;
5912 }
5913
5914 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5915                                 struct sk_buff *skb, u32 *opts)
5916 {
5917         u32 transport_offset = (u32)skb_transport_offset(skb);
5918         u32 mss = skb_shinfo(skb)->gso_size;
5919
5920         if (mss) {
5921                 if (transport_offset > GTTCPHO_MAX) {
5922                         netif_warn(tp, tx_err, tp->dev,
5923                                    "Invalid transport offset 0x%x for TSO\n",
5924                                    transport_offset);
5925                         return false;
5926                 }
5927
5928                 switch (vlan_get_protocol(skb)) {
5929                 case htons(ETH_P_IP):
5930                         opts[0] |= TD1_GTSENV4;
5931                         break;
5932
5933                 case htons(ETH_P_IPV6):
5934                         if (msdn_giant_send_check(skb))
5935                                 return false;
5936
5937                         opts[0] |= TD1_GTSENV6;
5938                         break;
5939
5940                 default:
5941                         WARN_ON_ONCE(1);
5942                         break;
5943                 }
5944
5945                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5946                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5947         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5948                 u8 ip_protocol;
5949
5950                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5951                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5952
5953                 if (transport_offset > TCPHO_MAX) {
5954                         netif_warn(tp, tx_err, tp->dev,
5955                                    "Invalid transport offset 0x%x\n",
5956                                    transport_offset);
5957                         return false;
5958                 }
5959
5960                 switch (vlan_get_protocol(skb)) {
5961                 case htons(ETH_P_IP):
5962                         opts[1] |= TD1_IPv4_CS;
5963                         ip_protocol = ip_hdr(skb)->protocol;
5964                         break;
5965
5966                 case htons(ETH_P_IPV6):
5967                         opts[1] |= TD1_IPv6_CS;
5968                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5969                         break;
5970
5971                 default:
5972                         ip_protocol = IPPROTO_RAW;
5973                         break;
5974                 }
5975
5976                 if (ip_protocol == IPPROTO_TCP)
5977                         opts[1] |= TD1_TCP_CS;
5978                 else if (ip_protocol == IPPROTO_UDP)
5979                         opts[1] |= TD1_UDP_CS;
5980                 else
5981                         WARN_ON_ONCE(1);
5982
5983                 opts[1] |= transport_offset << TCPHO_SHIFT;
5984         } else {
5985                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5986                         return !eth_skb_pad(skb);
5987         }
5988
5989         return true;
5990 }
5991
5992 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5993                                unsigned int nr_frags)
5994 {
5995         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5996
5997         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5998         return slots_avail > nr_frags;
5999 }
6000
6001 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6002                                       struct net_device *dev)
6003 {
6004         struct rtl8169_private *tp = netdev_priv(dev);
6005         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6006         struct TxDesc *txd = tp->TxDescArray + entry;
6007         struct device *d = tp_to_dev(tp);
6008         dma_addr_t mapping;
6009         u32 opts[2], len;
6010         int frags;
6011
6012         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6013                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6014                 goto err_stop_0;
6015         }
6016
6017         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6018                 goto err_stop_0;
6019
6020         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6021         opts[0] = DescOwn;
6022
6023         if (!tp->tso_csum(tp, skb, opts)) {
6024                 r8169_csum_workaround(tp, skb);
6025                 return NETDEV_TX_OK;
6026         }
6027
6028         len = skb_headlen(skb);
6029         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6030         if (unlikely(dma_mapping_error(d, mapping))) {
6031                 if (net_ratelimit())
6032                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6033                 goto err_dma_0;
6034         }
6035
6036         tp->tx_skb[entry].len = len;
6037         txd->addr = cpu_to_le64(mapping);
6038
6039         frags = rtl8169_xmit_frags(tp, skb, opts);
6040         if (frags < 0)
6041                 goto err_dma_1;
6042         else if (frags)
6043                 opts[0] |= FirstFrag;
6044         else {
6045                 opts[0] |= FirstFrag | LastFrag;
6046                 tp->tx_skb[entry].skb = skb;
6047         }
6048
6049         txd->opts2 = cpu_to_le32(opts[1]);
6050
6051         netdev_sent_queue(dev, skb->len);
6052
6053         skb_tx_timestamp(skb);
6054
6055         /* Force memory writes to complete before releasing descriptor */
6056         dma_wmb();
6057
6058         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6059
6060         /* Force all memory writes to complete before notifying device */
6061         wmb();
6062
6063         tp->cur_tx += frags + 1;
6064
6065         RTL_W8(tp, TxPoll, NPQ);
6066
6067         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6068                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6069                  * not miss a ring update when it notices a stopped queue.
6070                  */
6071                 smp_wmb();
6072                 netif_stop_queue(dev);
6073                 /* Sync with rtl_tx:
6074                  * - publish queue status and cur_tx ring index (write barrier)
6075                  * - refresh dirty_tx ring index (read barrier).
6076                  * May the current thread have a pessimistic view of the ring
6077                  * status and forget to wake up queue, a racing rtl_tx thread
6078                  * can't.
6079                  */
6080                 smp_mb();
6081                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6082                         netif_start_queue(dev);
6083         }
6084
6085         return NETDEV_TX_OK;
6086
6087 err_dma_1:
6088         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6089 err_dma_0:
6090         dev_kfree_skb_any(skb);
6091         dev->stats.tx_dropped++;
6092         return NETDEV_TX_OK;
6093
6094 err_stop_0:
6095         netif_stop_queue(dev);
6096         dev->stats.tx_dropped++;
6097         return NETDEV_TX_BUSY;
6098 }
6099
6100 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6101 {
6102         struct rtl8169_private *tp = netdev_priv(dev);
6103         struct pci_dev *pdev = tp->pci_dev;
6104         u16 pci_status, pci_cmd;
6105
6106         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6107         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6108
6109         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6110                   pci_cmd, pci_status);
6111
6112         /*
6113          * The recovery sequence below admits a very elaborated explanation:
6114          * - it seems to work;
6115          * - I did not see what else could be done;
6116          * - it makes iop3xx happy.
6117          *
6118          * Feel free to adjust to your needs.
6119          */
6120         if (pdev->broken_parity_status)
6121                 pci_cmd &= ~PCI_COMMAND_PARITY;
6122         else
6123                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6124
6125         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6126
6127         pci_write_config_word(pdev, PCI_STATUS,
6128                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6129                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6130                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6131
6132         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6133 }
6134
6135 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6136                    int budget)
6137 {
6138         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6139
6140         dirty_tx = tp->dirty_tx;
6141         smp_rmb();
6142         tx_left = tp->cur_tx - dirty_tx;
6143
6144         while (tx_left > 0) {
6145                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6146                 struct ring_info *tx_skb = tp->tx_skb + entry;
6147                 u32 status;
6148
6149                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6150                 if (status & DescOwn)
6151                         break;
6152
6153                 /* This barrier is needed to keep us from reading
6154                  * any other fields out of the Tx descriptor until
6155                  * we know the status of DescOwn
6156                  */
6157                 dma_rmb();
6158
6159                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6160                                      tp->TxDescArray + entry);
6161                 if (status & LastFrag) {
6162                         pkts_compl++;
6163                         bytes_compl += tx_skb->skb->len;
6164                         napi_consume_skb(tx_skb->skb, budget);
6165                         tx_skb->skb = NULL;
6166                 }
6167                 dirty_tx++;
6168                 tx_left--;
6169         }
6170
6171         if (tp->dirty_tx != dirty_tx) {
6172                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6173
6174                 u64_stats_update_begin(&tp->tx_stats.syncp);
6175                 tp->tx_stats.packets += pkts_compl;
6176                 tp->tx_stats.bytes += bytes_compl;
6177                 u64_stats_update_end(&tp->tx_stats.syncp);
6178
6179                 tp->dirty_tx = dirty_tx;
6180                 /* Sync with rtl8169_start_xmit:
6181                  * - publish dirty_tx ring index (write barrier)
6182                  * - refresh cur_tx ring index and queue status (read barrier)
6183                  * May the current thread miss the stopped queue condition,
6184                  * a racing xmit thread can only have a right view of the
6185                  * ring status.
6186                  */
6187                 smp_mb();
6188                 if (netif_queue_stopped(dev) &&
6189                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6190                         netif_wake_queue(dev);
6191                 }
6192                 /*
6193                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6194                  * too close. Let's kick an extra TxPoll request when a burst
6195                  * of start_xmit activity is detected (if it is not detected,
6196                  * it is slow enough). -- FR
6197                  */
6198                 if (tp->cur_tx != dirty_tx)
6199                         RTL_W8(tp, TxPoll, NPQ);
6200         }
6201 }
6202
6203 static inline int rtl8169_fragmented_frame(u32 status)
6204 {
6205         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6206 }
6207
6208 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6209 {
6210         u32 status = opts1 & RxProtoMask;
6211
6212         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6213             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6214                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6215         else
6216                 skb_checksum_none_assert(skb);
6217 }
6218
6219 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6220                                            struct rtl8169_private *tp,
6221                                            int pkt_size,
6222                                            dma_addr_t addr)
6223 {
6224         struct sk_buff *skb;
6225         struct device *d = tp_to_dev(tp);
6226
6227         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6228         prefetch(data);
6229         skb = napi_alloc_skb(&tp->napi, pkt_size);
6230         if (skb)
6231                 skb_copy_to_linear_data(skb, data, pkt_size);
6232         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6233
6234         return skb;
6235 }
6236
6237 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6238 {
6239         unsigned int cur_rx, rx_left;
6240         unsigned int count;
6241
6242         cur_rx = tp->cur_rx;
6243
6244         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6245                 unsigned int entry = cur_rx % NUM_RX_DESC;
6246                 struct RxDesc *desc = tp->RxDescArray + entry;
6247                 u32 status;
6248
6249                 status = le32_to_cpu(desc->opts1);
6250                 if (status & DescOwn)
6251                         break;
6252
6253                 /* This barrier is needed to keep us from reading
6254                  * any other fields out of the Rx descriptor until
6255                  * we know the status of DescOwn
6256                  */
6257                 dma_rmb();
6258
6259                 if (unlikely(status & RxRES)) {
6260                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6261                                    status);
6262                         dev->stats.rx_errors++;
6263                         if (status & (RxRWT | RxRUNT))
6264                                 dev->stats.rx_length_errors++;
6265                         if (status & RxCRC)
6266                                 dev->stats.rx_crc_errors++;
6267                         /* RxFOVF is a reserved bit on later chip versions */
6268                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6269                             status & RxFOVF) {
6270                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6271                                 dev->stats.rx_fifo_errors++;
6272                         } else if (status & (RxRUNT | RxCRC) &&
6273                                    !(status & RxRWT) &&
6274                                    dev->features & NETIF_F_RXALL) {
6275                                 goto process_pkt;
6276                         }
6277                 } else {
6278                         struct sk_buff *skb;
6279                         dma_addr_t addr;
6280                         int pkt_size;
6281
6282 process_pkt:
6283                         addr = le64_to_cpu(desc->addr);
6284                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6285                                 pkt_size = (status & 0x00003fff) - 4;
6286                         else
6287                                 pkt_size = status & 0x00003fff;
6288
6289                         /*
6290                          * The driver does not support incoming fragmented
6291                          * frames. They are seen as a symptom of over-mtu
6292                          * sized frames.
6293                          */
6294                         if (unlikely(rtl8169_fragmented_frame(status))) {
6295                                 dev->stats.rx_dropped++;
6296                                 dev->stats.rx_length_errors++;
6297                                 goto release_descriptor;
6298                         }
6299
6300                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6301                                                   tp, pkt_size, addr);
6302                         if (!skb) {
6303                                 dev->stats.rx_dropped++;
6304                                 goto release_descriptor;
6305                         }
6306
6307                         rtl8169_rx_csum(skb, status);
6308                         skb_put(skb, pkt_size);
6309                         skb->protocol = eth_type_trans(skb, dev);
6310
6311                         rtl8169_rx_vlan_tag(desc, skb);
6312
6313                         if (skb->pkt_type == PACKET_MULTICAST)
6314                                 dev->stats.multicast++;
6315
6316                         napi_gro_receive(&tp->napi, skb);
6317
6318                         u64_stats_update_begin(&tp->rx_stats.syncp);
6319                         tp->rx_stats.packets++;
6320                         tp->rx_stats.bytes += pkt_size;
6321                         u64_stats_update_end(&tp->rx_stats.syncp);
6322                 }
6323 release_descriptor:
6324                 desc->opts2 = 0;
6325                 rtl8169_mark_to_asic(desc);
6326         }
6327
6328         count = cur_rx - tp->cur_rx;
6329         tp->cur_rx = cur_rx;
6330
6331         return count;
6332 }
6333
6334 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6335 {
6336         struct rtl8169_private *tp = dev_instance;
6337         u16 status = RTL_R16(tp, IntrStatus);
6338
6339         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6340                 return IRQ_NONE;
6341
6342         if (unlikely(status & SYSErr)) {
6343                 rtl8169_pcierr_interrupt(tp->dev);
6344                 goto out;
6345         }
6346
6347         if (status & LinkChg)
6348                 phy_mac_interrupt(tp->phydev);
6349
6350         if (unlikely(status & RxFIFOOver &&
6351             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6352                 netif_stop_queue(tp->dev);
6353                 /* XXX - Hack alert. See rtl_task(). */
6354                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6355         }
6356
6357         rtl_irq_disable(tp);
6358         napi_schedule_irqoff(&tp->napi);
6359 out:
6360         rtl_ack_events(tp, status);
6361
6362         return IRQ_HANDLED;
6363 }
6364
6365 static void rtl_task(struct work_struct *work)
6366 {
6367         static const struct {
6368                 int bitnr;
6369                 void (*action)(struct rtl8169_private *);
6370         } rtl_work[] = {
6371                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6372         };
6373         struct rtl8169_private *tp =
6374                 container_of(work, struct rtl8169_private, wk.work);
6375         struct net_device *dev = tp->dev;
6376         int i;
6377
6378         rtl_lock_work(tp);
6379
6380         if (!netif_running(dev) ||
6381             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6382                 goto out_unlock;
6383
6384         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6385                 bool pending;
6386
6387                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6388                 if (pending)
6389                         rtl_work[i].action(tp);
6390         }
6391
6392 out_unlock:
6393         rtl_unlock_work(tp);
6394 }
6395
6396 static int rtl8169_poll(struct napi_struct *napi, int budget)
6397 {
6398         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6399         struct net_device *dev = tp->dev;
6400         int work_done;
6401
6402         work_done = rtl_rx(dev, tp, (u32) budget);
6403
6404         rtl_tx(dev, tp, budget);
6405
6406         if (work_done < budget) {
6407                 napi_complete_done(napi, work_done);
6408                 rtl_irq_enable(tp);
6409         }
6410
6411         return work_done;
6412 }
6413
6414 static void rtl8169_rx_missed(struct net_device *dev)
6415 {
6416         struct rtl8169_private *tp = netdev_priv(dev);
6417
6418         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6419                 return;
6420
6421         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6422         RTL_W32(tp, RxMissed, 0);
6423 }
6424
6425 static void r8169_phylink_handler(struct net_device *ndev)
6426 {
6427         struct rtl8169_private *tp = netdev_priv(ndev);
6428
6429         if (netif_carrier_ok(ndev)) {
6430                 rtl_link_chg_patch(tp);
6431                 pm_request_resume(&tp->pci_dev->dev);
6432         } else {
6433                 pm_runtime_idle(&tp->pci_dev->dev);
6434         }
6435
6436         if (net_ratelimit())
6437                 phy_print_status(tp->phydev);
6438 }
6439
6440 static int r8169_phy_connect(struct rtl8169_private *tp)
6441 {
6442         struct phy_device *phydev = tp->phydev;
6443         phy_interface_t phy_mode;
6444         int ret;
6445
6446         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6447                    PHY_INTERFACE_MODE_MII;
6448
6449         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6450                                  phy_mode);
6451         if (ret)
6452                 return ret;
6453
6454         if (!tp->supports_gmii)
6455                 phy_set_max_speed(phydev, SPEED_100);
6456
6457         phy_support_asym_pause(phydev);
6458
6459         phy_attached_info(phydev);
6460
6461         return 0;
6462 }
6463
6464 static void rtl8169_down(struct net_device *dev)
6465 {
6466         struct rtl8169_private *tp = netdev_priv(dev);
6467
6468         phy_stop(tp->phydev);
6469
6470         napi_disable(&tp->napi);
6471         netif_stop_queue(dev);
6472
6473         rtl8169_hw_reset(tp);
6474         /*
6475          * At this point device interrupts can not be enabled in any function,
6476          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6477          * and napi is disabled (rtl8169_poll).
6478          */
6479         rtl8169_rx_missed(dev);
6480
6481         /* Give a racing hard_start_xmit a few cycles to complete. */
6482         synchronize_rcu();
6483
6484         rtl8169_tx_clear(tp);
6485
6486         rtl8169_rx_clear(tp);
6487
6488         rtl_pll_power_down(tp);
6489 }
6490
6491 static int rtl8169_close(struct net_device *dev)
6492 {
6493         struct rtl8169_private *tp = netdev_priv(dev);
6494         struct pci_dev *pdev = tp->pci_dev;
6495
6496         pm_runtime_get_sync(&pdev->dev);
6497
6498         /* Update counters before going down */
6499         rtl8169_update_counters(tp);
6500
6501         rtl_lock_work(tp);
6502         /* Clear all task flags */
6503         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6504
6505         rtl8169_down(dev);
6506         rtl_unlock_work(tp);
6507
6508         cancel_work_sync(&tp->wk.work);
6509
6510         phy_disconnect(tp->phydev);
6511
6512         pci_free_irq(pdev, 0, tp);
6513
6514         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6515                           tp->RxPhyAddr);
6516         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6517                           tp->TxPhyAddr);
6518         tp->TxDescArray = NULL;
6519         tp->RxDescArray = NULL;
6520
6521         pm_runtime_put_sync(&pdev->dev);
6522
6523         return 0;
6524 }
6525
6526 #ifdef CONFIG_NET_POLL_CONTROLLER
6527 static void rtl8169_netpoll(struct net_device *dev)
6528 {
6529         struct rtl8169_private *tp = netdev_priv(dev);
6530
6531         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6532 }
6533 #endif
6534
6535 static int rtl_open(struct net_device *dev)
6536 {
6537         struct rtl8169_private *tp = netdev_priv(dev);
6538         struct pci_dev *pdev = tp->pci_dev;
6539         int retval = -ENOMEM;
6540
6541         pm_runtime_get_sync(&pdev->dev);
6542
6543         /*
6544          * Rx and Tx descriptors needs 256 bytes alignment.
6545          * dma_alloc_coherent provides more.
6546          */
6547         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6548                                              &tp->TxPhyAddr, GFP_KERNEL);
6549         if (!tp->TxDescArray)
6550                 goto err_pm_runtime_put;
6551
6552         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6553                                              &tp->RxPhyAddr, GFP_KERNEL);
6554         if (!tp->RxDescArray)
6555                 goto err_free_tx_0;
6556
6557         retval = rtl8169_init_ring(tp);
6558         if (retval < 0)
6559                 goto err_free_rx_1;
6560
6561         rtl_request_firmware(tp);
6562
6563         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6564                                  dev->name);
6565         if (retval < 0)
6566                 goto err_release_fw_2;
6567
6568         retval = r8169_phy_connect(tp);
6569         if (retval)
6570                 goto err_free_irq;
6571
6572         rtl_lock_work(tp);
6573
6574         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6575
6576         napi_enable(&tp->napi);
6577
6578         rtl8169_init_phy(dev, tp);
6579
6580         rtl_pll_power_up(tp);
6581
6582         rtl_hw_start(tp);
6583
6584         if (!rtl8169_init_counter_offsets(tp))
6585                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6586
6587         phy_start(tp->phydev);
6588         netif_start_queue(dev);
6589
6590         rtl_unlock_work(tp);
6591
6592         pm_runtime_put_sync(&pdev->dev);
6593 out:
6594         return retval;
6595
6596 err_free_irq:
6597         pci_free_irq(pdev, 0, tp);
6598 err_release_fw_2:
6599         rtl_release_firmware(tp);
6600         rtl8169_rx_clear(tp);
6601 err_free_rx_1:
6602         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6603                           tp->RxPhyAddr);
6604         tp->RxDescArray = NULL;
6605 err_free_tx_0:
6606         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6607                           tp->TxPhyAddr);
6608         tp->TxDescArray = NULL;
6609 err_pm_runtime_put:
6610         pm_runtime_put_noidle(&pdev->dev);
6611         goto out;
6612 }
6613
6614 static void
6615 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6616 {
6617         struct rtl8169_private *tp = netdev_priv(dev);
6618         struct pci_dev *pdev = tp->pci_dev;
6619         struct rtl8169_counters *counters = tp->counters;
6620         unsigned int start;
6621
6622         pm_runtime_get_noresume(&pdev->dev);
6623
6624         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6625                 rtl8169_rx_missed(dev);
6626
6627         do {
6628                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6629                 stats->rx_packets = tp->rx_stats.packets;
6630                 stats->rx_bytes = tp->rx_stats.bytes;
6631         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6632
6633         do {
6634                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6635                 stats->tx_packets = tp->tx_stats.packets;
6636                 stats->tx_bytes = tp->tx_stats.bytes;
6637         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6638
6639         stats->rx_dropped       = dev->stats.rx_dropped;
6640         stats->tx_dropped       = dev->stats.tx_dropped;
6641         stats->rx_length_errors = dev->stats.rx_length_errors;
6642         stats->rx_errors        = dev->stats.rx_errors;
6643         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6644         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6645         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6646         stats->multicast        = dev->stats.multicast;
6647
6648         /*
6649          * Fetch additonal counter values missing in stats collected by driver
6650          * from tally counters.
6651          */
6652         if (pm_runtime_active(&pdev->dev))
6653                 rtl8169_update_counters(tp);
6654
6655         /*
6656          * Subtract values fetched during initalization.
6657          * See rtl8169_init_counter_offsets for a description why we do that.
6658          */
6659         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6660                 le64_to_cpu(tp->tc_offset.tx_errors);
6661         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6662                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6663         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6664                 le16_to_cpu(tp->tc_offset.tx_aborted);
6665
6666         pm_runtime_put_noidle(&pdev->dev);
6667 }
6668
6669 static void rtl8169_net_suspend(struct net_device *dev)
6670 {
6671         struct rtl8169_private *tp = netdev_priv(dev);
6672
6673         if (!netif_running(dev))
6674                 return;
6675
6676         phy_stop(tp->phydev);
6677         netif_device_detach(dev);
6678
6679         rtl_lock_work(tp);
6680         napi_disable(&tp->napi);
6681         /* Clear all task flags */
6682         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6683
6684         rtl_unlock_work(tp);
6685
6686         rtl_pll_power_down(tp);
6687 }
6688
6689 #ifdef CONFIG_PM
6690
6691 static int rtl8169_suspend(struct device *device)
6692 {
6693         struct net_device *dev = dev_get_drvdata(device);
6694         struct rtl8169_private *tp = netdev_priv(dev);
6695
6696         rtl8169_net_suspend(dev);
6697         clk_disable_unprepare(tp->clk);
6698
6699         return 0;
6700 }
6701
6702 static void __rtl8169_resume(struct net_device *dev)
6703 {
6704         struct rtl8169_private *tp = netdev_priv(dev);
6705
6706         netif_device_attach(dev);
6707
6708         rtl_pll_power_up(tp);
6709         rtl8169_init_phy(dev, tp);
6710
6711         phy_start(tp->phydev);
6712
6713         rtl_lock_work(tp);
6714         napi_enable(&tp->napi);
6715         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6716         rtl_reset_work(tp);
6717         rtl_unlock_work(tp);
6718 }
6719
6720 static int rtl8169_resume(struct device *device)
6721 {
6722         struct net_device *dev = dev_get_drvdata(device);
6723         struct rtl8169_private *tp = netdev_priv(dev);
6724
6725         clk_prepare_enable(tp->clk);
6726
6727         if (netif_running(dev))
6728                 __rtl8169_resume(dev);
6729
6730         return 0;
6731 }
6732
6733 static int rtl8169_runtime_suspend(struct device *device)
6734 {
6735         struct net_device *dev = dev_get_drvdata(device);
6736         struct rtl8169_private *tp = netdev_priv(dev);
6737
6738         if (!tp->TxDescArray)
6739                 return 0;
6740
6741         rtl_lock_work(tp);
6742         __rtl8169_set_wol(tp, WAKE_ANY);
6743         rtl_unlock_work(tp);
6744
6745         rtl8169_net_suspend(dev);
6746
6747         /* Update counters before going runtime suspend */
6748         rtl8169_rx_missed(dev);
6749         rtl8169_update_counters(tp);
6750
6751         return 0;
6752 }
6753
6754 static int rtl8169_runtime_resume(struct device *device)
6755 {
6756         struct net_device *dev = dev_get_drvdata(device);
6757         struct rtl8169_private *tp = netdev_priv(dev);
6758         rtl_rar_set(tp, dev->dev_addr);
6759
6760         if (!tp->TxDescArray)
6761                 return 0;
6762
6763         rtl_lock_work(tp);
6764         __rtl8169_set_wol(tp, tp->saved_wolopts);
6765         rtl_unlock_work(tp);
6766
6767         __rtl8169_resume(dev);
6768
6769         return 0;
6770 }
6771
6772 static int rtl8169_runtime_idle(struct device *device)
6773 {
6774         struct net_device *dev = dev_get_drvdata(device);
6775
6776         if (!netif_running(dev) || !netif_carrier_ok(dev))
6777                 pm_schedule_suspend(device, 10000);
6778
6779         return -EBUSY;
6780 }
6781
6782 static const struct dev_pm_ops rtl8169_pm_ops = {
6783         .suspend                = rtl8169_suspend,
6784         .resume                 = rtl8169_resume,
6785         .freeze                 = rtl8169_suspend,
6786         .thaw                   = rtl8169_resume,
6787         .poweroff               = rtl8169_suspend,
6788         .restore                = rtl8169_resume,
6789         .runtime_suspend        = rtl8169_runtime_suspend,
6790         .runtime_resume         = rtl8169_runtime_resume,
6791         .runtime_idle           = rtl8169_runtime_idle,
6792 };
6793
6794 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6795
6796 #else /* !CONFIG_PM */
6797
6798 #define RTL8169_PM_OPS  NULL
6799
6800 #endif /* !CONFIG_PM */
6801
6802 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6803 {
6804         /* WoL fails with 8168b when the receiver is disabled. */
6805         switch (tp->mac_version) {
6806         case RTL_GIGA_MAC_VER_11:
6807         case RTL_GIGA_MAC_VER_12:
6808         case RTL_GIGA_MAC_VER_17:
6809                 pci_clear_master(tp->pci_dev);
6810
6811                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6812                 /* PCI commit */
6813                 RTL_R8(tp, ChipCmd);
6814                 break;
6815         default:
6816                 break;
6817         }
6818 }
6819
6820 static void rtl_shutdown(struct pci_dev *pdev)
6821 {
6822         struct net_device *dev = pci_get_drvdata(pdev);
6823         struct rtl8169_private *tp = netdev_priv(dev);
6824
6825         rtl8169_net_suspend(dev);
6826
6827         /* Restore original MAC address */
6828         rtl_rar_set(tp, dev->perm_addr);
6829
6830         rtl8169_hw_reset(tp);
6831
6832         if (system_state == SYSTEM_POWER_OFF) {
6833                 if (tp->saved_wolopts) {
6834                         rtl_wol_suspend_quirk(tp);
6835                         rtl_wol_shutdown_quirk(tp);
6836                 }
6837
6838                 pci_wake_from_d3(pdev, true);
6839                 pci_set_power_state(pdev, PCI_D3hot);
6840         }
6841 }
6842
6843 static void rtl_remove_one(struct pci_dev *pdev)
6844 {
6845         struct net_device *dev = pci_get_drvdata(pdev);
6846         struct rtl8169_private *tp = netdev_priv(dev);
6847
6848         if (r8168_check_dash(tp))
6849                 rtl8168_driver_stop(tp);
6850
6851         netif_napi_del(&tp->napi);
6852
6853         unregister_netdev(dev);
6854         mdiobus_unregister(tp->phydev->mdio.bus);
6855
6856         rtl_release_firmware(tp);
6857
6858         if (pci_dev_run_wake(pdev))
6859                 pm_runtime_get_noresume(&pdev->dev);
6860
6861         /* restore original MAC address */
6862         rtl_rar_set(tp, dev->perm_addr);
6863 }
6864
6865 static const struct net_device_ops rtl_netdev_ops = {
6866         .ndo_open               = rtl_open,
6867         .ndo_stop               = rtl8169_close,
6868         .ndo_get_stats64        = rtl8169_get_stats64,
6869         .ndo_start_xmit         = rtl8169_start_xmit,
6870         .ndo_tx_timeout         = rtl8169_tx_timeout,
6871         .ndo_validate_addr      = eth_validate_addr,
6872         .ndo_change_mtu         = rtl8169_change_mtu,
6873         .ndo_fix_features       = rtl8169_fix_features,
6874         .ndo_set_features       = rtl8169_set_features,
6875         .ndo_set_mac_address    = rtl_set_mac_address,
6876         .ndo_do_ioctl           = rtl8169_ioctl,
6877         .ndo_set_rx_mode        = rtl_set_rx_mode,
6878 #ifdef CONFIG_NET_POLL_CONTROLLER
6879         .ndo_poll_controller    = rtl8169_netpoll,
6880 #endif
6881
6882 };
6883
6884 static const struct rtl_cfg_info {
6885         void (*hw_start)(struct rtl8169_private *tp);
6886         u16 irq_mask;
6887         unsigned int has_gmii:1;
6888         const struct rtl_coalesce_info *coalesce_info;
6889 } rtl_cfg_infos [] = {
6890         [RTL_CFG_0] = {
6891                 .hw_start       = rtl_hw_start_8169,
6892                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6893                 .has_gmii       = 1,
6894                 .coalesce_info  = rtl_coalesce_info_8169,
6895         },
6896         [RTL_CFG_1] = {
6897                 .hw_start       = rtl_hw_start_8168,
6898                 .irq_mask       = LinkChg | RxOverflow,
6899                 .has_gmii       = 1,
6900                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6901         },
6902         [RTL_CFG_2] = {
6903                 .hw_start       = rtl_hw_start_8101,
6904                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6905                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6906         }
6907 };
6908
6909 static int rtl_alloc_irq(struct rtl8169_private *tp)
6910 {
6911         unsigned int flags;
6912
6913         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6914                 rtl_unlock_config_regs(tp);
6915                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6916                 rtl_lock_config_regs(tp);
6917                 flags = PCI_IRQ_LEGACY;
6918         } else {
6919                 flags = PCI_IRQ_ALL_TYPES;
6920         }
6921
6922         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6923 }
6924
6925 static void rtl_read_mac_address(struct rtl8169_private *tp,
6926                                  u8 mac_addr[ETH_ALEN])
6927 {
6928         u32 value;
6929
6930         /* Get MAC address */
6931         switch (tp->mac_version) {
6932         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6933         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6934                 value = rtl_eri_read(tp, 0xe0);
6935                 mac_addr[0] = (value >>  0) & 0xff;
6936                 mac_addr[1] = (value >>  8) & 0xff;
6937                 mac_addr[2] = (value >> 16) & 0xff;
6938                 mac_addr[3] = (value >> 24) & 0xff;
6939
6940                 value = rtl_eri_read(tp, 0xe4);
6941                 mac_addr[4] = (value >>  0) & 0xff;
6942                 mac_addr[5] = (value >>  8) & 0xff;
6943                 break;
6944         default:
6945                 break;
6946         }
6947 }
6948
6949 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6950 {
6951         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6952 }
6953
6954 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6955 {
6956         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6957 }
6958
6959 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6960 {
6961         struct rtl8169_private *tp = mii_bus->priv;
6962
6963         if (phyaddr > 0)
6964                 return -ENODEV;
6965
6966         return rtl_readphy(tp, phyreg);
6967 }
6968
6969 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6970                                 int phyreg, u16 val)
6971 {
6972         struct rtl8169_private *tp = mii_bus->priv;
6973
6974         if (phyaddr > 0)
6975                 return -ENODEV;
6976
6977         rtl_writephy(tp, phyreg, val);
6978
6979         return 0;
6980 }
6981
6982 static int r8169_mdio_register(struct rtl8169_private *tp)
6983 {
6984         struct pci_dev *pdev = tp->pci_dev;
6985         struct mii_bus *new_bus;
6986         int ret;
6987
6988         new_bus = devm_mdiobus_alloc(&pdev->dev);
6989         if (!new_bus)
6990                 return -ENOMEM;
6991
6992         new_bus->name = "r8169";
6993         new_bus->priv = tp;
6994         new_bus->parent = &pdev->dev;
6995         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6996         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6997
6998         new_bus->read = r8169_mdio_read_reg;
6999         new_bus->write = r8169_mdio_write_reg;
7000
7001         ret = mdiobus_register(new_bus);
7002         if (ret)
7003                 return ret;
7004
7005         tp->phydev = mdiobus_get_phy(new_bus, 0);
7006         if (!tp->phydev) {
7007                 mdiobus_unregister(new_bus);
7008                 return -ENODEV;
7009         }
7010
7011         /* PHY will be woken up in rtl_open() */
7012         phy_suspend(tp->phydev);
7013
7014         return 0;
7015 }
7016
7017 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7018 {
7019         u32 data;
7020
7021         tp->ocp_base = OCP_STD_PHY_BASE;
7022
7023         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7024
7025         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7026                 return;
7027
7028         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7029                 return;
7030
7031         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7032         msleep(1);
7033         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7034
7035         data = r8168_mac_ocp_read(tp, 0xe8de);
7036         data &= ~(1 << 14);
7037         r8168_mac_ocp_write(tp, 0xe8de, data);
7038
7039         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7040                 return;
7041
7042         data = r8168_mac_ocp_read(tp, 0xe8de);
7043         data |= (1 << 15);
7044         r8168_mac_ocp_write(tp, 0xe8de, data);
7045
7046         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7047                 return;
7048 }
7049
7050 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7051 {
7052         rtl8168ep_stop_cmac(tp);
7053         rtl_hw_init_8168g(tp);
7054 }
7055
7056 static void rtl_hw_initialize(struct rtl8169_private *tp)
7057 {
7058         switch (tp->mac_version) {
7059         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7060                 rtl_hw_init_8168g(tp);
7061                 break;
7062         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7063                 rtl_hw_init_8168ep(tp);
7064                 break;
7065         default:
7066                 break;
7067         }
7068 }
7069
7070 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7071 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7072 {
7073         switch (tp->mac_version) {
7074         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7075         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7076                 return false;
7077         default:
7078                 return true;
7079         }
7080 }
7081
7082 static int rtl_jumbo_max(struct rtl8169_private *tp)
7083 {
7084         /* Non-GBit versions don't support jumbo frames */
7085         if (!tp->supports_gmii)
7086                 return JUMBO_1K;
7087
7088         switch (tp->mac_version) {
7089         /* RTL8169 */
7090         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7091                 return JUMBO_7K;
7092         /* RTL8168b */
7093         case RTL_GIGA_MAC_VER_11:
7094         case RTL_GIGA_MAC_VER_12:
7095         case RTL_GIGA_MAC_VER_17:
7096                 return JUMBO_4K;
7097         /* RTL8168c */
7098         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7099                 return JUMBO_6K;
7100         default:
7101                 return JUMBO_9K;
7102         }
7103 }
7104
7105 static void rtl_disable_clk(void *data)
7106 {
7107         clk_disable_unprepare(data);
7108 }
7109
7110 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7111 {
7112         struct device *d = tp_to_dev(tp);
7113         struct clk *clk;
7114         int rc;
7115
7116         clk = devm_clk_get(d, "ether_clk");
7117         if (IS_ERR(clk)) {
7118                 rc = PTR_ERR(clk);
7119                 if (rc == -ENOENT)
7120                         /* clk-core allows NULL (for suspend / resume) */
7121                         rc = 0;
7122                 else if (rc != -EPROBE_DEFER)
7123                         dev_err(d, "failed to get clk: %d\n", rc);
7124         } else {
7125                 tp->clk = clk;
7126                 rc = clk_prepare_enable(clk);
7127                 if (rc)
7128                         dev_err(d, "failed to enable clk: %d\n", rc);
7129                 else
7130                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7131         }
7132
7133         return rc;
7134 }
7135
7136 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7137 {
7138         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7139         /* align to u16 for is_valid_ether_addr() */
7140         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7141         struct rtl8169_private *tp;
7142         struct net_device *dev;
7143         int chipset, region, i;
7144         int jumbo_max, rc;
7145
7146         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7147         if (!dev)
7148                 return -ENOMEM;
7149
7150         SET_NETDEV_DEV(dev, &pdev->dev);
7151         dev->netdev_ops = &rtl_netdev_ops;
7152         tp = netdev_priv(dev);
7153         tp->dev = dev;
7154         tp->pci_dev = pdev;
7155         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7156         tp->supports_gmii = cfg->has_gmii;
7157
7158         /* Get the *optional* external "ether_clk" used on some boards */
7159         rc = rtl_get_ether_clk(tp);
7160         if (rc)
7161                 return rc;
7162
7163         /* Disable ASPM completely as that cause random device stop working
7164          * problems as well as full system hangs for some PCIe devices users.
7165          */
7166         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7167
7168         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7169         rc = pcim_enable_device(pdev);
7170         if (rc < 0) {
7171                 dev_err(&pdev->dev, "enable failure\n");
7172                 return rc;
7173         }
7174
7175         if (pcim_set_mwi(pdev) < 0)
7176                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7177
7178         /* use first MMIO region */
7179         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7180         if (region < 0) {
7181                 dev_err(&pdev->dev, "no MMIO resource found\n");
7182                 return -ENODEV;
7183         }
7184
7185         /* check for weird/broken PCI region reporting */
7186         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7187                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7188                 return -ENODEV;
7189         }
7190
7191         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7192         if (rc < 0) {
7193                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7194                 return rc;
7195         }
7196
7197         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7198
7199         /* Identify chip attached to board */
7200         rtl8169_get_mac_version(tp);
7201         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7202                 return -ENODEV;
7203
7204         if (rtl_tbi_enabled(tp)) {
7205                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7206                 return -ENODEV;
7207         }
7208
7209         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7210
7211         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7212             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7213                 dev->features |= NETIF_F_HIGHDMA;
7214         } else {
7215                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7216                 if (rc < 0) {
7217                         dev_err(&pdev->dev, "DMA configuration failed\n");
7218                         return rc;
7219                 }
7220         }
7221
7222         rtl_init_rxcfg(tp);
7223
7224         rtl8169_irq_mask_and_ack(tp);
7225
7226         rtl_hw_initialize(tp);
7227
7228         rtl_hw_reset(tp);
7229
7230         pci_set_master(pdev);
7231
7232         rtl_init_mdio_ops(tp);
7233         rtl_init_jumbo_ops(tp);
7234
7235         chipset = tp->mac_version;
7236
7237         rc = rtl_alloc_irq(tp);
7238         if (rc < 0) {
7239                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7240                 return rc;
7241         }
7242
7243         mutex_init(&tp->wk.mutex);
7244         INIT_WORK(&tp->wk.work, rtl_task);
7245         u64_stats_init(&tp->rx_stats.syncp);
7246         u64_stats_init(&tp->tx_stats.syncp);
7247
7248         /* get MAC address */
7249         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7250         if (rc)
7251                 rtl_read_mac_address(tp, mac_addr);
7252
7253         if (is_valid_ether_addr(mac_addr))
7254                 rtl_rar_set(tp, mac_addr);
7255
7256         for (i = 0; i < ETH_ALEN; i++)
7257                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7258
7259         dev->ethtool_ops = &rtl8169_ethtool_ops;
7260
7261         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7262
7263         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7264          * properly for all devices */
7265         dev->features |= NETIF_F_RXCSUM |
7266                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7267
7268         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7269                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7270                 NETIF_F_HW_VLAN_CTAG_RX;
7271         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7272                 NETIF_F_HIGHDMA;
7273         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7274
7275         tp->cp_cmd |= RxChkSum | RxVlan;
7276
7277         /*
7278          * Pretend we are using VLANs; This bypasses a nasty bug where
7279          * Interrupts stop flowing on high load on 8110SCd controllers.
7280          */
7281         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7282                 /* Disallow toggling */
7283                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7284
7285         if (rtl_chip_supports_csum_v2(tp)) {
7286                 tp->tso_csum = rtl8169_tso_csum_v2;
7287                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7288         } else {
7289                 tp->tso_csum = rtl8169_tso_csum_v1;
7290         }
7291
7292         dev->hw_features |= NETIF_F_RXALL;
7293         dev->hw_features |= NETIF_F_RXFCS;
7294
7295         /* MTU range: 60 - hw-specific max */
7296         dev->min_mtu = ETH_ZLEN;
7297         jumbo_max = rtl_jumbo_max(tp);
7298         dev->max_mtu = jumbo_max;
7299
7300         tp->hw_start = cfg->hw_start;
7301         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7302         tp->coalesce_info = cfg->coalesce_info;
7303
7304         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7305
7306         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7307                                             &tp->counters_phys_addr,
7308                                             GFP_KERNEL);
7309         if (!tp->counters)
7310                 return -ENOMEM;
7311
7312         pci_set_drvdata(pdev, dev);
7313
7314         rc = r8169_mdio_register(tp);
7315         if (rc)
7316                 return rc;
7317
7318         /* chip gets powered up in rtl_open() */
7319         rtl_pll_power_down(tp);
7320
7321         rc = register_netdev(dev);
7322         if (rc)
7323                 goto err_mdio_unregister;
7324
7325         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7326                    rtl_chip_infos[chipset].name, dev->dev_addr,
7327                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7328                    pci_irq_vector(pdev, 0));
7329
7330         if (jumbo_max > JUMBO_1K)
7331                 netif_info(tp, probe, dev,
7332                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7333                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7334                            "ok" : "ko");
7335
7336         if (r8168_check_dash(tp))
7337                 rtl8168_driver_start(tp);
7338
7339         if (pci_dev_run_wake(pdev))
7340                 pm_runtime_put_sync(&pdev->dev);
7341
7342         return 0;
7343
7344 err_mdio_unregister:
7345         mdiobus_unregister(tp->phydev->mdio.bus);
7346         return rc;
7347 }
7348
7349 static struct pci_driver rtl8169_pci_driver = {
7350         .name           = MODULENAME,
7351         .id_table       = rtl8169_pci_tbl,
7352         .probe          = rtl_init_one,
7353         .remove         = rtl_remove_one,
7354         .shutdown       = rtl_shutdown,
7355         .driver.pm      = RTL8169_PM_OPS,
7356 };
7357
7358 module_pci_driver(rtl8169_pci_driver);