2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/phy.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
33 #define MODULENAME "r8169"
35 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
36 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
37 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
38 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
39 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
40 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
41 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
42 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
43 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
44 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
46 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
47 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
48 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
49 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
50 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
51 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
52 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
53 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
55 #define R8169_MSG_DEFAULT \
56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58 #define TX_SLOTS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
62 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
63 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
67 static const int multicast_filter_limit = 32;
69 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
70 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72 #define R8169_REGS_SIZE 256
73 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
74 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
76 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
77 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79 #define RTL8169_TX_TIMEOUT (6*HZ)
81 /* write/read MMIO register */
82 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
83 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
84 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
85 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
86 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
87 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
90 RTL_GIGA_MAC_VER_01 = 0,
141 RTL_GIGA_MAC_NONE = 0xff,
144 #define JUMBO_1K ETH_DATA_LEN
145 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
146 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
147 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
148 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150 static const struct {
153 } rtl_chip_infos[] = {
155 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
197 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
198 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
199 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
215 static const struct pci_device_id rtl8169_pci_tbl[] = {
216 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
222 { PCI_VENDOR_ID_DLINK, 0x4300,
223 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
224 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
225 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
226 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
227 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
228 { PCI_VENDOR_ID_LINKSYS, 0x1032,
229 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
231 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
237 static int use_dac = -1;
243 MAC0 = 0, /* Ethernet hardware address. */
245 MAR0 = 8, /* Multicast filter. */
246 CounterAddrLow = 0x10,
247 CounterAddrHigh = 0x14,
248 TxDescStartAddrLow = 0x20,
249 TxDescStartAddrHigh = 0x24,
250 TxHDescStartAddrLow = 0x28,
251 TxHDescStartAddrHigh = 0x2c,
260 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
261 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
264 #define RX128_INT_EN (1 << 15) /* 8111c and later */
265 #define RX_MULTI_EN (1 << 14) /* 8111c only */
266 #define RXCFG_FIFO_SHIFT 13
267 /* No threshold before first PCI xfer */
268 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
269 #define RX_EARLY_OFF (1 << 11)
270 #define RXCFG_DMA_SHIFT 8
271 /* Unlimited maximum PCI burst. */
272 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
279 #define PME_SIGNAL (1 << 5) /* 8168c and later */
291 #define RTL_COALESCE_MASK 0x0f
292 #define RTL_COALESCE_SHIFT 4
293 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
294 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
296 RxDescAddrLow = 0xe4,
297 RxDescAddrHigh = 0xe8,
298 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
300 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
302 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
304 #define TxPacketMax (8064 >> 7)
305 #define EarlySize 0x27
308 FuncEventMask = 0xf4,
309 FuncPresetState = 0xf8,
314 FuncForceEvent = 0xfc,
317 enum rtl8168_8101_registers {
320 #define CSIAR_FLAG 0x80000000
321 #define CSIAR_WRITE_CMD 0x80000000
322 #define CSIAR_BYTE_ENABLE 0x0000f000
323 #define CSIAR_ADDR_MASK 0x00000fff
326 #define EPHYAR_FLAG 0x80000000
327 #define EPHYAR_WRITE_CMD 0x80000000
328 #define EPHYAR_REG_MASK 0x1f
329 #define EPHYAR_REG_SHIFT 16
330 #define EPHYAR_DATA_MASK 0xffff
332 #define PFM_EN (1 << 6)
333 #define TX_10M_PS_EN (1 << 7)
335 #define FIX_NAK_1 (1 << 4)
336 #define FIX_NAK_2 (1 << 3)
339 #define NOW_IS_OOB (1 << 7)
340 #define TX_EMPTY (1 << 5)
341 #define RX_EMPTY (1 << 4)
342 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
343 #define EN_NDP (1 << 3)
344 #define EN_OOB_RESET (1 << 2)
345 #define LINK_LIST_RDY (1 << 1)
347 #define EFUSEAR_FLAG 0x80000000
348 #define EFUSEAR_WRITE_CMD 0x80000000
349 #define EFUSEAR_READ_CMD 0x00000000
350 #define EFUSEAR_REG_MASK 0x03ff
351 #define EFUSEAR_REG_SHIFT 8
352 #define EFUSEAR_DATA_MASK 0xff
354 #define PFM_D3COLD_EN (1 << 6)
357 enum rtl8168_registers {
362 #define ERIAR_FLAG 0x80000000
363 #define ERIAR_WRITE_CMD 0x80000000
364 #define ERIAR_READ_CMD 0x00000000
365 #define ERIAR_ADDR_BYTE_ALIGN 4
366 #define ERIAR_TYPE_SHIFT 16
367 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
368 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
369 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
370 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_MASK_SHIFT 12
372 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
373 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
374 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
377 EPHY_RXER_NUM = 0x7c,
378 OCPDR = 0xb0, /* OCP GPHY access */
379 #define OCPDR_WRITE_CMD 0x80000000
380 #define OCPDR_READ_CMD 0x00000000
381 #define OCPDR_REG_MASK 0x7f
382 #define OCPDR_GPHY_REG_SHIFT 16
383 #define OCPDR_DATA_MASK 0xffff
385 #define OCPAR_FLAG 0x80000000
386 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
387 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
393 #define PWM_EN (1 << 22)
394 #define RXDV_GATED_EN (1 << 19)
395 #define EARLY_TALLY_EN (1 << 16)
398 enum rtl_register_content {
399 /* InterruptStatusBits */
403 TxDescUnavail = 0x0080,
427 /* TXPoll register p.5 */
428 HPQ = 0x80, /* Poll cmd on the high prio queue */
429 NPQ = 0x40, /* Poll cmd on the low prio queue */
430 FSWInt = 0x01, /* Forced software interrupt */
434 Cfg9346_Unlock = 0xc0,
439 AcceptBroadcast = 0x08,
440 AcceptMulticast = 0x04,
442 AcceptAllPhys = 0x01,
443 #define RX_CONFIG_ACCEPT_MASK 0x3f
446 TxInterFrameGapShift = 24,
447 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
449 /* Config1 register p.24 */
452 Speed_down = (1 << 4),
456 PMEnable = (1 << 0), /* Power Management Enable */
458 /* Config2 register p. 25 */
459 ClkReqEn = (1 << 7), /* Clock Request Enable */
460 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
461 PCI_Clock_66MHz = 0x01,
462 PCI_Clock_33MHz = 0x00,
464 /* Config3 register p.25 */
465 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
466 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
467 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
468 Rdy_to_L23 = (1 << 1), /* L23 Enable */
469 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
471 /* Config4 register */
472 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
474 /* Config5 register p.27 */
475 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
476 MWF = (1 << 5), /* Accept Multicast wakeup frame */
477 UWF = (1 << 4), /* Accept Unicast wakeup frame */
479 LanWake = (1 << 1), /* LanWake enable/disable */
480 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
481 ASPM_en = (1 << 0), /* ASPM enable */
484 EnableBist = (1 << 15), // 8168 8101
485 Mac_dbgo_oe = (1 << 14), // 8168 8101
486 Normal_mode = (1 << 13), // unused
487 Force_half_dup = (1 << 12), // 8168 8101
488 Force_rxflow_en = (1 << 11), // 8168 8101
489 Force_txflow_en = (1 << 10), // 8168 8101
490 Cxpl_dbg_sel = (1 << 9), // 8168 8101
491 ASF = (1 << 8), // 8168 8101
492 PktCntrDisable = (1 << 7), // 8168 8101
493 Mac_dbgo_sel = 0x001c, // 8168
498 #define INTT_MASK GENMASK(1, 0)
499 INTT_0 = 0x0000, // 8168
500 INTT_1 = 0x0001, // 8168
501 INTT_2 = 0x0002, // 8168
502 INTT_3 = 0x0003, // 8168
504 /* rtl8169_PHYstatus */
515 TBILinkOK = 0x02000000,
517 /* ResetCounterCommand */
520 /* DumpCounterCommand */
523 /* magic enable v2 */
524 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
528 /* First doubleword. */
529 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
530 RingEnd = (1 << 30), /* End of descriptor ring */
531 FirstFrag = (1 << 29), /* First segment of a packet */
532 LastFrag = (1 << 28), /* Final segment of a packet */
536 enum rtl_tx_desc_bit {
537 /* First doubleword. */
538 TD_LSO = (1 << 27), /* Large Send Offload */
539 #define TD_MSS_MAX 0x07ffu /* MSS value */
541 /* Second doubleword. */
542 TxVlanTag = (1 << 17), /* Add VLAN tag */
545 /* 8169, 8168b and 810x except 8102e. */
546 enum rtl_tx_desc_bit_0 {
547 /* First doubleword. */
548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
549 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
550 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
551 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
554 /* 8102e, 8168c and beyond. */
555 enum rtl_tx_desc_bit_1 {
556 /* First doubleword. */
557 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
558 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
559 #define GTTCPHO_SHIFT 18
560 #define GTTCPHO_MAX 0x7fU
562 /* Second doubleword. */
563 #define TCPHO_SHIFT 18
564 #define TCPHO_MAX 0x3ffU
565 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
566 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
567 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
568 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
569 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
572 enum rtl_rx_desc_bit {
574 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
575 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
577 #define RxProtoUDP (PID1)
578 #define RxProtoTCP (PID0)
579 #define RxProtoIP (PID1 | PID0)
580 #define RxProtoMask RxProtoIP
582 IPFail = (1 << 16), /* IP checksum failed */
583 UDPFail = (1 << 15), /* UDP/IP checksum failed */
584 TCPFail = (1 << 14), /* TCP/IP checksum failed */
585 RxVlanTag = (1 << 16), /* VLAN tag available */
588 #define RsvdMask 0x3fffc000
589 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
606 u8 __pad[sizeof(void *) - sizeof(u32)];
609 struct rtl8169_counters {
616 __le32 tx_one_collision;
617 __le32 tx_multi_collision;
625 struct rtl8169_tc_offsets {
628 __le32 tx_multi_collision;
633 RTL_FLAG_TASK_ENABLED,
634 RTL_FLAG_TASK_SLOW_PENDING,
635 RTL_FLAG_TASK_RESET_PENDING,
639 struct rtl8169_stats {
642 struct u64_stats_sync syncp;
645 struct rtl8169_private {
646 void __iomem *mmio_addr; /* memory map physical address */
647 struct pci_dev *pci_dev;
648 struct net_device *dev;
649 struct napi_struct napi;
652 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
653 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
655 struct rtl8169_stats rx_stats;
656 struct rtl8169_stats tx_stats;
657 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
658 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
659 dma_addr_t TxPhyAddr;
660 dma_addr_t RxPhyAddr;
661 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
662 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
666 const struct rtl_coalesce_info *coalesce_info;
669 void (*write)(struct rtl8169_private *, int, int);
670 int (*read)(struct rtl8169_private *, int);
674 void (*enable)(struct rtl8169_private *);
675 void (*disable)(struct rtl8169_private *);
678 void (*hw_start)(struct rtl8169_private *tp);
679 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
682 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
684 struct work_struct work;
687 unsigned supports_gmii:1;
688 struct mii_bus *mii_bus;
689 dma_addr_t counters_phys_addr;
690 struct rtl8169_counters *counters;
691 struct rtl8169_tc_offsets tc_offset;
695 const struct firmware *fw;
697 #define RTL_VER_SIZE 32
699 char version[RTL_VER_SIZE];
701 struct rtl_fw_phy_action {
706 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
711 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
712 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
713 module_param(use_dac, int, 0);
714 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
715 module_param_named(debug, debug.msg_enable, int, 0);
716 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
717 MODULE_LICENSE("GPL");
718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
722 MODULE_FIRMWARE(FIRMWARE_8168E_3);
723 MODULE_FIRMWARE(FIRMWARE_8105E_1);
724 MODULE_FIRMWARE(FIRMWARE_8168F_1);
725 MODULE_FIRMWARE(FIRMWARE_8168F_2);
726 MODULE_FIRMWARE(FIRMWARE_8402_1);
727 MODULE_FIRMWARE(FIRMWARE_8411_1);
728 MODULE_FIRMWARE(FIRMWARE_8411_2);
729 MODULE_FIRMWARE(FIRMWARE_8106E_1);
730 MODULE_FIRMWARE(FIRMWARE_8106E_2);
731 MODULE_FIRMWARE(FIRMWARE_8168G_2);
732 MODULE_FIRMWARE(FIRMWARE_8168G_3);
733 MODULE_FIRMWARE(FIRMWARE_8168H_1);
734 MODULE_FIRMWARE(FIRMWARE_8168H_2);
735 MODULE_FIRMWARE(FIRMWARE_8107E_1);
736 MODULE_FIRMWARE(FIRMWARE_8107E_2);
738 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
740 return &tp->pci_dev->dev;
743 static void rtl_lock_work(struct rtl8169_private *tp)
745 mutex_lock(&tp->wk.mutex);
748 static void rtl_unlock_work(struct rtl8169_private *tp)
750 mutex_unlock(&tp->wk.mutex);
753 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
755 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
756 PCI_EXP_DEVCTL_READRQ, force);
760 bool (*check)(struct rtl8169_private *);
764 static void rtl_udelay(unsigned int d)
769 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
770 void (*delay)(unsigned int), unsigned int d, int n,
775 for (i = 0; i < n; i++) {
777 if (c->check(tp) == high)
780 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
781 c->msg, !high, n, d);
785 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
786 const struct rtl_cond *c,
787 unsigned int d, int n)
789 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
792 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
793 const struct rtl_cond *c,
794 unsigned int d, int n)
796 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
799 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
800 const struct rtl_cond *c,
801 unsigned int d, int n)
803 return rtl_loop_wait(tp, c, msleep, d, n, true);
806 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
807 const struct rtl_cond *c,
808 unsigned int d, int n)
810 return rtl_loop_wait(tp, c, msleep, d, n, false);
813 #define DECLARE_RTL_COND(name) \
814 static bool name ## _check(struct rtl8169_private *); \
816 static const struct rtl_cond name = { \
817 .check = name ## _check, \
821 static bool name ## _check(struct rtl8169_private *tp)
823 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
825 if (reg & 0xffff0001) {
826 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
832 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
834 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
837 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
839 if (rtl_ocp_reg_failure(tp, reg))
842 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
844 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
847 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
849 if (rtl_ocp_reg_failure(tp, reg))
852 RTL_W32(tp, GPHY_OCP, reg << 15);
854 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
855 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
858 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
860 if (rtl_ocp_reg_failure(tp, reg))
863 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
866 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
868 if (rtl_ocp_reg_failure(tp, reg))
871 RTL_W32(tp, OCPDR, reg << 15);
873 return RTL_R32(tp, OCPDR);
876 #define OCP_STD_PHY_BASE 0xa400
878 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
881 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
885 if (tp->ocp_base != OCP_STD_PHY_BASE)
888 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
891 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
893 if (tp->ocp_base != OCP_STD_PHY_BASE)
896 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
899 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
902 tp->ocp_base = value << 4;
906 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
909 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
911 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
914 DECLARE_RTL_COND(rtl_phyar_cond)
916 return RTL_R32(tp, PHYAR) & 0x80000000;
919 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
921 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
923 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
925 * According to hardware specs a 20us delay is required after write
926 * complete indication, but before sending next command.
931 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
935 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
937 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
938 RTL_R32(tp, PHYAR) & 0xffff : ~0;
941 * According to hardware specs a 20us delay is required after read
942 * complete indication, but before sending next command.
949 DECLARE_RTL_COND(rtl_ocpar_cond)
951 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
954 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
956 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
957 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
958 RTL_W32(tp, EPHY_RXER_NUM, 0);
960 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
963 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
965 r8168dp_1_mdio_access(tp, reg,
966 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
969 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
971 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
974 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
975 RTL_W32(tp, EPHY_RXER_NUM, 0);
977 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
978 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
981 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
983 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
985 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
988 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
990 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
993 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
995 r8168dp_2_mdio_start(tp);
997 r8169_mdio_write(tp, reg, value);
999 r8168dp_2_mdio_stop(tp);
1002 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006 r8168dp_2_mdio_start(tp);
1008 value = r8169_mdio_read(tp, reg);
1010 r8168dp_2_mdio_stop(tp);
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1017 tp->mdio_ops.write(tp, location, val);
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1022 return tp->mdio_ops.read(tp, location);
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1027 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 val = rtl_readphy(tp, reg_addr);
1035 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1038 DECLARE_RTL_COND(rtl_ephyar_cond)
1040 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1043 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1045 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1046 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1048 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1053 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1055 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1057 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1058 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1061 DECLARE_RTL_COND(rtl_eriar_cond)
1063 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1066 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1069 BUG_ON((addr & 3) || (mask == 0));
1070 RTL_W32(tp, ERIDR, val);
1071 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1073 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1078 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1080 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1081 RTL_R32(tp, ERIDR) : ~0;
1084 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1089 val = rtl_eri_read(tp, addr, type);
1090 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1093 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1095 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1096 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1097 RTL_R32(tp, OCPDR) : ~0;
1100 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1102 return rtl_eri_read(tp, reg, ERIAR_OOB);
1105 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1107 switch (tp->mac_version) {
1108 case RTL_GIGA_MAC_VER_27:
1109 case RTL_GIGA_MAC_VER_28:
1110 case RTL_GIGA_MAC_VER_31:
1111 return r8168dp_ocp_read(tp, mask, reg);
1112 case RTL_GIGA_MAC_VER_49:
1113 case RTL_GIGA_MAC_VER_50:
1114 case RTL_GIGA_MAC_VER_51:
1115 return r8168ep_ocp_read(tp, mask, reg);
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1125 RTL_W32(tp, OCPDR, data);
1126 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1133 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1139 switch (tp->mac_version) {
1140 case RTL_GIGA_MAC_VER_27:
1141 case RTL_GIGA_MAC_VER_28:
1142 case RTL_GIGA_MAC_VER_31:
1143 r8168dp_ocp_write(tp, mask, reg, data);
1145 case RTL_GIGA_MAC_VER_49:
1146 case RTL_GIGA_MAC_VER_50:
1147 case RTL_GIGA_MAC_VER_51:
1148 r8168ep_ocp_write(tp, mask, reg, data);
1156 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1158 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1160 ocp_write(tp, 0x1, 0x30, 0x00000001);
1163 #define OOB_CMD_RESET 0x00
1164 #define OOB_CMD_DRIVER_START 0x05
1165 #define OOB_CMD_DRIVER_STOP 0x06
1167 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1169 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1172 DECLARE_RTL_COND(rtl_ocp_read_cond)
1176 reg = rtl8168_get_ocp_reg(tp);
1178 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1181 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1183 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1186 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1188 return RTL_R8(tp, IBISR0) & 0x20;
1191 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1193 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1194 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1195 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1196 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1199 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1201 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1202 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1205 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1207 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1208 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1209 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1212 static void rtl8168_driver_start(struct rtl8169_private *tp)
1214 switch (tp->mac_version) {
1215 case RTL_GIGA_MAC_VER_27:
1216 case RTL_GIGA_MAC_VER_28:
1217 case RTL_GIGA_MAC_VER_31:
1218 rtl8168dp_driver_start(tp);
1220 case RTL_GIGA_MAC_VER_49:
1221 case RTL_GIGA_MAC_VER_50:
1222 case RTL_GIGA_MAC_VER_51:
1223 rtl8168ep_driver_start(tp);
1231 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1233 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1234 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1237 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1239 rtl8168ep_stop_cmac(tp);
1240 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1241 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1242 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1245 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1247 switch (tp->mac_version) {
1248 case RTL_GIGA_MAC_VER_27:
1249 case RTL_GIGA_MAC_VER_28:
1250 case RTL_GIGA_MAC_VER_31:
1251 rtl8168dp_driver_stop(tp);
1253 case RTL_GIGA_MAC_VER_49:
1254 case RTL_GIGA_MAC_VER_50:
1255 case RTL_GIGA_MAC_VER_51:
1256 rtl8168ep_driver_stop(tp);
1264 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1266 u16 reg = rtl8168_get_ocp_reg(tp);
1268 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1271 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1273 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1276 static bool r8168_check_dash(struct rtl8169_private *tp)
1278 switch (tp->mac_version) {
1279 case RTL_GIGA_MAC_VER_27:
1280 case RTL_GIGA_MAC_VER_28:
1281 case RTL_GIGA_MAC_VER_31:
1282 return r8168dp_check_dash(tp);
1283 case RTL_GIGA_MAC_VER_49:
1284 case RTL_GIGA_MAC_VER_50:
1285 case RTL_GIGA_MAC_VER_51:
1286 return r8168ep_check_dash(tp);
1298 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1299 const struct exgmac_reg *r, int len)
1302 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1309 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1314 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1316 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1320 static u16 rtl_get_events(struct rtl8169_private *tp)
1322 return RTL_R16(tp, IntrStatus);
1325 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1327 RTL_W16(tp, IntrStatus, bits);
1331 static void rtl_irq_disable(struct rtl8169_private *tp)
1333 RTL_W16(tp, IntrMask, 0);
1337 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1339 RTL_W16(tp, IntrMask, bits);
1342 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1343 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1344 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1346 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1348 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1353 rtl_irq_disable(tp);
1354 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1355 RTL_R8(tp, ChipCmd);
1358 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1360 struct net_device *dev = tp->dev;
1361 struct phy_device *phydev = dev->phydev;
1363 if (!netif_running(dev))
1366 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1367 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1368 if (phydev->speed == SPEED_1000) {
1369 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1371 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1373 } else if (phydev->speed == SPEED_100) {
1374 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1376 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1379 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1381 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1384 /* Reset packet filter */
1385 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1387 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1389 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1390 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1391 if (phydev->speed == SPEED_1000) {
1392 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1394 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1397 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1399 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1402 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1403 if (phydev->speed == SPEED_10) {
1404 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1406 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1409 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1415 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1417 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1422 options = RTL_R8(tp, Config1);
1423 if (!(options & PMEnable))
1426 options = RTL_R8(tp, Config3);
1427 if (options & LinkUp)
1428 wolopts |= WAKE_PHY;
1429 switch (tp->mac_version) {
1430 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1431 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1432 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1433 wolopts |= WAKE_MAGIC;
1436 if (options & MagicPacket)
1437 wolopts |= WAKE_MAGIC;
1441 options = RTL_R8(tp, Config5);
1443 wolopts |= WAKE_UCAST;
1445 wolopts |= WAKE_BCAST;
1447 wolopts |= WAKE_MCAST;
1452 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1454 struct rtl8169_private *tp = netdev_priv(dev);
1457 wol->supported = WAKE_ANY;
1458 wol->wolopts = tp->saved_wolopts;
1459 rtl_unlock_work(tp);
1462 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1464 unsigned int i, tmp;
1465 static const struct {
1470 { WAKE_PHY, Config3, LinkUp },
1471 { WAKE_UCAST, Config5, UWF },
1472 { WAKE_BCAST, Config5, BWF },
1473 { WAKE_MCAST, Config5, MWF },
1474 { WAKE_ANY, Config5, LanWake },
1475 { WAKE_MAGIC, Config3, MagicPacket }
1479 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1483 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1484 tmp = ARRAY_SIZE(cfg) - 1;
1485 if (wolopts & WAKE_MAGIC)
1501 tmp = ARRAY_SIZE(cfg);
1505 for (i = 0; i < tmp; i++) {
1506 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1507 if (wolopts & cfg[i].opt)
1508 options |= cfg[i].mask;
1509 RTL_W8(tp, cfg[i].reg, options);
1512 switch (tp->mac_version) {
1513 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1514 options = RTL_R8(tp, Config1) & ~PMEnable;
1516 options |= PMEnable;
1517 RTL_W8(tp, Config1, options);
1520 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1522 options |= PME_SIGNAL;
1523 RTL_W8(tp, Config2, options);
1527 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1530 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1532 struct rtl8169_private *tp = netdev_priv(dev);
1533 struct device *d = tp_to_dev(tp);
1535 if (wol->wolopts & ~WAKE_ANY)
1538 pm_runtime_get_noresume(d);
1542 tp->saved_wolopts = wol->wolopts;
1544 if (pm_runtime_active(d))
1545 __rtl8169_set_wol(tp, tp->saved_wolopts);
1547 rtl_unlock_work(tp);
1549 device_set_wakeup_enable(d, tp->saved_wolopts);
1551 pm_runtime_put_noidle(d);
1556 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1558 return rtl_chip_infos[tp->mac_version].fw_name;
1561 static void rtl8169_get_drvinfo(struct net_device *dev,
1562 struct ethtool_drvinfo *info)
1564 struct rtl8169_private *tp = netdev_priv(dev);
1565 struct rtl_fw *rtl_fw = tp->rtl_fw;
1567 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1568 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1569 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1570 if (!IS_ERR_OR_NULL(rtl_fw))
1571 strlcpy(info->fw_version, rtl_fw->version,
1572 sizeof(info->fw_version));
1575 static int rtl8169_get_regs_len(struct net_device *dev)
1577 return R8169_REGS_SIZE;
1580 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1581 netdev_features_t features)
1583 struct rtl8169_private *tp = netdev_priv(dev);
1585 if (dev->mtu > TD_MSS_MAX)
1586 features &= ~NETIF_F_ALL_TSO;
1588 if (dev->mtu > JUMBO_1K &&
1589 tp->mac_version > RTL_GIGA_MAC_VER_06)
1590 features &= ~NETIF_F_IP_CSUM;
1595 static int rtl8169_set_features(struct net_device *dev,
1596 netdev_features_t features)
1598 struct rtl8169_private *tp = netdev_priv(dev);
1603 rx_config = RTL_R32(tp, RxConfig);
1604 if (features & NETIF_F_RXALL)
1605 rx_config |= (AcceptErr | AcceptRunt);
1607 rx_config &= ~(AcceptErr | AcceptRunt);
1609 RTL_W32(tp, RxConfig, rx_config);
1611 if (features & NETIF_F_RXCSUM)
1612 tp->cp_cmd |= RxChkSum;
1614 tp->cp_cmd &= ~RxChkSum;
1616 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1617 tp->cp_cmd |= RxVlan;
1619 tp->cp_cmd &= ~RxVlan;
1621 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1622 RTL_R16(tp, CPlusCmd);
1624 rtl_unlock_work(tp);
1629 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1631 return (skb_vlan_tag_present(skb)) ?
1632 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1635 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1637 u32 opts2 = le32_to_cpu(desc->opts2);
1639 if (opts2 & RxVlanTag)
1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1643 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1646 struct rtl8169_private *tp = netdev_priv(dev);
1647 u32 __iomem *data = tp->mmio_addr;
1652 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1653 memcpy_fromio(dw++, data++, 4);
1654 rtl_unlock_work(tp);
1657 static u32 rtl8169_get_msglevel(struct net_device *dev)
1659 struct rtl8169_private *tp = netdev_priv(dev);
1661 return tp->msg_enable;
1664 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1666 struct rtl8169_private *tp = netdev_priv(dev);
1668 tp->msg_enable = value;
1671 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1678 "tx_single_collisions",
1679 "tx_multi_collisions",
1687 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1691 return ARRAY_SIZE(rtl8169_gstrings);
1697 DECLARE_RTL_COND(rtl_counters_cond)
1699 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1702 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1704 dma_addr_t paddr = tp->counters_phys_addr;
1707 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1708 RTL_R32(tp, CounterAddrHigh);
1709 cmd = (u64)paddr & DMA_BIT_MASK(32);
1710 RTL_W32(tp, CounterAddrLow, cmd);
1711 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1713 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1716 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1719 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1722 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1725 return rtl8169_do_counters(tp, CounterReset);
1728 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1731 * Some chips are unable to dump tally counters when the receiver
1734 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1737 return rtl8169_do_counters(tp, CounterDump);
1740 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1742 struct rtl8169_counters *counters = tp->counters;
1746 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1747 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1748 * reset by a power cycle, while the counter values collected by the
1749 * driver are reset at every driver unload/load cycle.
1751 * To make sure the HW values returned by @get_stats64 match the SW
1752 * values, we collect the initial values at first open(*) and use them
1753 * as offsets to normalize the values returned by @get_stats64.
1755 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1756 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1757 * set at open time by rtl_hw_start.
1760 if (tp->tc_offset.inited)
1763 /* If both, reset and update fail, propagate to caller. */
1764 if (rtl8169_reset_counters(tp))
1767 if (rtl8169_update_counters(tp))
1770 tp->tc_offset.tx_errors = counters->tx_errors;
1771 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1772 tp->tc_offset.tx_aborted = counters->tx_aborted;
1773 tp->tc_offset.inited = true;
1778 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1779 struct ethtool_stats *stats, u64 *data)
1781 struct rtl8169_private *tp = netdev_priv(dev);
1782 struct device *d = tp_to_dev(tp);
1783 struct rtl8169_counters *counters = tp->counters;
1787 pm_runtime_get_noresume(d);
1789 if (pm_runtime_active(d))
1790 rtl8169_update_counters(tp);
1792 pm_runtime_put_noidle(d);
1794 data[0] = le64_to_cpu(counters->tx_packets);
1795 data[1] = le64_to_cpu(counters->rx_packets);
1796 data[2] = le64_to_cpu(counters->tx_errors);
1797 data[3] = le32_to_cpu(counters->rx_errors);
1798 data[4] = le16_to_cpu(counters->rx_missed);
1799 data[5] = le16_to_cpu(counters->align_errors);
1800 data[6] = le32_to_cpu(counters->tx_one_collision);
1801 data[7] = le32_to_cpu(counters->tx_multi_collision);
1802 data[8] = le64_to_cpu(counters->rx_unicast);
1803 data[9] = le64_to_cpu(counters->rx_broadcast);
1804 data[10] = le32_to_cpu(counters->rx_multicast);
1805 data[11] = le16_to_cpu(counters->tx_aborted);
1806 data[12] = le16_to_cpu(counters->tx_underun);
1809 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1813 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1819 * Interrupt coalescing
1821 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1822 * > 8169, 8168 and 810x line of chipsets
1824 * 8169, 8168, and 8136(810x) serial chipsets support it.
1826 * > 2 - the Tx timer unit at gigabit speed
1828 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1829 * (0xe0) bit 1 and bit 0.
1832 * bit[1:0] \ speed 1000M 100M 10M
1833 * 0 0 320ns 2.56us 40.96us
1834 * 0 1 2.56us 20.48us 327.7us
1835 * 1 0 5.12us 40.96us 655.4us
1836 * 1 1 10.24us 81.92us 1.31ms
1839 * bit[1:0] \ speed 1000M 100M 10M
1840 * 0 0 5us 2.56us 40.96us
1841 * 0 1 40us 20.48us 327.7us
1842 * 1 0 80us 40.96us 655.4us
1843 * 1 1 160us 81.92us 1.31ms
1846 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1847 struct rtl_coalesce_scale {
1852 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1853 struct rtl_coalesce_info {
1855 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1858 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1859 #define rxtx_x1822(r, t) { \
1862 {{(r)*8*2, (t)*8*2}}, \
1863 {{(r)*8*2*2, (t)*8*2*2}}, \
1865 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1866 /* speed delays: rx00 tx00 */
1867 { SPEED_10, rxtx_x1822(40960, 40960) },
1868 { SPEED_100, rxtx_x1822( 2560, 2560) },
1869 { SPEED_1000, rxtx_x1822( 320, 320) },
1873 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1874 /* speed delays: rx00 tx00 */
1875 { SPEED_10, rxtx_x1822(40960, 40960) },
1876 { SPEED_100, rxtx_x1822( 2560, 2560) },
1877 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1882 /* get rx/tx scale vector corresponding to current speed */
1883 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1885 struct rtl8169_private *tp = netdev_priv(dev);
1886 struct ethtool_link_ksettings ecmd;
1887 const struct rtl_coalesce_info *ci;
1890 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1894 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1895 if (ecmd.base.speed == ci->speed) {
1900 return ERR_PTR(-ELNRNG);
1903 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1905 struct rtl8169_private *tp = netdev_priv(dev);
1906 const struct rtl_coalesce_info *ci;
1907 const struct rtl_coalesce_scale *scale;
1911 } coal_settings [] = {
1912 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1913 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1914 }, *p = coal_settings;
1918 memset(ec, 0, sizeof(*ec));
1920 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1921 ci = rtl_coalesce_info(dev);
1925 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1927 /* read IntrMitigate and adjust according to scale */
1928 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1929 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1930 w >>= RTL_COALESCE_SHIFT;
1931 *p->usecs = w & RTL_COALESCE_MASK;
1934 for (i = 0; i < 2; i++) {
1935 p = coal_settings + i;
1936 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1939 * ethtool_coalesce says it is illegal to set both usecs and
1942 if (!*p->usecs && !*p->max_frames)
1949 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1950 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1951 struct net_device *dev, u32 nsec, u16 *cp01)
1953 const struct rtl_coalesce_info *ci;
1956 ci = rtl_coalesce_info(dev);
1958 return ERR_CAST(ci);
1960 for (i = 0; i < 4; i++) {
1961 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1962 ci->scalev[i].nsecs[1]);
1963 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1965 return &ci->scalev[i];
1969 return ERR_PTR(-EINVAL);
1972 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1974 struct rtl8169_private *tp = netdev_priv(dev);
1975 const struct rtl_coalesce_scale *scale;
1979 } coal_settings [] = {
1980 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1981 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1982 }, *p = coal_settings;
1986 scale = rtl_coalesce_choose_scale(dev,
1987 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1989 return PTR_ERR(scale);
1991 for (i = 0; i < 2; i++, p++) {
1995 * accept max_frames=1 we returned in rtl_get_coalesce.
1996 * accept it not only when usecs=0 because of e.g. the following scenario:
1998 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1999 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2000 * - then user does `ethtool -C eth0 rx-usecs 100`
2002 * since ethtool sends to kernel whole ethtool_coalesce
2003 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2004 * we'll reject it below in `frames % 4 != 0`.
2006 if (p->frames == 1) {
2010 units = p->usecs * 1000 / scale->nsecs[i];
2011 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2014 w <<= RTL_COALESCE_SHIFT;
2016 w <<= RTL_COALESCE_SHIFT;
2017 w |= p->frames >> 2;
2022 RTL_W16(tp, IntrMitigate, swab16(w));
2024 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2025 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2026 RTL_R16(tp, CPlusCmd);
2028 rtl_unlock_work(tp);
2033 static const struct ethtool_ops rtl8169_ethtool_ops = {
2034 .get_drvinfo = rtl8169_get_drvinfo,
2035 .get_regs_len = rtl8169_get_regs_len,
2036 .get_link = ethtool_op_get_link,
2037 .get_coalesce = rtl_get_coalesce,
2038 .set_coalesce = rtl_set_coalesce,
2039 .get_msglevel = rtl8169_get_msglevel,
2040 .set_msglevel = rtl8169_set_msglevel,
2041 .get_regs = rtl8169_get_regs,
2042 .get_wol = rtl8169_get_wol,
2043 .set_wol = rtl8169_set_wol,
2044 .get_strings = rtl8169_get_strings,
2045 .get_sset_count = rtl8169_get_sset_count,
2046 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2047 .get_ts_info = ethtool_op_get_ts_info,
2048 .nway_reset = phy_ethtool_nway_reset,
2049 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2050 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2053 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2057 * The driver currently handles the 8168Bf and the 8168Be identically
2058 * but they can be identified more specifically through the test below
2061 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2063 * Same thing for the 8101Eb and the 8101Ec:
2065 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2067 static const struct rtl_mac_info {
2072 /* 8168EP family. */
2073 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2074 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2075 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2078 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2079 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2082 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2083 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2084 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2085 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2088 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2089 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2090 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2093 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2094 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2095 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2098 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2099 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2101 /* 8168DP family. */
2102 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2103 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2104 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2107 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2108 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2109 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2110 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2111 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2112 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2113 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2116 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2117 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2118 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2121 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2122 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2123 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2124 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2125 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2126 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2127 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2128 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2129 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2130 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2131 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2132 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2133 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2134 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2135 /* FIXME: where did these entries come from ? -- FR */
2136 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2137 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2140 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2141 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2142 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2143 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2144 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2145 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2148 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2150 const struct rtl_mac_info *p = mac_info;
2153 reg = RTL_R32(tp, TxConfig);
2154 while ((reg & p->mask) != p->val)
2156 tp->mac_version = p->mac_version;
2158 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2159 dev_notice(tp_to_dev(tp),
2160 "unknown MAC, using family default\n");
2161 tp->mac_version = default_version;
2162 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2163 tp->mac_version = tp->supports_gmii ?
2164 RTL_GIGA_MAC_VER_42 :
2165 RTL_GIGA_MAC_VER_43;
2166 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2167 tp->mac_version = tp->supports_gmii ?
2168 RTL_GIGA_MAC_VER_45 :
2169 RTL_GIGA_MAC_VER_47;
2170 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2171 tp->mac_version = tp->supports_gmii ?
2172 RTL_GIGA_MAC_VER_46 :
2173 RTL_GIGA_MAC_VER_48;
2177 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2179 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2187 static void rtl_writephy_batch(struct rtl8169_private *tp,
2188 const struct phy_reg *regs, int len)
2191 rtl_writephy(tp, regs->reg, regs->val);
2196 #define PHY_READ 0x00000000
2197 #define PHY_DATA_OR 0x10000000
2198 #define PHY_DATA_AND 0x20000000
2199 #define PHY_BJMPN 0x30000000
2200 #define PHY_MDIO_CHG 0x40000000
2201 #define PHY_CLEAR_READCOUNT 0x70000000
2202 #define PHY_WRITE 0x80000000
2203 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2204 #define PHY_COMP_EQ_SKIPN 0xa0000000
2205 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2206 #define PHY_WRITE_PREVIOUS 0xc0000000
2207 #define PHY_SKIPN 0xd0000000
2208 #define PHY_DELAY_MS 0xe0000000
2212 char version[RTL_VER_SIZE];
2218 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2220 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2222 const struct firmware *fw = rtl_fw->fw;
2223 struct fw_info *fw_info = (struct fw_info *)fw->data;
2224 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2225 char *version = rtl_fw->version;
2228 if (fw->size < FW_OPCODE_SIZE)
2231 if (!fw_info->magic) {
2232 size_t i, size, start;
2235 if (fw->size < sizeof(*fw_info))
2238 for (i = 0; i < fw->size; i++)
2239 checksum += fw->data[i];
2243 start = le32_to_cpu(fw_info->fw_start);
2244 if (start > fw->size)
2247 size = le32_to_cpu(fw_info->fw_len);
2248 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2251 memcpy(version, fw_info->version, RTL_VER_SIZE);
2253 pa->code = (__le32 *)(fw->data + start);
2256 if (fw->size % FW_OPCODE_SIZE)
2259 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2261 pa->code = (__le32 *)fw->data;
2262 pa->size = fw->size / FW_OPCODE_SIZE;
2264 version[RTL_VER_SIZE - 1] = 0;
2271 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2272 struct rtl_fw_phy_action *pa)
2277 for (index = 0; index < pa->size; index++) {
2278 u32 action = le32_to_cpu(pa->code[index]);
2279 u32 regno = (action & 0x0fff0000) >> 16;
2281 switch(action & 0xf0000000) {
2286 case PHY_CLEAR_READCOUNT:
2288 case PHY_WRITE_PREVIOUS:
2293 if (regno > index) {
2294 netif_err(tp, ifup, tp->dev,
2295 "Out of range of firmware\n");
2299 case PHY_READCOUNT_EQ_SKIP:
2300 if (index + 2 >= pa->size) {
2301 netif_err(tp, ifup, tp->dev,
2302 "Out of range of firmware\n");
2306 case PHY_COMP_EQ_SKIPN:
2307 case PHY_COMP_NEQ_SKIPN:
2309 if (index + 1 + regno >= pa->size) {
2310 netif_err(tp, ifup, tp->dev,
2311 "Out of range of firmware\n");
2317 netif_err(tp, ifup, tp->dev,
2318 "Invalid action 0x%08x\n", action);
2327 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2329 struct net_device *dev = tp->dev;
2332 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2333 netif_err(tp, ifup, dev, "invalid firmware\n");
2337 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2343 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2345 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2346 struct mdio_ops org, *ops = &tp->mdio_ops;
2350 predata = count = 0;
2351 org.write = ops->write;
2352 org.read = ops->read;
2354 for (index = 0; index < pa->size; ) {
2355 u32 action = le32_to_cpu(pa->code[index]);
2356 u32 data = action & 0x0000ffff;
2357 u32 regno = (action & 0x0fff0000) >> 16;
2362 switch(action & 0xf0000000) {
2364 predata = rtl_readphy(tp, regno);
2381 ops->write = org.write;
2382 ops->read = org.read;
2383 } else if (data == 1) {
2384 ops->write = mac_mcu_write;
2385 ops->read = mac_mcu_read;
2390 case PHY_CLEAR_READCOUNT:
2395 rtl_writephy(tp, regno, data);
2398 case PHY_READCOUNT_EQ_SKIP:
2399 index += (count == data) ? 2 : 1;
2401 case PHY_COMP_EQ_SKIPN:
2402 if (predata == data)
2406 case PHY_COMP_NEQ_SKIPN:
2407 if (predata != data)
2411 case PHY_WRITE_PREVIOUS:
2412 rtl_writephy(tp, regno, predata);
2428 ops->write = org.write;
2429 ops->read = org.read;
2432 static void rtl_release_firmware(struct rtl8169_private *tp)
2434 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2435 release_firmware(tp->rtl_fw->fw);
2438 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2441 static void rtl_apply_firmware(struct rtl8169_private *tp)
2443 struct rtl_fw *rtl_fw = tp->rtl_fw;
2445 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2446 if (!IS_ERR_OR_NULL(rtl_fw))
2447 rtl_phy_write_fw(tp, rtl_fw);
2450 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2452 if (rtl_readphy(tp, reg) != val)
2453 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2455 rtl_apply_firmware(tp);
2458 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2460 static const struct phy_reg phy_reg_init[] = {
2522 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2525 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2527 static const struct phy_reg phy_reg_init[] = {
2533 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2536 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2538 struct pci_dev *pdev = tp->pci_dev;
2540 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2541 (pdev->subsystem_device != 0xe000))
2544 rtl_writephy(tp, 0x1f, 0x0001);
2545 rtl_writephy(tp, 0x10, 0xf01b);
2546 rtl_writephy(tp, 0x1f, 0x0000);
2549 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2551 static const struct phy_reg phy_reg_init[] = {
2591 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593 rtl8169scd_hw_phy_config_quirk(tp);
2596 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2598 static const struct phy_reg phy_reg_init[] = {
2646 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2649 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2651 static const struct phy_reg phy_reg_init[] = {
2656 rtl_writephy(tp, 0x1f, 0x0001);
2657 rtl_patchphy(tp, 0x16, 1 << 0);
2659 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2662 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2664 static const struct phy_reg phy_reg_init[] = {
2670 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2673 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2675 static const struct phy_reg phy_reg_init[] = {
2683 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2686 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2688 static const struct phy_reg phy_reg_init[] = {
2694 rtl_writephy(tp, 0x1f, 0x0000);
2695 rtl_patchphy(tp, 0x14, 1 << 5);
2696 rtl_patchphy(tp, 0x0d, 1 << 5);
2698 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2701 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2703 static const struct phy_reg phy_reg_init[] = {
2723 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2725 rtl_patchphy(tp, 0x14, 1 << 5);
2726 rtl_patchphy(tp, 0x0d, 1 << 5);
2727 rtl_writephy(tp, 0x1f, 0x0000);
2730 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2732 static const struct phy_reg phy_reg_init[] = {
2750 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2752 rtl_patchphy(tp, 0x16, 1 << 0);
2753 rtl_patchphy(tp, 0x14, 1 << 5);
2754 rtl_patchphy(tp, 0x0d, 1 << 5);
2755 rtl_writephy(tp, 0x1f, 0x0000);
2758 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2760 static const struct phy_reg phy_reg_init[] = {
2772 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2774 rtl_patchphy(tp, 0x16, 1 << 0);
2775 rtl_patchphy(tp, 0x14, 1 << 5);
2776 rtl_patchphy(tp, 0x0d, 1 << 5);
2777 rtl_writephy(tp, 0x1f, 0x0000);
2780 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2782 rtl8168c_3_hw_phy_config(tp);
2785 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2787 static const struct phy_reg phy_reg_init_0[] = {
2788 /* Channel Estimation */
2809 * Enhance line driver power
2818 * Can not link to 1Gbps with bad cable
2819 * Decrease SNR threshold form 21.07dB to 19.04dB
2828 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2832 * Fine Tune Switching regulator parameter
2834 rtl_writephy(tp, 0x1f, 0x0002);
2835 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2836 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2838 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2839 static const struct phy_reg phy_reg_init[] = {
2849 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851 val = rtl_readphy(tp, 0x0d);
2853 if ((val & 0x00ff) != 0x006c) {
2854 static const u32 set[] = {
2855 0x0065, 0x0066, 0x0067, 0x0068,
2856 0x0069, 0x006a, 0x006b, 0x006c
2860 rtl_writephy(tp, 0x1f, 0x0002);
2863 for (i = 0; i < ARRAY_SIZE(set); i++)
2864 rtl_writephy(tp, 0x0d, val | set[i]);
2867 static const struct phy_reg phy_reg_init[] = {
2875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2878 /* RSET couple improve */
2879 rtl_writephy(tp, 0x1f, 0x0002);
2880 rtl_patchphy(tp, 0x0d, 0x0300);
2881 rtl_patchphy(tp, 0x0f, 0x0010);
2883 /* Fine tune PLL performance */
2884 rtl_writephy(tp, 0x1f, 0x0002);
2885 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2886 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2888 rtl_writephy(tp, 0x1f, 0x0005);
2889 rtl_writephy(tp, 0x05, 0x001b);
2891 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2893 rtl_writephy(tp, 0x1f, 0x0000);
2896 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2898 static const struct phy_reg phy_reg_init_0[] = {
2899 /* Channel Estimation */
2920 * Enhance line driver power
2929 * Can not link to 1Gbps with bad cable
2930 * Decrease SNR threshold form 21.07dB to 19.04dB
2939 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2941 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2942 static const struct phy_reg phy_reg_init[] = {
2953 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2955 val = rtl_readphy(tp, 0x0d);
2956 if ((val & 0x00ff) != 0x006c) {
2957 static const u32 set[] = {
2958 0x0065, 0x0066, 0x0067, 0x0068,
2959 0x0069, 0x006a, 0x006b, 0x006c
2963 rtl_writephy(tp, 0x1f, 0x0002);
2966 for (i = 0; i < ARRAY_SIZE(set); i++)
2967 rtl_writephy(tp, 0x0d, val | set[i]);
2970 static const struct phy_reg phy_reg_init[] = {
2978 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2981 /* Fine tune PLL performance */
2982 rtl_writephy(tp, 0x1f, 0x0002);
2983 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2984 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2986 /* Switching regulator Slew rate */
2987 rtl_writephy(tp, 0x1f, 0x0002);
2988 rtl_patchphy(tp, 0x0f, 0x0017);
2990 rtl_writephy(tp, 0x1f, 0x0005);
2991 rtl_writephy(tp, 0x05, 0x001b);
2993 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2995 rtl_writephy(tp, 0x1f, 0x0000);
2998 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3000 static const struct phy_reg phy_reg_init[] = {
3056 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3059 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3061 static const struct phy_reg phy_reg_init[] = {
3071 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3072 rtl_patchphy(tp, 0x0d, 1 << 5);
3075 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3077 static const struct phy_reg phy_reg_init[] = {
3078 /* Enable Delay cap */
3084 /* Channel estimation fine tune */
3093 /* Update PFM & 10M TX idle timer */
3105 rtl_apply_firmware(tp);
3107 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109 /* DCO enable for 10M IDLE Power */
3110 rtl_writephy(tp, 0x1f, 0x0007);
3111 rtl_writephy(tp, 0x1e, 0x0023);
3112 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3113 rtl_writephy(tp, 0x1f, 0x0000);
3115 /* For impedance matching */
3116 rtl_writephy(tp, 0x1f, 0x0002);
3117 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3118 rtl_writephy(tp, 0x1f, 0x0000);
3120 /* PHY auto speed down */
3121 rtl_writephy(tp, 0x1f, 0x0007);
3122 rtl_writephy(tp, 0x1e, 0x002d);
3123 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3124 rtl_writephy(tp, 0x1f, 0x0000);
3125 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3127 rtl_writephy(tp, 0x1f, 0x0005);
3128 rtl_writephy(tp, 0x05, 0x8b86);
3129 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3130 rtl_writephy(tp, 0x1f, 0x0000);
3132 rtl_writephy(tp, 0x1f, 0x0005);
3133 rtl_writephy(tp, 0x05, 0x8b85);
3134 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3135 rtl_writephy(tp, 0x1f, 0x0007);
3136 rtl_writephy(tp, 0x1e, 0x0020);
3137 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3138 rtl_writephy(tp, 0x1f, 0x0006);
3139 rtl_writephy(tp, 0x00, 0x5a00);
3140 rtl_writephy(tp, 0x1f, 0x0000);
3141 rtl_writephy(tp, 0x0d, 0x0007);
3142 rtl_writephy(tp, 0x0e, 0x003c);
3143 rtl_writephy(tp, 0x0d, 0x4007);
3144 rtl_writephy(tp, 0x0e, 0x0000);
3145 rtl_writephy(tp, 0x0d, 0x0000);
3148 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3151 addr[0] | (addr[1] << 8),
3152 addr[2] | (addr[3] << 8),
3153 addr[4] | (addr[5] << 8)
3155 const struct exgmac_reg e[] = {
3156 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3157 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3158 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3159 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3162 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3165 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3167 static const struct phy_reg phy_reg_init[] = {
3168 /* Enable Delay cap */
3177 /* Channel estimation fine tune */
3194 rtl_apply_firmware(tp);
3196 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3198 /* For 4-corner performance improve */
3199 rtl_writephy(tp, 0x1f, 0x0005);
3200 rtl_writephy(tp, 0x05, 0x8b80);
3201 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3202 rtl_writephy(tp, 0x1f, 0x0000);
3204 /* PHY auto speed down */
3205 rtl_writephy(tp, 0x1f, 0x0004);
3206 rtl_writephy(tp, 0x1f, 0x0007);
3207 rtl_writephy(tp, 0x1e, 0x002d);
3208 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3209 rtl_writephy(tp, 0x1f, 0x0002);
3210 rtl_writephy(tp, 0x1f, 0x0000);
3211 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3213 /* improve 10M EEE waveform */
3214 rtl_writephy(tp, 0x1f, 0x0005);
3215 rtl_writephy(tp, 0x05, 0x8b86);
3216 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3217 rtl_writephy(tp, 0x1f, 0x0000);
3219 /* Improve 2-pair detection performance */
3220 rtl_writephy(tp, 0x1f, 0x0005);
3221 rtl_writephy(tp, 0x05, 0x8b85);
3222 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3223 rtl_writephy(tp, 0x1f, 0x0000);
3226 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3227 rtl_writephy(tp, 0x1f, 0x0005);
3228 rtl_writephy(tp, 0x05, 0x8b85);
3229 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3230 rtl_writephy(tp, 0x1f, 0x0004);
3231 rtl_writephy(tp, 0x1f, 0x0007);
3232 rtl_writephy(tp, 0x1e, 0x0020);
3233 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3234 rtl_writephy(tp, 0x1f, 0x0002);
3235 rtl_writephy(tp, 0x1f, 0x0000);
3236 rtl_writephy(tp, 0x0d, 0x0007);
3237 rtl_writephy(tp, 0x0e, 0x003c);
3238 rtl_writephy(tp, 0x0d, 0x4007);
3239 rtl_writephy(tp, 0x0e, 0x0006);
3240 rtl_writephy(tp, 0x0d, 0x0000);
3243 rtl_writephy(tp, 0x1f, 0x0003);
3244 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3245 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3246 rtl_writephy(tp, 0x1f, 0x0000);
3247 rtl_writephy(tp, 0x1f, 0x0005);
3248 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3249 rtl_writephy(tp, 0x1f, 0x0000);
3251 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3252 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3255 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3257 /* For 4-corner performance improve */
3258 rtl_writephy(tp, 0x1f, 0x0005);
3259 rtl_writephy(tp, 0x05, 0x8b80);
3260 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3261 rtl_writephy(tp, 0x1f, 0x0000);
3263 /* PHY auto speed down */
3264 rtl_writephy(tp, 0x1f, 0x0007);
3265 rtl_writephy(tp, 0x1e, 0x002d);
3266 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3267 rtl_writephy(tp, 0x1f, 0x0000);
3268 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3270 /* Improve 10M EEE waveform */
3271 rtl_writephy(tp, 0x1f, 0x0005);
3272 rtl_writephy(tp, 0x05, 0x8b86);
3273 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3274 rtl_writephy(tp, 0x1f, 0x0000);
3277 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3279 static const struct phy_reg phy_reg_init[] = {
3280 /* Channel estimation fine tune */
3285 /* Modify green table for giga & fnet */
3302 /* Modify green table for 10M */
3308 /* Disable hiimpedance detection (RTCT) */
3314 rtl_apply_firmware(tp);
3316 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3318 rtl8168f_hw_phy_config(tp);
3320 /* Improve 2-pair detection performance */
3321 rtl_writephy(tp, 0x1f, 0x0005);
3322 rtl_writephy(tp, 0x05, 0x8b85);
3323 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3324 rtl_writephy(tp, 0x1f, 0x0000);
3327 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3329 rtl_apply_firmware(tp);
3331 rtl8168f_hw_phy_config(tp);
3334 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3336 static const struct phy_reg phy_reg_init[] = {
3337 /* Channel estimation fine tune */
3342 /* Modify green table for giga & fnet */
3359 /* Modify green table for 10M */
3365 /* Disable hiimpedance detection (RTCT) */
3372 rtl_apply_firmware(tp);
3374 rtl8168f_hw_phy_config(tp);
3376 /* Improve 2-pair detection performance */
3377 rtl_writephy(tp, 0x1f, 0x0005);
3378 rtl_writephy(tp, 0x05, 0x8b85);
3379 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3380 rtl_writephy(tp, 0x1f, 0x0000);
3382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3384 /* Modify green table for giga */
3385 rtl_writephy(tp, 0x1f, 0x0005);
3386 rtl_writephy(tp, 0x05, 0x8b54);
3387 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3388 rtl_writephy(tp, 0x05, 0x8b5d);
3389 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3390 rtl_writephy(tp, 0x05, 0x8a7c);
3391 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3392 rtl_writephy(tp, 0x05, 0x8a7f);
3393 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3394 rtl_writephy(tp, 0x05, 0x8a82);
3395 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3396 rtl_writephy(tp, 0x05, 0x8a85);
3397 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3398 rtl_writephy(tp, 0x05, 0x8a88);
3399 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3400 rtl_writephy(tp, 0x1f, 0x0000);
3402 /* uc same-seed solution */
3403 rtl_writephy(tp, 0x1f, 0x0005);
3404 rtl_writephy(tp, 0x05, 0x8b85);
3405 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3406 rtl_writephy(tp, 0x1f, 0x0000);
3409 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3410 rtl_writephy(tp, 0x1f, 0x0005);
3411 rtl_writephy(tp, 0x05, 0x8b85);
3412 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3413 rtl_writephy(tp, 0x1f, 0x0004);
3414 rtl_writephy(tp, 0x1f, 0x0007);
3415 rtl_writephy(tp, 0x1e, 0x0020);
3416 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3417 rtl_writephy(tp, 0x1f, 0x0000);
3418 rtl_writephy(tp, 0x0d, 0x0007);
3419 rtl_writephy(tp, 0x0e, 0x003c);
3420 rtl_writephy(tp, 0x0d, 0x4007);
3421 rtl_writephy(tp, 0x0e, 0x0000);
3422 rtl_writephy(tp, 0x0d, 0x0000);
3425 rtl_writephy(tp, 0x1f, 0x0003);
3426 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3427 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3428 rtl_writephy(tp, 0x1f, 0x0000);
3431 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3433 rtl_apply_firmware(tp);
3435 rtl_writephy(tp, 0x1f, 0x0a46);
3436 if (rtl_readphy(tp, 0x10) & 0x0100) {
3437 rtl_writephy(tp, 0x1f, 0x0bcc);
3438 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3440 rtl_writephy(tp, 0x1f, 0x0bcc);
3441 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3444 rtl_writephy(tp, 0x1f, 0x0a46);
3445 if (rtl_readphy(tp, 0x13) & 0x0100) {
3446 rtl_writephy(tp, 0x1f, 0x0c41);
3447 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3449 rtl_writephy(tp, 0x1f, 0x0c41);
3450 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3453 /* Enable PHY auto speed down */
3454 rtl_writephy(tp, 0x1f, 0x0a44);
3455 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3457 rtl_writephy(tp, 0x1f, 0x0bcc);
3458 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3459 rtl_writephy(tp, 0x1f, 0x0a44);
3460 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3461 rtl_writephy(tp, 0x1f, 0x0a43);
3462 rtl_writephy(tp, 0x13, 0x8084);
3463 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3464 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3466 /* EEE auto-fallback function */
3467 rtl_writephy(tp, 0x1f, 0x0a4b);
3468 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3470 /* Enable UC LPF tune function */
3471 rtl_writephy(tp, 0x1f, 0x0a43);
3472 rtl_writephy(tp, 0x13, 0x8012);
3473 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3475 rtl_writephy(tp, 0x1f, 0x0c42);
3476 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3478 /* Improve SWR Efficiency */
3479 rtl_writephy(tp, 0x1f, 0x0bcd);
3480 rtl_writephy(tp, 0x14, 0x5065);
3481 rtl_writephy(tp, 0x14, 0xd065);
3482 rtl_writephy(tp, 0x1f, 0x0bc8);
3483 rtl_writephy(tp, 0x11, 0x5655);
3484 rtl_writephy(tp, 0x1f, 0x0bcd);
3485 rtl_writephy(tp, 0x14, 0x1065);
3486 rtl_writephy(tp, 0x14, 0x9065);
3487 rtl_writephy(tp, 0x14, 0x1065);
3489 /* Check ALDPS bit, disable it if enabled */
3490 rtl_writephy(tp, 0x1f, 0x0a43);
3491 if (rtl_readphy(tp, 0x10) & 0x0004)
3492 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3494 rtl_writephy(tp, 0x1f, 0x0000);
3497 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3499 rtl_apply_firmware(tp);
3502 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3507 rtl_apply_firmware(tp);
3509 /* CHN EST parameters adjust - giga master */
3510 rtl_writephy(tp, 0x1f, 0x0a43);
3511 rtl_writephy(tp, 0x13, 0x809b);
3512 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3513 rtl_writephy(tp, 0x13, 0x80a2);
3514 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3515 rtl_writephy(tp, 0x13, 0x80a4);
3516 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3517 rtl_writephy(tp, 0x13, 0x809c);
3518 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3519 rtl_writephy(tp, 0x1f, 0x0000);
3521 /* CHN EST parameters adjust - giga slave */
3522 rtl_writephy(tp, 0x1f, 0x0a43);
3523 rtl_writephy(tp, 0x13, 0x80ad);
3524 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3525 rtl_writephy(tp, 0x13, 0x80b4);
3526 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3527 rtl_writephy(tp, 0x13, 0x80ac);
3528 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3529 rtl_writephy(tp, 0x1f, 0x0000);
3531 /* CHN EST parameters adjust - fnet */
3532 rtl_writephy(tp, 0x1f, 0x0a43);
3533 rtl_writephy(tp, 0x13, 0x808e);
3534 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3535 rtl_writephy(tp, 0x13, 0x8090);
3536 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3537 rtl_writephy(tp, 0x13, 0x8092);
3538 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3539 rtl_writephy(tp, 0x1f, 0x0000);
3541 /* enable R-tune & PGA-retune function */
3543 rtl_writephy(tp, 0x1f, 0x0a46);
3544 data = rtl_readphy(tp, 0x13);
3547 dout_tapbin |= data;
3548 data = rtl_readphy(tp, 0x12);
3551 dout_tapbin |= data;
3552 dout_tapbin = ~(dout_tapbin^0x08);
3554 dout_tapbin &= 0xf000;
3555 rtl_writephy(tp, 0x1f, 0x0a43);
3556 rtl_writephy(tp, 0x13, 0x827a);
3557 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3558 rtl_writephy(tp, 0x13, 0x827b);
3559 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3560 rtl_writephy(tp, 0x13, 0x827c);
3561 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3562 rtl_writephy(tp, 0x13, 0x827d);
3563 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3565 rtl_writephy(tp, 0x1f, 0x0a43);
3566 rtl_writephy(tp, 0x13, 0x0811);
3567 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3568 rtl_writephy(tp, 0x1f, 0x0a42);
3569 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3570 rtl_writephy(tp, 0x1f, 0x0000);
3572 /* enable GPHY 10M */
3573 rtl_writephy(tp, 0x1f, 0x0a44);
3574 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3575 rtl_writephy(tp, 0x1f, 0x0000);
3577 /* SAR ADC performance */
3578 rtl_writephy(tp, 0x1f, 0x0bca);
3579 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3580 rtl_writephy(tp, 0x1f, 0x0000);
3582 rtl_writephy(tp, 0x1f, 0x0a43);
3583 rtl_writephy(tp, 0x13, 0x803f);
3584 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3585 rtl_writephy(tp, 0x13, 0x8047);
3586 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3587 rtl_writephy(tp, 0x13, 0x804f);
3588 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3589 rtl_writephy(tp, 0x13, 0x8057);
3590 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3591 rtl_writephy(tp, 0x13, 0x805f);
3592 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3593 rtl_writephy(tp, 0x13, 0x8067);
3594 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3595 rtl_writephy(tp, 0x13, 0x806f);
3596 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3597 rtl_writephy(tp, 0x1f, 0x0000);
3599 /* disable phy pfm mode */
3600 rtl_writephy(tp, 0x1f, 0x0a44);
3601 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3602 rtl_writephy(tp, 0x1f, 0x0000);
3604 /* Check ALDPS bit, disable it if enabled */
3605 rtl_writephy(tp, 0x1f, 0x0a43);
3606 if (rtl_readphy(tp, 0x10) & 0x0004)
3607 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3609 rtl_writephy(tp, 0x1f, 0x0000);
3612 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3614 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3618 rtl_apply_firmware(tp);
3620 /* CHIN EST parameter update */
3621 rtl_writephy(tp, 0x1f, 0x0a43);
3622 rtl_writephy(tp, 0x13, 0x808a);
3623 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3624 rtl_writephy(tp, 0x1f, 0x0000);
3626 /* enable R-tune & PGA-retune function */
3627 rtl_writephy(tp, 0x1f, 0x0a43);
3628 rtl_writephy(tp, 0x13, 0x0811);
3629 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3630 rtl_writephy(tp, 0x1f, 0x0a42);
3631 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3632 rtl_writephy(tp, 0x1f, 0x0000);
3634 /* enable GPHY 10M */
3635 rtl_writephy(tp, 0x1f, 0x0a44);
3636 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3637 rtl_writephy(tp, 0x1f, 0x0000);
3639 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3640 data = r8168_mac_ocp_read(tp, 0xdd02);
3641 ioffset_p3 = ((data & 0x80)>>7);
3644 data = r8168_mac_ocp_read(tp, 0xdd00);
3645 ioffset_p3 |= ((data & (0xe000))>>13);
3646 ioffset_p2 = ((data & (0x1e00))>>9);
3647 ioffset_p1 = ((data & (0x01e0))>>5);
3648 ioffset_p0 = ((data & 0x0010)>>4);
3650 ioffset_p0 |= (data & (0x07));
3651 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3653 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3654 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3655 rtl_writephy(tp, 0x1f, 0x0bcf);
3656 rtl_writephy(tp, 0x16, data);
3657 rtl_writephy(tp, 0x1f, 0x0000);
3660 /* Modify rlen (TX LPF corner frequency) level */
3661 rtl_writephy(tp, 0x1f, 0x0bcd);
3662 data = rtl_readphy(tp, 0x16);
3667 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3668 rtl_writephy(tp, 0x17, data);
3669 rtl_writephy(tp, 0x1f, 0x0bcd);
3670 rtl_writephy(tp, 0x1f, 0x0000);
3672 /* disable phy pfm mode */
3673 rtl_writephy(tp, 0x1f, 0x0a44);
3674 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3675 rtl_writephy(tp, 0x1f, 0x0000);
3677 /* Check ALDPS bit, disable it if enabled */
3678 rtl_writephy(tp, 0x1f, 0x0a43);
3679 if (rtl_readphy(tp, 0x10) & 0x0004)
3680 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3682 rtl_writephy(tp, 0x1f, 0x0000);
3685 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3687 /* Enable PHY auto speed down */
3688 rtl_writephy(tp, 0x1f, 0x0a44);
3689 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3690 rtl_writephy(tp, 0x1f, 0x0000);
3692 /* patch 10M & ALDPS */
3693 rtl_writephy(tp, 0x1f, 0x0bcc);
3694 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3695 rtl_writephy(tp, 0x1f, 0x0a44);
3696 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3697 rtl_writephy(tp, 0x1f, 0x0a43);
3698 rtl_writephy(tp, 0x13, 0x8084);
3699 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3700 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3701 rtl_writephy(tp, 0x1f, 0x0000);
3703 /* Enable EEE auto-fallback function */
3704 rtl_writephy(tp, 0x1f, 0x0a4b);
3705 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3706 rtl_writephy(tp, 0x1f, 0x0000);
3708 /* Enable UC LPF tune function */
3709 rtl_writephy(tp, 0x1f, 0x0a43);
3710 rtl_writephy(tp, 0x13, 0x8012);
3711 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3712 rtl_writephy(tp, 0x1f, 0x0000);
3714 /* set rg_sel_sdm_rate */
3715 rtl_writephy(tp, 0x1f, 0x0c42);
3716 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3717 rtl_writephy(tp, 0x1f, 0x0000);
3719 /* Check ALDPS bit, disable it if enabled */
3720 rtl_writephy(tp, 0x1f, 0x0a43);
3721 if (rtl_readphy(tp, 0x10) & 0x0004)
3722 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3724 rtl_writephy(tp, 0x1f, 0x0000);
3727 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3729 /* patch 10M & ALDPS */
3730 rtl_writephy(tp, 0x1f, 0x0bcc);
3731 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3732 rtl_writephy(tp, 0x1f, 0x0a44);
3733 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3734 rtl_writephy(tp, 0x1f, 0x0a43);
3735 rtl_writephy(tp, 0x13, 0x8084);
3736 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3737 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3738 rtl_writephy(tp, 0x1f, 0x0000);
3740 /* Enable UC LPF tune function */
3741 rtl_writephy(tp, 0x1f, 0x0a43);
3742 rtl_writephy(tp, 0x13, 0x8012);
3743 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3744 rtl_writephy(tp, 0x1f, 0x0000);
3746 /* Set rg_sel_sdm_rate */
3747 rtl_writephy(tp, 0x1f, 0x0c42);
3748 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3749 rtl_writephy(tp, 0x1f, 0x0000);
3751 /* Channel estimation parameters */
3752 rtl_writephy(tp, 0x1f, 0x0a43);
3753 rtl_writephy(tp, 0x13, 0x80f3);
3754 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3755 rtl_writephy(tp, 0x13, 0x80f0);
3756 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3757 rtl_writephy(tp, 0x13, 0x80ef);
3758 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3759 rtl_writephy(tp, 0x13, 0x80f6);
3760 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3761 rtl_writephy(tp, 0x13, 0x80ec);
3762 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3763 rtl_writephy(tp, 0x13, 0x80ed);
3764 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3765 rtl_writephy(tp, 0x13, 0x80f2);
3766 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3767 rtl_writephy(tp, 0x13, 0x80f4);
3768 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3769 rtl_writephy(tp, 0x1f, 0x0a43);
3770 rtl_writephy(tp, 0x13, 0x8110);
3771 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3772 rtl_writephy(tp, 0x13, 0x810f);
3773 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3774 rtl_writephy(tp, 0x13, 0x8111);
3775 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3776 rtl_writephy(tp, 0x13, 0x8113);
3777 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3778 rtl_writephy(tp, 0x13, 0x8115);
3779 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3780 rtl_writephy(tp, 0x13, 0x810e);
3781 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3782 rtl_writephy(tp, 0x13, 0x810c);
3783 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3784 rtl_writephy(tp, 0x13, 0x810b);
3785 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3786 rtl_writephy(tp, 0x1f, 0x0a43);
3787 rtl_writephy(tp, 0x13, 0x80d1);
3788 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3789 rtl_writephy(tp, 0x13, 0x80cd);
3790 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3791 rtl_writephy(tp, 0x13, 0x80d3);
3792 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3793 rtl_writephy(tp, 0x13, 0x80d5);
3794 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3795 rtl_writephy(tp, 0x13, 0x80d7);
3796 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3798 /* Force PWM-mode */
3799 rtl_writephy(tp, 0x1f, 0x0bcd);
3800 rtl_writephy(tp, 0x14, 0x5065);
3801 rtl_writephy(tp, 0x14, 0xd065);
3802 rtl_writephy(tp, 0x1f, 0x0bc8);
3803 rtl_writephy(tp, 0x12, 0x00ed);
3804 rtl_writephy(tp, 0x1f, 0x0bcd);
3805 rtl_writephy(tp, 0x14, 0x1065);
3806 rtl_writephy(tp, 0x14, 0x9065);
3807 rtl_writephy(tp, 0x14, 0x1065);
3808 rtl_writephy(tp, 0x1f, 0x0000);
3810 /* Check ALDPS bit, disable it if enabled */
3811 rtl_writephy(tp, 0x1f, 0x0a43);
3812 if (rtl_readphy(tp, 0x10) & 0x0004)
3813 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3815 rtl_writephy(tp, 0x1f, 0x0000);
3818 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3820 static const struct phy_reg phy_reg_init[] = {
3827 rtl_writephy(tp, 0x1f, 0x0000);
3828 rtl_patchphy(tp, 0x11, 1 << 12);
3829 rtl_patchphy(tp, 0x19, 1 << 13);
3830 rtl_patchphy(tp, 0x10, 1 << 15);
3832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3835 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3837 static const struct phy_reg phy_reg_init[] = {
3851 /* Disable ALDPS before ram code */
3852 rtl_writephy(tp, 0x1f, 0x0000);
3853 rtl_writephy(tp, 0x18, 0x0310);
3856 rtl_apply_firmware(tp);
3858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3861 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3863 /* Disable ALDPS before setting firmware */
3864 rtl_writephy(tp, 0x1f, 0x0000);
3865 rtl_writephy(tp, 0x18, 0x0310);
3868 rtl_apply_firmware(tp);
3871 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3872 rtl_writephy(tp, 0x1f, 0x0004);
3873 rtl_writephy(tp, 0x10, 0x401f);
3874 rtl_writephy(tp, 0x19, 0x7030);
3875 rtl_writephy(tp, 0x1f, 0x0000);
3878 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3880 static const struct phy_reg phy_reg_init[] = {
3887 /* Disable ALDPS before ram code */
3888 rtl_writephy(tp, 0x1f, 0x0000);
3889 rtl_writephy(tp, 0x18, 0x0310);
3892 rtl_apply_firmware(tp);
3894 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3895 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3897 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3900 static void rtl_hw_phy_config(struct net_device *dev)
3902 struct rtl8169_private *tp = netdev_priv(dev);
3904 rtl8169_print_mac_version(tp);
3906 switch (tp->mac_version) {
3907 case RTL_GIGA_MAC_VER_01:
3909 case RTL_GIGA_MAC_VER_02:
3910 case RTL_GIGA_MAC_VER_03:
3911 rtl8169s_hw_phy_config(tp);
3913 case RTL_GIGA_MAC_VER_04:
3914 rtl8169sb_hw_phy_config(tp);
3916 case RTL_GIGA_MAC_VER_05:
3917 rtl8169scd_hw_phy_config(tp);
3919 case RTL_GIGA_MAC_VER_06:
3920 rtl8169sce_hw_phy_config(tp);
3922 case RTL_GIGA_MAC_VER_07:
3923 case RTL_GIGA_MAC_VER_08:
3924 case RTL_GIGA_MAC_VER_09:
3925 rtl8102e_hw_phy_config(tp);
3927 case RTL_GIGA_MAC_VER_11:
3928 rtl8168bb_hw_phy_config(tp);
3930 case RTL_GIGA_MAC_VER_12:
3931 rtl8168bef_hw_phy_config(tp);
3933 case RTL_GIGA_MAC_VER_17:
3934 rtl8168bef_hw_phy_config(tp);
3936 case RTL_GIGA_MAC_VER_18:
3937 rtl8168cp_1_hw_phy_config(tp);
3939 case RTL_GIGA_MAC_VER_19:
3940 rtl8168c_1_hw_phy_config(tp);
3942 case RTL_GIGA_MAC_VER_20:
3943 rtl8168c_2_hw_phy_config(tp);
3945 case RTL_GIGA_MAC_VER_21:
3946 rtl8168c_3_hw_phy_config(tp);
3948 case RTL_GIGA_MAC_VER_22:
3949 rtl8168c_4_hw_phy_config(tp);
3951 case RTL_GIGA_MAC_VER_23:
3952 case RTL_GIGA_MAC_VER_24:
3953 rtl8168cp_2_hw_phy_config(tp);
3955 case RTL_GIGA_MAC_VER_25:
3956 rtl8168d_1_hw_phy_config(tp);
3958 case RTL_GIGA_MAC_VER_26:
3959 rtl8168d_2_hw_phy_config(tp);
3961 case RTL_GIGA_MAC_VER_27:
3962 rtl8168d_3_hw_phy_config(tp);
3964 case RTL_GIGA_MAC_VER_28:
3965 rtl8168d_4_hw_phy_config(tp);
3967 case RTL_GIGA_MAC_VER_29:
3968 case RTL_GIGA_MAC_VER_30:
3969 rtl8105e_hw_phy_config(tp);
3971 case RTL_GIGA_MAC_VER_31:
3974 case RTL_GIGA_MAC_VER_32:
3975 case RTL_GIGA_MAC_VER_33:
3976 rtl8168e_1_hw_phy_config(tp);
3978 case RTL_GIGA_MAC_VER_34:
3979 rtl8168e_2_hw_phy_config(tp);
3981 case RTL_GIGA_MAC_VER_35:
3982 rtl8168f_1_hw_phy_config(tp);
3984 case RTL_GIGA_MAC_VER_36:
3985 rtl8168f_2_hw_phy_config(tp);
3988 case RTL_GIGA_MAC_VER_37:
3989 rtl8402_hw_phy_config(tp);
3992 case RTL_GIGA_MAC_VER_38:
3993 rtl8411_hw_phy_config(tp);
3996 case RTL_GIGA_MAC_VER_39:
3997 rtl8106e_hw_phy_config(tp);
4000 case RTL_GIGA_MAC_VER_40:
4001 rtl8168g_1_hw_phy_config(tp);
4003 case RTL_GIGA_MAC_VER_42:
4004 case RTL_GIGA_MAC_VER_43:
4005 case RTL_GIGA_MAC_VER_44:
4006 rtl8168g_2_hw_phy_config(tp);
4008 case RTL_GIGA_MAC_VER_45:
4009 case RTL_GIGA_MAC_VER_47:
4010 rtl8168h_1_hw_phy_config(tp);
4012 case RTL_GIGA_MAC_VER_46:
4013 case RTL_GIGA_MAC_VER_48:
4014 rtl8168h_2_hw_phy_config(tp);
4017 case RTL_GIGA_MAC_VER_49:
4018 rtl8168ep_1_hw_phy_config(tp);
4020 case RTL_GIGA_MAC_VER_50:
4021 case RTL_GIGA_MAC_VER_51:
4022 rtl8168ep_2_hw_phy_config(tp);
4025 case RTL_GIGA_MAC_VER_41:
4031 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4033 if (!test_and_set_bit(flag, tp->wk.flags))
4034 schedule_work(&tp->wk.work);
4037 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4039 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4040 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4043 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4045 rtl_hw_phy_config(dev);
4047 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4048 netif_dbg(tp, drv, dev,
4049 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4050 RTL_W8(tp, 0x82, 0x01);
4053 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4055 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4056 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4058 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4059 netif_dbg(tp, drv, dev,
4060 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4061 RTL_W8(tp, 0x82, 0x01);
4062 netif_dbg(tp, drv, dev,
4063 "Set PHY Reg 0x0bh = 0x00h\n");
4064 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4067 /* We may have called phy_speed_down before */
4068 phy_speed_up(dev->phydev);
4070 genphy_soft_reset(dev->phydev);
4073 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4077 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4079 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4082 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4085 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4086 rtl_rar_exgmac_set(tp, addr);
4088 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4090 rtl_unlock_work(tp);
4093 static int rtl_set_mac_address(struct net_device *dev, void *p)
4095 struct rtl8169_private *tp = netdev_priv(dev);
4096 struct device *d = tp_to_dev(tp);
4099 ret = eth_mac_addr(dev, p);
4103 pm_runtime_get_noresume(d);
4105 if (pm_runtime_active(d))
4106 rtl_rar_set(tp, dev->dev_addr);
4108 pm_runtime_put_noidle(d);
4113 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4115 if (!netif_running(dev))
4118 return phy_mii_ioctl(dev->phydev, ifr, cmd);
4121 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4123 struct mdio_ops *ops = &tp->mdio_ops;
4125 switch (tp->mac_version) {
4126 case RTL_GIGA_MAC_VER_27:
4127 ops->write = r8168dp_1_mdio_write;
4128 ops->read = r8168dp_1_mdio_read;
4130 case RTL_GIGA_MAC_VER_28:
4131 case RTL_GIGA_MAC_VER_31:
4132 ops->write = r8168dp_2_mdio_write;
4133 ops->read = r8168dp_2_mdio_read;
4135 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4136 ops->write = r8168g_mdio_write;
4137 ops->read = r8168g_mdio_read;
4140 ops->write = r8169_mdio_write;
4141 ops->read = r8169_mdio_read;
4146 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4148 switch (tp->mac_version) {
4149 case RTL_GIGA_MAC_VER_25:
4150 case RTL_GIGA_MAC_VER_26:
4151 case RTL_GIGA_MAC_VER_29:
4152 case RTL_GIGA_MAC_VER_30:
4153 case RTL_GIGA_MAC_VER_32:
4154 case RTL_GIGA_MAC_VER_33:
4155 case RTL_GIGA_MAC_VER_34:
4156 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4157 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4158 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4165 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4167 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4170 phy_speed_down(tp->dev->phydev, false);
4171 rtl_wol_suspend_quirk(tp);
4176 static void r8168_pll_power_down(struct rtl8169_private *tp)
4178 if (r8168_check_dash(tp))
4181 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4182 tp->mac_version == RTL_GIGA_MAC_VER_33)
4183 rtl_ephy_write(tp, 0x19, 0xff64);
4185 if (rtl_wol_pll_power_down(tp))
4188 switch (tp->mac_version) {
4189 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4190 case RTL_GIGA_MAC_VER_37:
4191 case RTL_GIGA_MAC_VER_39:
4192 case RTL_GIGA_MAC_VER_43:
4193 case RTL_GIGA_MAC_VER_44:
4194 case RTL_GIGA_MAC_VER_45:
4195 case RTL_GIGA_MAC_VER_46:
4196 case RTL_GIGA_MAC_VER_47:
4197 case RTL_GIGA_MAC_VER_48:
4198 case RTL_GIGA_MAC_VER_50:
4199 case RTL_GIGA_MAC_VER_51:
4200 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4202 case RTL_GIGA_MAC_VER_40:
4203 case RTL_GIGA_MAC_VER_41:
4204 case RTL_GIGA_MAC_VER_49:
4205 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4206 0xfc000000, ERIAR_EXGMAC);
4207 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4212 static void r8168_pll_power_up(struct rtl8169_private *tp)
4214 switch (tp->mac_version) {
4215 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4216 case RTL_GIGA_MAC_VER_37:
4217 case RTL_GIGA_MAC_VER_39:
4218 case RTL_GIGA_MAC_VER_43:
4219 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4221 case RTL_GIGA_MAC_VER_44:
4222 case RTL_GIGA_MAC_VER_45:
4223 case RTL_GIGA_MAC_VER_46:
4224 case RTL_GIGA_MAC_VER_47:
4225 case RTL_GIGA_MAC_VER_48:
4226 case RTL_GIGA_MAC_VER_50:
4227 case RTL_GIGA_MAC_VER_51:
4228 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4230 case RTL_GIGA_MAC_VER_40:
4231 case RTL_GIGA_MAC_VER_41:
4232 case RTL_GIGA_MAC_VER_49:
4233 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4234 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4235 0x00000000, ERIAR_EXGMAC);
4239 phy_resume(tp->dev->phydev);
4240 /* give MAC/PHY some time to resume */
4244 static void rtl_pll_power_down(struct rtl8169_private *tp)
4246 switch (tp->mac_version) {
4247 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4248 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4251 r8168_pll_power_down(tp);
4255 static void rtl_pll_power_up(struct rtl8169_private *tp)
4257 switch (tp->mac_version) {
4258 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4259 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4262 r8168_pll_power_up(tp);
4266 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4268 switch (tp->mac_version) {
4269 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4270 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4271 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4273 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4274 case RTL_GIGA_MAC_VER_34:
4275 case RTL_GIGA_MAC_VER_35:
4276 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4278 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4279 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4282 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4287 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4289 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4292 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4294 if (tp->jumbo_ops.enable) {
4295 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4296 tp->jumbo_ops.enable(tp);
4297 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4301 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4303 if (tp->jumbo_ops.disable) {
4304 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4305 tp->jumbo_ops.disable(tp);
4306 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4310 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4312 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4313 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4314 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4317 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4319 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4320 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4321 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4324 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4326 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4329 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4331 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4334 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4336 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4337 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4338 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4339 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4342 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4344 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4345 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4346 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4347 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4350 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4352 rtl_tx_performance_tweak(tp,
4353 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4356 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4358 rtl_tx_performance_tweak(tp,
4359 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4362 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4364 r8168b_0_hw_jumbo_enable(tp);
4366 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4369 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4371 r8168b_0_hw_jumbo_disable(tp);
4373 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4376 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4378 struct jumbo_ops *ops = &tp->jumbo_ops;
4380 switch (tp->mac_version) {
4381 case RTL_GIGA_MAC_VER_11:
4382 ops->disable = r8168b_0_hw_jumbo_disable;
4383 ops->enable = r8168b_0_hw_jumbo_enable;
4385 case RTL_GIGA_MAC_VER_12:
4386 case RTL_GIGA_MAC_VER_17:
4387 ops->disable = r8168b_1_hw_jumbo_disable;
4388 ops->enable = r8168b_1_hw_jumbo_enable;
4390 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4391 case RTL_GIGA_MAC_VER_19:
4392 case RTL_GIGA_MAC_VER_20:
4393 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4394 case RTL_GIGA_MAC_VER_22:
4395 case RTL_GIGA_MAC_VER_23:
4396 case RTL_GIGA_MAC_VER_24:
4397 case RTL_GIGA_MAC_VER_25:
4398 case RTL_GIGA_MAC_VER_26:
4399 ops->disable = r8168c_hw_jumbo_disable;
4400 ops->enable = r8168c_hw_jumbo_enable;
4402 case RTL_GIGA_MAC_VER_27:
4403 case RTL_GIGA_MAC_VER_28:
4404 ops->disable = r8168dp_hw_jumbo_disable;
4405 ops->enable = r8168dp_hw_jumbo_enable;
4407 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4408 case RTL_GIGA_MAC_VER_32:
4409 case RTL_GIGA_MAC_VER_33:
4410 case RTL_GIGA_MAC_VER_34:
4411 ops->disable = r8168e_hw_jumbo_disable;
4412 ops->enable = r8168e_hw_jumbo_enable;
4416 * No action needed for jumbo frames with 8169.
4417 * No jumbo for 810x at all.
4419 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4421 ops->disable = NULL;
4427 DECLARE_RTL_COND(rtl_chipcmd_cond)
4429 return RTL_R8(tp, ChipCmd) & CmdReset;
4432 static void rtl_hw_reset(struct rtl8169_private *tp)
4434 RTL_W8(tp, ChipCmd, CmdReset);
4436 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4439 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4441 struct rtl_fw *rtl_fw;
4445 name = rtl_lookup_firmware_name(tp);
4447 goto out_no_firmware;
4449 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4453 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4457 rc = rtl_check_firmware(tp, rtl_fw);
4459 goto err_release_firmware;
4461 tp->rtl_fw = rtl_fw;
4465 err_release_firmware:
4466 release_firmware(rtl_fw->fw);
4470 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4477 static void rtl_request_firmware(struct rtl8169_private *tp)
4479 if (IS_ERR(tp->rtl_fw))
4480 rtl_request_uncached_firmware(tp);
4483 static void rtl_rx_close(struct rtl8169_private *tp)
4485 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4488 DECLARE_RTL_COND(rtl_npq_cond)
4490 return RTL_R8(tp, TxPoll) & NPQ;
4493 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4495 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4498 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4500 /* Disable interrupts */
4501 rtl8169_irq_mask_and_ack(tp);
4505 switch (tp->mac_version) {
4506 case RTL_GIGA_MAC_VER_27:
4507 case RTL_GIGA_MAC_VER_28:
4508 case RTL_GIGA_MAC_VER_31:
4509 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4511 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4512 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4513 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4514 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4517 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4525 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4527 /* Set DMA burst size and Interframe Gap Time */
4528 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4529 (InterFrameGap << TxInterFrameGapShift));
4532 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4534 /* Low hurts. Let's disable the filtering. */
4535 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4538 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4541 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4542 * register to be written before TxDescAddrLow to work.
4543 * Switching from MMIO to I/O access fixes the issue as well.
4545 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4546 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4547 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4548 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4551 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4553 static const struct rtl_cfg2_info {
4558 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4559 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4560 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4561 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4563 const struct rtl_cfg2_info *p = cfg2_info;
4567 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4568 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4569 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4570 RTL_W32(tp, 0x7c, p->val);
4576 static void rtl_set_rx_mode(struct net_device *dev)
4578 struct rtl8169_private *tp = netdev_priv(dev);
4579 u32 mc_filter[2]; /* Multicast hash filter */
4583 if (dev->flags & IFF_PROMISC) {
4584 /* Unconditionally log net taps. */
4585 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4587 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4589 mc_filter[1] = mc_filter[0] = 0xffffffff;
4590 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4591 (dev->flags & IFF_ALLMULTI)) {
4592 /* Too many to filter perfectly -- accept all multicasts. */
4593 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4594 mc_filter[1] = mc_filter[0] = 0xffffffff;
4596 struct netdev_hw_addr *ha;
4598 rx_mode = AcceptBroadcast | AcceptMyPhys;
4599 mc_filter[1] = mc_filter[0] = 0;
4600 netdev_for_each_mc_addr(ha, dev) {
4601 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4602 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4603 rx_mode |= AcceptMulticast;
4607 if (dev->features & NETIF_F_RXALL)
4608 rx_mode |= (AcceptErr | AcceptRunt);
4610 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4612 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4613 u32 data = mc_filter[0];
4615 mc_filter[0] = swab32(mc_filter[1]);
4616 mc_filter[1] = swab32(data);
4619 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4620 mc_filter[1] = mc_filter[0] = 0xffffffff;
4622 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4623 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4625 RTL_W32(tp, RxConfig, tmp);
4628 static void rtl_hw_start(struct rtl8169_private *tp)
4630 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4634 rtl_set_rx_max_size(tp);
4635 rtl_set_rx_tx_desc_registers(tp);
4636 rtl_set_rx_tx_config_registers(tp);
4637 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4639 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4640 RTL_R8(tp, IntrMask);
4641 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4642 rtl_set_rx_mode(tp->dev);
4643 /* no early-rx interrupts */
4644 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4645 rtl_irq_enable_all(tp);
4648 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4650 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4651 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4653 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4655 tp->cp_cmd |= PCIMulRW;
4657 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4658 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4659 netif_dbg(tp, drv, tp->dev,
4660 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4661 tp->cp_cmd |= (1 << 14);
4664 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4666 rtl8169_set_magic_reg(tp, tp->mac_version);
4669 * Undocumented corner. Supposedly:
4670 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4672 RTL_W16(tp, IntrMitigate, 0x0000);
4674 RTL_W32(tp, RxMissed, 0);
4677 DECLARE_RTL_COND(rtl_csiar_cond)
4679 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4682 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4684 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4686 RTL_W32(tp, CSIDR, value);
4687 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4688 CSIAR_BYTE_ENABLE | func << 16);
4690 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4693 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4695 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4697 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4700 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4701 RTL_R32(tp, CSIDR) : ~0;
4704 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4706 struct pci_dev *pdev = tp->pci_dev;
4709 /* According to Realtek the value at config space address 0x070f
4710 * controls the L0s/L1 entrance latency. We try standard ECAM access
4711 * first and if it fails fall back to CSI.
4713 if (pdev->cfg_size > 0x070f &&
4714 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4717 netdev_notice_once(tp->dev,
4718 "No native access to PCI extended config space, falling back to CSI\n");
4719 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4720 rtl_csi_write(tp, 0x070c, csi | val << 24);
4723 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4725 rtl_csi_access_enable(tp, 0x27);
4729 unsigned int offset;
4734 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4740 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4741 rtl_ephy_write(tp, e->offset, w);
4746 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4748 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4749 PCI_EXP_LNKCTL_CLKREQ_EN);
4752 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4754 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4755 PCI_EXP_LNKCTL_CLKREQ_EN);
4758 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4762 data = RTL_R8(tp, Config3);
4767 data &= ~Rdy_to_L23;
4769 RTL_W8(tp, Config3, data);
4772 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4775 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4776 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4778 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4779 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4783 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4785 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4787 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4788 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4790 if (tp->dev->mtu <= ETH_DATA_LEN) {
4791 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4792 PCI_EXP_DEVCTL_NOSNOOP_EN);
4796 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4798 rtl_hw_start_8168bb(tp);
4800 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4802 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4805 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4807 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4809 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4811 if (tp->dev->mtu <= ETH_DATA_LEN)
4812 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4814 rtl_disable_clock_request(tp);
4816 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4817 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4820 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4822 static const struct ephy_info e_info_8168cp[] = {
4823 { 0x01, 0, 0x0001 },
4824 { 0x02, 0x0800, 0x1000 },
4825 { 0x03, 0, 0x0042 },
4826 { 0x06, 0x0080, 0x0000 },
4830 rtl_set_def_aspm_entry_latency(tp);
4832 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4834 __rtl_hw_start_8168cp(tp);
4837 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4839 rtl_set_def_aspm_entry_latency(tp);
4841 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4843 if (tp->dev->mtu <= ETH_DATA_LEN)
4844 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4846 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4847 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4850 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4852 rtl_set_def_aspm_entry_latency(tp);
4854 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4857 RTL_W8(tp, DBG_REG, 0x20);
4859 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4861 if (tp->dev->mtu <= ETH_DATA_LEN)
4862 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4864 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4865 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4868 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4870 static const struct ephy_info e_info_8168c_1[] = {
4871 { 0x02, 0x0800, 0x1000 },
4872 { 0x03, 0, 0x0002 },
4873 { 0x06, 0x0080, 0x0000 }
4876 rtl_set_def_aspm_entry_latency(tp);
4878 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4880 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4882 __rtl_hw_start_8168cp(tp);
4885 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4887 static const struct ephy_info e_info_8168c_2[] = {
4888 { 0x01, 0, 0x0001 },
4889 { 0x03, 0x0400, 0x0220 }
4892 rtl_set_def_aspm_entry_latency(tp);
4894 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4896 __rtl_hw_start_8168cp(tp);
4899 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4901 rtl_hw_start_8168c_2(tp);
4904 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4906 rtl_set_def_aspm_entry_latency(tp);
4908 __rtl_hw_start_8168cp(tp);
4911 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4913 rtl_set_def_aspm_entry_latency(tp);
4915 rtl_disable_clock_request(tp);
4917 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4919 if (tp->dev->mtu <= ETH_DATA_LEN)
4920 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4922 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4923 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4926 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4928 rtl_set_def_aspm_entry_latency(tp);
4930 if (tp->dev->mtu <= ETH_DATA_LEN)
4931 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4933 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4935 rtl_disable_clock_request(tp);
4938 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4940 static const struct ephy_info e_info_8168d_4[] = {
4941 { 0x0b, 0x0000, 0x0048 },
4942 { 0x19, 0x0020, 0x0050 },
4943 { 0x0c, 0x0100, 0x0020 }
4946 rtl_set_def_aspm_entry_latency(tp);
4948 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4950 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4952 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4954 rtl_enable_clock_request(tp);
4957 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4959 static const struct ephy_info e_info_8168e_1[] = {
4960 { 0x00, 0x0200, 0x0100 },
4961 { 0x00, 0x0000, 0x0004 },
4962 { 0x06, 0x0002, 0x0001 },
4963 { 0x06, 0x0000, 0x0030 },
4964 { 0x07, 0x0000, 0x2000 },
4965 { 0x00, 0x0000, 0x0020 },
4966 { 0x03, 0x5800, 0x2000 },
4967 { 0x03, 0x0000, 0x0001 },
4968 { 0x01, 0x0800, 0x1000 },
4969 { 0x07, 0x0000, 0x4000 },
4970 { 0x1e, 0x0000, 0x2000 },
4971 { 0x19, 0xffff, 0xfe6c },
4972 { 0x0a, 0x0000, 0x0040 }
4975 rtl_set_def_aspm_entry_latency(tp);
4977 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4979 if (tp->dev->mtu <= ETH_DATA_LEN)
4980 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4982 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4984 rtl_disable_clock_request(tp);
4986 /* Reset tx FIFO pointer */
4987 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4988 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4990 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4993 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4995 static const struct ephy_info e_info_8168e_2[] = {
4996 { 0x09, 0x0000, 0x0080 },
4997 { 0x19, 0x0000, 0x0224 }
5000 rtl_set_def_aspm_entry_latency(tp);
5002 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5004 if (tp->dev->mtu <= ETH_DATA_LEN)
5005 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5007 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5008 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5009 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5010 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5011 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5012 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5013 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5014 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5016 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5018 rtl_disable_clock_request(tp);
5020 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5021 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5023 /* Adjust EEE LED frequency */
5024 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5026 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5027 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5028 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5030 rtl_hw_aspm_clkreq_enable(tp, true);
5033 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5035 rtl_set_def_aspm_entry_latency(tp);
5037 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5039 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5040 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5041 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5042 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5043 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5044 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5045 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5046 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5047 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5048 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5050 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5052 rtl_disable_clock_request(tp);
5054 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5055 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5056 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5057 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5058 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5061 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5063 static const struct ephy_info e_info_8168f_1[] = {
5064 { 0x06, 0x00c0, 0x0020 },
5065 { 0x08, 0x0001, 0x0002 },
5066 { 0x09, 0x0000, 0x0080 },
5067 { 0x19, 0x0000, 0x0224 }
5070 rtl_hw_start_8168f(tp);
5072 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5074 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5076 /* Adjust EEE LED frequency */
5077 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5080 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5082 static const struct ephy_info e_info_8168f_1[] = {
5083 { 0x06, 0x00c0, 0x0020 },
5084 { 0x0f, 0xffff, 0x5200 },
5085 { 0x1e, 0x0000, 0x4000 },
5086 { 0x19, 0x0000, 0x0224 }
5089 rtl_hw_start_8168f(tp);
5090 rtl_pcie_state_l2l3_enable(tp, false);
5092 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5094 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5097 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5099 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5101 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5102 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5103 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5104 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5106 rtl_set_def_aspm_entry_latency(tp);
5108 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5110 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5111 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5112 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5114 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5115 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5117 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5118 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5120 /* Adjust EEE LED frequency */
5121 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5123 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5124 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5126 rtl_pcie_state_l2l3_enable(tp, false);
5129 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5131 static const struct ephy_info e_info_8168g_1[] = {
5132 { 0x00, 0x0000, 0x0008 },
5133 { 0x0c, 0x37d0, 0x0820 },
5134 { 0x1e, 0x0000, 0x0001 },
5135 { 0x19, 0x8000, 0x0000 }
5138 rtl_hw_start_8168g(tp);
5140 /* disable aspm and clock request before access ephy */
5141 rtl_hw_aspm_clkreq_enable(tp, false);
5142 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5143 rtl_hw_aspm_clkreq_enable(tp, true);
5146 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5148 static const struct ephy_info e_info_8168g_2[] = {
5149 { 0x00, 0x0000, 0x0008 },
5150 { 0x0c, 0x3df0, 0x0200 },
5151 { 0x19, 0xffff, 0xfc00 },
5152 { 0x1e, 0xffff, 0x20eb }
5155 rtl_hw_start_8168g(tp);
5157 /* disable aspm and clock request before access ephy */
5158 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5159 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5160 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5163 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5165 static const struct ephy_info e_info_8411_2[] = {
5166 { 0x00, 0x0000, 0x0008 },
5167 { 0x0c, 0x3df0, 0x0200 },
5168 { 0x0f, 0xffff, 0x5200 },
5169 { 0x19, 0x0020, 0x0000 },
5170 { 0x1e, 0x0000, 0x2000 }
5173 rtl_hw_start_8168g(tp);
5175 /* disable aspm and clock request before access ephy */
5176 rtl_hw_aspm_clkreq_enable(tp, false);
5177 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5178 rtl_hw_aspm_clkreq_enable(tp, true);
5181 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5185 static const struct ephy_info e_info_8168h_1[] = {
5186 { 0x1e, 0x0800, 0x0001 },
5187 { 0x1d, 0x0000, 0x0800 },
5188 { 0x05, 0xffff, 0x2089 },
5189 { 0x06, 0xffff, 0x5881 },
5190 { 0x04, 0xffff, 0x154a },
5191 { 0x01, 0xffff, 0x068b }
5194 /* disable aspm and clock request before access ephy */
5195 rtl_hw_aspm_clkreq_enable(tp, false);
5196 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5198 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5200 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5201 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5202 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5203 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5205 rtl_set_def_aspm_entry_latency(tp);
5207 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5209 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5210 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5212 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5214 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5216 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5218 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5219 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5221 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5222 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5224 /* Adjust EEE LED frequency */
5225 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5227 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5228 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5230 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5232 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5234 rtl_pcie_state_l2l3_enable(tp, false);
5236 rtl_writephy(tp, 0x1f, 0x0c42);
5237 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5238 rtl_writephy(tp, 0x1f, 0x0000);
5239 if (rg_saw_cnt > 0) {
5242 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5243 sw_cnt_1ms_ini &= 0x0fff;
5244 data = r8168_mac_ocp_read(tp, 0xd412);
5246 data |= sw_cnt_1ms_ini;
5247 r8168_mac_ocp_write(tp, 0xd412, data);
5250 data = r8168_mac_ocp_read(tp, 0xe056);
5253 r8168_mac_ocp_write(tp, 0xe056, data);
5255 data = r8168_mac_ocp_read(tp, 0xe052);
5258 r8168_mac_ocp_write(tp, 0xe052, data);
5260 data = r8168_mac_ocp_read(tp, 0xe0d6);
5263 r8168_mac_ocp_write(tp, 0xe0d6, data);
5265 data = r8168_mac_ocp_read(tp, 0xd420);
5268 r8168_mac_ocp_write(tp, 0xd420, data);
5270 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5271 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5272 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5273 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5275 rtl_hw_aspm_clkreq_enable(tp, true);
5278 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5280 rtl8168ep_stop_cmac(tp);
5282 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5284 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5285 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5286 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5287 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5289 rtl_set_def_aspm_entry_latency(tp);
5291 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5293 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5294 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5296 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5298 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5300 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5301 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5303 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5304 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5306 /* Adjust EEE LED frequency */
5307 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5309 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5311 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5313 rtl_pcie_state_l2l3_enable(tp, false);
5316 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5318 static const struct ephy_info e_info_8168ep_1[] = {
5319 { 0x00, 0xffff, 0x10ab },
5320 { 0x06, 0xffff, 0xf030 },
5321 { 0x08, 0xffff, 0x2006 },
5322 { 0x0d, 0xffff, 0x1666 },
5323 { 0x0c, 0x3ff0, 0x0000 }
5326 /* disable aspm and clock request before access ephy */
5327 rtl_hw_aspm_clkreq_enable(tp, false);
5328 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5330 rtl_hw_start_8168ep(tp);
5332 rtl_hw_aspm_clkreq_enable(tp, true);
5335 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5337 static const struct ephy_info e_info_8168ep_2[] = {
5338 { 0x00, 0xffff, 0x10a3 },
5339 { 0x19, 0xffff, 0xfc00 },
5340 { 0x1e, 0xffff, 0x20ea }
5343 /* disable aspm and clock request before access ephy */
5344 rtl_hw_aspm_clkreq_enable(tp, false);
5345 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5347 rtl_hw_start_8168ep(tp);
5349 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5350 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5352 rtl_hw_aspm_clkreq_enable(tp, true);
5355 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5358 static const struct ephy_info e_info_8168ep_3[] = {
5359 { 0x00, 0xffff, 0x10a3 },
5360 { 0x19, 0xffff, 0x7c00 },
5361 { 0x1e, 0xffff, 0x20eb },
5362 { 0x0d, 0xffff, 0x1666 }
5365 /* disable aspm and clock request before access ephy */
5366 rtl_hw_aspm_clkreq_enable(tp, false);
5367 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5369 rtl_hw_start_8168ep(tp);
5371 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5372 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5374 data = r8168_mac_ocp_read(tp, 0xd3e2);
5377 r8168_mac_ocp_write(tp, 0xd3e2, data);
5379 data = r8168_mac_ocp_read(tp, 0xd3e4);
5381 r8168_mac_ocp_write(tp, 0xd3e4, data);
5383 data = r8168_mac_ocp_read(tp, 0xe860);
5385 r8168_mac_ocp_write(tp, 0xe860, data);
5387 rtl_hw_aspm_clkreq_enable(tp, true);
5390 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5392 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5394 tp->cp_cmd &= ~INTT_MASK;
5395 tp->cp_cmd |= PktCntrDisable | INTT_1;
5396 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5398 RTL_W16(tp, IntrMitigate, 0x5151);
5400 /* Work around for RxFIFO overflow. */
5401 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5402 tp->event_slow |= RxFIFOOver | PCSTimeout;
5403 tp->event_slow &= ~RxOverflow;
5406 switch (tp->mac_version) {
5407 case RTL_GIGA_MAC_VER_11:
5408 rtl_hw_start_8168bb(tp);
5411 case RTL_GIGA_MAC_VER_12:
5412 case RTL_GIGA_MAC_VER_17:
5413 rtl_hw_start_8168bef(tp);
5416 case RTL_GIGA_MAC_VER_18:
5417 rtl_hw_start_8168cp_1(tp);
5420 case RTL_GIGA_MAC_VER_19:
5421 rtl_hw_start_8168c_1(tp);
5424 case RTL_GIGA_MAC_VER_20:
5425 rtl_hw_start_8168c_2(tp);
5428 case RTL_GIGA_MAC_VER_21:
5429 rtl_hw_start_8168c_3(tp);
5432 case RTL_GIGA_MAC_VER_22:
5433 rtl_hw_start_8168c_4(tp);
5436 case RTL_GIGA_MAC_VER_23:
5437 rtl_hw_start_8168cp_2(tp);
5440 case RTL_GIGA_MAC_VER_24:
5441 rtl_hw_start_8168cp_3(tp);
5444 case RTL_GIGA_MAC_VER_25:
5445 case RTL_GIGA_MAC_VER_26:
5446 case RTL_GIGA_MAC_VER_27:
5447 rtl_hw_start_8168d(tp);
5450 case RTL_GIGA_MAC_VER_28:
5451 rtl_hw_start_8168d_4(tp);
5454 case RTL_GIGA_MAC_VER_31:
5455 rtl_hw_start_8168dp(tp);
5458 case RTL_GIGA_MAC_VER_32:
5459 case RTL_GIGA_MAC_VER_33:
5460 rtl_hw_start_8168e_1(tp);
5462 case RTL_GIGA_MAC_VER_34:
5463 rtl_hw_start_8168e_2(tp);
5466 case RTL_GIGA_MAC_VER_35:
5467 case RTL_GIGA_MAC_VER_36:
5468 rtl_hw_start_8168f_1(tp);
5471 case RTL_GIGA_MAC_VER_38:
5472 rtl_hw_start_8411(tp);
5475 case RTL_GIGA_MAC_VER_40:
5476 case RTL_GIGA_MAC_VER_41:
5477 rtl_hw_start_8168g_1(tp);
5479 case RTL_GIGA_MAC_VER_42:
5480 rtl_hw_start_8168g_2(tp);
5483 case RTL_GIGA_MAC_VER_44:
5484 rtl_hw_start_8411_2(tp);
5487 case RTL_GIGA_MAC_VER_45:
5488 case RTL_GIGA_MAC_VER_46:
5489 rtl_hw_start_8168h_1(tp);
5492 case RTL_GIGA_MAC_VER_49:
5493 rtl_hw_start_8168ep_1(tp);
5496 case RTL_GIGA_MAC_VER_50:
5497 rtl_hw_start_8168ep_2(tp);
5500 case RTL_GIGA_MAC_VER_51:
5501 rtl_hw_start_8168ep_3(tp);
5505 netif_err(tp, drv, tp->dev,
5506 "unknown chipset (mac_version = %d)\n",
5512 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5514 static const struct ephy_info e_info_8102e_1[] = {
5515 { 0x01, 0, 0x6e65 },
5516 { 0x02, 0, 0x091f },
5517 { 0x03, 0, 0xc2f9 },
5518 { 0x06, 0, 0xafb5 },
5519 { 0x07, 0, 0x0e00 },
5520 { 0x19, 0, 0xec80 },
5521 { 0x01, 0, 0x2e65 },
5526 rtl_set_def_aspm_entry_latency(tp);
5528 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5530 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5533 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5534 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5536 cfg1 = RTL_R8(tp, Config1);
5537 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5538 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5540 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5543 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5545 rtl_set_def_aspm_entry_latency(tp);
5547 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5549 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5550 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5553 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5555 rtl_hw_start_8102e_2(tp);
5557 rtl_ephy_write(tp, 0x03, 0xc2f9);
5560 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5562 static const struct ephy_info e_info_8105e_1[] = {
5563 { 0x07, 0, 0x4000 },
5564 { 0x19, 0, 0x0200 },
5565 { 0x19, 0, 0x0020 },
5566 { 0x1e, 0, 0x2000 },
5567 { 0x03, 0, 0x0001 },
5568 { 0x19, 0, 0x0100 },
5569 { 0x19, 0, 0x0004 },
5573 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5574 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5576 /* Disable Early Tally Counter */
5577 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5579 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5580 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5582 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5584 rtl_pcie_state_l2l3_enable(tp, false);
5587 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5589 rtl_hw_start_8105e_1(tp);
5590 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5593 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5595 static const struct ephy_info e_info_8402[] = {
5596 { 0x19, 0xffff, 0xff64 },
5600 rtl_set_def_aspm_entry_latency(tp);
5602 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5603 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5605 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5606 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5608 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5610 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5612 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5613 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5614 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5615 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5616 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5617 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5618 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5620 rtl_pcie_state_l2l3_enable(tp, false);
5623 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5625 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5626 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5628 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5629 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5630 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5632 rtl_pcie_state_l2l3_enable(tp, false);
5635 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5637 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5638 tp->event_slow &= ~RxFIFOOver;
5640 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5641 tp->mac_version == RTL_GIGA_MAC_VER_16)
5642 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5643 PCI_EXP_DEVCTL_NOSNOOP_EN);
5645 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5647 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5648 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5650 switch (tp->mac_version) {
5651 case RTL_GIGA_MAC_VER_07:
5652 rtl_hw_start_8102e_1(tp);
5655 case RTL_GIGA_MAC_VER_08:
5656 rtl_hw_start_8102e_3(tp);
5659 case RTL_GIGA_MAC_VER_09:
5660 rtl_hw_start_8102e_2(tp);
5663 case RTL_GIGA_MAC_VER_29:
5664 rtl_hw_start_8105e_1(tp);
5666 case RTL_GIGA_MAC_VER_30:
5667 rtl_hw_start_8105e_2(tp);
5670 case RTL_GIGA_MAC_VER_37:
5671 rtl_hw_start_8402(tp);
5674 case RTL_GIGA_MAC_VER_39:
5675 rtl_hw_start_8106(tp);
5677 case RTL_GIGA_MAC_VER_43:
5678 rtl_hw_start_8168g_2(tp);
5680 case RTL_GIGA_MAC_VER_47:
5681 case RTL_GIGA_MAC_VER_48:
5682 rtl_hw_start_8168h_1(tp);
5686 RTL_W16(tp, IntrMitigate, 0x0000);
5689 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5691 struct rtl8169_private *tp = netdev_priv(dev);
5693 if (new_mtu > ETH_DATA_LEN)
5694 rtl_hw_jumbo_enable(tp);
5696 rtl_hw_jumbo_disable(tp);
5699 netdev_update_features(dev);
5704 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5706 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5707 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5710 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5711 void **data_buff, struct RxDesc *desc)
5713 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5714 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5718 rtl8169_make_unusable_by_asic(desc);
5721 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5723 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5725 /* Force memory writes to complete before releasing descriptor */
5728 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5731 static inline void *rtl8169_align(void *data)
5733 return (void *)ALIGN((long)data, 16);
5736 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5737 struct RxDesc *desc)
5741 struct device *d = tp_to_dev(tp);
5742 int node = dev_to_node(d);
5744 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5748 if (rtl8169_align(data) != data) {
5750 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5755 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5757 if (unlikely(dma_mapping_error(d, mapping))) {
5758 if (net_ratelimit())
5759 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5763 desc->addr = cpu_to_le64(mapping);
5764 rtl8169_mark_to_asic(desc);
5772 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5776 for (i = 0; i < NUM_RX_DESC; i++) {
5777 if (tp->Rx_databuff[i]) {
5778 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5779 tp->RxDescArray + i);
5784 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5786 desc->opts1 |= cpu_to_le32(RingEnd);
5789 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5793 for (i = 0; i < NUM_RX_DESC; i++) {
5796 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5798 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5801 tp->Rx_databuff[i] = data;
5804 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5808 rtl8169_rx_clear(tp);
5812 static int rtl8169_init_ring(struct rtl8169_private *tp)
5814 rtl8169_init_ring_indexes(tp);
5816 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5817 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5819 return rtl8169_rx_fill(tp);
5822 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5823 struct TxDesc *desc)
5825 unsigned int len = tx_skb->len;
5827 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5835 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5840 for (i = 0; i < n; i++) {
5841 unsigned int entry = (start + i) % NUM_TX_DESC;
5842 struct ring_info *tx_skb = tp->tx_skb + entry;
5843 unsigned int len = tx_skb->len;
5846 struct sk_buff *skb = tx_skb->skb;
5848 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5849 tp->TxDescArray + entry);
5851 dev_consume_skb_any(skb);
5858 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5860 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5861 tp->cur_tx = tp->dirty_tx = 0;
5864 static void rtl_reset_work(struct rtl8169_private *tp)
5866 struct net_device *dev = tp->dev;
5869 napi_disable(&tp->napi);
5870 netif_stop_queue(dev);
5871 synchronize_sched();
5873 rtl8169_hw_reset(tp);
5875 for (i = 0; i < NUM_RX_DESC; i++)
5876 rtl8169_mark_to_asic(tp->RxDescArray + i);
5878 rtl8169_tx_clear(tp);
5879 rtl8169_init_ring_indexes(tp);
5881 napi_enable(&tp->napi);
5883 netif_wake_queue(dev);
5886 static void rtl8169_tx_timeout(struct net_device *dev)
5888 struct rtl8169_private *tp = netdev_priv(dev);
5890 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5893 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5896 struct skb_shared_info *info = skb_shinfo(skb);
5897 unsigned int cur_frag, entry;
5898 struct TxDesc *uninitialized_var(txd);
5899 struct device *d = tp_to_dev(tp);
5902 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5903 const skb_frag_t *frag = info->frags + cur_frag;
5908 entry = (entry + 1) % NUM_TX_DESC;
5910 txd = tp->TxDescArray + entry;
5911 len = skb_frag_size(frag);
5912 addr = skb_frag_address(frag);
5913 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5914 if (unlikely(dma_mapping_error(d, mapping))) {
5915 if (net_ratelimit())
5916 netif_err(tp, drv, tp->dev,
5917 "Failed to map TX fragments DMA!\n");
5921 /* Anti gcc 2.95.3 bugware (sic) */
5922 status = opts[0] | len |
5923 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5925 txd->opts1 = cpu_to_le32(status);
5926 txd->opts2 = cpu_to_le32(opts[1]);
5927 txd->addr = cpu_to_le64(mapping);
5929 tp->tx_skb[entry].len = len;
5933 tp->tx_skb[entry].skb = skb;
5934 txd->opts1 |= cpu_to_le32(LastFrag);
5940 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5944 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5946 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5949 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5950 struct net_device *dev);
5951 /* r8169_csum_workaround()
5952 * The hw limites the value the transport offset. When the offset is out of the
5953 * range, calculate the checksum by sw.
5955 static void r8169_csum_workaround(struct rtl8169_private *tp,
5956 struct sk_buff *skb)
5958 if (skb_shinfo(skb)->gso_size) {
5959 netdev_features_t features = tp->dev->features;
5960 struct sk_buff *segs, *nskb;
5962 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5963 segs = skb_gso_segment(skb, features);
5964 if (IS_ERR(segs) || !segs)
5971 rtl8169_start_xmit(nskb, tp->dev);
5974 dev_consume_skb_any(skb);
5975 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5976 if (skb_checksum_help(skb) < 0)
5979 rtl8169_start_xmit(skb, tp->dev);
5981 struct net_device_stats *stats;
5984 stats = &tp->dev->stats;
5985 stats->tx_dropped++;
5986 dev_kfree_skb_any(skb);
5990 /* msdn_giant_send_check()
5991 * According to the document of microsoft, the TCP Pseudo Header excludes the
5992 * packet length for IPv6 TCP large packets.
5994 static int msdn_giant_send_check(struct sk_buff *skb)
5996 const struct ipv6hdr *ipv6h;
6000 ret = skb_cow_head(skb, 0);
6004 ipv6h = ipv6_hdr(skb);
6008 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6013 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6014 struct sk_buff *skb, u32 *opts)
6016 u32 mss = skb_shinfo(skb)->gso_size;
6020 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6021 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6022 const struct iphdr *ip = ip_hdr(skb);
6024 if (ip->protocol == IPPROTO_TCP)
6025 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6026 else if (ip->protocol == IPPROTO_UDP)
6027 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6035 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6036 struct sk_buff *skb, u32 *opts)
6038 u32 transport_offset = (u32)skb_transport_offset(skb);
6039 u32 mss = skb_shinfo(skb)->gso_size;
6042 if (transport_offset > GTTCPHO_MAX) {
6043 netif_warn(tp, tx_err, tp->dev,
6044 "Invalid transport offset 0x%x for TSO\n",
6049 switch (vlan_get_protocol(skb)) {
6050 case htons(ETH_P_IP):
6051 opts[0] |= TD1_GTSENV4;
6054 case htons(ETH_P_IPV6):
6055 if (msdn_giant_send_check(skb))
6058 opts[0] |= TD1_GTSENV6;
6066 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6067 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6068 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6071 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6072 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6074 if (transport_offset > TCPHO_MAX) {
6075 netif_warn(tp, tx_err, tp->dev,
6076 "Invalid transport offset 0x%x\n",
6081 switch (vlan_get_protocol(skb)) {
6082 case htons(ETH_P_IP):
6083 opts[1] |= TD1_IPv4_CS;
6084 ip_protocol = ip_hdr(skb)->protocol;
6087 case htons(ETH_P_IPV6):
6088 opts[1] |= TD1_IPv6_CS;
6089 ip_protocol = ipv6_hdr(skb)->nexthdr;
6093 ip_protocol = IPPROTO_RAW;
6097 if (ip_protocol == IPPROTO_TCP)
6098 opts[1] |= TD1_TCP_CS;
6099 else if (ip_protocol == IPPROTO_UDP)
6100 opts[1] |= TD1_UDP_CS;
6104 opts[1] |= transport_offset << TCPHO_SHIFT;
6106 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6107 return !eth_skb_pad(skb);
6113 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6114 struct net_device *dev)
6116 struct rtl8169_private *tp = netdev_priv(dev);
6117 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6118 struct TxDesc *txd = tp->TxDescArray + entry;
6119 struct device *d = tp_to_dev(tp);
6125 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6126 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6130 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6133 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6136 if (!tp->tso_csum(tp, skb, opts)) {
6137 r8169_csum_workaround(tp, skb);
6138 return NETDEV_TX_OK;
6141 len = skb_headlen(skb);
6142 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6143 if (unlikely(dma_mapping_error(d, mapping))) {
6144 if (net_ratelimit())
6145 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6149 tp->tx_skb[entry].len = len;
6150 txd->addr = cpu_to_le64(mapping);
6152 frags = rtl8169_xmit_frags(tp, skb, opts);
6156 opts[0] |= FirstFrag;
6158 opts[0] |= FirstFrag | LastFrag;
6159 tp->tx_skb[entry].skb = skb;
6162 txd->opts2 = cpu_to_le32(opts[1]);
6164 skb_tx_timestamp(skb);
6166 /* Force memory writes to complete before releasing descriptor */
6169 /* Anti gcc 2.95.3 bugware (sic) */
6170 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6171 txd->opts1 = cpu_to_le32(status);
6173 /* Force all memory writes to complete before notifying device */
6176 tp->cur_tx += frags + 1;
6178 RTL_W8(tp, TxPoll, NPQ);
6182 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6183 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6184 * not miss a ring update when it notices a stopped queue.
6187 netif_stop_queue(dev);
6188 /* Sync with rtl_tx:
6189 * - publish queue status and cur_tx ring index (write barrier)
6190 * - refresh dirty_tx ring index (read barrier).
6191 * May the current thread have a pessimistic view of the ring
6192 * status and forget to wake up queue, a racing rtl_tx thread
6196 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6197 netif_wake_queue(dev);
6200 return NETDEV_TX_OK;
6203 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6205 dev_kfree_skb_any(skb);
6206 dev->stats.tx_dropped++;
6207 return NETDEV_TX_OK;
6210 netif_stop_queue(dev);
6211 dev->stats.tx_dropped++;
6212 return NETDEV_TX_BUSY;
6215 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6217 struct rtl8169_private *tp = netdev_priv(dev);
6218 struct pci_dev *pdev = tp->pci_dev;
6219 u16 pci_status, pci_cmd;
6221 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6222 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6224 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6225 pci_cmd, pci_status);
6228 * The recovery sequence below admits a very elaborated explanation:
6229 * - it seems to work;
6230 * - I did not see what else could be done;
6231 * - it makes iop3xx happy.
6233 * Feel free to adjust to your needs.
6235 if (pdev->broken_parity_status)
6236 pci_cmd &= ~PCI_COMMAND_PARITY;
6238 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6240 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6242 pci_write_config_word(pdev, PCI_STATUS,
6243 pci_status & (PCI_STATUS_DETECTED_PARITY |
6244 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6245 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6247 /* The infamous DAC f*ckup only happens at boot time */
6248 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6249 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6250 tp->cp_cmd &= ~PCIDAC;
6251 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6252 dev->features &= ~NETIF_F_HIGHDMA;
6255 rtl8169_hw_reset(tp);
6257 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6260 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6262 unsigned int dirty_tx, tx_left;
6264 dirty_tx = tp->dirty_tx;
6266 tx_left = tp->cur_tx - dirty_tx;
6268 while (tx_left > 0) {
6269 unsigned int entry = dirty_tx % NUM_TX_DESC;
6270 struct ring_info *tx_skb = tp->tx_skb + entry;
6273 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6274 if (status & DescOwn)
6277 /* This barrier is needed to keep us from reading
6278 * any other fields out of the Tx descriptor until
6279 * we know the status of DescOwn
6283 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6284 tp->TxDescArray + entry);
6285 if (status & LastFrag) {
6286 u64_stats_update_begin(&tp->tx_stats.syncp);
6287 tp->tx_stats.packets++;
6288 tp->tx_stats.bytes += tx_skb->skb->len;
6289 u64_stats_update_end(&tp->tx_stats.syncp);
6290 dev_consume_skb_any(tx_skb->skb);
6297 if (tp->dirty_tx != dirty_tx) {
6298 tp->dirty_tx = dirty_tx;
6299 /* Sync with rtl8169_start_xmit:
6300 * - publish dirty_tx ring index (write barrier)
6301 * - refresh cur_tx ring index and queue status (read barrier)
6302 * May the current thread miss the stopped queue condition,
6303 * a racing xmit thread can only have a right view of the
6307 if (netif_queue_stopped(dev) &&
6308 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6309 netif_wake_queue(dev);
6312 * 8168 hack: TxPoll requests are lost when the Tx packets are
6313 * too close. Let's kick an extra TxPoll request when a burst
6314 * of start_xmit activity is detected (if it is not detected,
6315 * it is slow enough). -- FR
6317 if (tp->cur_tx != dirty_tx)
6318 RTL_W8(tp, TxPoll, NPQ);
6322 static inline int rtl8169_fragmented_frame(u32 status)
6324 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6327 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6329 u32 status = opts1 & RxProtoMask;
6331 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6332 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6333 skb->ip_summed = CHECKSUM_UNNECESSARY;
6335 skb_checksum_none_assert(skb);
6338 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6339 struct rtl8169_private *tp,
6343 struct sk_buff *skb;
6344 struct device *d = tp_to_dev(tp);
6346 data = rtl8169_align(data);
6347 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6349 skb = napi_alloc_skb(&tp->napi, pkt_size);
6351 skb_copy_to_linear_data(skb, data, pkt_size);
6352 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6357 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6359 unsigned int cur_rx, rx_left;
6362 cur_rx = tp->cur_rx;
6364 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6365 unsigned int entry = cur_rx % NUM_RX_DESC;
6366 struct RxDesc *desc = tp->RxDescArray + entry;
6369 status = le32_to_cpu(desc->opts1);
6370 if (status & DescOwn)
6373 /* This barrier is needed to keep us from reading
6374 * any other fields out of the Rx descriptor until
6375 * we know the status of DescOwn
6379 if (unlikely(status & RxRES)) {
6380 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6382 dev->stats.rx_errors++;
6383 if (status & (RxRWT | RxRUNT))
6384 dev->stats.rx_length_errors++;
6386 dev->stats.rx_crc_errors++;
6387 /* RxFOVF is a reserved bit on later chip versions */
6388 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6390 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6391 dev->stats.rx_fifo_errors++;
6392 } else if (status & (RxRUNT | RxCRC) &&
6393 !(status & RxRWT) &&
6394 dev->features & NETIF_F_RXALL) {
6398 struct sk_buff *skb;
6403 addr = le64_to_cpu(desc->addr);
6404 if (likely(!(dev->features & NETIF_F_RXFCS)))
6405 pkt_size = (status & 0x00003fff) - 4;
6407 pkt_size = status & 0x00003fff;
6410 * The driver does not support incoming fragmented
6411 * frames. They are seen as a symptom of over-mtu
6414 if (unlikely(rtl8169_fragmented_frame(status))) {
6415 dev->stats.rx_dropped++;
6416 dev->stats.rx_length_errors++;
6417 goto release_descriptor;
6420 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6421 tp, pkt_size, addr);
6423 dev->stats.rx_dropped++;
6424 goto release_descriptor;
6427 rtl8169_rx_csum(skb, status);
6428 skb_put(skb, pkt_size);
6429 skb->protocol = eth_type_trans(skb, dev);
6431 rtl8169_rx_vlan_tag(desc, skb);
6433 if (skb->pkt_type == PACKET_MULTICAST)
6434 dev->stats.multicast++;
6436 napi_gro_receive(&tp->napi, skb);
6438 u64_stats_update_begin(&tp->rx_stats.syncp);
6439 tp->rx_stats.packets++;
6440 tp->rx_stats.bytes += pkt_size;
6441 u64_stats_update_end(&tp->rx_stats.syncp);
6445 rtl8169_mark_to_asic(desc);
6448 count = cur_rx - tp->cur_rx;
6449 tp->cur_rx = cur_rx;
6454 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6456 struct rtl8169_private *tp = dev_instance;
6457 u16 status = rtl_get_events(tp);
6459 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6462 rtl_irq_disable(tp);
6463 napi_schedule_irqoff(&tp->napi);
6469 * Workqueue context.
6471 static void rtl_slow_event_work(struct rtl8169_private *tp)
6473 struct net_device *dev = tp->dev;
6476 status = rtl_get_events(tp) & tp->event_slow;
6477 rtl_ack_events(tp, status);
6479 if (unlikely(status & RxFIFOOver)) {
6480 switch (tp->mac_version) {
6481 /* Work around for rx fifo overflow */
6482 case RTL_GIGA_MAC_VER_11:
6483 netif_stop_queue(dev);
6484 /* XXX - Hack alert. See rtl_task(). */
6485 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6491 if (unlikely(status & SYSErr))
6492 rtl8169_pcierr_interrupt(dev);
6494 if (status & LinkChg)
6495 phy_mac_interrupt(dev->phydev);
6497 rtl_irq_enable_all(tp);
6500 static void rtl_task(struct work_struct *work)
6502 static const struct {
6504 void (*action)(struct rtl8169_private *);
6506 /* XXX - keep rtl_slow_event_work() as first element. */
6507 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6508 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6510 struct rtl8169_private *tp =
6511 container_of(work, struct rtl8169_private, wk.work);
6512 struct net_device *dev = tp->dev;
6517 if (!netif_running(dev) ||
6518 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6521 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6524 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6526 rtl_work[i].action(tp);
6530 rtl_unlock_work(tp);
6533 static int rtl8169_poll(struct napi_struct *napi, int budget)
6535 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6536 struct net_device *dev = tp->dev;
6537 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6541 status = rtl_get_events(tp);
6542 rtl_ack_events(tp, status & ~tp->event_slow);
6544 if (status & RTL_EVENT_NAPI_RX)
6545 work_done = rtl_rx(dev, tp, (u32) budget);
6547 if (status & RTL_EVENT_NAPI_TX)
6550 if (status & tp->event_slow) {
6551 enable_mask &= ~tp->event_slow;
6553 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6556 if (work_done < budget) {
6557 napi_complete_done(napi, work_done);
6559 rtl_irq_enable(tp, enable_mask);
6566 static void rtl8169_rx_missed(struct net_device *dev)
6568 struct rtl8169_private *tp = netdev_priv(dev);
6570 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6573 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6574 RTL_W32(tp, RxMissed, 0);
6577 static void r8169_phylink_handler(struct net_device *ndev)
6579 struct rtl8169_private *tp = netdev_priv(ndev);
6581 if (netif_carrier_ok(ndev)) {
6582 rtl_link_chg_patch(tp);
6583 pm_request_resume(&tp->pci_dev->dev);
6585 pm_runtime_idle(&tp->pci_dev->dev);
6588 if (net_ratelimit())
6589 phy_print_status(ndev->phydev);
6592 static int r8169_phy_connect(struct rtl8169_private *tp)
6594 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6595 phy_interface_t phy_mode;
6598 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6599 PHY_INTERFACE_MODE_MII;
6601 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6606 if (!tp->supports_gmii)
6607 phy_set_max_speed(phydev, SPEED_100);
6609 /* Ensure to advertise everything, incl. pause */
6610 phydev->advertising = phydev->supported;
6612 phy_attached_info(phydev);
6617 static void rtl8169_down(struct net_device *dev)
6619 struct rtl8169_private *tp = netdev_priv(dev);
6621 phy_stop(dev->phydev);
6623 napi_disable(&tp->napi);
6624 netif_stop_queue(dev);
6626 rtl8169_hw_reset(tp);
6628 * At this point device interrupts can not be enabled in any function,
6629 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6630 * and napi is disabled (rtl8169_poll).
6632 rtl8169_rx_missed(dev);
6634 /* Give a racing hard_start_xmit a few cycles to complete. */
6635 synchronize_sched();
6637 rtl8169_tx_clear(tp);
6639 rtl8169_rx_clear(tp);
6641 rtl_pll_power_down(tp);
6644 static int rtl8169_close(struct net_device *dev)
6646 struct rtl8169_private *tp = netdev_priv(dev);
6647 struct pci_dev *pdev = tp->pci_dev;
6649 pm_runtime_get_sync(&pdev->dev);
6651 /* Update counters before going down */
6652 rtl8169_update_counters(tp);
6655 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6658 rtl_unlock_work(tp);
6660 cancel_work_sync(&tp->wk.work);
6662 phy_disconnect(dev->phydev);
6664 pci_free_irq(pdev, 0, tp);
6666 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6668 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6670 tp->TxDescArray = NULL;
6671 tp->RxDescArray = NULL;
6673 pm_runtime_put_sync(&pdev->dev);
6678 #ifdef CONFIG_NET_POLL_CONTROLLER
6679 static void rtl8169_netpoll(struct net_device *dev)
6681 struct rtl8169_private *tp = netdev_priv(dev);
6683 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6687 static int rtl_open(struct net_device *dev)
6689 struct rtl8169_private *tp = netdev_priv(dev);
6690 struct pci_dev *pdev = tp->pci_dev;
6691 int retval = -ENOMEM;
6693 pm_runtime_get_sync(&pdev->dev);
6696 * Rx and Tx descriptors needs 256 bytes alignment.
6697 * dma_alloc_coherent provides more.
6699 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6700 &tp->TxPhyAddr, GFP_KERNEL);
6701 if (!tp->TxDescArray)
6702 goto err_pm_runtime_put;
6704 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6705 &tp->RxPhyAddr, GFP_KERNEL);
6706 if (!tp->RxDescArray)
6709 retval = rtl8169_init_ring(tp);
6713 INIT_WORK(&tp->wk.work, rtl_task);
6717 rtl_request_firmware(tp);
6719 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6722 goto err_release_fw_2;
6724 retval = r8169_phy_connect(tp);
6730 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6732 napi_enable(&tp->napi);
6734 rtl8169_init_phy(dev, tp);
6736 rtl_pll_power_up(tp);
6740 if (!rtl8169_init_counter_offsets(tp))
6741 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6743 phy_start(dev->phydev);
6744 netif_start_queue(dev);
6746 rtl_unlock_work(tp);
6748 pm_runtime_put_sync(&pdev->dev);
6753 pci_free_irq(pdev, 0, tp);
6755 rtl_release_firmware(tp);
6756 rtl8169_rx_clear(tp);
6758 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6760 tp->RxDescArray = NULL;
6762 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6764 tp->TxDescArray = NULL;
6766 pm_runtime_put_noidle(&pdev->dev);
6771 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6773 struct rtl8169_private *tp = netdev_priv(dev);
6774 struct pci_dev *pdev = tp->pci_dev;
6775 struct rtl8169_counters *counters = tp->counters;
6778 pm_runtime_get_noresume(&pdev->dev);
6780 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6781 rtl8169_rx_missed(dev);
6784 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6785 stats->rx_packets = tp->rx_stats.packets;
6786 stats->rx_bytes = tp->rx_stats.bytes;
6787 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6790 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6791 stats->tx_packets = tp->tx_stats.packets;
6792 stats->tx_bytes = tp->tx_stats.bytes;
6793 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6795 stats->rx_dropped = dev->stats.rx_dropped;
6796 stats->tx_dropped = dev->stats.tx_dropped;
6797 stats->rx_length_errors = dev->stats.rx_length_errors;
6798 stats->rx_errors = dev->stats.rx_errors;
6799 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6800 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6801 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6802 stats->multicast = dev->stats.multicast;
6805 * Fetch additonal counter values missing in stats collected by driver
6806 * from tally counters.
6808 if (pm_runtime_active(&pdev->dev))
6809 rtl8169_update_counters(tp);
6812 * Subtract values fetched during initalization.
6813 * See rtl8169_init_counter_offsets for a description why we do that.
6815 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6816 le64_to_cpu(tp->tc_offset.tx_errors);
6817 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6818 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6819 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6820 le16_to_cpu(tp->tc_offset.tx_aborted);
6822 pm_runtime_put_noidle(&pdev->dev);
6825 static void rtl8169_net_suspend(struct net_device *dev)
6827 struct rtl8169_private *tp = netdev_priv(dev);
6829 if (!netif_running(dev))
6832 phy_stop(dev->phydev);
6833 netif_device_detach(dev);
6834 netif_stop_queue(dev);
6837 napi_disable(&tp->napi);
6838 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6839 rtl_unlock_work(tp);
6841 rtl_pll_power_down(tp);
6846 static int rtl8169_suspend(struct device *device)
6848 struct pci_dev *pdev = to_pci_dev(device);
6849 struct net_device *dev = pci_get_drvdata(pdev);
6851 rtl8169_net_suspend(dev);
6856 static void __rtl8169_resume(struct net_device *dev)
6858 struct rtl8169_private *tp = netdev_priv(dev);
6860 netif_device_attach(dev);
6862 rtl_pll_power_up(tp);
6863 rtl8169_init_phy(dev, tp);
6865 phy_start(tp->dev->phydev);
6868 napi_enable(&tp->napi);
6869 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6870 rtl_unlock_work(tp);
6872 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6875 static int rtl8169_resume(struct device *device)
6877 struct pci_dev *pdev = to_pci_dev(device);
6878 struct net_device *dev = pci_get_drvdata(pdev);
6880 if (netif_running(dev))
6881 __rtl8169_resume(dev);
6886 static int rtl8169_runtime_suspend(struct device *device)
6888 struct pci_dev *pdev = to_pci_dev(device);
6889 struct net_device *dev = pci_get_drvdata(pdev);
6890 struct rtl8169_private *tp = netdev_priv(dev);
6892 if (!tp->TxDescArray)
6896 __rtl8169_set_wol(tp, WAKE_ANY);
6897 rtl_unlock_work(tp);
6899 rtl8169_net_suspend(dev);
6901 /* Update counters before going runtime suspend */
6902 rtl8169_rx_missed(dev);
6903 rtl8169_update_counters(tp);
6908 static int rtl8169_runtime_resume(struct device *device)
6910 struct pci_dev *pdev = to_pci_dev(device);
6911 struct net_device *dev = pci_get_drvdata(pdev);
6912 struct rtl8169_private *tp = netdev_priv(dev);
6913 rtl_rar_set(tp, dev->dev_addr);
6915 if (!tp->TxDescArray)
6919 __rtl8169_set_wol(tp, tp->saved_wolopts);
6920 rtl_unlock_work(tp);
6922 __rtl8169_resume(dev);
6927 static int rtl8169_runtime_idle(struct device *device)
6929 struct pci_dev *pdev = to_pci_dev(device);
6930 struct net_device *dev = pci_get_drvdata(pdev);
6932 if (!netif_running(dev) || !netif_carrier_ok(dev))
6933 pm_schedule_suspend(device, 10000);
6938 static const struct dev_pm_ops rtl8169_pm_ops = {
6939 .suspend = rtl8169_suspend,
6940 .resume = rtl8169_resume,
6941 .freeze = rtl8169_suspend,
6942 .thaw = rtl8169_resume,
6943 .poweroff = rtl8169_suspend,
6944 .restore = rtl8169_resume,
6945 .runtime_suspend = rtl8169_runtime_suspend,
6946 .runtime_resume = rtl8169_runtime_resume,
6947 .runtime_idle = rtl8169_runtime_idle,
6950 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6952 #else /* !CONFIG_PM */
6954 #define RTL8169_PM_OPS NULL
6956 #endif /* !CONFIG_PM */
6958 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6960 /* WoL fails with 8168b when the receiver is disabled. */
6961 switch (tp->mac_version) {
6962 case RTL_GIGA_MAC_VER_11:
6963 case RTL_GIGA_MAC_VER_12:
6964 case RTL_GIGA_MAC_VER_17:
6965 pci_clear_master(tp->pci_dev);
6967 RTL_W8(tp, ChipCmd, CmdRxEnb);
6969 RTL_R8(tp, ChipCmd);
6976 static void rtl_shutdown(struct pci_dev *pdev)
6978 struct net_device *dev = pci_get_drvdata(pdev);
6979 struct rtl8169_private *tp = netdev_priv(dev);
6981 rtl8169_net_suspend(dev);
6983 /* Restore original MAC address */
6984 rtl_rar_set(tp, dev->perm_addr);
6986 rtl8169_hw_reset(tp);
6988 if (system_state == SYSTEM_POWER_OFF) {
6989 if (tp->saved_wolopts) {
6990 rtl_wol_suspend_quirk(tp);
6991 rtl_wol_shutdown_quirk(tp);
6994 pci_wake_from_d3(pdev, true);
6995 pci_set_power_state(pdev, PCI_D3hot);
6999 static void rtl_remove_one(struct pci_dev *pdev)
7001 struct net_device *dev = pci_get_drvdata(pdev);
7002 struct rtl8169_private *tp = netdev_priv(dev);
7004 if (r8168_check_dash(tp))
7005 rtl8168_driver_stop(tp);
7007 netif_napi_del(&tp->napi);
7009 unregister_netdev(dev);
7010 mdiobus_unregister(tp->mii_bus);
7012 rtl_release_firmware(tp);
7014 if (pci_dev_run_wake(pdev))
7015 pm_runtime_get_noresume(&pdev->dev);
7017 /* restore original MAC address */
7018 rtl_rar_set(tp, dev->perm_addr);
7021 static const struct net_device_ops rtl_netdev_ops = {
7022 .ndo_open = rtl_open,
7023 .ndo_stop = rtl8169_close,
7024 .ndo_get_stats64 = rtl8169_get_stats64,
7025 .ndo_start_xmit = rtl8169_start_xmit,
7026 .ndo_tx_timeout = rtl8169_tx_timeout,
7027 .ndo_validate_addr = eth_validate_addr,
7028 .ndo_change_mtu = rtl8169_change_mtu,
7029 .ndo_fix_features = rtl8169_fix_features,
7030 .ndo_set_features = rtl8169_set_features,
7031 .ndo_set_mac_address = rtl_set_mac_address,
7032 .ndo_do_ioctl = rtl8169_ioctl,
7033 .ndo_set_rx_mode = rtl_set_rx_mode,
7034 #ifdef CONFIG_NET_POLL_CONTROLLER
7035 .ndo_poll_controller = rtl8169_netpoll,
7040 static const struct rtl_cfg_info {
7041 void (*hw_start)(struct rtl8169_private *tp);
7043 unsigned int has_gmii:1;
7044 const struct rtl_coalesce_info *coalesce_info;
7046 } rtl_cfg_infos [] = {
7048 .hw_start = rtl_hw_start_8169,
7049 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7051 .coalesce_info = rtl_coalesce_info_8169,
7052 .default_ver = RTL_GIGA_MAC_VER_01,
7055 .hw_start = rtl_hw_start_8168,
7056 .event_slow = SYSErr | LinkChg | RxOverflow,
7058 .coalesce_info = rtl_coalesce_info_8168_8136,
7059 .default_ver = RTL_GIGA_MAC_VER_11,
7062 .hw_start = rtl_hw_start_8101,
7063 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7065 .coalesce_info = rtl_coalesce_info_8168_8136,
7066 .default_ver = RTL_GIGA_MAC_VER_13,
7070 static int rtl_alloc_irq(struct rtl8169_private *tp)
7074 switch (tp->mac_version) {
7075 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7076 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7077 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7078 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7079 flags = PCI_IRQ_LEGACY;
7081 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_40:
7082 /* This version was reported to have issues with resume
7083 * from suspend when using MSI-X
7085 flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
7088 flags = PCI_IRQ_ALL_TYPES;
7091 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7094 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7096 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7099 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7101 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7104 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7106 struct rtl8169_private *tp = mii_bus->priv;
7111 return rtl_readphy(tp, phyreg);
7114 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7115 int phyreg, u16 val)
7117 struct rtl8169_private *tp = mii_bus->priv;
7122 rtl_writephy(tp, phyreg, val);
7127 static int r8169_mdio_register(struct rtl8169_private *tp)
7129 struct pci_dev *pdev = tp->pci_dev;
7130 struct phy_device *phydev;
7131 struct mii_bus *new_bus;
7134 new_bus = devm_mdiobus_alloc(&pdev->dev);
7138 new_bus->name = "r8169";
7140 new_bus->parent = &pdev->dev;
7141 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7142 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7143 PCI_DEVID(pdev->bus->number, pdev->devfn));
7145 new_bus->read = r8169_mdio_read_reg;
7146 new_bus->write = r8169_mdio_write_reg;
7148 ret = mdiobus_register(new_bus);
7152 phydev = mdiobus_get_phy(new_bus, 0);
7154 mdiobus_unregister(new_bus);
7158 /* PHY will be woken up in rtl_open() */
7159 phy_suspend(phydev);
7161 tp->mii_bus = new_bus;
7166 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7170 tp->ocp_base = OCP_STD_PHY_BASE;
7172 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7174 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7177 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7180 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7182 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7184 data = r8168_mac_ocp_read(tp, 0xe8de);
7186 r8168_mac_ocp_write(tp, 0xe8de, data);
7188 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7191 data = r8168_mac_ocp_read(tp, 0xe8de);
7193 r8168_mac_ocp_write(tp, 0xe8de, data);
7195 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7199 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7201 rtl8168ep_stop_cmac(tp);
7202 rtl_hw_init_8168g(tp);
7205 static void rtl_hw_initialize(struct rtl8169_private *tp)
7207 switch (tp->mac_version) {
7208 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7209 rtl_hw_init_8168g(tp);
7211 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7212 rtl_hw_init_8168ep(tp);
7219 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7220 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7222 switch (tp->mac_version) {
7223 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7224 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7231 static int rtl_jumbo_max(struct rtl8169_private *tp)
7233 /* Non-GBit versions don't support jumbo frames */
7234 if (!tp->supports_gmii)
7237 switch (tp->mac_version) {
7239 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7242 case RTL_GIGA_MAC_VER_11:
7243 case RTL_GIGA_MAC_VER_12:
7244 case RTL_GIGA_MAC_VER_17:
7247 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7254 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7256 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7257 struct rtl8169_private *tp;
7258 struct net_device *dev;
7259 int chipset, region, i;
7262 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7266 SET_NETDEV_DEV(dev, &pdev->dev);
7267 dev->netdev_ops = &rtl_netdev_ops;
7268 tp = netdev_priv(dev);
7271 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7272 tp->supports_gmii = cfg->has_gmii;
7274 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7275 rc = pcim_enable_device(pdev);
7277 dev_err(&pdev->dev, "enable failure\n");
7281 if (pcim_set_mwi(pdev) < 0)
7282 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7284 /* use first MMIO region */
7285 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7287 dev_err(&pdev->dev, "no MMIO resource found\n");
7291 /* check for weird/broken PCI region reporting */
7292 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7293 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7297 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7299 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7303 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7305 if (!pci_is_pcie(pdev))
7306 dev_info(&pdev->dev, "not PCI Express\n");
7308 /* Identify chip attached to board */
7309 rtl8169_get_mac_version(tp, cfg->default_ver);
7311 if (rtl_tbi_enabled(tp)) {
7312 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7316 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7318 if ((sizeof(dma_addr_t) > 4) &&
7319 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7320 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7321 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7322 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7324 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7325 if (!pci_is_pcie(pdev))
7326 tp->cp_cmd |= PCIDAC;
7327 dev->features |= NETIF_F_HIGHDMA;
7329 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7331 dev_err(&pdev->dev, "DMA configuration failed\n");
7338 rtl_irq_disable(tp);
7340 rtl_hw_initialize(tp);
7344 rtl_ack_events(tp, 0xffff);
7346 pci_set_master(pdev);
7348 rtl_init_mdio_ops(tp);
7349 rtl_init_jumbo_ops(tp);
7351 rtl8169_print_mac_version(tp);
7353 chipset = tp->mac_version;
7355 rc = rtl_alloc_irq(tp);
7357 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7361 tp->saved_wolopts = __rtl8169_get_wol(tp);
7363 mutex_init(&tp->wk.mutex);
7364 u64_stats_init(&tp->rx_stats.syncp);
7365 u64_stats_init(&tp->tx_stats.syncp);
7367 /* Get MAC address */
7368 switch (tp->mac_version) {
7369 u8 mac_addr[ETH_ALEN] __aligned(4);
7370 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7371 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7372 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7373 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7375 if (is_valid_ether_addr(mac_addr))
7376 rtl_rar_set(tp, mac_addr);
7381 for (i = 0; i < ETH_ALEN; i++)
7382 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7384 dev->ethtool_ops = &rtl8169_ethtool_ops;
7385 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7387 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7389 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7390 * properly for all devices */
7391 dev->features |= NETIF_F_RXCSUM |
7392 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7394 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7395 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7396 NETIF_F_HW_VLAN_CTAG_RX;
7397 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7399 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7401 tp->cp_cmd |= RxChkSum | RxVlan;
7404 * Pretend we are using VLANs; This bypasses a nasty bug where
7405 * Interrupts stop flowing on high load on 8110SCd controllers.
7407 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7408 /* Disallow toggling */
7409 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7411 if (rtl_chip_supports_csum_v2(tp)) {
7412 tp->tso_csum = rtl8169_tso_csum_v2;
7413 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7415 tp->tso_csum = rtl8169_tso_csum_v1;
7418 dev->hw_features |= NETIF_F_RXALL;
7419 dev->hw_features |= NETIF_F_RXFCS;
7421 /* MTU range: 60 - hw-specific max */
7422 dev->min_mtu = ETH_ZLEN;
7423 jumbo_max = rtl_jumbo_max(tp);
7424 dev->max_mtu = jumbo_max;
7426 tp->hw_start = cfg->hw_start;
7427 tp->event_slow = cfg->event_slow;
7428 tp->coalesce_info = cfg->coalesce_info;
7430 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7432 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7433 &tp->counters_phys_addr,
7438 pci_set_drvdata(pdev, dev);
7440 rc = r8169_mdio_register(tp);
7444 /* chip gets powered up in rtl_open() */
7445 rtl_pll_power_down(tp);
7447 rc = register_netdev(dev);
7449 goto err_mdio_unregister;
7451 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7452 rtl_chip_infos[chipset].name, dev->dev_addr,
7453 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7454 pci_irq_vector(pdev, 0));
7456 if (jumbo_max > JUMBO_1K)
7457 netif_info(tp, probe, dev,
7458 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7459 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7462 if (r8168_check_dash(tp))
7463 rtl8168_driver_start(tp);
7465 if (pci_dev_run_wake(pdev))
7466 pm_runtime_put_sync(&pdev->dev);
7470 err_mdio_unregister:
7471 mdiobus_unregister(tp->mii_bus);
7475 static struct pci_driver rtl8169_pci_driver = {
7477 .id_table = rtl8169_pci_tbl,
7478 .probe = rtl_init_one,
7479 .remove = rtl_remove_one,
7480 .shutdown = rtl_shutdown,
7481 .driver.pm = RTL8169_PM_OPS,
7484 module_pci_driver(rtl8169_pci_driver);