2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/if_vlan.h>
37 #include <linux/skbuff.h>
38 #include <linux/delay.h>
40 #include <linux/vmalloc.h>
41 #include <linux/prefetch.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
54 static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER | */
61 /* NETIF_MSG_TX_QUEUED | */
62 /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
66 static int debug = -1; /* defaults above */
67 module_param(debug, int, 0664);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static int qlge_irq_type = MSIX_IRQ;
74 module_param(qlge_irq_type, int, 0664);
75 MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static int qlge_mpi_coredump;
78 module_param(qlge_mpi_coredump, int, 0);
79 MODULE_PARM_DESC(qlge_mpi_coredump,
80 "Option to enable MPI firmware dump. "
81 "Default is OFF - Do Not allocate memory. ");
83 static int qlge_force_coredump;
84 module_param(qlge_force_coredump, int, 0);
85 MODULE_PARM_DESC(qlge_force_coredump,
86 "Option to allow force of firmware core dump. "
87 "Default is OFF - Do not allow.");
89 static const struct pci_device_id qlge_pci_tbl[] = {
90 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
91 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
92 /* required last entry */
96 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
98 static int ql_wol(struct ql_adapter *);
99 static void qlge_set_multicast_list(struct net_device *);
100 static int ql_adapter_down(struct ql_adapter *);
101 static int ql_adapter_up(struct ql_adapter *);
103 /* This hardware semaphore causes exclusive access to
104 * resources shared between the NIC driver, MPI firmware,
105 * FCOE firmware and the FC driver.
107 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
112 case SEM_XGMAC0_MASK:
113 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
115 case SEM_XGMAC1_MASK:
116 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
119 sem_bits = SEM_SET << SEM_ICB_SHIFT;
121 case SEM_MAC_ADDR_MASK:
122 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
125 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
128 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
130 case SEM_RT_IDX_MASK:
131 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
133 case SEM_PROC_REG_MASK:
134 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
137 netif_alert(qdev, probe, qdev->ndev, "bad Semaphore mask!.\n");
141 ql_write32(qdev, SEM, sem_bits | sem_mask);
142 return !(ql_read32(qdev, SEM) & sem_bits);
145 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
147 unsigned int wait_count = 30;
149 if (!ql_sem_trylock(qdev, sem_mask))
152 } while (--wait_count);
156 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
158 ql_write32(qdev, SEM, sem_mask);
159 ql_read32(qdev, SEM); /* flush */
162 /* This function waits for a specific bit to come ready
163 * in a given register. It is used mostly by the initialize
164 * process, but is also used in kernel thread API such as
165 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
167 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
170 int count = UDELAY_COUNT;
173 temp = ql_read32(qdev, reg);
175 /* check for errors */
176 if (temp & err_bit) {
177 netif_alert(qdev, probe, qdev->ndev,
178 "register 0x%.08x access error, value = 0x%.08x!.\n",
181 } else if (temp & bit)
183 udelay(UDELAY_DELAY);
186 netif_alert(qdev, probe, qdev->ndev,
187 "Timed out waiting for reg %x to come ready.\n", reg);
191 /* The CFG register is used to download TX and RX control blocks
192 * to the chip. This function waits for an operation to complete.
194 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
196 int count = UDELAY_COUNT;
200 temp = ql_read32(qdev, CFG);
205 udelay(UDELAY_DELAY);
212 /* Used to issue init control blocks to hw. Maps control block,
213 * sets address, triggers download, waits for completion.
215 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
225 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
228 map = pci_map_single(qdev->pdev, ptr, size, direction);
229 if (pci_dma_mapping_error(qdev->pdev, map)) {
230 netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n");
234 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
238 status = ql_wait_cfg(qdev, bit);
240 netif_err(qdev, ifup, qdev->ndev,
241 "Timed out waiting for CFG to come ready.\n");
245 ql_write32(qdev, ICB_L, (u32) map);
246 ql_write32(qdev, ICB_H, (u32) (map >> 32));
248 mask = CFG_Q_MASK | (bit << 16);
249 value = bit | (q_id << CFG_Q_SHIFT);
250 ql_write32(qdev, CFG, (mask | value));
253 * Wait for the bit to clear after signaling hw.
255 status = ql_wait_cfg(qdev, bit);
257 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
258 pci_unmap_single(qdev->pdev, map, size, direction);
262 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
263 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
270 case MAC_ADDR_TYPE_MULTI_MAC:
271 case MAC_ADDR_TYPE_CAM_MAC:
274 ql_wait_reg_rdy(qdev,
275 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
278 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
279 (index << MAC_ADDR_IDX_SHIFT) | /* index */
280 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
282 ql_wait_reg_rdy(qdev,
283 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
286 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
288 ql_wait_reg_rdy(qdev,
289 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
292 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
293 (index << MAC_ADDR_IDX_SHIFT) | /* index */
294 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
296 ql_wait_reg_rdy(qdev,
297 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
300 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
301 if (type == MAC_ADDR_TYPE_CAM_MAC) {
303 ql_wait_reg_rdy(qdev,
304 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
307 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
308 (index << MAC_ADDR_IDX_SHIFT) | /* index */
309 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
311 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
315 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
319 case MAC_ADDR_TYPE_VLAN:
320 case MAC_ADDR_TYPE_MULTI_FLTR:
322 netif_crit(qdev, ifup, qdev->ndev,
323 "Address type %d not yet supported.\n", type);
330 /* Set up a MAC, multicast or VLAN address for the
331 * inbound frame matching.
333 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
340 case MAC_ADDR_TYPE_MULTI_MAC:
342 u32 upper = (addr[0] << 8) | addr[1];
343 u32 lower = (addr[2] << 24) | (addr[3] << 16) |
344 (addr[4] << 8) | (addr[5]);
347 ql_wait_reg_rdy(qdev,
348 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
351 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
352 (index << MAC_ADDR_IDX_SHIFT) |
354 ql_write32(qdev, MAC_ADDR_DATA, lower);
356 ql_wait_reg_rdy(qdev,
357 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
360 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
361 (index << MAC_ADDR_IDX_SHIFT) |
364 ql_write32(qdev, MAC_ADDR_DATA, upper);
366 ql_wait_reg_rdy(qdev,
367 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
372 case MAC_ADDR_TYPE_CAM_MAC:
375 u32 upper = (addr[0] << 8) | addr[1];
377 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
380 ql_wait_reg_rdy(qdev,
381 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
384 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
385 (index << MAC_ADDR_IDX_SHIFT) | /* index */
387 ql_write32(qdev, MAC_ADDR_DATA, lower);
389 ql_wait_reg_rdy(qdev,
390 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
393 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
394 (index << MAC_ADDR_IDX_SHIFT) | /* index */
396 ql_write32(qdev, MAC_ADDR_DATA, upper);
398 ql_wait_reg_rdy(qdev,
399 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
402 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
403 (index << MAC_ADDR_IDX_SHIFT) | /* index */
405 /* This field should also include the queue id
406 and possibly the function id. Right now we hardcode
407 the route field to NIC core.
409 cam_output = (CAM_OUT_ROUTE_NIC |
411 func << CAM_OUT_FUNC_SHIFT) |
412 (0 << CAM_OUT_CQ_ID_SHIFT));
413 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
414 cam_output |= CAM_OUT_RV;
415 /* route to NIC core */
416 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
419 case MAC_ADDR_TYPE_VLAN:
421 u32 enable_bit = *((u32 *) &addr[0]);
422 /* For VLAN, the addr actually holds a bit that
423 * either enables or disables the vlan id we are
424 * addressing. It's either MAC_ADDR_E on or off.
425 * That's bit-27 we're talking about.
428 ql_wait_reg_rdy(qdev,
429 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
432 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
433 (index << MAC_ADDR_IDX_SHIFT) | /* index */
435 enable_bit); /* enable/disable */
438 case MAC_ADDR_TYPE_MULTI_FLTR:
440 netif_crit(qdev, ifup, qdev->ndev,
441 "Address type %d not yet supported.\n", type);
448 /* Set or clear MAC address in hardware. We sometimes
449 * have to clear it to prevent wrong frame routing
450 * especially in a bonding environment.
452 static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
455 char zero_mac_addr[ETH_ALEN];
459 addr = &qdev->current_mac_addr[0];
460 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
461 "Set Mac addr %pM\n", addr);
463 eth_zero_addr(zero_mac_addr);
464 addr = &zero_mac_addr[0];
465 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
466 "Clearing MAC address\n");
468 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
471 status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
472 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
473 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
475 netif_err(qdev, ifup, qdev->ndev,
476 "Failed to init mac address.\n");
480 void ql_link_on(struct ql_adapter *qdev)
482 netif_err(qdev, link, qdev->ndev, "Link is up.\n");
483 netif_carrier_on(qdev->ndev);
484 ql_set_mac_addr(qdev, 1);
487 void ql_link_off(struct ql_adapter *qdev)
489 netif_err(qdev, link, qdev->ndev, "Link is down.\n");
490 netif_carrier_off(qdev->ndev);
491 ql_set_mac_addr(qdev, 0);
494 /* Get a specific frame routing value from the CAM.
495 * Used for debug and reg dump.
497 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
501 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
505 ql_write32(qdev, RT_IDX,
506 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
507 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
510 *value = ql_read32(qdev, RT_DATA);
515 /* The NIC function for this chip has 16 routing indexes. Each one can be used
516 * to route different frame types to various inbound queues. We send broadcast/
517 * multicast/error frames to the default queue for slow handling,
518 * and CAM hit/RSS frames to the fast handling queues.
520 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
523 int status = -EINVAL; /* Return error if no mask match. */
529 value = RT_IDX_DST_CAM_Q | /* dest */
530 RT_IDX_TYPE_NICQ | /* type */
531 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
534 case RT_IDX_VALID: /* Promiscuous Mode frames. */
536 value = RT_IDX_DST_DFLT_Q | /* dest */
537 RT_IDX_TYPE_NICQ | /* type */
538 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
541 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
543 value = RT_IDX_DST_DFLT_Q | /* dest */
544 RT_IDX_TYPE_NICQ | /* type */
545 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
548 case RT_IDX_IP_CSUM_ERR: /* Pass up IP CSUM error frames. */
550 value = RT_IDX_DST_DFLT_Q | /* dest */
551 RT_IDX_TYPE_NICQ | /* type */
552 (RT_IDX_IP_CSUM_ERR_SLOT <<
553 RT_IDX_IDX_SHIFT); /* index */
556 case RT_IDX_TU_CSUM_ERR: /* Pass up TCP/UDP CSUM error frames. */
558 value = RT_IDX_DST_DFLT_Q | /* dest */
559 RT_IDX_TYPE_NICQ | /* type */
560 (RT_IDX_TCP_UDP_CSUM_ERR_SLOT <<
561 RT_IDX_IDX_SHIFT); /* index */
564 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
566 value = RT_IDX_DST_DFLT_Q | /* dest */
567 RT_IDX_TYPE_NICQ | /* type */
568 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
571 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
573 value = RT_IDX_DST_DFLT_Q | /* dest */
574 RT_IDX_TYPE_NICQ | /* type */
575 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
578 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
580 value = RT_IDX_DST_DFLT_Q | /* dest */
581 RT_IDX_TYPE_NICQ | /* type */
582 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
585 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
587 value = RT_IDX_DST_RSS | /* dest */
588 RT_IDX_TYPE_NICQ | /* type */
589 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
592 case 0: /* Clear the E-bit on an entry. */
594 value = RT_IDX_DST_DFLT_Q | /* dest */
595 RT_IDX_TYPE_NICQ | /* type */
596 (index << RT_IDX_IDX_SHIFT);/* index */
600 netif_err(qdev, ifup, qdev->ndev,
601 "Mask type %d not yet supported.\n", mask);
607 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
610 value |= (enable ? RT_IDX_E : 0);
611 ql_write32(qdev, RT_IDX, value);
612 ql_write32(qdev, RT_DATA, enable ? mask : 0);
618 static void ql_enable_interrupts(struct ql_adapter *qdev)
620 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
623 static void ql_disable_interrupts(struct ql_adapter *qdev)
625 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
628 /* If we're running with multiple MSI-X vectors then we enable on the fly.
629 * Otherwise, we may have multiple outstanding workers and don't want to
630 * enable until the last one finishes. In this case, the irq_cnt gets
631 * incremented every time we queue a worker and decremented every time
632 * a worker finishes. Once it hits zero we enable the interrupt.
634 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
637 unsigned long hw_flags = 0;
638 struct intr_context *ctx = qdev->intr_context + intr;
640 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
641 /* Always enable if we're MSIX multi interrupts and
642 * it's not the default (zeroeth) interrupt.
644 ql_write32(qdev, INTR_EN,
646 var = ql_read32(qdev, STS);
650 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
651 if (atomic_dec_and_test(&ctx->irq_cnt)) {
652 ql_write32(qdev, INTR_EN,
654 var = ql_read32(qdev, STS);
656 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
660 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
663 struct intr_context *ctx;
665 /* HW disables for us if we're MSIX multi interrupts and
666 * it's not the default (zeroeth) interrupt.
668 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
671 ctx = qdev->intr_context + intr;
672 spin_lock(&qdev->hw_lock);
673 if (!atomic_read(&ctx->irq_cnt)) {
674 ql_write32(qdev, INTR_EN,
676 var = ql_read32(qdev, STS);
678 atomic_inc(&ctx->irq_cnt);
679 spin_unlock(&qdev->hw_lock);
683 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
686 for (i = 0; i < qdev->intr_count; i++) {
687 /* The enable call does a atomic_dec_and_test
688 * and enables only if the result is zero.
689 * So we precharge it here.
691 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
693 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
694 ql_enable_completion_interrupt(qdev, i);
699 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
703 __le16 *flash = (__le16 *)&qdev->flash;
705 status = strncmp((char *)&qdev->flash, str, 4);
707 netif_err(qdev, ifup, qdev->ndev, "Invalid flash signature.\n");
711 for (i = 0; i < size; i++)
712 csum += le16_to_cpu(*flash++);
715 netif_err(qdev, ifup, qdev->ndev,
716 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
721 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
724 /* wait for reg to come ready */
725 status = ql_wait_reg_rdy(qdev,
726 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
729 /* set up for reg read */
730 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
731 /* wait for reg to come ready */
732 status = ql_wait_reg_rdy(qdev,
733 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
736 /* This data is stored on flash as an array of
737 * __le32. Since ql_read32() returns cpu endian
738 * we need to swap it back.
740 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
745 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
749 __le32 *p = (__le32 *)&qdev->flash;
753 /* Get flash offset for function and adjust
757 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
759 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
761 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
764 size = sizeof(struct flash_params_8000) / sizeof(u32);
765 for (i = 0; i < size; i++, p++) {
766 status = ql_read_flash_word(qdev, i+offset, p);
768 netif_err(qdev, ifup, qdev->ndev,
769 "Error reading flash.\n");
774 status = ql_validate_flash(qdev,
775 sizeof(struct flash_params_8000) / sizeof(u16),
778 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
783 /* Extract either manufacturer or BOFM modified
786 if (qdev->flash.flash_params_8000.data_type1 == 2)
788 qdev->flash.flash_params_8000.mac_addr1,
789 qdev->ndev->addr_len);
792 qdev->flash.flash_params_8000.mac_addr,
793 qdev->ndev->addr_len);
795 if (!is_valid_ether_addr(mac_addr)) {
796 netif_err(qdev, ifup, qdev->ndev, "Invalid MAC address.\n");
801 memcpy(qdev->ndev->dev_addr,
803 qdev->ndev->addr_len);
806 ql_sem_unlock(qdev, SEM_FLASH_MASK);
810 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
814 __le32 *p = (__le32 *)&qdev->flash;
816 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
818 /* Second function's parameters follow the first
824 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
827 for (i = 0; i < size; i++, p++) {
828 status = ql_read_flash_word(qdev, i+offset, p);
830 netif_err(qdev, ifup, qdev->ndev,
831 "Error reading flash.\n");
837 status = ql_validate_flash(qdev,
838 sizeof(struct flash_params_8012) / sizeof(u16),
841 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
846 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
851 memcpy(qdev->ndev->dev_addr,
852 qdev->flash.flash_params_8012.mac_addr,
853 qdev->ndev->addr_len);
856 ql_sem_unlock(qdev, SEM_FLASH_MASK);
860 /* xgmac register are located behind the xgmac_addr and xgmac_data
861 * register pair. Each read/write requires us to wait for the ready
862 * bit before reading/writing the data.
864 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
867 /* wait for reg to come ready */
868 status = ql_wait_reg_rdy(qdev,
869 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
872 /* write the data to the data reg */
873 ql_write32(qdev, XGMAC_DATA, data);
874 /* trigger the write */
875 ql_write32(qdev, XGMAC_ADDR, reg);
879 /* xgmac register are located behind the xgmac_addr and xgmac_data
880 * register pair. Each read/write requires us to wait for the ready
881 * bit before reading/writing the data.
883 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
886 /* wait for reg to come ready */
887 status = ql_wait_reg_rdy(qdev,
888 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
891 /* set up for reg read */
892 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
893 /* wait for reg to come ready */
894 status = ql_wait_reg_rdy(qdev,
895 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
899 *data = ql_read32(qdev, XGMAC_DATA);
904 /* This is used for reading the 64-bit statistics regs. */
905 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
911 status = ql_read_xgmac_reg(qdev, reg, &lo);
915 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
919 *data = (u64) lo | ((u64) hi << 32);
925 static int ql_8000_port_initialize(struct ql_adapter *qdev)
929 * Get MPI firmware version for driver banner
932 status = ql_mb_about_fw(qdev);
935 status = ql_mb_get_fw_state(qdev);
938 /* Wake up a worker to get/set the TX/RX frame sizes. */
939 queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
944 /* Take the MAC Core out of reset.
945 * Enable statistics counting.
946 * Take the transmitter/receiver out of reset.
947 * This functionality may be done in the MPI firmware at a
950 static int ql_8012_port_initialize(struct ql_adapter *qdev)
955 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
956 /* Another function has the semaphore, so
957 * wait for the port init bit to come ready.
959 netif_info(qdev, link, qdev->ndev,
960 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
961 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
963 netif_crit(qdev, link, qdev->ndev,
964 "Port initialize timed out.\n");
969 netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n");
970 /* Set the core reset. */
971 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
974 data |= GLOBAL_CFG_RESET;
975 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
979 /* Clear the core reset and turn on jumbo for receiver. */
980 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
981 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
982 data |= GLOBAL_CFG_TX_STAT_EN;
983 data |= GLOBAL_CFG_RX_STAT_EN;
984 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
988 /* Enable transmitter, and clear it's reset. */
989 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
992 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
993 data |= TX_CFG_EN; /* Enable the transmitter. */
994 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
998 /* Enable receiver and clear it's reset. */
999 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
1002 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
1003 data |= RX_CFG_EN; /* Enable the receiver. */
1004 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
1008 /* Turn on jumbo. */
1010 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
1014 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
1018 /* Signal to the world that the port is enabled. */
1019 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
1021 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1025 static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev)
1027 return PAGE_SIZE << qdev->lbq_buf_order;
1030 /* Get the next large buffer. */
1031 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
1033 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1034 rx_ring->lbq_curr_idx++;
1035 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1036 rx_ring->lbq_curr_idx = 0;
1037 rx_ring->lbq_free_cnt++;
1041 static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev,
1042 struct rx_ring *rx_ring)
1044 struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring);
1046 pci_dma_sync_single_for_cpu(qdev->pdev,
1047 dma_unmap_addr(lbq_desc, mapaddr),
1048 rx_ring->lbq_buf_size,
1049 PCI_DMA_FROMDEVICE);
1051 /* If it's the last chunk of our master page then
1054 if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size)
1055 == ql_lbq_block_size(qdev))
1056 pci_unmap_page(qdev->pdev,
1057 lbq_desc->p.pg_chunk.map,
1058 ql_lbq_block_size(qdev),
1059 PCI_DMA_FROMDEVICE);
1063 /* Get the next small buffer. */
1064 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
1066 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1067 rx_ring->sbq_curr_idx++;
1068 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1069 rx_ring->sbq_curr_idx = 0;
1070 rx_ring->sbq_free_cnt++;
1074 /* Update an rx ring index. */
1075 static void ql_update_cq(struct rx_ring *rx_ring)
1077 rx_ring->cnsmr_idx++;
1078 rx_ring->curr_entry++;
1079 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1080 rx_ring->cnsmr_idx = 0;
1081 rx_ring->curr_entry = rx_ring->cq_base;
1085 static void ql_write_cq_idx(struct rx_ring *rx_ring)
1087 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1090 static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring,
1091 struct bq_desc *lbq_desc)
1093 if (!rx_ring->pg_chunk.page) {
1095 rx_ring->pg_chunk.page = alloc_pages(__GFP_COMP | GFP_ATOMIC,
1096 qdev->lbq_buf_order);
1097 if (unlikely(!rx_ring->pg_chunk.page)) {
1098 netif_err(qdev, drv, qdev->ndev,
1099 "page allocation failed.\n");
1102 rx_ring->pg_chunk.offset = 0;
1103 map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page,
1104 0, ql_lbq_block_size(qdev),
1105 PCI_DMA_FROMDEVICE);
1106 if (pci_dma_mapping_error(qdev->pdev, map)) {
1107 __free_pages(rx_ring->pg_chunk.page,
1108 qdev->lbq_buf_order);
1109 rx_ring->pg_chunk.page = NULL;
1110 netif_err(qdev, drv, qdev->ndev,
1111 "PCI mapping failed.\n");
1114 rx_ring->pg_chunk.map = map;
1115 rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page);
1118 /* Copy the current master pg_chunk info
1119 * to the current descriptor.
1121 lbq_desc->p.pg_chunk = rx_ring->pg_chunk;
1123 /* Adjust the master page chunk for next
1126 rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size;
1127 if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) {
1128 rx_ring->pg_chunk.page = NULL;
1129 lbq_desc->p.pg_chunk.last_flag = 1;
1131 rx_ring->pg_chunk.va += rx_ring->lbq_buf_size;
1132 get_page(rx_ring->pg_chunk.page);
1133 lbq_desc->p.pg_chunk.last_flag = 0;
1137 /* Process (refill) a large buffer queue. */
1138 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1140 u32 clean_idx = rx_ring->lbq_clean_idx;
1141 u32 start_idx = clean_idx;
1142 struct bq_desc *lbq_desc;
1146 while (rx_ring->lbq_free_cnt > 32) {
1147 for (i = (rx_ring->lbq_clean_idx % 16); i < 16; i++) {
1148 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1149 "lbq: try cleaning clean_idx = %d.\n",
1151 lbq_desc = &rx_ring->lbq[clean_idx];
1152 if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) {
1153 rx_ring->lbq_clean_idx = clean_idx;
1154 netif_err(qdev, ifup, qdev->ndev,
1155 "Could not get a page chunk, i=%d, clean_idx =%d .\n",
1160 map = lbq_desc->p.pg_chunk.map +
1161 lbq_desc->p.pg_chunk.offset;
1162 dma_unmap_addr_set(lbq_desc, mapaddr, map);
1163 dma_unmap_len_set(lbq_desc, maplen,
1164 rx_ring->lbq_buf_size);
1165 *lbq_desc->addr = cpu_to_le64(map);
1167 pci_dma_sync_single_for_device(qdev->pdev, map,
1168 rx_ring->lbq_buf_size,
1169 PCI_DMA_FROMDEVICE);
1171 if (clean_idx == rx_ring->lbq_len)
1175 rx_ring->lbq_clean_idx = clean_idx;
1176 rx_ring->lbq_prod_idx += 16;
1177 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1178 rx_ring->lbq_prod_idx = 0;
1179 rx_ring->lbq_free_cnt -= 16;
1182 if (start_idx != clean_idx) {
1183 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1184 "lbq: updating prod idx = %d.\n",
1185 rx_ring->lbq_prod_idx);
1186 ql_write_db_reg(rx_ring->lbq_prod_idx,
1187 rx_ring->lbq_prod_idx_db_reg);
1191 /* Process (refill) a small buffer queue. */
1192 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1194 u32 clean_idx = rx_ring->sbq_clean_idx;
1195 u32 start_idx = clean_idx;
1196 struct bq_desc *sbq_desc;
1200 while (rx_ring->sbq_free_cnt > 16) {
1201 for (i = (rx_ring->sbq_clean_idx % 16); i < 16; i++) {
1202 sbq_desc = &rx_ring->sbq[clean_idx];
1203 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1204 "sbq: try cleaning clean_idx = %d.\n",
1206 if (sbq_desc->p.skb == NULL) {
1207 netif_printk(qdev, rx_status, KERN_DEBUG,
1209 "sbq: getting new skb for index %d.\n",
1212 netdev_alloc_skb(qdev->ndev,
1214 if (sbq_desc->p.skb == NULL) {
1215 rx_ring->sbq_clean_idx = clean_idx;
1218 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1219 map = pci_map_single(qdev->pdev,
1220 sbq_desc->p.skb->data,
1221 rx_ring->sbq_buf_size,
1222 PCI_DMA_FROMDEVICE);
1223 if (pci_dma_mapping_error(qdev->pdev, map)) {
1224 netif_err(qdev, ifup, qdev->ndev,
1225 "PCI mapping failed.\n");
1226 rx_ring->sbq_clean_idx = clean_idx;
1227 dev_kfree_skb_any(sbq_desc->p.skb);
1228 sbq_desc->p.skb = NULL;
1231 dma_unmap_addr_set(sbq_desc, mapaddr, map);
1232 dma_unmap_len_set(sbq_desc, maplen,
1233 rx_ring->sbq_buf_size);
1234 *sbq_desc->addr = cpu_to_le64(map);
1238 if (clean_idx == rx_ring->sbq_len)
1241 rx_ring->sbq_clean_idx = clean_idx;
1242 rx_ring->sbq_prod_idx += 16;
1243 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1244 rx_ring->sbq_prod_idx = 0;
1245 rx_ring->sbq_free_cnt -= 16;
1248 if (start_idx != clean_idx) {
1249 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1250 "sbq: updating prod idx = %d.\n",
1251 rx_ring->sbq_prod_idx);
1252 ql_write_db_reg(rx_ring->sbq_prod_idx,
1253 rx_ring->sbq_prod_idx_db_reg);
1257 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1258 struct rx_ring *rx_ring)
1260 ql_update_sbq(qdev, rx_ring);
1261 ql_update_lbq(qdev, rx_ring);
1264 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1265 * fails at some stage, or from the interrupt when a tx completes.
1267 static void ql_unmap_send(struct ql_adapter *qdev,
1268 struct tx_ring_desc *tx_ring_desc, int mapped)
1271 for (i = 0; i < mapped; i++) {
1272 if (i == 0 || (i == 7 && mapped > 7)) {
1274 * Unmap the skb->data area, or the
1275 * external sglist (AKA the Outbound
1276 * Address List (OAL)).
1277 * If its the zeroeth element, then it's
1278 * the skb->data area. If it's the 7th
1279 * element and there is more than 6 frags,
1283 netif_printk(qdev, tx_done, KERN_DEBUG,
1285 "unmapping OAL area.\n");
1287 pci_unmap_single(qdev->pdev,
1288 dma_unmap_addr(&tx_ring_desc->map[i],
1290 dma_unmap_len(&tx_ring_desc->map[i],
1294 netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev,
1295 "unmapping frag %d.\n", i);
1296 pci_unmap_page(qdev->pdev,
1297 dma_unmap_addr(&tx_ring_desc->map[i],
1299 dma_unmap_len(&tx_ring_desc->map[i],
1300 maplen), PCI_DMA_TODEVICE);
1306 /* Map the buffers for this transmit. This will return
1307 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1309 static int ql_map_send(struct ql_adapter *qdev,
1310 struct ob_mac_iocb_req *mac_iocb_ptr,
1311 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1313 int len = skb_headlen(skb);
1315 int frag_idx, err, map_idx = 0;
1316 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1317 int frag_cnt = skb_shinfo(skb)->nr_frags;
1320 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
1321 "frag_cnt = %d.\n", frag_cnt);
1324 * Map the skb buffer first.
1326 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1328 err = pci_dma_mapping_error(qdev->pdev, map);
1330 netif_err(qdev, tx_queued, qdev->ndev,
1331 "PCI mapping failed with error: %d\n", err);
1333 return NETDEV_TX_BUSY;
1336 tbd->len = cpu_to_le32(len);
1337 tbd->addr = cpu_to_le64(map);
1338 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1339 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1343 * This loop fills the remainder of the 8 address descriptors
1344 * in the IOCB. If there are more than 7 fragments, then the
1345 * eighth address desc will point to an external list (OAL).
1346 * When this happens, the remainder of the frags will be stored
1349 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1350 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1352 if (frag_idx == 6 && frag_cnt > 7) {
1353 /* Let's tack on an sglist.
1354 * Our control block will now
1356 * iocb->seg[0] = skb->data
1357 * iocb->seg[1] = frag[0]
1358 * iocb->seg[2] = frag[1]
1359 * iocb->seg[3] = frag[2]
1360 * iocb->seg[4] = frag[3]
1361 * iocb->seg[5] = frag[4]
1362 * iocb->seg[6] = frag[5]
1363 * iocb->seg[7] = ptr to OAL (external sglist)
1364 * oal->seg[0] = frag[6]
1365 * oal->seg[1] = frag[7]
1366 * oal->seg[2] = frag[8]
1367 * oal->seg[3] = frag[9]
1368 * oal->seg[4] = frag[10]
1371 /* Tack on the OAL in the eighth segment of IOCB. */
1372 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1375 err = pci_dma_mapping_error(qdev->pdev, map);
1377 netif_err(qdev, tx_queued, qdev->ndev,
1378 "PCI mapping outbound address list with error: %d\n",
1383 tbd->addr = cpu_to_le64(map);
1385 * The length is the number of fragments
1386 * that remain to be mapped times the length
1387 * of our sglist (OAL).
1390 cpu_to_le32((sizeof(struct tx_buf_desc) *
1391 (frag_cnt - frag_idx)) | TX_DESC_C);
1392 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1394 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1395 sizeof(struct oal));
1396 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1400 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
1403 err = dma_mapping_error(&qdev->pdev->dev, map);
1405 netif_err(qdev, tx_queued, qdev->ndev,
1406 "PCI mapping frags failed with error: %d.\n",
1411 tbd->addr = cpu_to_le64(map);
1412 tbd->len = cpu_to_le32(skb_frag_size(frag));
1413 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1414 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1415 skb_frag_size(frag));
1418 /* Save the number of segments we've mapped. */
1419 tx_ring_desc->map_cnt = map_idx;
1420 /* Terminate the last segment. */
1421 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1422 return NETDEV_TX_OK;
1426 * If the first frag mapping failed, then i will be zero.
1427 * This causes the unmap of the skb->data area. Otherwise
1428 * we pass in the number of frags that mapped successfully
1429 * so they can be umapped.
1431 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1432 return NETDEV_TX_BUSY;
1435 /* Categorizing receive firmware frame errors */
1436 static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err,
1437 struct rx_ring *rx_ring)
1439 struct nic_stats *stats = &qdev->nic_stats;
1441 stats->rx_err_count++;
1442 rx_ring->rx_errors++;
1444 switch (rx_err & IB_MAC_IOCB_RSP_ERR_MASK) {
1445 case IB_MAC_IOCB_RSP_ERR_CODE_ERR:
1446 stats->rx_code_err++;
1448 case IB_MAC_IOCB_RSP_ERR_OVERSIZE:
1449 stats->rx_oversize_err++;
1451 case IB_MAC_IOCB_RSP_ERR_UNDERSIZE:
1452 stats->rx_undersize_err++;
1454 case IB_MAC_IOCB_RSP_ERR_PREAMBLE:
1455 stats->rx_preamble_err++;
1457 case IB_MAC_IOCB_RSP_ERR_FRAME_LEN:
1458 stats->rx_frame_len_err++;
1460 case IB_MAC_IOCB_RSP_ERR_CRC:
1461 stats->rx_crc_err++;
1468 * ql_update_mac_hdr_len - helper routine to update the mac header length
1469 * based on vlan tags if present
1471 static void ql_update_mac_hdr_len(struct ql_adapter *qdev,
1472 struct ib_mac_iocb_rsp *ib_mac_rsp,
1473 void *page, size_t *len)
1477 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
1479 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) {
1481 /* Look for stacked vlan tags in ethertype field */
1482 if (tags[6] == ETH_P_8021Q &&
1483 tags[8] == ETH_P_8021Q)
1484 *len += 2 * VLAN_HLEN;
1490 /* Process an inbound completion from an rx ring. */
1491 static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev,
1492 struct rx_ring *rx_ring,
1493 struct ib_mac_iocb_rsp *ib_mac_rsp,
1497 struct sk_buff *skb;
1498 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1499 struct napi_struct *napi = &rx_ring->napi;
1501 /* Frame error, so drop the packet. */
1502 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1503 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1504 put_page(lbq_desc->p.pg_chunk.page);
1507 napi->dev = qdev->ndev;
1509 skb = napi_get_frags(napi);
1511 netif_err(qdev, drv, qdev->ndev,
1512 "Couldn't get an skb, exiting.\n");
1513 rx_ring->rx_dropped++;
1514 put_page(lbq_desc->p.pg_chunk.page);
1517 prefetch(lbq_desc->p.pg_chunk.va);
1518 __skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1519 lbq_desc->p.pg_chunk.page,
1520 lbq_desc->p.pg_chunk.offset,
1524 skb->data_len += length;
1525 skb->truesize += length;
1526 skb_shinfo(skb)->nr_frags++;
1528 rx_ring->rx_packets++;
1529 rx_ring->rx_bytes += length;
1530 skb->ip_summed = CHECKSUM_UNNECESSARY;
1531 skb_record_rx_queue(skb, rx_ring->cq_id);
1532 if (vlan_id != 0xffff)
1533 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1534 napi_gro_frags(napi);
1537 /* Process an inbound completion from an rx ring. */
1538 static void ql_process_mac_rx_page(struct ql_adapter *qdev,
1539 struct rx_ring *rx_ring,
1540 struct ib_mac_iocb_rsp *ib_mac_rsp,
1544 struct net_device *ndev = qdev->ndev;
1545 struct sk_buff *skb = NULL;
1547 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1548 struct napi_struct *napi = &rx_ring->napi;
1549 size_t hlen = ETH_HLEN;
1551 skb = netdev_alloc_skb(ndev, length);
1553 rx_ring->rx_dropped++;
1554 put_page(lbq_desc->p.pg_chunk.page);
1558 addr = lbq_desc->p.pg_chunk.va;
1561 /* Frame error, so drop the packet. */
1562 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1563 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1567 /* Update the MAC header length*/
1568 ql_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen);
1570 /* The max framesize filter on this chip is set higher than
1571 * MTU since FCoE uses 2k frames.
1573 if (skb->len > ndev->mtu + hlen) {
1574 netif_err(qdev, drv, qdev->ndev,
1575 "Segment too small, dropping.\n");
1576 rx_ring->rx_dropped++;
1579 skb_put_data(skb, addr, hlen);
1580 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1581 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1583 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1584 lbq_desc->p.pg_chunk.offset + hlen,
1586 skb->len += length - hlen;
1587 skb->data_len += length - hlen;
1588 skb->truesize += length - hlen;
1590 rx_ring->rx_packets++;
1591 rx_ring->rx_bytes += skb->len;
1592 skb->protocol = eth_type_trans(skb, ndev);
1593 skb_checksum_none_assert(skb);
1595 if ((ndev->features & NETIF_F_RXCSUM) &&
1596 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1598 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1599 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1600 "TCP checksum done!\n");
1601 skb->ip_summed = CHECKSUM_UNNECESSARY;
1602 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1603 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1604 /* Unfragmented ipv4 UDP frame. */
1606 (struct iphdr *)((u8 *)addr + hlen);
1607 if (!(iph->frag_off &
1608 htons(IP_MF|IP_OFFSET))) {
1609 skb->ip_summed = CHECKSUM_UNNECESSARY;
1610 netif_printk(qdev, rx_status, KERN_DEBUG,
1612 "UDP checksum done!\n");
1617 skb_record_rx_queue(skb, rx_ring->cq_id);
1618 if (vlan_id != 0xffff)
1619 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1620 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1621 napi_gro_receive(napi, skb);
1623 netif_receive_skb(skb);
1626 dev_kfree_skb_any(skb);
1627 put_page(lbq_desc->p.pg_chunk.page);
1630 /* Process an inbound completion from an rx ring. */
1631 static void ql_process_mac_rx_skb(struct ql_adapter *qdev,
1632 struct rx_ring *rx_ring,
1633 struct ib_mac_iocb_rsp *ib_mac_rsp,
1637 struct net_device *ndev = qdev->ndev;
1638 struct sk_buff *skb = NULL;
1639 struct sk_buff *new_skb = NULL;
1640 struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring);
1642 skb = sbq_desc->p.skb;
1643 /* Allocate new_skb and copy */
1644 new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN);
1645 if (new_skb == NULL) {
1646 rx_ring->rx_dropped++;
1649 skb_reserve(new_skb, NET_IP_ALIGN);
1651 pci_dma_sync_single_for_cpu(qdev->pdev,
1652 dma_unmap_addr(sbq_desc, mapaddr),
1653 dma_unmap_len(sbq_desc, maplen),
1654 PCI_DMA_FROMDEVICE);
1656 skb_put_data(new_skb, skb->data, length);
1658 pci_dma_sync_single_for_device(qdev->pdev,
1659 dma_unmap_addr(sbq_desc, mapaddr),
1660 dma_unmap_len(sbq_desc, maplen),
1661 PCI_DMA_FROMDEVICE);
1664 /* Frame error, so drop the packet. */
1665 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1666 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1667 dev_kfree_skb_any(skb);
1671 /* loopback self test for ethtool */
1672 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1673 ql_check_lb_frame(qdev, skb);
1674 dev_kfree_skb_any(skb);
1678 /* The max framesize filter on this chip is set higher than
1679 * MTU since FCoE uses 2k frames.
1681 if (skb->len > ndev->mtu + ETH_HLEN) {
1682 dev_kfree_skb_any(skb);
1683 rx_ring->rx_dropped++;
1687 prefetch(skb->data);
1688 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1689 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1691 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1692 IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
1693 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1694 IB_MAC_IOCB_RSP_M_REG ? "Registered" :
1695 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1696 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1698 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P)
1699 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1700 "Promiscuous Packet.\n");
1702 rx_ring->rx_packets++;
1703 rx_ring->rx_bytes += skb->len;
1704 skb->protocol = eth_type_trans(skb, ndev);
1705 skb_checksum_none_assert(skb);
1707 /* If rx checksum is on, and there are no
1708 * csum or frame errors.
1710 if ((ndev->features & NETIF_F_RXCSUM) &&
1711 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1713 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1714 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1715 "TCP checksum done!\n");
1716 skb->ip_summed = CHECKSUM_UNNECESSARY;
1717 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1718 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1719 /* Unfragmented ipv4 UDP frame. */
1720 struct iphdr *iph = (struct iphdr *) skb->data;
1721 if (!(iph->frag_off &
1722 htons(IP_MF|IP_OFFSET))) {
1723 skb->ip_summed = CHECKSUM_UNNECESSARY;
1724 netif_printk(qdev, rx_status, KERN_DEBUG,
1726 "UDP checksum done!\n");
1731 skb_record_rx_queue(skb, rx_ring->cq_id);
1732 if (vlan_id != 0xffff)
1733 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1734 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1735 napi_gro_receive(&rx_ring->napi, skb);
1737 netif_receive_skb(skb);
1740 static void ql_realign_skb(struct sk_buff *skb, int len)
1742 void *temp_addr = skb->data;
1744 /* Undo the skb_reserve(skb,32) we did before
1745 * giving to hardware, and realign data on
1746 * a 2-byte boundary.
1748 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1749 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1750 memmove(skb->data, temp_addr, len);
1754 * This function builds an skb for the given inbound
1755 * completion. It will be rewritten for readability in the near
1756 * future, but for not it works well.
1758 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1759 struct rx_ring *rx_ring,
1760 struct ib_mac_iocb_rsp *ib_mac_rsp)
1762 struct bq_desc *lbq_desc;
1763 struct bq_desc *sbq_desc;
1764 struct sk_buff *skb = NULL;
1765 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1766 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1767 size_t hlen = ETH_HLEN;
1770 * Handle the header buffer if present.
1772 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1773 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1774 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1775 "Header of %d bytes in small buffer.\n", hdr_len);
1777 * Headers fit nicely into a small buffer.
1779 sbq_desc = ql_get_curr_sbuf(rx_ring);
1780 pci_unmap_single(qdev->pdev,
1781 dma_unmap_addr(sbq_desc, mapaddr),
1782 dma_unmap_len(sbq_desc, maplen),
1783 PCI_DMA_FROMDEVICE);
1784 skb = sbq_desc->p.skb;
1785 ql_realign_skb(skb, hdr_len);
1786 skb_put(skb, hdr_len);
1787 sbq_desc->p.skb = NULL;
1791 * Handle the data buffer(s).
1793 if (unlikely(!length)) { /* Is there data too? */
1794 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1795 "No Data buffer in this packet.\n");
1799 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1800 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1801 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1802 "Headers in small, data of %d bytes in small, combine them.\n",
1805 * Data is less than small buffer size so it's
1806 * stuffed in a small buffer.
1807 * For this case we append the data
1808 * from the "data" small buffer to the "header" small
1811 sbq_desc = ql_get_curr_sbuf(rx_ring);
1812 pci_dma_sync_single_for_cpu(qdev->pdev,
1814 (sbq_desc, mapaddr),
1817 PCI_DMA_FROMDEVICE);
1818 skb_put_data(skb, sbq_desc->p.skb->data, length);
1819 pci_dma_sync_single_for_device(qdev->pdev,
1826 PCI_DMA_FROMDEVICE);
1828 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1829 "%d bytes in a single small buffer.\n",
1831 sbq_desc = ql_get_curr_sbuf(rx_ring);
1832 skb = sbq_desc->p.skb;
1833 ql_realign_skb(skb, length);
1834 skb_put(skb, length);
1835 pci_unmap_single(qdev->pdev,
1836 dma_unmap_addr(sbq_desc,
1838 dma_unmap_len(sbq_desc,
1840 PCI_DMA_FROMDEVICE);
1841 sbq_desc->p.skb = NULL;
1843 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1844 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1845 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1846 "Header in small, %d bytes in large. Chain large to small!\n",
1849 * The data is in a single large buffer. We
1850 * chain it to the header buffer's skb and let
1853 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1854 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1855 "Chaining page at offset = %d, for %d bytes to skb.\n",
1856 lbq_desc->p.pg_chunk.offset, length);
1857 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1858 lbq_desc->p.pg_chunk.offset,
1861 skb->data_len += length;
1862 skb->truesize += length;
1865 * The headers and data are in a single large buffer. We
1866 * copy it to a new skb and let it go. This can happen with
1867 * jumbo mtu on a non-TCP/UDP frame.
1869 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1870 skb = netdev_alloc_skb(qdev->ndev, length);
1872 netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev,
1873 "No skb available, drop the packet.\n");
1876 pci_unmap_page(qdev->pdev,
1877 dma_unmap_addr(lbq_desc,
1879 dma_unmap_len(lbq_desc, maplen),
1880 PCI_DMA_FROMDEVICE);
1881 skb_reserve(skb, NET_IP_ALIGN);
1882 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1883 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1885 skb_fill_page_desc(skb, 0,
1886 lbq_desc->p.pg_chunk.page,
1887 lbq_desc->p.pg_chunk.offset,
1890 skb->data_len += length;
1891 skb->truesize += length;
1892 ql_update_mac_hdr_len(qdev, ib_mac_rsp,
1893 lbq_desc->p.pg_chunk.va,
1895 __pskb_pull_tail(skb, hlen);
1899 * The data is in a chain of large buffers
1900 * pointed to by a small buffer. We loop
1901 * thru and chain them to the our small header
1903 * frags: There are 18 max frags and our small
1904 * buffer will hold 32 of them. The thing is,
1905 * we'll use 3 max for our 9000 byte jumbo
1906 * frames. If the MTU goes up we could
1907 * eventually be in trouble.
1910 sbq_desc = ql_get_curr_sbuf(rx_ring);
1911 pci_unmap_single(qdev->pdev,
1912 dma_unmap_addr(sbq_desc, mapaddr),
1913 dma_unmap_len(sbq_desc, maplen),
1914 PCI_DMA_FROMDEVICE);
1915 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1917 * This is an non TCP/UDP IP frame, so
1918 * the headers aren't split into a small
1919 * buffer. We have to use the small buffer
1920 * that contains our sg list as our skb to
1921 * send upstairs. Copy the sg list here to
1922 * a local buffer and use it to find the
1925 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1926 "%d bytes of headers & data in chain of large.\n",
1928 skb = sbq_desc->p.skb;
1929 sbq_desc->p.skb = NULL;
1930 skb_reserve(skb, NET_IP_ALIGN);
1933 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1934 size = (length < rx_ring->lbq_buf_size) ? length :
1935 rx_ring->lbq_buf_size;
1937 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1938 "Adding page %d to skb for %d bytes.\n",
1940 skb_fill_page_desc(skb, i,
1941 lbq_desc->p.pg_chunk.page,
1942 lbq_desc->p.pg_chunk.offset,
1945 skb->data_len += size;
1946 skb->truesize += size;
1949 } while (length > 0);
1950 ql_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va,
1952 __pskb_pull_tail(skb, hlen);
1957 /* Process an inbound completion from an rx ring. */
1958 static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev,
1959 struct rx_ring *rx_ring,
1960 struct ib_mac_iocb_rsp *ib_mac_rsp,
1963 struct net_device *ndev = qdev->ndev;
1964 struct sk_buff *skb = NULL;
1966 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1968 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1969 if (unlikely(!skb)) {
1970 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1971 "No skb available, drop packet.\n");
1972 rx_ring->rx_dropped++;
1976 /* Frame error, so drop the packet. */
1977 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1978 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1979 dev_kfree_skb_any(skb);
1983 /* The max framesize filter on this chip is set higher than
1984 * MTU since FCoE uses 2k frames.
1986 if (skb->len > ndev->mtu + ETH_HLEN) {
1987 dev_kfree_skb_any(skb);
1988 rx_ring->rx_dropped++;
1992 /* loopback self test for ethtool */
1993 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1994 ql_check_lb_frame(qdev, skb);
1995 dev_kfree_skb_any(skb);
1999 prefetch(skb->data);
2000 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
2001 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%s Multicast.\n",
2002 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2003 IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
2004 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2005 IB_MAC_IOCB_RSP_M_REG ? "Registered" :
2006 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2007 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
2008 rx_ring->rx_multicast++;
2010 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
2011 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2012 "Promiscuous Packet.\n");
2015 skb->protocol = eth_type_trans(skb, ndev);
2016 skb_checksum_none_assert(skb);
2018 /* If rx checksum is on, and there are no
2019 * csum or frame errors.
2021 if ((ndev->features & NETIF_F_RXCSUM) &&
2022 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
2024 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
2025 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2026 "TCP checksum done!\n");
2027 skb->ip_summed = CHECKSUM_UNNECESSARY;
2028 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
2029 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
2030 /* Unfragmented ipv4 UDP frame. */
2031 struct iphdr *iph = (struct iphdr *) skb->data;
2032 if (!(iph->frag_off &
2033 htons(IP_MF|IP_OFFSET))) {
2034 skb->ip_summed = CHECKSUM_UNNECESSARY;
2035 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2036 "TCP checksum done!\n");
2041 rx_ring->rx_packets++;
2042 rx_ring->rx_bytes += skb->len;
2043 skb_record_rx_queue(skb, rx_ring->cq_id);
2044 if (vlan_id != 0xffff)
2045 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
2046 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
2047 napi_gro_receive(&rx_ring->napi, skb);
2049 netif_receive_skb(skb);
2052 /* Process an inbound completion from an rx ring. */
2053 static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev,
2054 struct rx_ring *rx_ring,
2055 struct ib_mac_iocb_rsp *ib_mac_rsp)
2057 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
2058 u16 vlan_id = ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
2059 (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ?
2060 ((le16_to_cpu(ib_mac_rsp->vlan_id) &
2061 IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff;
2063 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
2065 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
2066 /* The data and headers are split into
2069 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2071 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
2072 /* The data fit in a single small buffer.
2073 * Allocate a new skb, copy the data and
2074 * return the buffer to the free pool.
2076 ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp,
2078 } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) &&
2079 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) &&
2080 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) {
2081 /* TCP packet in a page chunk that's been checksummed.
2082 * Tack it on to our GRO skb and let it go.
2084 ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp,
2086 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
2087 /* Non-TCP packet in a page chunk. Allocate an
2088 * skb, tack it on frags, and send it up.
2090 ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp,
2093 /* Non-TCP/UDP large frames that span multiple buffers
2094 * can be processed corrrectly by the split frame logic.
2096 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2100 return (unsigned long)length;
2103 /* Process an outbound completion from an rx ring. */
2104 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
2105 struct ob_mac_iocb_rsp *mac_rsp)
2107 struct tx_ring *tx_ring;
2108 struct tx_ring_desc *tx_ring_desc;
2110 QL_DUMP_OB_MAC_RSP(mac_rsp);
2111 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
2112 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
2113 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
2114 tx_ring->tx_bytes += (tx_ring_desc->skb)->len;
2115 tx_ring->tx_packets++;
2116 dev_kfree_skb(tx_ring_desc->skb);
2117 tx_ring_desc->skb = NULL;
2119 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
2122 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
2123 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
2124 netif_warn(qdev, tx_done, qdev->ndev,
2125 "Total descriptor length did not match transfer length.\n");
2127 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
2128 netif_warn(qdev, tx_done, qdev->ndev,
2129 "Frame too short to be valid, not sent.\n");
2131 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
2132 netif_warn(qdev, tx_done, qdev->ndev,
2133 "Frame too long, but sent anyway.\n");
2135 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
2136 netif_warn(qdev, tx_done, qdev->ndev,
2137 "PCI backplane error. Frame not sent.\n");
2140 atomic_inc(&tx_ring->tx_count);
2143 /* Fire up a handler to reset the MPI processor. */
2144 void ql_queue_fw_error(struct ql_adapter *qdev)
2147 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
2150 void ql_queue_asic_error(struct ql_adapter *qdev)
2153 ql_disable_interrupts(qdev);
2154 /* Clear adapter up bit to signal the recovery
2155 * process that it shouldn't kill the reset worker
2158 clear_bit(QL_ADAPTER_UP, &qdev->flags);
2159 /* Set asic recovery bit to indicate reset process that we are
2160 * in fatal error recovery process rather than normal close
2162 set_bit(QL_ASIC_RECOVERY, &qdev->flags);
2163 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
2166 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
2167 struct ib_ae_iocb_rsp *ib_ae_rsp)
2169 switch (ib_ae_rsp->event) {
2170 case MGMT_ERR_EVENT:
2171 netif_err(qdev, rx_err, qdev->ndev,
2172 "Management Processor Fatal Error.\n");
2173 ql_queue_fw_error(qdev);
2176 case CAM_LOOKUP_ERR_EVENT:
2177 netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n");
2178 netdev_err(qdev->ndev, "This event shouldn't occur.\n");
2179 ql_queue_asic_error(qdev);
2182 case SOFT_ECC_ERROR_EVENT:
2183 netdev_err(qdev->ndev, "Soft ECC error detected.\n");
2184 ql_queue_asic_error(qdev);
2187 case PCI_ERR_ANON_BUF_RD:
2188 netdev_err(qdev->ndev, "PCI error occurred when reading "
2189 "anonymous buffers from rx_ring %d.\n",
2191 ql_queue_asic_error(qdev);
2195 netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n",
2197 ql_queue_asic_error(qdev);
2202 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
2204 struct ql_adapter *qdev = rx_ring->qdev;
2205 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2206 struct ob_mac_iocb_rsp *net_rsp = NULL;
2209 struct tx_ring *tx_ring;
2210 /* While there are entries in the completion queue. */
2211 while (prod != rx_ring->cnsmr_idx) {
2213 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2214 "cq_id = %d, prod = %d, cnsmr = %d\n",
2215 rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2217 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
2219 switch (net_rsp->opcode) {
2221 case OPCODE_OB_MAC_TSO_IOCB:
2222 case OPCODE_OB_MAC_IOCB:
2223 ql_process_mac_tx_intr(qdev, net_rsp);
2226 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2227 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2231 ql_update_cq(rx_ring);
2232 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2236 ql_write_cq_idx(rx_ring);
2237 tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
2238 if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) {
2239 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2241 * The queue got stopped because the tx_ring was full.
2242 * Wake it up, because it's now at least 25% empty.
2244 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2250 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
2252 struct ql_adapter *qdev = rx_ring->qdev;
2253 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2254 struct ql_net_rsp_iocb *net_rsp;
2257 /* While there are entries in the completion queue. */
2258 while (prod != rx_ring->cnsmr_idx) {
2260 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2261 "cq_id = %d, prod = %d, cnsmr = %d\n",
2262 rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2264 net_rsp = rx_ring->curr_entry;
2266 switch (net_rsp->opcode) {
2267 case OPCODE_IB_MAC_IOCB:
2268 ql_process_mac_rx_intr(qdev, rx_ring,
2269 (struct ib_mac_iocb_rsp *)
2273 case OPCODE_IB_AE_IOCB:
2274 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
2278 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2279 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2284 ql_update_cq(rx_ring);
2285 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2286 if (count == budget)
2289 ql_update_buffer_queues(qdev, rx_ring);
2290 ql_write_cq_idx(rx_ring);
2294 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
2296 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
2297 struct ql_adapter *qdev = rx_ring->qdev;
2298 struct rx_ring *trx_ring;
2299 int i, work_done = 0;
2300 struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
2302 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2303 "Enter, NAPI POLL cq_id = %d.\n", rx_ring->cq_id);
2305 /* Service the TX rings first. They start
2306 * right after the RSS rings. */
2307 for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
2308 trx_ring = &qdev->rx_ring[i];
2309 /* If this TX completion ring belongs to this vector and
2310 * it's not empty then service it.
2312 if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
2313 (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
2314 trx_ring->cnsmr_idx)) {
2315 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2316 "%s: Servicing TX completion ring %d.\n",
2317 __func__, trx_ring->cq_id);
2318 ql_clean_outbound_rx_ring(trx_ring);
2323 * Now service the RSS ring if it's active.
2325 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
2326 rx_ring->cnsmr_idx) {
2327 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2328 "%s: Servicing RX completion ring %d.\n",
2329 __func__, rx_ring->cq_id);
2330 work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
2333 if (work_done < budget) {
2334 napi_complete_done(napi, work_done);
2335 ql_enable_completion_interrupt(qdev, rx_ring->irq);
2340 static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features)
2342 struct ql_adapter *qdev = netdev_priv(ndev);
2344 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2345 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
2346 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
2348 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
2353 * qlge_update_hw_vlan_features - helper routine to reinitialize the adapter
2354 * based on the features to enable/disable hardware vlan accel
2356 static int qlge_update_hw_vlan_features(struct net_device *ndev,
2357 netdev_features_t features)
2359 struct ql_adapter *qdev = netdev_priv(ndev);
2361 bool need_restart = netif_running(ndev);
2364 status = ql_adapter_down(qdev);
2366 netif_err(qdev, link, qdev->ndev,
2367 "Failed to bring down the adapter\n");
2372 /* update the features with resent change */
2373 ndev->features = features;
2376 status = ql_adapter_up(qdev);
2378 netif_err(qdev, link, qdev->ndev,
2379 "Failed to bring up the adapter\n");
2387 static netdev_features_t qlge_fix_features(struct net_device *ndev,
2388 netdev_features_t features)
2392 /* Update the behavior of vlan accel in the adapter */
2393 err = qlge_update_hw_vlan_features(ndev, features);
2400 static int qlge_set_features(struct net_device *ndev,
2401 netdev_features_t features)
2403 netdev_features_t changed = ndev->features ^ features;
2405 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2406 qlge_vlan_mode(ndev, features);
2411 static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid)
2413 u32 enable_bit = MAC_ADDR_E;
2416 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2417 MAC_ADDR_TYPE_VLAN, vid);
2419 netif_err(qdev, ifup, qdev->ndev,
2420 "Failed to init vlan address.\n");
2424 static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
2426 struct ql_adapter *qdev = netdev_priv(ndev);
2430 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2434 err = __qlge_vlan_rx_add_vid(qdev, vid);
2435 set_bit(vid, qdev->active_vlans);
2437 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2442 static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid)
2447 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2448 MAC_ADDR_TYPE_VLAN, vid);
2450 netif_err(qdev, ifup, qdev->ndev,
2451 "Failed to clear vlan address.\n");
2455 static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
2457 struct ql_adapter *qdev = netdev_priv(ndev);
2461 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2465 err = __qlge_vlan_rx_kill_vid(qdev, vid);
2466 clear_bit(vid, qdev->active_vlans);
2468 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2473 static void qlge_restore_vlan(struct ql_adapter *qdev)
2478 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2482 for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID)
2483 __qlge_vlan_rx_add_vid(qdev, vid);
2485 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2488 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
2489 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
2491 struct rx_ring *rx_ring = dev_id;
2492 napi_schedule(&rx_ring->napi);
2496 /* This handles a fatal error, MPI activity, and the default
2497 * rx_ring in an MSI-X multiple vector environment.
2498 * In MSI/Legacy environment it also process the rest of
2501 static irqreturn_t qlge_isr(int irq, void *dev_id)
2503 struct rx_ring *rx_ring = dev_id;
2504 struct ql_adapter *qdev = rx_ring->qdev;
2505 struct intr_context *intr_context = &qdev->intr_context[0];
2509 spin_lock(&qdev->hw_lock);
2510 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
2511 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2512 "Shared Interrupt, Not ours!\n");
2513 spin_unlock(&qdev->hw_lock);
2516 spin_unlock(&qdev->hw_lock);
2518 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
2521 * Check for fatal error.
2524 ql_queue_asic_error(qdev);
2525 netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var);
2526 var = ql_read32(qdev, ERR_STS);
2527 netdev_err(qdev->ndev, "Resetting chip. "
2528 "Error Status Register = 0x%x\n", var);
2533 * Check MPI processor activity.
2535 if ((var & STS_PI) &&
2536 (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
2538 * We've got an async event or mailbox completion.
2539 * Handle it and clear the source of the interrupt.
2541 netif_err(qdev, intr, qdev->ndev,
2542 "Got MPI processor interrupt.\n");
2543 ql_disable_completion_interrupt(qdev, intr_context->intr);
2544 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
2545 queue_delayed_work_on(smp_processor_id(),
2546 qdev->workqueue, &qdev->mpi_work, 0);
2551 * Get the bit-mask that shows the active queues for this
2552 * pass. Compare it to the queues that this irq services
2553 * and call napi if there's a match.
2555 var = ql_read32(qdev, ISR1);
2556 if (var & intr_context->irq_mask) {
2557 netif_info(qdev, intr, qdev->ndev,
2558 "Waking handler for rx_ring[0].\n");
2559 ql_disable_completion_interrupt(qdev, intr_context->intr);
2560 napi_schedule(&rx_ring->napi);
2563 ql_enable_completion_interrupt(qdev, intr_context->intr);
2564 return work_done ? IRQ_HANDLED : IRQ_NONE;
2567 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2570 if (skb_is_gso(skb)) {
2572 __be16 l3_proto = vlan_get_protocol(skb);
2574 err = skb_cow_head(skb, 0);
2578 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2579 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2580 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2581 mac_iocb_ptr->total_hdrs_len =
2582 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2583 mac_iocb_ptr->net_trans_offset =
2584 cpu_to_le16(skb_network_offset(skb) |
2585 skb_transport_offset(skb)
2586 << OB_MAC_TRANSPORT_HDR_SHIFT);
2587 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2588 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2589 if (likely(l3_proto == htons(ETH_P_IP))) {
2590 struct iphdr *iph = ip_hdr(skb);
2592 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2593 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2597 } else if (l3_proto == htons(ETH_P_IPV6)) {
2598 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2599 tcp_hdr(skb)->check =
2600 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2601 &ipv6_hdr(skb)->daddr,
2609 static void ql_hw_csum_setup(struct sk_buff *skb,
2610 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2613 struct iphdr *iph = ip_hdr(skb);
2615 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2616 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2617 mac_iocb_ptr->net_trans_offset =
2618 cpu_to_le16(skb_network_offset(skb) |
2619 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2621 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2622 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2623 if (likely(iph->protocol == IPPROTO_TCP)) {
2624 check = &(tcp_hdr(skb)->check);
2625 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2626 mac_iocb_ptr->total_hdrs_len =
2627 cpu_to_le16(skb_transport_offset(skb) +
2628 (tcp_hdr(skb)->doff << 2));
2630 check = &(udp_hdr(skb)->check);
2631 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2632 mac_iocb_ptr->total_hdrs_len =
2633 cpu_to_le16(skb_transport_offset(skb) +
2634 sizeof(struct udphdr));
2636 *check = ~csum_tcpudp_magic(iph->saddr,
2637 iph->daddr, len, iph->protocol, 0);
2640 static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
2642 struct tx_ring_desc *tx_ring_desc;
2643 struct ob_mac_iocb_req *mac_iocb_ptr;
2644 struct ql_adapter *qdev = netdev_priv(ndev);
2646 struct tx_ring *tx_ring;
2647 u32 tx_ring_idx = (u32) skb->queue_mapping;
2649 tx_ring = &qdev->tx_ring[tx_ring_idx];
2651 if (skb_padto(skb, ETH_ZLEN))
2652 return NETDEV_TX_OK;
2654 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2655 netif_info(qdev, tx_queued, qdev->ndev,
2656 "%s: BUG! shutting down tx queue %d due to lack of resources.\n",
2657 __func__, tx_ring_idx);
2658 netif_stop_subqueue(ndev, tx_ring->wq_id);
2659 tx_ring->tx_errors++;
2660 return NETDEV_TX_BUSY;
2662 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2663 mac_iocb_ptr = tx_ring_desc->queue_entry;
2664 memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
2666 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2667 mac_iocb_ptr->tid = tx_ring_desc->index;
2668 /* We use the upper 32-bits to store the tx queue for this IO.
2669 * When we get the completion we can use it to establish the context.
2671 mac_iocb_ptr->txq_idx = tx_ring_idx;
2672 tx_ring_desc->skb = skb;
2674 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2676 if (skb_vlan_tag_present(skb)) {
2677 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2678 "Adding a vlan tag %d.\n", skb_vlan_tag_get(skb));
2679 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2680 mac_iocb_ptr->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
2682 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2684 dev_kfree_skb_any(skb);
2685 return NETDEV_TX_OK;
2686 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2687 ql_hw_csum_setup(skb,
2688 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2690 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2692 netif_err(qdev, tx_queued, qdev->ndev,
2693 "Could not map the segments.\n");
2694 tx_ring->tx_errors++;
2695 return NETDEV_TX_BUSY;
2697 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2698 tx_ring->prod_idx++;
2699 if (tx_ring->prod_idx == tx_ring->wq_len)
2700 tx_ring->prod_idx = 0;
2703 ql_write_db_reg_relaxed(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2705 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2706 "tx queued, slot %d, len %d\n",
2707 tx_ring->prod_idx, skb->len);
2709 atomic_dec(&tx_ring->tx_count);
2711 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2712 netif_stop_subqueue(ndev, tx_ring->wq_id);
2713 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2715 * The queue got stopped because the tx_ring was full.
2716 * Wake it up, because it's now at least 25% empty.
2718 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2720 return NETDEV_TX_OK;
2724 static void ql_free_shadow_space(struct ql_adapter *qdev)
2726 if (qdev->rx_ring_shadow_reg_area) {
2727 pci_free_consistent(qdev->pdev,
2729 qdev->rx_ring_shadow_reg_area,
2730 qdev->rx_ring_shadow_reg_dma);
2731 qdev->rx_ring_shadow_reg_area = NULL;
2733 if (qdev->tx_ring_shadow_reg_area) {
2734 pci_free_consistent(qdev->pdev,
2736 qdev->tx_ring_shadow_reg_area,
2737 qdev->tx_ring_shadow_reg_dma);
2738 qdev->tx_ring_shadow_reg_area = NULL;
2742 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2744 qdev->rx_ring_shadow_reg_area =
2745 pci_zalloc_consistent(qdev->pdev, PAGE_SIZE,
2746 &qdev->rx_ring_shadow_reg_dma);
2747 if (qdev->rx_ring_shadow_reg_area == NULL) {
2748 netif_err(qdev, ifup, qdev->ndev,
2749 "Allocation of RX shadow space failed.\n");
2753 qdev->tx_ring_shadow_reg_area =
2754 pci_zalloc_consistent(qdev->pdev, PAGE_SIZE,
2755 &qdev->tx_ring_shadow_reg_dma);
2756 if (qdev->tx_ring_shadow_reg_area == NULL) {
2757 netif_err(qdev, ifup, qdev->ndev,
2758 "Allocation of TX shadow space failed.\n");
2759 goto err_wqp_sh_area;
2764 pci_free_consistent(qdev->pdev,
2766 qdev->rx_ring_shadow_reg_area,
2767 qdev->rx_ring_shadow_reg_dma);
2771 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2773 struct tx_ring_desc *tx_ring_desc;
2775 struct ob_mac_iocb_req *mac_iocb_ptr;
2777 mac_iocb_ptr = tx_ring->wq_base;
2778 tx_ring_desc = tx_ring->q;
2779 for (i = 0; i < tx_ring->wq_len; i++) {
2780 tx_ring_desc->index = i;
2781 tx_ring_desc->skb = NULL;
2782 tx_ring_desc->queue_entry = mac_iocb_ptr;
2786 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2789 static void ql_free_tx_resources(struct ql_adapter *qdev,
2790 struct tx_ring *tx_ring)
2792 if (tx_ring->wq_base) {
2793 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2794 tx_ring->wq_base, tx_ring->wq_base_dma);
2795 tx_ring->wq_base = NULL;
2801 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2802 struct tx_ring *tx_ring)
2805 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2806 &tx_ring->wq_base_dma);
2808 if ((tx_ring->wq_base == NULL) ||
2809 tx_ring->wq_base_dma & WQ_ADDR_ALIGN)
2813 kmalloc_array(tx_ring->wq_len, sizeof(struct tx_ring_desc),
2815 if (tx_ring->q == NULL)
2820 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2821 tx_ring->wq_base, tx_ring->wq_base_dma);
2822 tx_ring->wq_base = NULL;
2824 netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n");
2828 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2830 struct bq_desc *lbq_desc;
2832 uint32_t curr_idx, clean_idx;
2834 curr_idx = rx_ring->lbq_curr_idx;
2835 clean_idx = rx_ring->lbq_clean_idx;
2836 while (curr_idx != clean_idx) {
2837 lbq_desc = &rx_ring->lbq[curr_idx];
2839 if (lbq_desc->p.pg_chunk.last_flag) {
2840 pci_unmap_page(qdev->pdev,
2841 lbq_desc->p.pg_chunk.map,
2842 ql_lbq_block_size(qdev),
2843 PCI_DMA_FROMDEVICE);
2844 lbq_desc->p.pg_chunk.last_flag = 0;
2847 put_page(lbq_desc->p.pg_chunk.page);
2848 lbq_desc->p.pg_chunk.page = NULL;
2850 if (++curr_idx == rx_ring->lbq_len)
2854 if (rx_ring->pg_chunk.page) {
2855 pci_unmap_page(qdev->pdev, rx_ring->pg_chunk.map,
2856 ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE);
2857 put_page(rx_ring->pg_chunk.page);
2858 rx_ring->pg_chunk.page = NULL;
2862 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2865 struct bq_desc *sbq_desc;
2867 for (i = 0; i < rx_ring->sbq_len; i++) {
2868 sbq_desc = &rx_ring->sbq[i];
2869 if (sbq_desc == NULL) {
2870 netif_err(qdev, ifup, qdev->ndev,
2871 "sbq_desc %d is NULL.\n", i);
2874 if (sbq_desc->p.skb) {
2875 pci_unmap_single(qdev->pdev,
2876 dma_unmap_addr(sbq_desc, mapaddr),
2877 dma_unmap_len(sbq_desc, maplen),
2878 PCI_DMA_FROMDEVICE);
2879 dev_kfree_skb(sbq_desc->p.skb);
2880 sbq_desc->p.skb = NULL;
2885 /* Free all large and small rx buffers associated
2886 * with the completion queues for this device.
2888 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2891 struct rx_ring *rx_ring;
2893 for (i = 0; i < qdev->rx_ring_count; i++) {
2894 rx_ring = &qdev->rx_ring[i];
2896 ql_free_lbq_buffers(qdev, rx_ring);
2898 ql_free_sbq_buffers(qdev, rx_ring);
2902 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2904 struct rx_ring *rx_ring;
2907 for (i = 0; i < qdev->rx_ring_count; i++) {
2908 rx_ring = &qdev->rx_ring[i];
2909 if (rx_ring->type != TX_Q)
2910 ql_update_buffer_queues(qdev, rx_ring);
2914 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2915 struct rx_ring *rx_ring)
2918 struct bq_desc *lbq_desc;
2919 __le64 *bq = rx_ring->lbq_base;
2921 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2922 for (i = 0; i < rx_ring->lbq_len; i++) {
2923 lbq_desc = &rx_ring->lbq[i];
2924 memset(lbq_desc, 0, sizeof(*lbq_desc));
2925 lbq_desc->index = i;
2926 lbq_desc->addr = bq;
2931 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2932 struct rx_ring *rx_ring)
2935 struct bq_desc *sbq_desc;
2936 __le64 *bq = rx_ring->sbq_base;
2938 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2939 for (i = 0; i < rx_ring->sbq_len; i++) {
2940 sbq_desc = &rx_ring->sbq[i];
2941 memset(sbq_desc, 0, sizeof(*sbq_desc));
2942 sbq_desc->index = i;
2943 sbq_desc->addr = bq;
2948 static void ql_free_rx_resources(struct ql_adapter *qdev,
2949 struct rx_ring *rx_ring)
2951 /* Free the small buffer queue. */
2952 if (rx_ring->sbq_base) {
2953 pci_free_consistent(qdev->pdev,
2955 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2956 rx_ring->sbq_base = NULL;
2959 /* Free the small buffer queue control blocks. */
2960 kfree(rx_ring->sbq);
2961 rx_ring->sbq = NULL;
2963 /* Free the large buffer queue. */
2964 if (rx_ring->lbq_base) {
2965 pci_free_consistent(qdev->pdev,
2967 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2968 rx_ring->lbq_base = NULL;
2971 /* Free the large buffer queue control blocks. */
2972 kfree(rx_ring->lbq);
2973 rx_ring->lbq = NULL;
2975 /* Free the rx queue. */
2976 if (rx_ring->cq_base) {
2977 pci_free_consistent(qdev->pdev,
2979 rx_ring->cq_base, rx_ring->cq_base_dma);
2980 rx_ring->cq_base = NULL;
2984 /* Allocate queues and buffers for this completions queue based
2985 * on the values in the parameter structure. */
2986 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2987 struct rx_ring *rx_ring)
2991 * Allocate the completion queue for this rx_ring.
2994 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2995 &rx_ring->cq_base_dma);
2997 if (rx_ring->cq_base == NULL) {
2998 netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n");
3002 if (rx_ring->sbq_len) {
3004 * Allocate small buffer queue.
3007 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
3008 &rx_ring->sbq_base_dma);
3010 if (rx_ring->sbq_base == NULL) {
3011 netif_err(qdev, ifup, qdev->ndev,
3012 "Small buffer queue allocation failed.\n");
3017 * Allocate small buffer queue control blocks.
3019 rx_ring->sbq = kmalloc_array(rx_ring->sbq_len,
3020 sizeof(struct bq_desc),
3022 if (rx_ring->sbq == NULL)
3025 ql_init_sbq_ring(qdev, rx_ring);
3028 if (rx_ring->lbq_len) {
3030 * Allocate large buffer queue.
3033 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
3034 &rx_ring->lbq_base_dma);
3036 if (rx_ring->lbq_base == NULL) {
3037 netif_err(qdev, ifup, qdev->ndev,
3038 "Large buffer queue allocation failed.\n");
3042 * Allocate large buffer queue control blocks.
3044 rx_ring->lbq = kmalloc_array(rx_ring->lbq_len,
3045 sizeof(struct bq_desc),
3047 if (rx_ring->lbq == NULL)
3050 ql_init_lbq_ring(qdev, rx_ring);
3056 ql_free_rx_resources(qdev, rx_ring);
3060 static void ql_tx_ring_clean(struct ql_adapter *qdev)
3062 struct tx_ring *tx_ring;
3063 struct tx_ring_desc *tx_ring_desc;
3067 * Loop through all queues and free
3070 for (j = 0; j < qdev->tx_ring_count; j++) {
3071 tx_ring = &qdev->tx_ring[j];
3072 for (i = 0; i < tx_ring->wq_len; i++) {
3073 tx_ring_desc = &tx_ring->q[i];
3074 if (tx_ring_desc && tx_ring_desc->skb) {
3075 netif_err(qdev, ifdown, qdev->ndev,
3076 "Freeing lost SKB %p, from queue %d, index %d.\n",
3077 tx_ring_desc->skb, j,
3078 tx_ring_desc->index);
3079 ql_unmap_send(qdev, tx_ring_desc,
3080 tx_ring_desc->map_cnt);
3081 dev_kfree_skb(tx_ring_desc->skb);
3082 tx_ring_desc->skb = NULL;
3088 static void ql_free_mem_resources(struct ql_adapter *qdev)
3092 for (i = 0; i < qdev->tx_ring_count; i++)
3093 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
3094 for (i = 0; i < qdev->rx_ring_count; i++)
3095 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
3096 ql_free_shadow_space(qdev);
3099 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
3103 /* Allocate space for our shadow registers and such. */
3104 if (ql_alloc_shadow_space(qdev))
3107 for (i = 0; i < qdev->rx_ring_count; i++) {
3108 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
3109 netif_err(qdev, ifup, qdev->ndev,
3110 "RX resource allocation failed.\n");
3114 /* Allocate tx queue resources */
3115 for (i = 0; i < qdev->tx_ring_count; i++) {
3116 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
3117 netif_err(qdev, ifup, qdev->ndev,
3118 "TX resource allocation failed.\n");
3125 ql_free_mem_resources(qdev);
3129 /* Set up the rx ring control block and pass it to the chip.
3130 * The control block is defined as
3131 * "Completion Queue Initialization Control Block", or cqicb.
3133 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
3135 struct cqicb *cqicb = &rx_ring->cqicb;
3136 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
3137 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3138 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
3139 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3140 void __iomem *doorbell_area =
3141 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
3145 __le64 *base_indirect_ptr;
3148 /* Set up the shadow registers for this ring. */
3149 rx_ring->prod_idx_sh_reg = shadow_reg;
3150 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
3151 *rx_ring->prod_idx_sh_reg = 0;
3152 shadow_reg += sizeof(u64);
3153 shadow_reg_dma += sizeof(u64);
3154 rx_ring->lbq_base_indirect = shadow_reg;
3155 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
3156 shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3157 shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3158 rx_ring->sbq_base_indirect = shadow_reg;
3159 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
3161 /* PCI doorbell mem area + 0x00 for consumer index register */
3162 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
3163 rx_ring->cnsmr_idx = 0;
3164 rx_ring->curr_entry = rx_ring->cq_base;
3166 /* PCI doorbell mem area + 0x04 for valid register */
3167 rx_ring->valid_db_reg = doorbell_area + 0x04;
3169 /* PCI doorbell mem area + 0x18 for large buffer consumer */
3170 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
3172 /* PCI doorbell mem area + 0x1c */
3173 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
3175 memset((void *)cqicb, 0, sizeof(struct cqicb));
3176 cqicb->msix_vect = rx_ring->irq;
3178 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
3179 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
3181 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
3183 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
3186 * Set up the control block load flags.
3188 cqicb->flags = FLAGS_LC | /* Load queue base address */
3189 FLAGS_LV | /* Load MSI-X vector */
3190 FLAGS_LI; /* Load irq delay values */
3191 if (rx_ring->lbq_len) {
3192 cqicb->flags |= FLAGS_LL; /* Load lbq values */
3193 tmp = (u64)rx_ring->lbq_base_dma;
3194 base_indirect_ptr = rx_ring->lbq_base_indirect;
3197 *base_indirect_ptr = cpu_to_le64(tmp);
3198 tmp += DB_PAGE_SIZE;
3199 base_indirect_ptr++;
3201 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3203 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
3204 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
3205 (u16) rx_ring->lbq_buf_size;
3206 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
3207 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
3208 (u16) rx_ring->lbq_len;
3209 cqicb->lbq_len = cpu_to_le16(bq_len);
3210 rx_ring->lbq_prod_idx = 0;
3211 rx_ring->lbq_curr_idx = 0;
3212 rx_ring->lbq_clean_idx = 0;
3213 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
3215 if (rx_ring->sbq_len) {
3216 cqicb->flags |= FLAGS_LS; /* Load sbq values */
3217 tmp = (u64)rx_ring->sbq_base_dma;
3218 base_indirect_ptr = rx_ring->sbq_base_indirect;
3221 *base_indirect_ptr = cpu_to_le64(tmp);
3222 tmp += DB_PAGE_SIZE;
3223 base_indirect_ptr++;
3225 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
3227 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
3228 cqicb->sbq_buf_size =
3229 cpu_to_le16((u16)(rx_ring->sbq_buf_size));
3230 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
3231 (u16) rx_ring->sbq_len;
3232 cqicb->sbq_len = cpu_to_le16(bq_len);
3233 rx_ring->sbq_prod_idx = 0;
3234 rx_ring->sbq_curr_idx = 0;
3235 rx_ring->sbq_clean_idx = 0;
3236 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
3238 switch (rx_ring->type) {
3240 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
3241 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
3244 /* Inbound completion handling rx_rings run in
3245 * separate NAPI contexts.
3247 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
3249 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
3250 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
3253 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3254 "Invalid rx_ring->type = %d.\n", rx_ring->type);
3256 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
3257 CFG_LCQ, rx_ring->cq_id);
3259 netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n");
3265 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
3267 struct wqicb *wqicb = (struct wqicb *)tx_ring;
3268 void __iomem *doorbell_area =
3269 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
3270 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
3271 (tx_ring->wq_id * sizeof(u64));
3272 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
3273 (tx_ring->wq_id * sizeof(u64));
3277 * Assign doorbell registers for this tx_ring.
3279 /* TX PCI doorbell mem area for tx producer index */
3280 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
3281 tx_ring->prod_idx = 0;
3282 /* TX PCI doorbell mem area + 0x04 */
3283 tx_ring->valid_db_reg = doorbell_area + 0x04;
3286 * Assign shadow registers for this tx_ring.
3288 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
3289 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
3291 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
3292 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
3293 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
3294 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
3296 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
3298 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
3300 ql_init_tx_ring(qdev, tx_ring);
3302 err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
3303 (u16) tx_ring->wq_id);
3305 netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n");
3311 static void ql_disable_msix(struct ql_adapter *qdev)
3313 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3314 pci_disable_msix(qdev->pdev);
3315 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
3316 kfree(qdev->msi_x_entry);
3317 qdev->msi_x_entry = NULL;
3318 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3319 pci_disable_msi(qdev->pdev);
3320 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3324 /* We start by trying to get the number of vectors
3325 * stored in qdev->intr_count. If we don't get that
3326 * many then we reduce the count and try again.
3328 static void ql_enable_msix(struct ql_adapter *qdev)
3332 /* Get the MSIX vectors. */
3333 if (qlge_irq_type == MSIX_IRQ) {
3334 /* Try to alloc space for the msix struct,
3335 * if it fails then go to MSI/legacy.
3337 qdev->msi_x_entry = kcalloc(qdev->intr_count,
3338 sizeof(struct msix_entry),
3340 if (!qdev->msi_x_entry) {
3341 qlge_irq_type = MSI_IRQ;
3345 for (i = 0; i < qdev->intr_count; i++)
3346 qdev->msi_x_entry[i].entry = i;
3348 err = pci_enable_msix_range(qdev->pdev, qdev->msi_x_entry,
3349 1, qdev->intr_count);
3351 kfree(qdev->msi_x_entry);
3352 qdev->msi_x_entry = NULL;
3353 netif_warn(qdev, ifup, qdev->ndev,
3354 "MSI-X Enable failed, trying MSI.\n");
3355 qlge_irq_type = MSI_IRQ;
3357 qdev->intr_count = err;
3358 set_bit(QL_MSIX_ENABLED, &qdev->flags);
3359 netif_info(qdev, ifup, qdev->ndev,
3360 "MSI-X Enabled, got %d vectors.\n",
3366 qdev->intr_count = 1;
3367 if (qlge_irq_type == MSI_IRQ) {
3368 if (!pci_enable_msi(qdev->pdev)) {
3369 set_bit(QL_MSI_ENABLED, &qdev->flags);
3370 netif_info(qdev, ifup, qdev->ndev,
3371 "Running with MSI interrupts.\n");
3375 qlge_irq_type = LEG_IRQ;
3376 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3377 "Running with legacy interrupts.\n");
3380 /* Each vector services 1 RSS ring and and 1 or more
3381 * TX completion rings. This function loops through
3382 * the TX completion rings and assigns the vector that
3383 * will service it. An example would be if there are
3384 * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
3385 * This would mean that vector 0 would service RSS ring 0
3386 * and TX completion rings 0,1,2 and 3. Vector 1 would
3387 * service RSS ring 1 and TX completion rings 4,5,6 and 7.
3389 static void ql_set_tx_vect(struct ql_adapter *qdev)
3392 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3394 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3395 /* Assign irq vectors to TX rx_rings.*/
3396 for (vect = 0, j = 0, i = qdev->rss_ring_count;
3397 i < qdev->rx_ring_count; i++) {
3398 if (j == tx_rings_per_vector) {
3402 qdev->rx_ring[i].irq = vect;
3406 /* For single vector all rings have an irq
3409 for (i = 0; i < qdev->rx_ring_count; i++)
3410 qdev->rx_ring[i].irq = 0;
3414 /* Set the interrupt mask for this vector. Each vector
3415 * will service 1 RSS ring and 1 or more TX completion
3416 * rings. This function sets up a bit mask per vector
3417 * that indicates which rings it services.
3419 static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
3421 int j, vect = ctx->intr;
3422 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3424 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3425 /* Add the RSS ring serviced by this vector
3428 ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
3429 /* Add the TX ring(s) serviced by this vector
3431 for (j = 0; j < tx_rings_per_vector; j++) {
3433 (1 << qdev->rx_ring[qdev->rss_ring_count +
3434 (vect * tx_rings_per_vector) + j].cq_id);
3437 /* For single vector we just shift each queue's
3440 for (j = 0; j < qdev->rx_ring_count; j++)
3441 ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
3446 * Here we build the intr_context structures based on
3447 * our rx_ring count and intr vector count.
3448 * The intr_context structure is used to hook each vector
3449 * to possibly different handlers.
3451 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
3454 struct intr_context *intr_context = &qdev->intr_context[0];
3456 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3457 /* Each rx_ring has it's
3458 * own intr_context since we have separate
3459 * vectors for each queue.
3461 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3462 qdev->rx_ring[i].irq = i;
3463 intr_context->intr = i;
3464 intr_context->qdev = qdev;
3465 /* Set up this vector's bit-mask that indicates
3466 * which queues it services.
3468 ql_set_irq_mask(qdev, intr_context);
3470 * We set up each vectors enable/disable/read bits so
3471 * there's no bit/mask calculations in the critical path.
3473 intr_context->intr_en_mask =
3474 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3475 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
3477 intr_context->intr_dis_mask =
3478 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3479 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
3481 intr_context->intr_read_mask =
3482 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3483 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
3486 /* The first vector/queue handles
3487 * broadcast/multicast, fatal errors,
3488 * and firmware events. This in addition
3489 * to normal inbound NAPI processing.
3491 intr_context->handler = qlge_isr;
3492 sprintf(intr_context->name, "%s-rx-%d",
3493 qdev->ndev->name, i);
3496 * Inbound queues handle unicast frames only.
3498 intr_context->handler = qlge_msix_rx_isr;
3499 sprintf(intr_context->name, "%s-rx-%d",
3500 qdev->ndev->name, i);
3505 * All rx_rings use the same intr_context since
3506 * there is only one vector.
3508 intr_context->intr = 0;
3509 intr_context->qdev = qdev;
3511 * We set up each vectors enable/disable/read bits so
3512 * there's no bit/mask calculations in the critical path.
3514 intr_context->intr_en_mask =
3515 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
3516 intr_context->intr_dis_mask =
3517 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3518 INTR_EN_TYPE_DISABLE;
3519 intr_context->intr_read_mask =
3520 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
3522 * Single interrupt means one handler for all rings.
3524 intr_context->handler = qlge_isr;
3525 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
3526 /* Set up this vector's bit-mask that indicates
3527 * which queues it services. In this case there is
3528 * a single vector so it will service all RSS and
3529 * TX completion rings.
3531 ql_set_irq_mask(qdev, intr_context);
3533 /* Tell the TX completion rings which MSIx vector
3534 * they will be using.
3536 ql_set_tx_vect(qdev);
3539 static void ql_free_irq(struct ql_adapter *qdev)
3542 struct intr_context *intr_context = &qdev->intr_context[0];
3544 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3545 if (intr_context->hooked) {
3546 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3547 free_irq(qdev->msi_x_entry[i].vector,
3550 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
3554 ql_disable_msix(qdev);
3557 static int ql_request_irq(struct ql_adapter *qdev)
3561 struct pci_dev *pdev = qdev->pdev;
3562 struct intr_context *intr_context = &qdev->intr_context[0];
3564 ql_resolve_queues_to_irqs(qdev);
3566 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3567 atomic_set(&intr_context->irq_cnt, 0);
3568 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3569 status = request_irq(qdev->msi_x_entry[i].vector,
3570 intr_context->handler,
3575 netif_err(qdev, ifup, qdev->ndev,
3576 "Failed request for MSIX interrupt %d.\n",
3581 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3582 "trying msi or legacy interrupts.\n");
3583 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3584 "%s: irq = %d.\n", __func__, pdev->irq);
3585 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3586 "%s: context->name = %s.\n", __func__,
3587 intr_context->name);
3588 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3589 "%s: dev_id = 0x%p.\n", __func__,
3592 request_irq(pdev->irq, qlge_isr,
3593 test_bit(QL_MSI_ENABLED,
3595 flags) ? 0 : IRQF_SHARED,
3596 intr_context->name, &qdev->rx_ring[0]);
3600 netif_err(qdev, ifup, qdev->ndev,
3601 "Hooked intr %d, queue type %s, with name %s.\n",
3603 qdev->rx_ring[0].type == DEFAULT_Q ?
3605 qdev->rx_ring[0].type == TX_Q ? "TX_Q" :
3606 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3607 intr_context->name);
3609 intr_context->hooked = 1;
3613 netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!\n");
3618 static int ql_start_rss(struct ql_adapter *qdev)
3620 static const u8 init_hash_seed[] = {
3621 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
3622 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
3623 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
3624 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
3625 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
3627 struct ricb *ricb = &qdev->ricb;
3630 u8 *hash_id = (u8 *) ricb->hash_cq_id;
3632 memset((void *)ricb, 0, sizeof(*ricb));
3634 ricb->base_cq = RSS_L4K;
3636 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
3637 ricb->mask = cpu_to_le16((u16)(0x3ff));
3640 * Fill out the Indirection Table.
3642 for (i = 0; i < 1024; i++)
3643 hash_id[i] = (i & (qdev->rss_ring_count - 1));
3645 memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
3646 memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
3648 status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
3650 netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n");
3656 static int ql_clear_routing_entries(struct ql_adapter *qdev)
3660 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3663 /* Clear all the entries in the routing table. */
3664 for (i = 0; i < 16; i++) {
3665 status = ql_set_routing_reg(qdev, i, 0, 0);
3667 netif_err(qdev, ifup, qdev->ndev,
3668 "Failed to init routing register for CAM packets.\n");
3672 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3676 /* Initialize the frame-to-queue routing. */
3677 static int ql_route_initialize(struct ql_adapter *qdev)
3681 /* Clear all the entries in the routing table. */
3682 status = ql_clear_routing_entries(qdev);
3686 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3690 status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT,
3691 RT_IDX_IP_CSUM_ERR, 1);
3693 netif_err(qdev, ifup, qdev->ndev,
3694 "Failed to init routing register "
3695 "for IP CSUM error packets.\n");
3698 status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT,
3699 RT_IDX_TU_CSUM_ERR, 1);
3701 netif_err(qdev, ifup, qdev->ndev,
3702 "Failed to init routing register "
3703 "for TCP/UDP CSUM error packets.\n");
3706 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3708 netif_err(qdev, ifup, qdev->ndev,
3709 "Failed to init routing register for broadcast packets.\n");
3712 /* If we have more than one inbound queue, then turn on RSS in the
3715 if (qdev->rss_ring_count > 1) {
3716 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3717 RT_IDX_RSS_MATCH, 1);
3719 netif_err(qdev, ifup, qdev->ndev,
3720 "Failed to init routing register for MATCH RSS packets.\n");
3725 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3728 netif_err(qdev, ifup, qdev->ndev,
3729 "Failed to init routing register for CAM packets.\n");
3731 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3735 int ql_cam_route_initialize(struct ql_adapter *qdev)
3739 /* If check if the link is up and use to
3740 * determine if we are setting or clearing
3741 * the MAC address in the CAM.
3743 set = ql_read32(qdev, STS);
3744 set &= qdev->port_link_up;
3745 status = ql_set_mac_addr(qdev, set);
3747 netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n");
3751 status = ql_route_initialize(qdev);
3753 netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n");
3758 static int ql_adapter_initialize(struct ql_adapter *qdev)
3765 * Set up the System register to halt on errors.
3767 value = SYS_EFE | SYS_FAE;
3769 ql_write32(qdev, SYS, mask | value);
3771 /* Set the default queue, and VLAN behavior. */
3772 value = NIC_RCV_CFG_DFQ;
3773 mask = NIC_RCV_CFG_DFQ_MASK;
3774 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3775 value |= NIC_RCV_CFG_RV;
3776 mask |= (NIC_RCV_CFG_RV << 16);
3778 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3780 /* Set the MPI interrupt to enabled. */
3781 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3783 /* Enable the function, set pagesize, enable error checking. */
3784 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3785 FSC_EC | FSC_VM_PAGE_4K;
3786 value |= SPLT_SETTING;
3788 /* Set/clear header splitting. */
3789 mask = FSC_VM_PAGESIZE_MASK |
3790 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3791 ql_write32(qdev, FSC, mask | value);
3793 ql_write32(qdev, SPLT_HDR, SPLT_LEN);
3795 /* Set RX packet routing to use port/pci function on which the
3796 * packet arrived on in addition to usual frame routing.
3797 * This is helpful on bonding where both interfaces can have
3798 * the same MAC address.
3800 ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
3801 /* Reroute all packets to our Interface.
3802 * They may have been routed to MPI firmware
3805 value = ql_read32(qdev, MGMT_RCV_CFG);
3806 value &= ~MGMT_RCV_CFG_RM;
3809 /* Sticky reg needs clearing due to WOL. */
3810 ql_write32(qdev, MGMT_RCV_CFG, mask);
3811 ql_write32(qdev, MGMT_RCV_CFG, mask | value);
3813 /* Default WOL is enable on Mezz cards */
3814 if (qdev->pdev->subsystem_device == 0x0068 ||
3815 qdev->pdev->subsystem_device == 0x0180)
3816 qdev->wol = WAKE_MAGIC;
3818 /* Start up the rx queues. */
3819 for (i = 0; i < qdev->rx_ring_count; i++) {
3820 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3822 netif_err(qdev, ifup, qdev->ndev,
3823 "Failed to start rx ring[%d].\n", i);
3828 /* If there is more than one inbound completion queue
3829 * then download a RICB to configure RSS.
3831 if (qdev->rss_ring_count > 1) {
3832 status = ql_start_rss(qdev);
3834 netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n");
3839 /* Start up the tx queues. */
3840 for (i = 0; i < qdev->tx_ring_count; i++) {
3841 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3843 netif_err(qdev, ifup, qdev->ndev,
3844 "Failed to start tx ring[%d].\n", i);
3849 /* Initialize the port and set the max framesize. */
3850 status = qdev->nic_ops->port_initialize(qdev);
3852 netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n");
3854 /* Set up the MAC address and frame routing filter. */
3855 status = ql_cam_route_initialize(qdev);
3857 netif_err(qdev, ifup, qdev->ndev,
3858 "Failed to init CAM/Routing tables.\n");
3862 /* Start NAPI for the RSS queues. */
3863 for (i = 0; i < qdev->rss_ring_count; i++)
3864 napi_enable(&qdev->rx_ring[i].napi);
3869 /* Issue soft reset to chip. */
3870 static int ql_adapter_reset(struct ql_adapter *qdev)
3874 unsigned long end_jiffies;
3876 /* Clear all the entries in the routing table. */
3877 status = ql_clear_routing_entries(qdev);
3879 netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n");
3883 /* Check if bit is set then skip the mailbox command and
3884 * clear the bit, else we are in normal reset process.
3886 if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) {
3887 /* Stop management traffic. */
3888 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
3890 /* Wait for the NIC and MGMNT FIFOs to empty. */
3891 ql_wait_fifo_empty(qdev);
3893 clear_bit(QL_ASIC_RECOVERY, &qdev->flags);
3895 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3897 end_jiffies = jiffies + usecs_to_jiffies(30);
3899 value = ql_read32(qdev, RST_FO);
3900 if ((value & RST_FO_FR) == 0)
3903 } while (time_before(jiffies, end_jiffies));
3905 if (value & RST_FO_FR) {
3906 netif_err(qdev, ifdown, qdev->ndev,
3907 "ETIMEDOUT!!! errored out of resetting the chip!\n");
3908 status = -ETIMEDOUT;
3911 /* Resume management traffic. */
3912 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
3916 static void ql_display_dev_info(struct net_device *ndev)
3918 struct ql_adapter *qdev = netdev_priv(ndev);
3920 netif_info(qdev, probe, qdev->ndev,
3921 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3922 "XG Roll = %d, XG Rev = %d.\n",
3925 qdev->chip_rev_id & 0x0000000f,
3926 qdev->chip_rev_id >> 4 & 0x0000000f,
3927 qdev->chip_rev_id >> 8 & 0x0000000f,
3928 qdev->chip_rev_id >> 12 & 0x0000000f);
3929 netif_info(qdev, probe, qdev->ndev,
3930 "MAC address %pM\n", ndev->dev_addr);
3933 static int ql_wol(struct ql_adapter *qdev)
3936 u32 wol = MB_WOL_DISABLE;
3938 /* The CAM is still intact after a reset, but if we
3939 * are doing WOL, then we may need to program the
3940 * routing regs. We would also need to issue the mailbox
3941 * commands to instruct the MPI what to do per the ethtool
3945 if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |
3946 WAKE_MCAST | WAKE_BCAST)) {
3947 netif_err(qdev, ifdown, qdev->ndev,
3948 "Unsupported WOL parameter. qdev->wol = 0x%x.\n",
3953 if (qdev->wol & WAKE_MAGIC) {
3954 status = ql_mb_wol_set_magic(qdev, 1);
3956 netif_err(qdev, ifdown, qdev->ndev,
3957 "Failed to set magic packet on %s.\n",
3961 netif_info(qdev, drv, qdev->ndev,
3962 "Enabled magic packet successfully on %s.\n",
3965 wol |= MB_WOL_MAGIC_PKT;
3969 wol |= MB_WOL_MODE_ON;
3970 status = ql_mb_wol_mode(qdev, wol);
3971 netif_err(qdev, drv, qdev->ndev,
3972 "WOL %s (wol code 0x%x) on %s\n",
3973 (status == 0) ? "Successfully set" : "Failed",
3974 wol, qdev->ndev->name);
3980 static void ql_cancel_all_work_sync(struct ql_adapter *qdev)
3983 /* Don't kill the reset worker thread if we
3984 * are in the process of recovery.
3986 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3987 cancel_delayed_work_sync(&qdev->asic_reset_work);
3988 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3989 cancel_delayed_work_sync(&qdev->mpi_work);
3990 cancel_delayed_work_sync(&qdev->mpi_idc_work);
3991 cancel_delayed_work_sync(&qdev->mpi_core_to_log);
3992 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3995 static int ql_adapter_down(struct ql_adapter *qdev)
4001 ql_cancel_all_work_sync(qdev);
4003 for (i = 0; i < qdev->rss_ring_count; i++)
4004 napi_disable(&qdev->rx_ring[i].napi);
4006 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4008 ql_disable_interrupts(qdev);
4010 ql_tx_ring_clean(qdev);
4012 /* Call netif_napi_del() from common point.
4014 for (i = 0; i < qdev->rss_ring_count; i++)
4015 netif_napi_del(&qdev->rx_ring[i].napi);
4017 status = ql_adapter_reset(qdev);
4019 netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n",
4021 ql_free_rx_buffers(qdev);
4026 static int ql_adapter_up(struct ql_adapter *qdev)
4030 err = ql_adapter_initialize(qdev);
4032 netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n");
4035 set_bit(QL_ADAPTER_UP, &qdev->flags);
4036 ql_alloc_rx_buffers(qdev);
4037 /* If the port is initialized and the
4038 * link is up the turn on the carrier.
4040 if ((ql_read32(qdev, STS) & qdev->port_init) &&
4041 (ql_read32(qdev, STS) & qdev->port_link_up))
4043 /* Restore rx mode. */
4044 clear_bit(QL_ALLMULTI, &qdev->flags);
4045 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4046 qlge_set_multicast_list(qdev->ndev);
4048 /* Restore vlan setting. */
4049 qlge_restore_vlan(qdev);
4051 ql_enable_interrupts(qdev);
4052 ql_enable_all_completion_interrupts(qdev);
4053 netif_tx_start_all_queues(qdev->ndev);
4057 ql_adapter_reset(qdev);
4061 static void ql_release_adapter_resources(struct ql_adapter *qdev)
4063 ql_free_mem_resources(qdev);
4067 static int ql_get_adapter_resources(struct ql_adapter *qdev)
4071 if (ql_alloc_mem_resources(qdev)) {
4072 netif_err(qdev, ifup, qdev->ndev, "Unable to allocate memory.\n");
4075 status = ql_request_irq(qdev);
4079 static int qlge_close(struct net_device *ndev)
4081 struct ql_adapter *qdev = netdev_priv(ndev);
4083 /* If we hit pci_channel_io_perm_failure
4084 * failure condition, then we already
4085 * brought the adapter down.
4087 if (test_bit(QL_EEH_FATAL, &qdev->flags)) {
4088 netif_err(qdev, drv, qdev->ndev, "EEH fatal did unload.\n");
4089 clear_bit(QL_EEH_FATAL, &qdev->flags);
4094 * Wait for device to recover from a reset.
4095 * (Rarely happens, but possible.)
4097 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
4099 ql_adapter_down(qdev);
4100 ql_release_adapter_resources(qdev);
4104 static int ql_configure_rings(struct ql_adapter *qdev)
4107 struct rx_ring *rx_ring;
4108 struct tx_ring *tx_ring;
4109 int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
4110 unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4111 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4113 qdev->lbq_buf_order = get_order(lbq_buf_len);
4115 /* In a perfect world we have one RSS ring for each CPU
4116 * and each has it's own vector. To do that we ask for
4117 * cpu_cnt vectors. ql_enable_msix() will adjust the
4118 * vector count to what we actually get. We then
4119 * allocate an RSS ring for each.
4120 * Essentially, we are doing min(cpu_count, msix_vector_count).
4122 qdev->intr_count = cpu_cnt;
4123 ql_enable_msix(qdev);
4124 /* Adjust the RSS ring count to the actual vector count. */
4125 qdev->rss_ring_count = qdev->intr_count;
4126 qdev->tx_ring_count = cpu_cnt;
4127 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
4129 for (i = 0; i < qdev->tx_ring_count; i++) {
4130 tx_ring = &qdev->tx_ring[i];
4131 memset((void *)tx_ring, 0, sizeof(*tx_ring));
4132 tx_ring->qdev = qdev;
4134 tx_ring->wq_len = qdev->tx_ring_size;
4136 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
4139 * The completion queue ID for the tx rings start
4140 * immediately after the rss rings.
4142 tx_ring->cq_id = qdev->rss_ring_count + i;
4145 for (i = 0; i < qdev->rx_ring_count; i++) {
4146 rx_ring = &qdev->rx_ring[i];
4147 memset((void *)rx_ring, 0, sizeof(*rx_ring));
4148 rx_ring->qdev = qdev;
4150 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
4151 if (i < qdev->rss_ring_count) {
4153 * Inbound (RSS) queues.
4155 rx_ring->cq_len = qdev->rx_ring_size;
4157 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4158 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
4160 rx_ring->lbq_len * sizeof(__le64);
4161 rx_ring->lbq_buf_size = (u16)lbq_buf_len;
4162 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
4164 rx_ring->sbq_len * sizeof(__le64);
4165 rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE;
4166 rx_ring->type = RX_Q;
4169 * Outbound queue handles outbound completions only.
4171 /* outbound cq is same size as tx_ring it services. */
4172 rx_ring->cq_len = qdev->tx_ring_size;
4174 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4175 rx_ring->lbq_len = 0;
4176 rx_ring->lbq_size = 0;
4177 rx_ring->lbq_buf_size = 0;
4178 rx_ring->sbq_len = 0;
4179 rx_ring->sbq_size = 0;
4180 rx_ring->sbq_buf_size = 0;
4181 rx_ring->type = TX_Q;
4187 static int qlge_open(struct net_device *ndev)
4190 struct ql_adapter *qdev = netdev_priv(ndev);
4192 err = ql_adapter_reset(qdev);
4196 err = ql_configure_rings(qdev);
4200 err = ql_get_adapter_resources(qdev);
4204 err = ql_adapter_up(qdev);
4211 ql_release_adapter_resources(qdev);
4215 static int ql_change_rx_buffers(struct ql_adapter *qdev)
4217 struct rx_ring *rx_ring;
4221 /* Wait for an outstanding reset to complete. */
4222 if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4225 while (--i && !test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4226 netif_err(qdev, ifup, qdev->ndev,
4227 "Waiting for adapter UP...\n");
4232 netif_err(qdev, ifup, qdev->ndev,
4233 "Timed out waiting for adapter UP\n");
4238 status = ql_adapter_down(qdev);
4242 /* Get the new rx buffer size. */
4243 lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4244 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4245 qdev->lbq_buf_order = get_order(lbq_buf_len);
4247 for (i = 0; i < qdev->rss_ring_count; i++) {
4248 rx_ring = &qdev->rx_ring[i];
4249 /* Set the new size. */
4250 rx_ring->lbq_buf_size = lbq_buf_len;
4253 status = ql_adapter_up(qdev);
4259 netif_alert(qdev, ifup, qdev->ndev,
4260 "Driver up/down cycle failed, closing device.\n");
4261 set_bit(QL_ADAPTER_UP, &qdev->flags);
4262 dev_close(qdev->ndev);
4266 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
4268 struct ql_adapter *qdev = netdev_priv(ndev);
4271 if (ndev->mtu == 1500 && new_mtu == 9000) {
4272 netif_err(qdev, ifup, qdev->ndev, "Changing to jumbo MTU.\n");
4273 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
4274 netif_err(qdev, ifup, qdev->ndev, "Changing to normal MTU.\n");
4278 queue_delayed_work(qdev->workqueue,
4279 &qdev->mpi_port_cfg_work, 3*HZ);
4281 ndev->mtu = new_mtu;
4283 if (!netif_running(qdev->ndev)) {
4287 status = ql_change_rx_buffers(qdev);
4289 netif_err(qdev, ifup, qdev->ndev,
4290 "Changing MTU failed.\n");
4296 static struct net_device_stats *qlge_get_stats(struct net_device
4299 struct ql_adapter *qdev = netdev_priv(ndev);
4300 struct rx_ring *rx_ring = &qdev->rx_ring[0];
4301 struct tx_ring *tx_ring = &qdev->tx_ring[0];
4302 unsigned long pkts, mcast, dropped, errors, bytes;
4306 pkts = mcast = dropped = errors = bytes = 0;
4307 for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) {
4308 pkts += rx_ring->rx_packets;
4309 bytes += rx_ring->rx_bytes;
4310 dropped += rx_ring->rx_dropped;
4311 errors += rx_ring->rx_errors;
4312 mcast += rx_ring->rx_multicast;
4314 ndev->stats.rx_packets = pkts;
4315 ndev->stats.rx_bytes = bytes;
4316 ndev->stats.rx_dropped = dropped;
4317 ndev->stats.rx_errors = errors;
4318 ndev->stats.multicast = mcast;
4321 pkts = errors = bytes = 0;
4322 for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) {
4323 pkts += tx_ring->tx_packets;
4324 bytes += tx_ring->tx_bytes;
4325 errors += tx_ring->tx_errors;
4327 ndev->stats.tx_packets = pkts;
4328 ndev->stats.tx_bytes = bytes;
4329 ndev->stats.tx_errors = errors;
4330 return &ndev->stats;
4333 static void qlge_set_multicast_list(struct net_device *ndev)
4335 struct ql_adapter *qdev = netdev_priv(ndev);
4336 struct netdev_hw_addr *ha;
4339 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
4343 * Set or clear promiscuous mode if a
4344 * transition is taking place.
4346 if (ndev->flags & IFF_PROMISC) {
4347 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4348 if (ql_set_routing_reg
4349 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
4350 netif_err(qdev, hw, qdev->ndev,
4351 "Failed to set promiscuous mode.\n");
4353 set_bit(QL_PROMISCUOUS, &qdev->flags);
4357 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4358 if (ql_set_routing_reg
4359 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
4360 netif_err(qdev, hw, qdev->ndev,
4361 "Failed to clear promiscuous mode.\n");
4363 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4369 * Set or clear all multicast mode if a
4370 * transition is taking place.
4372 if ((ndev->flags & IFF_ALLMULTI) ||
4373 (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) {
4374 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
4375 if (ql_set_routing_reg
4376 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
4377 netif_err(qdev, hw, qdev->ndev,
4378 "Failed to set all-multi mode.\n");
4380 set_bit(QL_ALLMULTI, &qdev->flags);
4384 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
4385 if (ql_set_routing_reg
4386 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
4387 netif_err(qdev, hw, qdev->ndev,
4388 "Failed to clear all-multi mode.\n");
4390 clear_bit(QL_ALLMULTI, &qdev->flags);
4395 if (!netdev_mc_empty(ndev)) {
4396 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4400 netdev_for_each_mc_addr(ha, ndev) {
4401 if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr,
4402 MAC_ADDR_TYPE_MULTI_MAC, i)) {
4403 netif_err(qdev, hw, qdev->ndev,
4404 "Failed to loadmulticast address.\n");
4405 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4410 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4411 if (ql_set_routing_reg
4412 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
4413 netif_err(qdev, hw, qdev->ndev,
4414 "Failed to set multicast match mode.\n");
4416 set_bit(QL_ALLMULTI, &qdev->flags);
4420 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
4423 static int qlge_set_mac_address(struct net_device *ndev, void *p)
4425 struct ql_adapter *qdev = netdev_priv(ndev);
4426 struct sockaddr *addr = p;
4429 if (!is_valid_ether_addr(addr->sa_data))
4430 return -EADDRNOTAVAIL;
4431 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
4432 /* Update local copy of current mac address. */
4433 memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4435 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4438 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
4439 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
4441 netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n");
4442 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4446 static void qlge_tx_timeout(struct net_device *ndev)
4448 struct ql_adapter *qdev = netdev_priv(ndev);
4449 ql_queue_asic_error(qdev);
4452 static void ql_asic_reset_work(struct work_struct *work)
4454 struct ql_adapter *qdev =
4455 container_of(work, struct ql_adapter, asic_reset_work.work);
4458 status = ql_adapter_down(qdev);
4462 status = ql_adapter_up(qdev);
4466 /* Restore rx mode. */
4467 clear_bit(QL_ALLMULTI, &qdev->flags);
4468 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4469 qlge_set_multicast_list(qdev->ndev);
4474 netif_alert(qdev, ifup, qdev->ndev,
4475 "Driver up/down cycle failed, closing device\n");
4477 set_bit(QL_ADAPTER_UP, &qdev->flags);
4478 dev_close(qdev->ndev);
4482 static const struct nic_operations qla8012_nic_ops = {
4483 .get_flash = ql_get_8012_flash_params,
4484 .port_initialize = ql_8012_port_initialize,
4487 static const struct nic_operations qla8000_nic_ops = {
4488 .get_flash = ql_get_8000_flash_params,
4489 .port_initialize = ql_8000_port_initialize,
4492 /* Find the pcie function number for the other NIC
4493 * on this chip. Since both NIC functions share a
4494 * common firmware we have the lowest enabled function
4495 * do any common work. Examples would be resetting
4496 * after a fatal firmware error, or doing a firmware
4499 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
4503 u32 nic_func1, nic_func2;
4505 status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
4510 nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
4511 MPI_TEST_NIC_FUNC_MASK);
4512 nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
4513 MPI_TEST_NIC_FUNC_MASK);
4515 if (qdev->func == nic_func1)
4516 qdev->alt_func = nic_func2;
4517 else if (qdev->func == nic_func2)
4518 qdev->alt_func = nic_func1;
4525 static int ql_get_board_info(struct ql_adapter *qdev)
4529 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
4533 status = ql_get_alt_pcie_func(qdev);
4537 qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
4539 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
4540 qdev->port_link_up = STS_PL1;
4541 qdev->port_init = STS_PI1;
4542 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
4543 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
4545 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
4546 qdev->port_link_up = STS_PL0;
4547 qdev->port_init = STS_PI0;
4548 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
4549 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
4551 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
4552 qdev->device_id = qdev->pdev->device;
4553 if (qdev->device_id == QLGE_DEVICE_ID_8012)
4554 qdev->nic_ops = &qla8012_nic_ops;
4555 else if (qdev->device_id == QLGE_DEVICE_ID_8000)
4556 qdev->nic_ops = &qla8000_nic_ops;
4560 static void ql_release_all(struct pci_dev *pdev)
4562 struct net_device *ndev = pci_get_drvdata(pdev);
4563 struct ql_adapter *qdev = netdev_priv(ndev);
4565 if (qdev->workqueue) {
4566 destroy_workqueue(qdev->workqueue);
4567 qdev->workqueue = NULL;
4571 iounmap(qdev->reg_base);
4572 if (qdev->doorbell_area)
4573 iounmap(qdev->doorbell_area);
4574 vfree(qdev->mpi_coredump);
4575 pci_release_regions(pdev);
4578 static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev,
4581 struct ql_adapter *qdev = netdev_priv(ndev);
4584 memset((void *)qdev, 0, sizeof(*qdev));
4585 err = pci_enable_device(pdev);
4587 dev_err(&pdev->dev, "PCI device enable failed.\n");
4593 pci_set_drvdata(pdev, ndev);
4595 /* Set PCIe read request size */
4596 err = pcie_set_readrq(pdev, 4096);
4598 dev_err(&pdev->dev, "Set readrq failed.\n");
4602 err = pci_request_regions(pdev, DRV_NAME);
4604 dev_err(&pdev->dev, "PCI region request failed.\n");
4608 pci_set_master(pdev);
4609 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4610 set_bit(QL_DMA64, &qdev->flags);
4611 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4613 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4615 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4619 dev_err(&pdev->dev, "No usable DMA configuration.\n");
4623 /* Set PCIe reset type for EEH to fundamental. */
4624 pdev->needs_freset = 1;
4625 pci_save_state(pdev);
4627 ioremap_nocache(pci_resource_start(pdev, 1),
4628 pci_resource_len(pdev, 1));
4629 if (!qdev->reg_base) {
4630 dev_err(&pdev->dev, "Register mapping failed.\n");
4635 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
4636 qdev->doorbell_area =
4637 ioremap_nocache(pci_resource_start(pdev, 3),
4638 pci_resource_len(pdev, 3));
4639 if (!qdev->doorbell_area) {
4640 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
4645 err = ql_get_board_info(qdev);
4647 dev_err(&pdev->dev, "Register access failed.\n");
4651 qdev->msg_enable = netif_msg_init(debug, default_msg);
4652 spin_lock_init(&qdev->hw_lock);
4653 spin_lock_init(&qdev->stats_lock);
4655 if (qlge_mpi_coredump) {
4656 qdev->mpi_coredump =
4657 vmalloc(sizeof(struct ql_mpi_coredump));
4658 if (qdev->mpi_coredump == NULL) {
4662 if (qlge_force_coredump)
4663 set_bit(QL_FRC_COREDUMP, &qdev->flags);
4665 /* make sure the EEPROM is good */
4666 err = qdev->nic_ops->get_flash(qdev);
4668 dev_err(&pdev->dev, "Invalid FLASH.\n");
4672 /* Keep local copy of current mac address. */
4673 memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4675 /* Set up the default ring sizes. */
4676 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
4677 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
4679 /* Set up the coalescing parameters. */
4680 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
4681 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
4682 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4683 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4686 * Set up the operating parameters.
4688 qdev->workqueue = alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM,
4690 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
4691 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
4692 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
4693 INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
4694 INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
4695 INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log);
4696 init_completion(&qdev->ide_completion);
4697 mutex_init(&qdev->mpi_mutex);
4700 dev_info(&pdev->dev, "%s\n", DRV_STRING);
4701 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
4702 DRV_NAME, DRV_VERSION);
4706 ql_release_all(pdev);
4708 pci_disable_device(pdev);
4712 static const struct net_device_ops qlge_netdev_ops = {
4713 .ndo_open = qlge_open,
4714 .ndo_stop = qlge_close,
4715 .ndo_start_xmit = qlge_send,
4716 .ndo_change_mtu = qlge_change_mtu,
4717 .ndo_get_stats = qlge_get_stats,
4718 .ndo_set_rx_mode = qlge_set_multicast_list,
4719 .ndo_set_mac_address = qlge_set_mac_address,
4720 .ndo_validate_addr = eth_validate_addr,
4721 .ndo_tx_timeout = qlge_tx_timeout,
4722 .ndo_fix_features = qlge_fix_features,
4723 .ndo_set_features = qlge_set_features,
4724 .ndo_vlan_rx_add_vid = qlge_vlan_rx_add_vid,
4725 .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid,
4728 static void ql_timer(struct timer_list *t)
4730 struct ql_adapter *qdev = from_timer(qdev, t, timer);
4733 var = ql_read32(qdev, STS);
4734 if (pci_channel_offline(qdev->pdev)) {
4735 netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var);
4739 mod_timer(&qdev->timer, jiffies + (5*HZ));
4742 static int qlge_probe(struct pci_dev *pdev,
4743 const struct pci_device_id *pci_entry)
4745 struct net_device *ndev = NULL;
4746 struct ql_adapter *qdev = NULL;
4747 static int cards_found = 0;
4750 ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
4751 min(MAX_CPUS, netif_get_num_default_rss_queues()));
4755 err = ql_init_device(pdev, ndev, cards_found);
4761 qdev = netdev_priv(ndev);
4762 SET_NETDEV_DEV(ndev, &pdev->dev);
4763 ndev->hw_features = NETIF_F_SG |
4767 NETIF_F_HW_VLAN_CTAG_TX |
4768 NETIF_F_HW_VLAN_CTAG_RX |
4769 NETIF_F_HW_VLAN_CTAG_FILTER |
4771 ndev->features = ndev->hw_features;
4772 ndev->vlan_features = ndev->hw_features;
4773 /* vlan gets same features (except vlan filter) */
4774 ndev->vlan_features &= ~(NETIF_F_HW_VLAN_CTAG_FILTER |
4775 NETIF_F_HW_VLAN_CTAG_TX |
4776 NETIF_F_HW_VLAN_CTAG_RX);
4778 if (test_bit(QL_DMA64, &qdev->flags))
4779 ndev->features |= NETIF_F_HIGHDMA;
4782 * Set up net_device structure.
4784 ndev->tx_queue_len = qdev->tx_ring_size;
4785 ndev->irq = pdev->irq;
4787 ndev->netdev_ops = &qlge_netdev_ops;
4788 ndev->ethtool_ops = &qlge_ethtool_ops;
4789 ndev->watchdog_timeo = 10 * HZ;
4791 /* MTU range: this driver only supports 1500 or 9000, so this only
4792 * filters out values above or below, and we'll rely on
4793 * qlge_change_mtu to make sure only 1500 or 9000 are allowed
4795 ndev->min_mtu = ETH_DATA_LEN;
4796 ndev->max_mtu = 9000;
4798 err = register_netdev(ndev);
4800 dev_err(&pdev->dev, "net device registration failed.\n");
4801 ql_release_all(pdev);
4802 pci_disable_device(pdev);
4806 /* Start up the timer to trigger EEH if
4809 timer_setup(&qdev->timer, ql_timer, TIMER_DEFERRABLE);
4810 mod_timer(&qdev->timer, jiffies + (5*HZ));
4812 ql_display_dev_info(ndev);
4813 atomic_set(&qdev->lb_count, 0);
4818 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev)
4820 return qlge_send(skb, ndev);
4823 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget)
4825 return ql_clean_inbound_rx_ring(rx_ring, budget);
4828 static void qlge_remove(struct pci_dev *pdev)
4830 struct net_device *ndev = pci_get_drvdata(pdev);
4831 struct ql_adapter *qdev = netdev_priv(ndev);
4832 del_timer_sync(&qdev->timer);
4833 ql_cancel_all_work_sync(qdev);
4834 unregister_netdev(ndev);
4835 ql_release_all(pdev);
4836 pci_disable_device(pdev);
4840 /* Clean up resources without touching hardware. */
4841 static void ql_eeh_close(struct net_device *ndev)
4844 struct ql_adapter *qdev = netdev_priv(ndev);
4846 if (netif_carrier_ok(ndev)) {
4847 netif_carrier_off(ndev);
4848 netif_stop_queue(ndev);
4851 /* Disabling the timer */
4852 ql_cancel_all_work_sync(qdev);
4854 for (i = 0; i < qdev->rss_ring_count; i++)
4855 netif_napi_del(&qdev->rx_ring[i].napi);
4857 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4858 ql_tx_ring_clean(qdev);
4859 ql_free_rx_buffers(qdev);
4860 ql_release_adapter_resources(qdev);
4864 * This callback is called by the PCI subsystem whenever
4865 * a PCI bus error is detected.
4867 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4868 enum pci_channel_state state)
4870 struct net_device *ndev = pci_get_drvdata(pdev);
4871 struct ql_adapter *qdev = netdev_priv(ndev);
4874 case pci_channel_io_normal:
4875 return PCI_ERS_RESULT_CAN_RECOVER;
4876 case pci_channel_io_frozen:
4877 netif_device_detach(ndev);
4878 del_timer_sync(&qdev->timer);
4879 if (netif_running(ndev))
4881 pci_disable_device(pdev);
4882 return PCI_ERS_RESULT_NEED_RESET;
4883 case pci_channel_io_perm_failure:
4885 "%s: pci_channel_io_perm_failure.\n", __func__);
4886 del_timer_sync(&qdev->timer);
4888 set_bit(QL_EEH_FATAL, &qdev->flags);
4889 return PCI_ERS_RESULT_DISCONNECT;
4892 /* Request a slot reset. */
4893 return PCI_ERS_RESULT_NEED_RESET;
4897 * This callback is called after the PCI buss has been reset.
4898 * Basically, this tries to restart the card from scratch.
4899 * This is a shortened version of the device probe/discovery code,
4900 * it resembles the first-half of the () routine.
4902 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4904 struct net_device *ndev = pci_get_drvdata(pdev);
4905 struct ql_adapter *qdev = netdev_priv(ndev);
4907 pdev->error_state = pci_channel_io_normal;
4909 pci_restore_state(pdev);
4910 if (pci_enable_device(pdev)) {
4911 netif_err(qdev, ifup, qdev->ndev,
4912 "Cannot re-enable PCI device after reset.\n");
4913 return PCI_ERS_RESULT_DISCONNECT;
4915 pci_set_master(pdev);
4917 if (ql_adapter_reset(qdev)) {
4918 netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n");
4919 set_bit(QL_EEH_FATAL, &qdev->flags);
4920 return PCI_ERS_RESULT_DISCONNECT;
4923 return PCI_ERS_RESULT_RECOVERED;
4926 static void qlge_io_resume(struct pci_dev *pdev)
4928 struct net_device *ndev = pci_get_drvdata(pdev);
4929 struct ql_adapter *qdev = netdev_priv(ndev);
4932 if (netif_running(ndev)) {
4933 err = qlge_open(ndev);
4935 netif_err(qdev, ifup, qdev->ndev,
4936 "Device initialization failed after reset.\n");
4940 netif_err(qdev, ifup, qdev->ndev,
4941 "Device was not running prior to EEH.\n");
4943 mod_timer(&qdev->timer, jiffies + (5*HZ));
4944 netif_device_attach(ndev);
4947 static const struct pci_error_handlers qlge_err_handler = {
4948 .error_detected = qlge_io_error_detected,
4949 .slot_reset = qlge_io_slot_reset,
4950 .resume = qlge_io_resume,
4953 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4955 struct net_device *ndev = pci_get_drvdata(pdev);
4956 struct ql_adapter *qdev = netdev_priv(ndev);
4959 netif_device_detach(ndev);
4960 del_timer_sync(&qdev->timer);
4962 if (netif_running(ndev)) {
4963 err = ql_adapter_down(qdev);
4969 err = pci_save_state(pdev);
4973 pci_disable_device(pdev);
4975 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4981 static int qlge_resume(struct pci_dev *pdev)
4983 struct net_device *ndev = pci_get_drvdata(pdev);
4984 struct ql_adapter *qdev = netdev_priv(ndev);
4987 pci_set_power_state(pdev, PCI_D0);
4988 pci_restore_state(pdev);
4989 err = pci_enable_device(pdev);
4991 netif_err(qdev, ifup, qdev->ndev, "Cannot enable PCI device from suspend\n");
4994 pci_set_master(pdev);
4996 pci_enable_wake(pdev, PCI_D3hot, 0);
4997 pci_enable_wake(pdev, PCI_D3cold, 0);
4999 if (netif_running(ndev)) {
5000 err = ql_adapter_up(qdev);
5005 mod_timer(&qdev->timer, jiffies + (5*HZ));
5006 netif_device_attach(ndev);
5010 #endif /* CONFIG_PM */
5012 static void qlge_shutdown(struct pci_dev *pdev)
5014 qlge_suspend(pdev, PMSG_SUSPEND);
5017 static struct pci_driver qlge_driver = {
5019 .id_table = qlge_pci_tbl,
5020 .probe = qlge_probe,
5021 .remove = qlge_remove,
5023 .suspend = qlge_suspend,
5024 .resume = qlge_resume,
5026 .shutdown = qlge_shutdown,
5027 .err_handler = &qlge_err_handler
5030 module_pci_driver(qlge_driver);