2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qla3xxx for copyright and licensing details.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/list.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/if_arp.h>
28 #include <linux/if_ether.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/skbuff.h>
33 #include <linux/rtnetlink.h>
34 #include <linux/if_vlan.h>
35 #include <linux/delay.h>
37 #include <linux/prefetch.h>
41 #define DRV_NAME "qla3xxx"
42 #define DRV_STRING "QLogic ISP3XXX Network Driver"
43 #define DRV_VERSION "v2.03.00-k5"
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
48 #define TIMED_OUT_MSG \
49 "Timed out waiting for management port to get free before issuing command\n"
51 MODULE_AUTHOR("QLogic Corporation");
52 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
53 MODULE_LICENSE("GPL");
54 MODULE_VERSION(DRV_VERSION);
56 static const u32 default_msg
57 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
58 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
60 static int debug = -1; /* defaults above */
61 module_param(debug, int, 0);
62 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
65 module_param(msi, int, 0);
66 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
68 static const struct pci_device_id ql3xxx_pci_tbl[] = {
69 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
70 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
71 /* required last entry */
75 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
78 * These are the known PHY's which are used
80 enum PHY_DEVICE_TYPE {
87 struct PHY_DEVICE_INFO {
88 const enum PHY_DEVICE_TYPE phyDevice;
94 static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
95 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
96 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
97 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
102 * Caller must take hw_lock.
104 static int ql_sem_spinlock(struct ql3_adapter *qdev,
105 u32 sem_mask, u32 sem_bits)
107 struct ql3xxx_port_registers __iomem *port_regs =
108 qdev->mem_map_registers;
110 unsigned int seconds = 3;
113 writel((sem_mask | sem_bits),
114 &port_regs->CommonRegs.semaphoreReg);
115 value = readl(&port_regs->CommonRegs.semaphoreReg);
116 if ((value & (sem_mask >> 16)) == sem_bits)
123 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
125 struct ql3xxx_port_registers __iomem *port_regs =
126 qdev->mem_map_registers;
127 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
128 readl(&port_regs->CommonRegs.semaphoreReg);
131 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
133 struct ql3xxx_port_registers __iomem *port_regs =
134 qdev->mem_map_registers;
137 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
138 value = readl(&port_regs->CommonRegs.semaphoreReg);
139 return ((value & (sem_mask >> 16)) == sem_bits);
143 * Caller holds hw_lock.
145 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
150 if (ql_sem_lock(qdev,
152 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
154 netdev_printk(KERN_DEBUG, qdev->ndev,
155 "driver lock acquired\n");
161 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
165 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
167 struct ql3xxx_port_registers __iomem *port_regs =
168 qdev->mem_map_registers;
170 writel(((ISP_CONTROL_NP_MASK << 16) | page),
171 &port_regs->CommonRegs.ispControlStatus);
172 readl(&port_regs->CommonRegs.ispControlStatus);
173 qdev->current_page = page;
176 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
179 unsigned long hw_flags;
181 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
188 static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
193 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
196 unsigned long hw_flags;
198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
200 if (qdev->current_page != 0)
201 ql_set_register_page(qdev, 0);
204 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
208 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
210 if (qdev->current_page != 0)
211 ql_set_register_page(qdev, 0);
215 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
216 u32 __iomem *reg, u32 value)
218 unsigned long hw_flags;
220 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
223 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
226 static void ql_write_common_reg(struct ql3_adapter *qdev,
227 u32 __iomem *reg, u32 value)
233 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
234 u32 __iomem *reg, u32 value)
241 static void ql_write_page0_reg(struct ql3_adapter *qdev,
242 u32 __iomem *reg, u32 value)
244 if (qdev->current_page != 0)
245 ql_set_register_page(qdev, 0);
251 * Caller holds hw_lock. Only called during init.
253 static void ql_write_page1_reg(struct ql3_adapter *qdev,
254 u32 __iomem *reg, u32 value)
256 if (qdev->current_page != 1)
257 ql_set_register_page(qdev, 1);
263 * Caller holds hw_lock. Only called during init.
265 static void ql_write_page2_reg(struct ql3_adapter *qdev,
266 u32 __iomem *reg, u32 value)
268 if (qdev->current_page != 2)
269 ql_set_register_page(qdev, 2);
274 static void ql_disable_interrupts(struct ql3_adapter *qdev)
276 struct ql3xxx_port_registers __iomem *port_regs =
277 qdev->mem_map_registers;
279 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
280 (ISP_IMR_ENABLE_INT << 16));
284 static void ql_enable_interrupts(struct ql3_adapter *qdev)
286 struct ql3xxx_port_registers __iomem *port_regs =
287 qdev->mem_map_registers;
289 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
290 ((0xff << 16) | ISP_IMR_ENABLE_INT));
294 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
295 struct ql_rcv_buf_cb *lrg_buf_cb)
299 lrg_buf_cb->next = NULL;
301 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
302 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
304 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
305 qdev->lrg_buf_free_tail = lrg_buf_cb;
308 if (!lrg_buf_cb->skb) {
309 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
310 qdev->lrg_buffer_len);
311 if (unlikely(!lrg_buf_cb->skb)) {
312 qdev->lrg_buf_skb_check++;
315 * We save some space to copy the ethhdr from first
318 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
319 map = pci_map_single(qdev->pdev,
320 lrg_buf_cb->skb->data,
321 qdev->lrg_buffer_len -
324 err = pci_dma_mapping_error(qdev->pdev, map);
326 netdev_err(qdev->ndev,
327 "PCI mapping failed with error: %d\n",
329 dev_kfree_skb(lrg_buf_cb->skb);
330 lrg_buf_cb->skb = NULL;
332 qdev->lrg_buf_skb_check++;
336 lrg_buf_cb->buf_phy_addr_low =
337 cpu_to_le32(LS_64BITS(map));
338 lrg_buf_cb->buf_phy_addr_high =
339 cpu_to_le32(MS_64BITS(map));
340 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
341 dma_unmap_len_set(lrg_buf_cb, maplen,
342 qdev->lrg_buffer_len -
347 qdev->lrg_buf_free_count++;
350 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
353 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
355 if (lrg_buf_cb != NULL) {
356 qdev->lrg_buf_free_head = lrg_buf_cb->next;
357 if (qdev->lrg_buf_free_head == NULL)
358 qdev->lrg_buf_free_tail = NULL;
359 qdev->lrg_buf_free_count--;
365 static u32 addrBits = EEPROM_NO_ADDR_BITS;
366 static u32 dataBits = EEPROM_NO_DATA_BITS;
368 static void fm93c56a_deselect(struct ql3_adapter *qdev);
369 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
370 unsigned short *value);
373 * Caller holds hw_lock.
375 static void fm93c56a_select(struct ql3_adapter *qdev)
377 struct ql3xxx_port_registers __iomem *port_regs =
378 qdev->mem_map_registers;
379 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
381 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
382 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
386 * Caller holds hw_lock.
388 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
394 struct ql3xxx_port_registers __iomem *port_regs =
395 qdev->mem_map_registers;
396 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
398 /* Clock in a zero, then do the start bit */
399 ql_write_nvram_reg(qdev, spir,
400 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
401 AUBURN_EEPROM_DO_1));
402 ql_write_nvram_reg(qdev, spir,
403 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
404 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
405 ql_write_nvram_reg(qdev, spir,
406 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
409 mask = 1 << (FM93C56A_CMD_BITS - 1);
410 /* Force the previous data bit to be different */
411 previousBit = 0xffff;
412 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
413 dataBit = (cmd & mask)
415 : AUBURN_EEPROM_DO_0;
416 if (previousBit != dataBit) {
417 /* If the bit changed, change the DO state to match */
418 ql_write_nvram_reg(qdev, spir,
420 qdev->eeprom_cmd_data | dataBit));
421 previousBit = dataBit;
423 ql_write_nvram_reg(qdev, spir,
424 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
425 dataBit | AUBURN_EEPROM_CLK_RISE));
426 ql_write_nvram_reg(qdev, spir,
427 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
428 dataBit | AUBURN_EEPROM_CLK_FALL));
432 mask = 1 << (addrBits - 1);
433 /* Force the previous data bit to be different */
434 previousBit = 0xffff;
435 for (i = 0; i < addrBits; i++) {
436 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
437 : AUBURN_EEPROM_DO_0;
438 if (previousBit != dataBit) {
440 * If the bit changed, then change the DO state to
443 ql_write_nvram_reg(qdev, spir,
445 qdev->eeprom_cmd_data | dataBit));
446 previousBit = dataBit;
448 ql_write_nvram_reg(qdev, spir,
449 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
450 dataBit | AUBURN_EEPROM_CLK_RISE));
451 ql_write_nvram_reg(qdev, spir,
452 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
453 dataBit | AUBURN_EEPROM_CLK_FALL));
454 eepromAddr = eepromAddr << 1;
459 * Caller holds hw_lock.
461 static void fm93c56a_deselect(struct ql3_adapter *qdev)
463 struct ql3xxx_port_registers __iomem *port_regs =
464 qdev->mem_map_registers;
465 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
467 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
468 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
472 * Caller holds hw_lock.
474 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
479 struct ql3xxx_port_registers __iomem *port_regs =
480 qdev->mem_map_registers;
481 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
483 /* Read the data bits */
484 /* The first bit is a dummy. Clock right over it. */
485 for (i = 0; i < dataBits; i++) {
486 ql_write_nvram_reg(qdev, spir,
487 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
488 AUBURN_EEPROM_CLK_RISE);
489 ql_write_nvram_reg(qdev, spir,
490 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
491 AUBURN_EEPROM_CLK_FALL);
492 dataBit = (ql_read_common_reg(qdev, spir) &
493 AUBURN_EEPROM_DI_1) ? 1 : 0;
494 data = (data << 1) | dataBit;
500 * Caller holds hw_lock.
502 static void eeprom_readword(struct ql3_adapter *qdev,
503 u32 eepromAddr, unsigned short *value)
505 fm93c56a_select(qdev);
506 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
507 fm93c56a_datain(qdev, value);
508 fm93c56a_deselect(qdev);
511 static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
513 __le16 *p = (__le16 *)ndev->dev_addr;
514 p[0] = cpu_to_le16(addr[0]);
515 p[1] = cpu_to_le16(addr[1]);
516 p[2] = cpu_to_le16(addr[2]);
519 static int ql_get_nvram_params(struct ql3_adapter *qdev)
524 unsigned long hw_flags;
526 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
528 pEEPROMData = (u16 *)&qdev->nvram_data;
529 qdev->eeprom_cmd_data = 0;
530 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
531 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
533 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
534 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
538 for (index = 0; index < EEPROM_SIZE; index++) {
539 eeprom_readword(qdev, index, pEEPROMData);
540 checksum += *pEEPROMData;
543 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
546 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
548 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
552 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
556 static const u32 PHYAddr[2] = {
557 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
560 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
562 struct ql3xxx_port_registers __iomem *port_regs =
563 qdev->mem_map_registers;
568 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
569 if (!(temp & MAC_MII_STATUS_BSY))
577 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
579 struct ql3xxx_port_registers __iomem *port_regs =
580 qdev->mem_map_registers;
583 if (qdev->numPorts > 1) {
584 /* Auto scan will cycle through multiple ports */
585 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
587 scanControl = MAC_MII_CONTROL_SC;
591 * Scan register 1 of PHY/PETBI,
592 * Set up to scan both devices
593 * The autoscan starts from the first register, completes
594 * the last one before rolling over to the first
596 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
597 PHYAddr[0] | MII_SCAN_REGISTER);
599 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
601 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
604 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
607 struct ql3xxx_port_registers __iomem *port_regs =
608 qdev->mem_map_registers;
610 /* See if scan mode is enabled before we turn it off */
611 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
612 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
613 /* Scan is enabled */
616 /* Scan is disabled */
621 * When disabling scan mode you must first change the MII register
624 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
625 PHYAddr[0] | MII_SCAN_REGISTER);
627 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
628 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
629 MAC_MII_CONTROL_RC) << 16));
634 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
635 u16 regAddr, u16 value, u32 phyAddr)
637 struct ql3xxx_port_registers __iomem *port_regs =
638 qdev->mem_map_registers;
641 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
643 if (ql_wait_for_mii_ready(qdev)) {
644 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
648 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
653 /* Wait for write to complete 9/10/04 SJP */
654 if (ql_wait_for_mii_ready(qdev)) {
655 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
660 ql_mii_enable_scan_mode(qdev);
665 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
666 u16 *value, u32 phyAddr)
668 struct ql3xxx_port_registers __iomem *port_regs =
669 qdev->mem_map_registers;
673 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
675 if (ql_wait_for_mii_ready(qdev)) {
676 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
680 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
684 (MAC_MII_CONTROL_RC << 16));
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
687 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
689 /* Wait for the read to complete */
690 if (ql_wait_for_mii_ready(qdev)) {
691 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
695 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
699 ql_mii_enable_scan_mode(qdev);
704 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
706 struct ql3xxx_port_registers __iomem *port_regs =
707 qdev->mem_map_registers;
709 ql_mii_disable_scan_mode(qdev);
711 if (ql_wait_for_mii_ready(qdev)) {
712 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
716 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
717 qdev->PHYAddr | regAddr);
719 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
721 /* Wait for write to complete. */
722 if (ql_wait_for_mii_ready(qdev)) {
723 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
727 ql_mii_enable_scan_mode(qdev);
732 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
735 struct ql3xxx_port_registers __iomem *port_regs =
736 qdev->mem_map_registers;
738 ql_mii_disable_scan_mode(qdev);
740 if (ql_wait_for_mii_ready(qdev)) {
741 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
746 qdev->PHYAddr | regAddr);
748 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
749 (MAC_MII_CONTROL_RC << 16));
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
752 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
754 /* Wait for the read to complete */
755 if (ql_wait_for_mii_ready(qdev)) {
756 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
760 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
763 ql_mii_enable_scan_mode(qdev);
768 static void ql_petbi_reset(struct ql3_adapter *qdev)
770 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
773 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
777 /* Enable Auto-negotiation sense */
778 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
779 reg |= PETBI_TBI_AUTO_SENSE;
780 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
782 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
783 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
785 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
786 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
787 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
791 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
793 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
794 PHYAddr[qdev->mac_index]);
797 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
801 /* Enable Auto-negotiation sense */
802 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
803 PHYAddr[qdev->mac_index]);
804 reg |= PETBI_TBI_AUTO_SENSE;
805 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
806 PHYAddr[qdev->mac_index]);
808 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
809 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
810 PHYAddr[qdev->mac_index]);
812 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
813 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
814 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
815 PHYAddr[qdev->mac_index]);
818 static void ql_petbi_init(struct ql3_adapter *qdev)
820 ql_petbi_reset(qdev);
821 ql_petbi_start_neg(qdev);
824 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
826 ql_petbi_reset_ex(qdev);
827 ql_petbi_start_neg_ex(qdev);
830 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
834 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
837 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
840 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
842 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
843 /* power down device bit 11 = 1 */
844 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
845 /* enable diagnostic mode bit 2 = 1 */
846 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
847 /* 1000MB amplitude adjust (see Agere errata) */
848 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
849 /* 1000MB amplitude adjust (see Agere errata) */
850 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
851 /* 100MB amplitude adjust (see Agere errata) */
852 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
853 /* 100MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
855 /* 10MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
857 /* 10MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
859 /* point to hidden reg 0x2806 */
860 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
861 /* Write new PHYAD w/bit 5 set */
862 ql_mii_write_reg_ex(qdev, 0x11,
863 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
865 * Disable diagnostic mode bit 2 = 0
866 * Power up device bit 11 = 0
867 * Link up (on) and activity (blink)
869 ql_mii_write_reg(qdev, 0x12, 0x840a);
870 ql_mii_write_reg(qdev, 0x00, 0x1140);
871 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
874 static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
875 u16 phyIdReg0, u16 phyIdReg1)
877 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
882 if (phyIdReg0 == 0xffff)
885 if (phyIdReg1 == 0xffff)
888 /* oui is split between two registers */
889 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
891 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
893 /* Scan table for this PHY */
894 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
895 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
896 (model == PHY_DEVICES[i].phyIdModel)) {
897 netdev_info(qdev->ndev, "Phy: %s\n",
898 PHY_DEVICES[i].name);
899 result = PHY_DEVICES[i].phyDevice;
907 static int ql_phy_get_speed(struct ql3_adapter *qdev)
911 switch (qdev->phyType) {
912 case PHY_AGERE_ET1011C: {
913 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
916 reg = (reg >> 8) & 3;
920 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
923 reg = (((reg & 0x18) >> 3) & 3);
938 static int ql_is_full_dup(struct ql3_adapter *qdev)
942 switch (qdev->phyType) {
943 case PHY_AGERE_ET1011C: {
944 if (ql_mii_read_reg(qdev, 0x1A, ®))
947 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
949 case PHY_VITESSE_VSC8211:
951 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
953 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
958 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
962 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
965 return (reg & PHY_NEG_PAUSE) != 0;
968 static int PHY_Setup(struct ql3_adapter *qdev)
972 bool agereAddrChangeNeeded = false;
976 /* Determine the PHY we are using by reading the ID's */
977 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
979 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
983 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
985 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
989 /* Check if we have a Agere PHY */
990 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
992 /* Determine which MII address we should be using
993 determined by the index of the card */
994 if (qdev->mac_index == 0)
995 miiAddr = MII_AGERE_ADDR_1;
997 miiAddr = MII_AGERE_ADDR_2;
999 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1001 netdev_err(qdev->ndev,
1002 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1006 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1008 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1012 /* We need to remember to initialize the Agere PHY */
1013 agereAddrChangeNeeded = true;
1016 /* Determine the particular PHY we have on board to apply
1017 PHY specific initializations */
1018 qdev->phyType = getPhyType(qdev, reg1, reg2);
1020 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1021 /* need this here so address gets changed */
1022 phyAgereSpecificInit(qdev, miiAddr);
1023 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1024 netdev_err(qdev->ndev, "PHY is unknown\n");
1032 * Caller holds hw_lock.
1034 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1036 struct ql3xxx_port_registers __iomem *port_regs =
1037 qdev->mem_map_registers;
1041 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1043 value = (MAC_CONFIG_REG_PE << 16);
1045 if (qdev->mac_index)
1046 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1048 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1052 * Caller holds hw_lock.
1054 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1056 struct ql3xxx_port_registers __iomem *port_regs =
1057 qdev->mem_map_registers;
1061 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1063 value = (MAC_CONFIG_REG_SR << 16);
1065 if (qdev->mac_index)
1066 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1068 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1072 * Caller holds hw_lock.
1074 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1076 struct ql3xxx_port_registers __iomem *port_regs =
1077 qdev->mem_map_registers;
1081 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1083 value = (MAC_CONFIG_REG_GM << 16);
1085 if (qdev->mac_index)
1086 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1088 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1092 * Caller holds hw_lock.
1094 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1096 struct ql3xxx_port_registers __iomem *port_regs =
1097 qdev->mem_map_registers;
1101 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1103 value = (MAC_CONFIG_REG_FD << 16);
1105 if (qdev->mac_index)
1106 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1108 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1112 * Caller holds hw_lock.
1114 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1116 struct ql3xxx_port_registers __iomem *port_regs =
1117 qdev->mem_map_registers;
1122 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1123 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1125 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1127 if (qdev->mac_index)
1128 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1130 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1134 * Caller holds hw_lock.
1136 static int ql_is_fiber(struct ql3_adapter *qdev)
1138 struct ql3xxx_port_registers __iomem *port_regs =
1139 qdev->mem_map_registers;
1143 switch (qdev->mac_index) {
1145 bitToCheck = PORT_STATUS_SM0;
1148 bitToCheck = PORT_STATUS_SM1;
1152 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1153 return (temp & bitToCheck) != 0;
1156 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1159 ql_mii_read_reg(qdev, 0x00, ®);
1160 return (reg & 0x1000) != 0;
1164 * Caller holds hw_lock.
1166 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1168 struct ql3xxx_port_registers __iomem *port_regs =
1169 qdev->mem_map_registers;
1173 switch (qdev->mac_index) {
1175 bitToCheck = PORT_STATUS_AC0;
1178 bitToCheck = PORT_STATUS_AC1;
1182 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1183 if (temp & bitToCheck) {
1184 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1187 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1192 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1194 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1196 if (ql_is_fiber(qdev))
1197 return ql_is_petbi_neg_pause(qdev);
1199 return ql_is_phy_neg_pause(qdev);
1202 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1204 struct ql3xxx_port_registers __iomem *port_regs =
1205 qdev->mem_map_registers;
1209 switch (qdev->mac_index) {
1211 bitToCheck = PORT_STATUS_AE0;
1214 bitToCheck = PORT_STATUS_AE1;
1217 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1218 return (temp & bitToCheck) != 0;
1221 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1223 if (ql_is_fiber(qdev))
1226 return ql_phy_get_speed(qdev);
1229 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1231 if (ql_is_fiber(qdev))
1234 return ql_is_full_dup(qdev);
1238 * Caller holds hw_lock.
1240 static int ql_link_down_detect(struct ql3_adapter *qdev)
1242 struct ql3xxx_port_registers __iomem *port_regs =
1243 qdev->mem_map_registers;
1247 switch (qdev->mac_index) {
1249 bitToCheck = ISP_CONTROL_LINK_DN_0;
1252 bitToCheck = ISP_CONTROL_LINK_DN_1;
1257 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1258 return (temp & bitToCheck) != 0;
1262 * Caller holds hw_lock.
1264 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1266 struct ql3xxx_port_registers __iomem *port_regs =
1267 qdev->mem_map_registers;
1269 switch (qdev->mac_index) {
1271 ql_write_common_reg(qdev,
1272 &port_regs->CommonRegs.ispControlStatus,
1273 (ISP_CONTROL_LINK_DN_0) |
1274 (ISP_CONTROL_LINK_DN_0 << 16));
1278 ql_write_common_reg(qdev,
1279 &port_regs->CommonRegs.ispControlStatus,
1280 (ISP_CONTROL_LINK_DN_1) |
1281 (ISP_CONTROL_LINK_DN_1 << 16));
1292 * Caller holds hw_lock.
1294 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1296 struct ql3xxx_port_registers __iomem *port_regs =
1297 qdev->mem_map_registers;
1301 switch (qdev->mac_index) {
1303 bitToCheck = PORT_STATUS_F1_ENABLED;
1306 bitToCheck = PORT_STATUS_F3_ENABLED;
1312 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1313 if (temp & bitToCheck) {
1314 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1315 "not link master\n");
1319 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1323 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1325 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1326 PHYAddr[qdev->mac_index]);
1329 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1332 u16 portConfiguration;
1334 if (qdev->phyType == PHY_AGERE_ET1011C)
1335 ql_mii_write_reg(qdev, 0x13, 0x0000);
1336 /* turn off external loopback */
1338 if (qdev->mac_index == 0)
1340 qdev->nvram_data.macCfg_port0.portConfiguration;
1343 qdev->nvram_data.macCfg_port1.portConfiguration;
1345 /* Some HBA's in the field are set to 0 and they need to
1346 be reinterpreted with a default value */
1347 if (portConfiguration == 0)
1348 portConfiguration = PORT_CONFIG_DEFAULT;
1350 /* Set the 1000 advertisements */
1351 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1352 PHYAddr[qdev->mac_index]);
1353 reg &= ~PHY_GIG_ALL_PARAMS;
1355 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1356 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1357 reg |= PHY_GIG_ADV_1000F;
1359 reg |= PHY_GIG_ADV_1000H;
1362 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1363 PHYAddr[qdev->mac_index]);
1365 /* Set the 10/100 & pause negotiation advertisements */
1366 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1367 PHYAddr[qdev->mac_index]);
1368 reg &= ~PHY_NEG_ALL_PARAMS;
1370 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1371 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1373 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1374 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1375 reg |= PHY_NEG_ADV_100F;
1377 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1378 reg |= PHY_NEG_ADV_10F;
1381 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1382 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1383 reg |= PHY_NEG_ADV_100H;
1385 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1386 reg |= PHY_NEG_ADV_10H;
1389 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1392 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1393 PHYAddr[qdev->mac_index]);
1395 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1397 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1398 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1399 PHYAddr[qdev->mac_index]);
1402 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1404 ql_phy_reset_ex(qdev);
1406 ql_phy_start_neg_ex(qdev);
1410 * Caller holds hw_lock.
1412 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1414 struct ql3xxx_port_registers __iomem *port_regs =
1415 qdev->mem_map_registers;
1417 u32 temp, linkState;
1419 switch (qdev->mac_index) {
1421 bitToCheck = PORT_STATUS_UP0;
1424 bitToCheck = PORT_STATUS_UP1;
1428 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1429 if (temp & bitToCheck)
1432 linkState = LS_DOWN;
1437 static int ql_port_start(struct ql3_adapter *qdev)
1439 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1440 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1442 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1446 if (ql_is_fiber(qdev)) {
1447 ql_petbi_init(qdev);
1450 ql_phy_init_ex(qdev);
1453 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1457 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1460 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1461 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1465 if (!ql_auto_neg_error(qdev)) {
1466 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1467 /* configure the MAC */
1468 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1469 "Configuring link\n");
1470 ql_mac_cfg_soft_reset(qdev, 1);
1471 ql_mac_cfg_gig(qdev,
1475 ql_mac_cfg_full_dup(qdev,
1478 ql_mac_cfg_pause(qdev,
1481 ql_mac_cfg_soft_reset(qdev, 0);
1483 /* enable the MAC */
1484 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1486 ql_mac_enable(qdev, 1);
1489 qdev->port_link_state = LS_UP;
1490 netif_start_queue(qdev->ndev);
1491 netif_carrier_on(qdev->ndev);
1492 netif_info(qdev, link, qdev->ndev,
1493 "Link is up at %d Mbps, %s duplex\n",
1494 ql_get_link_speed(qdev),
1495 ql_is_link_full_dup(qdev) ? "full" : "half");
1497 } else { /* Remote error detected */
1499 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1500 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1501 "Remote error detected. Calling ql_port_start()\n");
1503 * ql_port_start() is shared code and needs
1504 * to lock the PHY on it's own.
1506 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1507 if (ql_port_start(qdev)) /* Restart port */
1512 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1516 static void ql_link_state_machine_work(struct work_struct *work)
1518 struct ql3_adapter *qdev =
1519 container_of(work, struct ql3_adapter, link_state_work.work);
1521 u32 curr_link_state;
1522 unsigned long hw_flags;
1524 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1526 curr_link_state = ql_get_link_state(qdev);
1528 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1529 netif_info(qdev, link, qdev->ndev,
1530 "Reset in progress, skip processing link state\n");
1532 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1534 /* Restart timer on 2 second interval. */
1535 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1540 switch (qdev->port_link_state) {
1542 if (test_bit(QL_LINK_MASTER, &qdev->flags))
1543 ql_port_start(qdev);
1544 qdev->port_link_state = LS_DOWN;
1548 if (curr_link_state == LS_UP) {
1549 netif_info(qdev, link, qdev->ndev, "Link is up\n");
1550 if (ql_is_auto_neg_complete(qdev))
1551 ql_finish_auto_neg(qdev);
1553 if (qdev->port_link_state == LS_UP)
1554 ql_link_down_detect_clear(qdev);
1556 qdev->port_link_state = LS_UP;
1562 * See if the link is currently down or went down and came
1565 if (curr_link_state == LS_DOWN) {
1566 netif_info(qdev, link, qdev->ndev, "Link is down\n");
1567 qdev->port_link_state = LS_DOWN;
1569 if (ql_link_down_detect(qdev))
1570 qdev->port_link_state = LS_DOWN;
1573 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1575 /* Restart timer on 2 second interval. */
1576 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1580 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1582 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1584 if (ql_this_adapter_controls_port(qdev))
1585 set_bit(QL_LINK_MASTER, &qdev->flags);
1587 clear_bit(QL_LINK_MASTER, &qdev->flags);
1591 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1593 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1595 ql_mii_enable_scan_mode(qdev);
1597 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1598 if (ql_this_adapter_controls_port(qdev))
1599 ql_petbi_init_ex(qdev);
1601 if (ql_this_adapter_controls_port(qdev))
1602 ql_phy_init_ex(qdev);
1607 * MII_Setup needs to be called before taking the PHY out of reset
1608 * so that the management interface clock speed can be set properly.
1609 * It would be better if we had a way to disable MDC until after the
1610 * PHY is out of reset, but we don't have that capability.
1612 static int ql_mii_setup(struct ql3_adapter *qdev)
1615 struct ql3xxx_port_registers __iomem *port_regs =
1616 qdev->mem_map_registers;
1618 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1619 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1623 if (qdev->device_id == QL3032_DEVICE_ID)
1624 ql_write_page0_reg(qdev,
1625 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1627 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1628 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1631 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1633 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1637 #define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1640 #define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1641 SUPPORTED_10baseT_Full | \
1642 SUPPORTED_100baseT_Half | \
1643 SUPPORTED_100baseT_Full | \
1644 SUPPORTED_1000baseT_Half | \
1645 SUPPORTED_1000baseT_Full | \
1646 SUPPORTED_Autoneg | \
1649 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1651 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1652 return SUPPORTED_OPTICAL_MODES;
1654 return SUPPORTED_TP_MODES;
1657 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1660 unsigned long hw_flags;
1661 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1662 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1663 (QL_RESOURCE_BITS_BASE_CODE |
1664 (qdev->mac_index) * 2) << 7)) {
1665 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1668 status = ql_is_auto_cfg(qdev);
1669 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1670 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1674 static u32 ql_get_speed(struct ql3_adapter *qdev)
1677 unsigned long hw_flags;
1678 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1679 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1680 (QL_RESOURCE_BITS_BASE_CODE |
1681 (qdev->mac_index) * 2) << 7)) {
1682 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1685 status = ql_get_link_speed(qdev);
1686 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1687 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1691 static int ql_get_full_dup(struct ql3_adapter *qdev)
1694 unsigned long hw_flags;
1695 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1696 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1697 (QL_RESOURCE_BITS_BASE_CODE |
1698 (qdev->mac_index) * 2) << 7)) {
1699 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1702 status = ql_is_link_full_dup(qdev);
1703 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1704 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1708 static int ql_get_link_ksettings(struct net_device *ndev,
1709 struct ethtool_link_ksettings *cmd)
1711 struct ql3_adapter *qdev = netdev_priv(ndev);
1712 u32 supported, advertising;
1714 supported = ql_supported_modes(qdev);
1716 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1717 cmd->base.port = PORT_FIBRE;
1719 cmd->base.port = PORT_TP;
1720 cmd->base.phy_address = qdev->PHYAddr;
1722 advertising = ql_supported_modes(qdev);
1723 cmd->base.autoneg = ql_get_auto_cfg_status(qdev);
1724 cmd->base.speed = ql_get_speed(qdev);
1725 cmd->base.duplex = ql_get_full_dup(qdev);
1727 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1729 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1735 static void ql_get_drvinfo(struct net_device *ndev,
1736 struct ethtool_drvinfo *drvinfo)
1738 struct ql3_adapter *qdev = netdev_priv(ndev);
1739 strlcpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1740 strlcpy(drvinfo->version, ql3xxx_driver_version,
1741 sizeof(drvinfo->version));
1742 strlcpy(drvinfo->bus_info, pci_name(qdev->pdev),
1743 sizeof(drvinfo->bus_info));
1746 static u32 ql_get_msglevel(struct net_device *ndev)
1748 struct ql3_adapter *qdev = netdev_priv(ndev);
1749 return qdev->msg_enable;
1752 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1754 struct ql3_adapter *qdev = netdev_priv(ndev);
1755 qdev->msg_enable = value;
1758 static void ql_get_pauseparam(struct net_device *ndev,
1759 struct ethtool_pauseparam *pause)
1761 struct ql3_adapter *qdev = netdev_priv(ndev);
1762 struct ql3xxx_port_registers __iomem *port_regs =
1763 qdev->mem_map_registers;
1766 if (qdev->mac_index == 0)
1767 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1769 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1771 pause->autoneg = ql_get_auto_cfg_status(qdev);
1772 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1773 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1776 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1777 .get_drvinfo = ql_get_drvinfo,
1778 .get_link = ethtool_op_get_link,
1779 .get_msglevel = ql_get_msglevel,
1780 .set_msglevel = ql_set_msglevel,
1781 .get_pauseparam = ql_get_pauseparam,
1782 .get_link_ksettings = ql_get_link_ksettings,
1785 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1787 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1791 while (lrg_buf_cb) {
1792 if (!lrg_buf_cb->skb) {
1794 netdev_alloc_skb(qdev->ndev,
1795 qdev->lrg_buffer_len);
1796 if (unlikely(!lrg_buf_cb->skb)) {
1797 netdev_printk(KERN_DEBUG, qdev->ndev,
1798 "Failed netdev_alloc_skb()\n");
1802 * We save some space to copy the ethhdr from
1805 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1806 map = pci_map_single(qdev->pdev,
1807 lrg_buf_cb->skb->data,
1808 qdev->lrg_buffer_len -
1810 PCI_DMA_FROMDEVICE);
1812 err = pci_dma_mapping_error(qdev->pdev, map);
1814 netdev_err(qdev->ndev,
1815 "PCI mapping failed with error: %d\n",
1817 dev_kfree_skb(lrg_buf_cb->skb);
1818 lrg_buf_cb->skb = NULL;
1823 lrg_buf_cb->buf_phy_addr_low =
1824 cpu_to_le32(LS_64BITS(map));
1825 lrg_buf_cb->buf_phy_addr_high =
1826 cpu_to_le32(MS_64BITS(map));
1827 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1828 dma_unmap_len_set(lrg_buf_cb, maplen,
1829 qdev->lrg_buffer_len -
1831 --qdev->lrg_buf_skb_check;
1832 if (!qdev->lrg_buf_skb_check)
1836 lrg_buf_cb = lrg_buf_cb->next;
1842 * Caller holds hw_lock.
1844 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1846 struct ql3xxx_port_registers __iomem *port_regs =
1847 qdev->mem_map_registers;
1849 if (qdev->small_buf_release_cnt >= 16) {
1850 while (qdev->small_buf_release_cnt >= 16) {
1851 qdev->small_buf_q_producer_index++;
1853 if (qdev->small_buf_q_producer_index ==
1855 qdev->small_buf_q_producer_index = 0;
1856 qdev->small_buf_release_cnt -= 8;
1859 writel_relaxed(qdev->small_buf_q_producer_index,
1860 &port_regs->CommonRegs.rxSmallQProducerIndex);
1865 * Caller holds hw_lock.
1867 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1869 struct bufq_addr_element *lrg_buf_q_ele;
1871 struct ql_rcv_buf_cb *lrg_buf_cb;
1872 struct ql3xxx_port_registers __iomem *port_regs =
1873 qdev->mem_map_registers;
1875 if ((qdev->lrg_buf_free_count >= 8) &&
1876 (qdev->lrg_buf_release_cnt >= 16)) {
1878 if (qdev->lrg_buf_skb_check)
1879 if (!ql_populate_free_queue(qdev))
1882 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1884 while ((qdev->lrg_buf_release_cnt >= 16) &&
1885 (qdev->lrg_buf_free_count >= 8)) {
1887 for (i = 0; i < 8; i++) {
1889 ql_get_from_lrg_buf_free_list(qdev);
1890 lrg_buf_q_ele->addr_high =
1891 lrg_buf_cb->buf_phy_addr_high;
1892 lrg_buf_q_ele->addr_low =
1893 lrg_buf_cb->buf_phy_addr_low;
1896 qdev->lrg_buf_release_cnt--;
1899 qdev->lrg_buf_q_producer_index++;
1901 if (qdev->lrg_buf_q_producer_index ==
1902 qdev->num_lbufq_entries)
1903 qdev->lrg_buf_q_producer_index = 0;
1905 if (qdev->lrg_buf_q_producer_index ==
1906 (qdev->num_lbufq_entries - 1)) {
1907 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1911 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1912 writel(qdev->lrg_buf_q_producer_index,
1913 &port_regs->CommonRegs.rxLargeQProducerIndex);
1917 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1918 struct ob_mac_iocb_rsp *mac_rsp)
1920 struct ql_tx_buf_cb *tx_cb;
1923 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1924 netdev_warn(qdev->ndev,
1925 "Frame too short but it was padded and sent\n");
1928 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1930 /* Check the transmit response flags for any errors */
1931 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1932 netdev_err(qdev->ndev,
1933 "Frame too short to be legal, frame not sent\n");
1935 qdev->ndev->stats.tx_errors++;
1936 goto frame_not_sent;
1939 if (tx_cb->seg_count == 0) {
1940 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1941 mac_rsp->transaction_id);
1943 qdev->ndev->stats.tx_errors++;
1944 goto invalid_seg_count;
1947 pci_unmap_single(qdev->pdev,
1948 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1949 dma_unmap_len(&tx_cb->map[0], maplen),
1952 if (tx_cb->seg_count) {
1953 for (i = 1; i < tx_cb->seg_count; i++) {
1954 pci_unmap_page(qdev->pdev,
1955 dma_unmap_addr(&tx_cb->map[i],
1957 dma_unmap_len(&tx_cb->map[i], maplen),
1961 qdev->ndev->stats.tx_packets++;
1962 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1965 dev_kfree_skb_irq(tx_cb->skb);
1969 atomic_inc(&qdev->tx_count);
1972 static void ql_get_sbuf(struct ql3_adapter *qdev)
1974 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1975 qdev->small_buf_index = 0;
1976 qdev->small_buf_release_cnt++;
1979 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1981 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1982 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1983 qdev->lrg_buf_release_cnt++;
1984 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1985 qdev->lrg_buf_index = 0;
1990 * The difference between 3022 and 3032 for inbound completions:
1991 * 3022 uses two buffers per completion. The first buffer contains
1992 * (some) header info, the second the remainder of the headers plus
1993 * the data. For this chip we reserve some space at the top of the
1994 * receive buffer so that the header info in buffer one can be
1995 * prepended to the buffer two. Buffer two is the sent up while
1996 * buffer one is returned to the hardware to be reused.
1997 * 3032 receives all of it's data and headers in one buffer for a
1998 * simpler process. 3032 also supports checksum verification as
1999 * can be seen in ql_process_macip_rx_intr().
2001 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2002 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2004 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2005 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2006 struct sk_buff *skb;
2007 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2010 * Get the inbound address list (small buffer).
2014 if (qdev->device_id == QL3022_DEVICE_ID)
2015 lrg_buf_cb1 = ql_get_lbuf(qdev);
2017 /* start of second buffer */
2018 lrg_buf_cb2 = ql_get_lbuf(qdev);
2019 skb = lrg_buf_cb2->skb;
2021 qdev->ndev->stats.rx_packets++;
2022 qdev->ndev->stats.rx_bytes += length;
2024 skb_put(skb, length);
2025 pci_unmap_single(qdev->pdev,
2026 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2027 dma_unmap_len(lrg_buf_cb2, maplen),
2028 PCI_DMA_FROMDEVICE);
2029 prefetch(skb->data);
2030 skb_checksum_none_assert(skb);
2031 skb->protocol = eth_type_trans(skb, qdev->ndev);
2033 napi_gro_receive(&qdev->napi, skb);
2034 lrg_buf_cb2->skb = NULL;
2036 if (qdev->device_id == QL3022_DEVICE_ID)
2037 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2038 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2041 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2042 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2044 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2045 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2046 struct sk_buff *skb1 = NULL, *skb2;
2047 struct net_device *ndev = qdev->ndev;
2048 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2052 * Get the inbound address list (small buffer).
2057 if (qdev->device_id == QL3022_DEVICE_ID) {
2058 /* start of first buffer on 3022 */
2059 lrg_buf_cb1 = ql_get_lbuf(qdev);
2060 skb1 = lrg_buf_cb1->skb;
2062 if (*((u16 *) skb1->data) != 0xFFFF)
2063 size += VLAN_ETH_HLEN - ETH_HLEN;
2066 /* start of second buffer */
2067 lrg_buf_cb2 = ql_get_lbuf(qdev);
2068 skb2 = lrg_buf_cb2->skb;
2070 skb_put(skb2, length); /* Just the second buffer length here. */
2071 pci_unmap_single(qdev->pdev,
2072 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2073 dma_unmap_len(lrg_buf_cb2, maplen),
2074 PCI_DMA_FROMDEVICE);
2075 prefetch(skb2->data);
2077 skb_checksum_none_assert(skb2);
2078 if (qdev->device_id == QL3022_DEVICE_ID) {
2080 * Copy the ethhdr from first buffer to second. This
2081 * is necessary for 3022 IP completions.
2083 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2084 skb_push(skb2, size), size);
2086 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2088 (IB_IP_IOCB_RSP_3032_ICE |
2089 IB_IP_IOCB_RSP_3032_CE)) {
2091 "%s: Bad checksum for this %s packet, checksum = %x\n",
2093 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2094 "TCP" : "UDP"), checksum);
2095 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2096 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2097 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2098 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2101 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2103 napi_gro_receive(&qdev->napi, skb2);
2104 ndev->stats.rx_packets++;
2105 ndev->stats.rx_bytes += length;
2106 lrg_buf_cb2->skb = NULL;
2108 if (qdev->device_id == QL3022_DEVICE_ID)
2109 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2110 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2113 static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget)
2115 struct net_rsp_iocb *net_rsp;
2116 struct net_device *ndev = qdev->ndev;
2119 /* While there are entries in the completion queue. */
2120 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2121 qdev->rsp_consumer_index) && (work_done < budget)) {
2123 net_rsp = qdev->rsp_current;
2126 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2127 * if the inbound completion is for a VLAN.
2129 if (qdev->device_id == QL3032_DEVICE_ID)
2130 net_rsp->opcode &= 0x7f;
2131 switch (net_rsp->opcode) {
2133 case OPCODE_OB_MAC_IOCB_FN0:
2134 case OPCODE_OB_MAC_IOCB_FN2:
2135 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2139 case OPCODE_IB_MAC_IOCB:
2140 case OPCODE_IB_3032_MAC_IOCB:
2141 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2146 case OPCODE_IB_IP_IOCB:
2147 case OPCODE_IB_3032_IP_IOCB:
2148 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2153 u32 *tmp = (u32 *)net_rsp;
2155 "Hit default case, not handled!\n"
2156 " dropping the packet, opcode = %x\n"
2157 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2159 (unsigned long int)tmp[0],
2160 (unsigned long int)tmp[1],
2161 (unsigned long int)tmp[2],
2162 (unsigned long int)tmp[3]);
2166 qdev->rsp_consumer_index++;
2168 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2169 qdev->rsp_consumer_index = 0;
2170 qdev->rsp_current = qdev->rsp_q_virt_addr;
2172 qdev->rsp_current++;
2180 static int ql_poll(struct napi_struct *napi, int budget)
2182 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2183 struct ql3xxx_port_registers __iomem *port_regs =
2184 qdev->mem_map_registers;
2187 work_done = ql_tx_rx_clean(qdev, budget);
2189 if (work_done < budget && napi_complete_done(napi, work_done)) {
2190 unsigned long flags;
2192 spin_lock_irqsave(&qdev->hw_lock, flags);
2193 ql_update_small_bufq_prod_index(qdev);
2194 ql_update_lrg_bufq_prod_index(qdev);
2195 writel(qdev->rsp_consumer_index,
2196 &port_regs->CommonRegs.rspQConsumerIndex);
2197 spin_unlock_irqrestore(&qdev->hw_lock, flags);
2199 ql_enable_interrupts(qdev);
2204 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2207 struct net_device *ndev = dev_id;
2208 struct ql3_adapter *qdev = netdev_priv(ndev);
2209 struct ql3xxx_port_registers __iomem *port_regs =
2210 qdev->mem_map_registers;
2215 value = ql_read_common_reg_l(qdev,
2216 &port_regs->CommonRegs.ispControlStatus);
2218 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2219 spin_lock(&qdev->adapter_lock);
2220 netif_stop_queue(qdev->ndev);
2221 netif_carrier_off(qdev->ndev);
2222 ql_disable_interrupts(qdev);
2223 qdev->port_link_state = LS_DOWN;
2224 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2226 if (value & ISP_CONTROL_FE) {
2231 ql_read_page0_reg_l(qdev,
2232 &port_regs->PortFatalErrStatus);
2234 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2236 set_bit(QL_RESET_START, &qdev->flags) ;
2239 * Soft Reset Requested.
2241 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2243 "Another function issued a reset to the chip. ISR value = %x\n",
2246 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2247 spin_unlock(&qdev->adapter_lock);
2248 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2249 ql_disable_interrupts(qdev);
2250 if (likely(napi_schedule_prep(&qdev->napi)))
2251 __napi_schedule(&qdev->napi);
2255 return IRQ_RETVAL(handled);
2259 * Get the total number of segments needed for the given number of fragments.
2260 * This is necessary because outbound address lists (OAL) will be used when
2261 * more than two frags are given. Each address list has 5 addr/len pairs.
2262 * The 5th pair in each OAL is used to point to the next OAL if more frags
2263 * are coming. That is why the frags:segment count ratio is not linear.
2265 static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2267 if (qdev->device_id == QL3022_DEVICE_ID)
2272 else if (frags <= 6)
2274 else if (frags <= 10)
2276 else if (frags <= 14)
2278 else if (frags <= 18)
2283 static void ql_hw_csum_setup(const struct sk_buff *skb,
2284 struct ob_mac_iocb_req *mac_iocb_ptr)
2286 const struct iphdr *ip = ip_hdr(skb);
2288 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2289 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2291 if (ip->protocol == IPPROTO_TCP) {
2292 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2293 OB_3032MAC_IOCB_REQ_IC;
2295 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2296 OB_3032MAC_IOCB_REQ_IC;
2302 * Map the buffers for this transmit.
2303 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2305 static int ql_send_map(struct ql3_adapter *qdev,
2306 struct ob_mac_iocb_req *mac_iocb_ptr,
2307 struct ql_tx_buf_cb *tx_cb,
2308 struct sk_buff *skb)
2311 struct oal_entry *oal_entry;
2312 int len = skb_headlen(skb);
2315 int completed_segs, i;
2316 int seg_cnt, seg = 0;
2317 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2319 seg_cnt = tx_cb->seg_count;
2321 * Map the skb buffer first.
2323 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2325 err = pci_dma_mapping_error(qdev->pdev, map);
2327 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2330 return NETDEV_TX_BUSY;
2333 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2334 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2335 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2336 oal_entry->len = cpu_to_le32(len);
2337 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2338 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2342 /* Terminate the last segment. */
2343 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2344 return NETDEV_TX_OK;
2347 for (completed_segs = 0;
2348 completed_segs < frag_cnt;
2349 completed_segs++, seg++) {
2350 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2353 * Check for continuation requirements.
2354 * It's strange but necessary.
2355 * Continuation entry points to outbound address list.
2357 if ((seg == 2 && seg_cnt > 3) ||
2358 (seg == 7 && seg_cnt > 8) ||
2359 (seg == 12 && seg_cnt > 13) ||
2360 (seg == 17 && seg_cnt > 18)) {
2361 map = pci_map_single(qdev->pdev, oal,
2365 err = pci_dma_mapping_error(qdev->pdev, map);
2367 netdev_err(qdev->ndev,
2368 "PCI mapping outbound address list with error: %d\n",
2373 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2374 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2375 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2377 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2378 dma_unmap_len_set(&tx_cb->map[seg], maplen,
2379 sizeof(struct oal));
2380 oal_entry = (struct oal_entry *)oal;
2385 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2388 err = dma_mapping_error(&qdev->pdev->dev, map);
2390 netdev_err(qdev->ndev,
2391 "PCI mapping frags failed with error: %d\n",
2396 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2397 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2398 oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2399 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2400 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2402 /* Terminate the last segment. */
2403 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2404 return NETDEV_TX_OK;
2407 /* A PCI mapping failed and now we will need to back out
2408 * We need to traverse through the oal's and associated pages which
2409 * have been mapped and now we must unmap them to clean up properly
2413 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2415 for (i = 0; i < completed_segs; i++, seg++) {
2419 * Check for continuation requirements.
2420 * It's strange but necessary.
2423 if ((seg == 2 && seg_cnt > 3) ||
2424 (seg == 7 && seg_cnt > 8) ||
2425 (seg == 12 && seg_cnt > 13) ||
2426 (seg == 17 && seg_cnt > 18)) {
2427 pci_unmap_single(qdev->pdev,
2428 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2429 dma_unmap_len(&tx_cb->map[seg], maplen),
2435 pci_unmap_page(qdev->pdev,
2436 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2437 dma_unmap_len(&tx_cb->map[seg], maplen),
2441 pci_unmap_single(qdev->pdev,
2442 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2443 dma_unmap_addr(&tx_cb->map[0], maplen),
2446 return NETDEV_TX_BUSY;
2451 * The difference between 3022 and 3032 sends:
2452 * 3022 only supports a simple single segment transmission.
2453 * 3032 supports checksumming and scatter/gather lists (fragments).
2454 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2455 * in the IOCB plus a chain of outbound address lists (OAL) that
2456 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2457 * will be used to point to an OAL when more ALP entries are required.
2458 * The IOCB is always the top of the chain followed by one or more
2459 * OALs (when necessary).
2461 static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2462 struct net_device *ndev)
2464 struct ql3_adapter *qdev = netdev_priv(ndev);
2465 struct ql3xxx_port_registers __iomem *port_regs =
2466 qdev->mem_map_registers;
2467 struct ql_tx_buf_cb *tx_cb;
2468 u32 tot_len = skb->len;
2469 struct ob_mac_iocb_req *mac_iocb_ptr;
2471 if (unlikely(atomic_read(&qdev->tx_count) < 2))
2472 return NETDEV_TX_BUSY;
2474 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2475 tx_cb->seg_count = ql_get_seg_count(qdev,
2476 skb_shinfo(skb)->nr_frags);
2477 if (tx_cb->seg_count == -1) {
2478 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2479 return NETDEV_TX_OK;
2482 mac_iocb_ptr = tx_cb->queue_entry;
2483 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2484 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2485 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2486 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2487 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2488 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2490 if (qdev->device_id == QL3032_DEVICE_ID &&
2491 skb->ip_summed == CHECKSUM_PARTIAL)
2492 ql_hw_csum_setup(skb, mac_iocb_ptr);
2494 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2495 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2496 return NETDEV_TX_BUSY;
2500 qdev->req_producer_index++;
2501 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2502 qdev->req_producer_index = 0;
2504 ql_write_common_reg_l(qdev,
2505 &port_regs->CommonRegs.reqQProducerIndex,
2506 qdev->req_producer_index);
2508 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2509 "tx queued, slot %d, len %d\n",
2510 qdev->req_producer_index, skb->len);
2512 atomic_dec(&qdev->tx_count);
2513 return NETDEV_TX_OK;
2516 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2519 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2521 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2523 /* The barrier is required to ensure request and response queue
2524 * addr writes to the registers.
2528 qdev->req_q_virt_addr =
2529 pci_alloc_consistent(qdev->pdev,
2530 (size_t) qdev->req_q_size,
2531 &qdev->req_q_phy_addr);
2533 if ((qdev->req_q_virt_addr == NULL) ||
2534 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2535 netdev_err(qdev->ndev, "reqQ failed\n");
2539 qdev->rsp_q_virt_addr =
2540 pci_alloc_consistent(qdev->pdev,
2541 (size_t) qdev->rsp_q_size,
2542 &qdev->rsp_q_phy_addr);
2544 if ((qdev->rsp_q_virt_addr == NULL) ||
2545 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2546 netdev_err(qdev->ndev, "rspQ allocation failed\n");
2547 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2548 qdev->req_q_virt_addr,
2549 qdev->req_q_phy_addr);
2553 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2558 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2560 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2561 netdev_info(qdev->ndev, "Already done\n");
2565 pci_free_consistent(qdev->pdev,
2567 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2569 qdev->req_q_virt_addr = NULL;
2571 pci_free_consistent(qdev->pdev,
2573 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2575 qdev->rsp_q_virt_addr = NULL;
2577 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2580 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2582 /* Create Large Buffer Queue */
2583 qdev->lrg_buf_q_size =
2584 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2585 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2586 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2588 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2590 qdev->lrg_buf = kmalloc_array(qdev->num_large_buffers,
2591 sizeof(struct ql_rcv_buf_cb),
2593 if (qdev->lrg_buf == NULL)
2596 qdev->lrg_buf_q_alloc_virt_addr =
2597 pci_alloc_consistent(qdev->pdev,
2598 qdev->lrg_buf_q_alloc_size,
2599 &qdev->lrg_buf_q_alloc_phy_addr);
2601 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2602 netdev_err(qdev->ndev, "lBufQ failed\n");
2605 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2606 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2608 /* Create Small Buffer Queue */
2609 qdev->small_buf_q_size =
2610 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2611 if (qdev->small_buf_q_size < PAGE_SIZE)
2612 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2614 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2616 qdev->small_buf_q_alloc_virt_addr =
2617 pci_alloc_consistent(qdev->pdev,
2618 qdev->small_buf_q_alloc_size,
2619 &qdev->small_buf_q_alloc_phy_addr);
2621 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2622 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2623 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2624 qdev->lrg_buf_q_alloc_virt_addr,
2625 qdev->lrg_buf_q_alloc_phy_addr);
2629 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2630 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2631 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2635 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2637 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2638 netdev_info(qdev->ndev, "Already done\n");
2641 kfree(qdev->lrg_buf);
2642 pci_free_consistent(qdev->pdev,
2643 qdev->lrg_buf_q_alloc_size,
2644 qdev->lrg_buf_q_alloc_virt_addr,
2645 qdev->lrg_buf_q_alloc_phy_addr);
2647 qdev->lrg_buf_q_virt_addr = NULL;
2649 pci_free_consistent(qdev->pdev,
2650 qdev->small_buf_q_alloc_size,
2651 qdev->small_buf_q_alloc_virt_addr,
2652 qdev->small_buf_q_alloc_phy_addr);
2654 qdev->small_buf_q_virt_addr = NULL;
2656 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2659 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2662 struct bufq_addr_element *small_buf_q_entry;
2664 /* Currently we allocate on one of memory and use it for smallbuffers */
2665 qdev->small_buf_total_size =
2666 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2667 QL_SMALL_BUFFER_SIZE);
2669 qdev->small_buf_virt_addr =
2670 pci_alloc_consistent(qdev->pdev,
2671 qdev->small_buf_total_size,
2672 &qdev->small_buf_phy_addr);
2674 if (qdev->small_buf_virt_addr == NULL) {
2675 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2679 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2680 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2682 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2684 /* Initialize the small buffer queue. */
2685 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2686 small_buf_q_entry->addr_high =
2687 cpu_to_le32(qdev->small_buf_phy_addr_high);
2688 small_buf_q_entry->addr_low =
2689 cpu_to_le32(qdev->small_buf_phy_addr_low +
2690 (i * QL_SMALL_BUFFER_SIZE));
2691 small_buf_q_entry++;
2693 qdev->small_buf_index = 0;
2694 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2698 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2700 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2701 netdev_info(qdev->ndev, "Already done\n");
2704 if (qdev->small_buf_virt_addr != NULL) {
2705 pci_free_consistent(qdev->pdev,
2706 qdev->small_buf_total_size,
2707 qdev->small_buf_virt_addr,
2708 qdev->small_buf_phy_addr);
2710 qdev->small_buf_virt_addr = NULL;
2714 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2717 struct ql_rcv_buf_cb *lrg_buf_cb;
2719 for (i = 0; i < qdev->num_large_buffers; i++) {
2720 lrg_buf_cb = &qdev->lrg_buf[i];
2721 if (lrg_buf_cb->skb) {
2722 dev_kfree_skb(lrg_buf_cb->skb);
2723 pci_unmap_single(qdev->pdev,
2724 dma_unmap_addr(lrg_buf_cb, mapaddr),
2725 dma_unmap_len(lrg_buf_cb, maplen),
2726 PCI_DMA_FROMDEVICE);
2727 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2734 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2737 struct ql_rcv_buf_cb *lrg_buf_cb;
2738 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2740 for (i = 0; i < qdev->num_large_buffers; i++) {
2741 lrg_buf_cb = &qdev->lrg_buf[i];
2742 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2743 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2746 qdev->lrg_buf_index = 0;
2747 qdev->lrg_buf_skb_check = 0;
2750 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2753 struct ql_rcv_buf_cb *lrg_buf_cb;
2754 struct sk_buff *skb;
2758 for (i = 0; i < qdev->num_large_buffers; i++) {
2759 skb = netdev_alloc_skb(qdev->ndev,
2760 qdev->lrg_buffer_len);
2761 if (unlikely(!skb)) {
2762 /* Better luck next round */
2763 netdev_err(qdev->ndev,
2764 "large buff alloc failed for %d bytes at index %d\n",
2765 qdev->lrg_buffer_len * 2, i);
2766 ql_free_large_buffers(qdev);
2770 lrg_buf_cb = &qdev->lrg_buf[i];
2771 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2772 lrg_buf_cb->index = i;
2773 lrg_buf_cb->skb = skb;
2775 * We save some space to copy the ethhdr from first
2778 skb_reserve(skb, QL_HEADER_SPACE);
2779 map = pci_map_single(qdev->pdev,
2781 qdev->lrg_buffer_len -
2783 PCI_DMA_FROMDEVICE);
2785 err = pci_dma_mapping_error(qdev->pdev, map);
2787 netdev_err(qdev->ndev,
2788 "PCI mapping failed with error: %d\n",
2790 ql_free_large_buffers(qdev);
2794 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2795 dma_unmap_len_set(lrg_buf_cb, maplen,
2796 qdev->lrg_buffer_len -
2798 lrg_buf_cb->buf_phy_addr_low =
2799 cpu_to_le32(LS_64BITS(map));
2800 lrg_buf_cb->buf_phy_addr_high =
2801 cpu_to_le32(MS_64BITS(map));
2807 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2809 struct ql_tx_buf_cb *tx_cb;
2812 tx_cb = &qdev->tx_buf[0];
2813 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2820 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2822 struct ql_tx_buf_cb *tx_cb;
2824 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2826 /* Create free list of transmit buffers */
2827 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2829 tx_cb = &qdev->tx_buf[i];
2831 tx_cb->queue_entry = req_q_curr;
2833 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2834 if (tx_cb->oal == NULL)
2840 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2842 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2843 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2844 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2845 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2847 * Bigger buffers, so less of them.
2849 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2850 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2852 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2853 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2856 qdev->num_large_buffers =
2857 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2858 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2859 qdev->max_frame_size =
2860 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2863 * First allocate a page of shared memory and use it for shadow
2864 * locations of Network Request Queue Consumer Address Register and
2865 * Network Completion Queue Producer Index Register
2867 qdev->shadow_reg_virt_addr =
2868 pci_alloc_consistent(qdev->pdev,
2869 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2871 if (qdev->shadow_reg_virt_addr != NULL) {
2872 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2873 qdev->req_consumer_index_phy_addr_high =
2874 MS_64BITS(qdev->shadow_reg_phy_addr);
2875 qdev->req_consumer_index_phy_addr_low =
2876 LS_64BITS(qdev->shadow_reg_phy_addr);
2878 qdev->prsp_producer_index =
2879 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2880 qdev->rsp_producer_index_phy_addr_high =
2881 qdev->req_consumer_index_phy_addr_high;
2882 qdev->rsp_producer_index_phy_addr_low =
2883 qdev->req_consumer_index_phy_addr_low + 8;
2885 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2889 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2890 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2894 if (ql_alloc_buffer_queues(qdev) != 0) {
2895 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2896 goto err_buffer_queues;
2899 if (ql_alloc_small_buffers(qdev) != 0) {
2900 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2901 goto err_small_buffers;
2904 if (ql_alloc_large_buffers(qdev) != 0) {
2905 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2906 goto err_small_buffers;
2909 /* Initialize the large buffer queue. */
2910 ql_init_large_buffers(qdev);
2911 if (ql_create_send_free_list(qdev))
2914 qdev->rsp_current = qdev->rsp_q_virt_addr;
2918 ql_free_send_free_list(qdev);
2920 ql_free_buffer_queues(qdev);
2922 ql_free_net_req_rsp_queues(qdev);
2924 pci_free_consistent(qdev->pdev,
2926 qdev->shadow_reg_virt_addr,
2927 qdev->shadow_reg_phy_addr);
2932 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2934 ql_free_send_free_list(qdev);
2935 ql_free_large_buffers(qdev);
2936 ql_free_small_buffers(qdev);
2937 ql_free_buffer_queues(qdev);
2938 ql_free_net_req_rsp_queues(qdev);
2939 if (qdev->shadow_reg_virt_addr != NULL) {
2940 pci_free_consistent(qdev->pdev,
2942 qdev->shadow_reg_virt_addr,
2943 qdev->shadow_reg_phy_addr);
2944 qdev->shadow_reg_virt_addr = NULL;
2948 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2950 struct ql3xxx_local_ram_registers __iomem *local_ram =
2951 (void __iomem *)qdev->mem_map_registers;
2953 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2954 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2958 ql_write_page2_reg(qdev,
2959 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2961 ql_write_page2_reg(qdev,
2962 &local_ram->maxBufletCount,
2963 qdev->nvram_data.bufletCount);
2965 ql_write_page2_reg(qdev,
2966 &local_ram->freeBufletThresholdLow,
2967 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2968 (qdev->nvram_data.tcpWindowThreshold0));
2970 ql_write_page2_reg(qdev,
2971 &local_ram->freeBufletThresholdHigh,
2972 qdev->nvram_data.tcpWindowThreshold50);
2974 ql_write_page2_reg(qdev,
2975 &local_ram->ipHashTableBase,
2976 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2977 qdev->nvram_data.ipHashTableBaseLo);
2978 ql_write_page2_reg(qdev,
2979 &local_ram->ipHashTableCount,
2980 qdev->nvram_data.ipHashTableSize);
2981 ql_write_page2_reg(qdev,
2982 &local_ram->tcpHashTableBase,
2983 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2984 qdev->nvram_data.tcpHashTableBaseLo);
2985 ql_write_page2_reg(qdev,
2986 &local_ram->tcpHashTableCount,
2987 qdev->nvram_data.tcpHashTableSize);
2988 ql_write_page2_reg(qdev,
2989 &local_ram->ncbBase,
2990 (qdev->nvram_data.ncbTableBaseHi << 16) |
2991 qdev->nvram_data.ncbTableBaseLo);
2992 ql_write_page2_reg(qdev,
2993 &local_ram->maxNcbCount,
2994 qdev->nvram_data.ncbTableSize);
2995 ql_write_page2_reg(qdev,
2996 &local_ram->drbBase,
2997 (qdev->nvram_data.drbTableBaseHi << 16) |
2998 qdev->nvram_data.drbTableBaseLo);
2999 ql_write_page2_reg(qdev,
3000 &local_ram->maxDrbCount,
3001 qdev->nvram_data.drbTableSize);
3002 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3006 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3009 struct ql3xxx_port_registers __iomem *port_regs =
3010 qdev->mem_map_registers;
3011 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3012 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3013 (void __iomem *)port_regs;
3017 if (ql_mii_setup(qdev))
3020 /* Bring out PHY out of reset */
3021 ql_write_common_reg(qdev, spir,
3022 (ISP_SERIAL_PORT_IF_WE |
3023 (ISP_SERIAL_PORT_IF_WE << 16)));
3024 /* Give the PHY time to come out of reset. */
3026 qdev->port_link_state = LS_DOWN;
3027 netif_carrier_off(qdev->ndev);
3029 /* V2 chip fix for ARS-39168. */
3030 ql_write_common_reg(qdev, spir,
3031 (ISP_SERIAL_PORT_IF_SDE |
3032 (ISP_SERIAL_PORT_IF_SDE << 16)));
3034 /* Request Queue Registers */
3035 *((u32 *)(qdev->preq_consumer_index)) = 0;
3036 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3037 qdev->req_producer_index = 0;
3039 ql_write_page1_reg(qdev,
3040 &hmem_regs->reqConsumerIndexAddrHigh,
3041 qdev->req_consumer_index_phy_addr_high);
3042 ql_write_page1_reg(qdev,
3043 &hmem_regs->reqConsumerIndexAddrLow,
3044 qdev->req_consumer_index_phy_addr_low);
3046 ql_write_page1_reg(qdev,
3047 &hmem_regs->reqBaseAddrHigh,
3048 MS_64BITS(qdev->req_q_phy_addr));
3049 ql_write_page1_reg(qdev,
3050 &hmem_regs->reqBaseAddrLow,
3051 LS_64BITS(qdev->req_q_phy_addr));
3052 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3054 /* Response Queue Registers */
3055 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3056 qdev->rsp_consumer_index = 0;
3057 qdev->rsp_current = qdev->rsp_q_virt_addr;
3059 ql_write_page1_reg(qdev,
3060 &hmem_regs->rspProducerIndexAddrHigh,
3061 qdev->rsp_producer_index_phy_addr_high);
3063 ql_write_page1_reg(qdev,
3064 &hmem_regs->rspProducerIndexAddrLow,
3065 qdev->rsp_producer_index_phy_addr_low);
3067 ql_write_page1_reg(qdev,
3068 &hmem_regs->rspBaseAddrHigh,
3069 MS_64BITS(qdev->rsp_q_phy_addr));
3071 ql_write_page1_reg(qdev,
3072 &hmem_regs->rspBaseAddrLow,
3073 LS_64BITS(qdev->rsp_q_phy_addr));
3075 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3077 /* Large Buffer Queue */
3078 ql_write_page1_reg(qdev,
3079 &hmem_regs->rxLargeQBaseAddrHigh,
3080 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3082 ql_write_page1_reg(qdev,
3083 &hmem_regs->rxLargeQBaseAddrLow,
3084 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3086 ql_write_page1_reg(qdev,
3087 &hmem_regs->rxLargeQLength,
3088 qdev->num_lbufq_entries);
3090 ql_write_page1_reg(qdev,
3091 &hmem_regs->rxLargeBufferLength,
3092 qdev->lrg_buffer_len);
3094 /* Small Buffer Queue */
3095 ql_write_page1_reg(qdev,
3096 &hmem_regs->rxSmallQBaseAddrHigh,
3097 MS_64BITS(qdev->small_buf_q_phy_addr));
3099 ql_write_page1_reg(qdev,
3100 &hmem_regs->rxSmallQBaseAddrLow,
3101 LS_64BITS(qdev->small_buf_q_phy_addr));
3103 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3104 ql_write_page1_reg(qdev,
3105 &hmem_regs->rxSmallBufferLength,
3106 QL_SMALL_BUFFER_SIZE);
3108 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3109 qdev->small_buf_release_cnt = 8;
3110 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3111 qdev->lrg_buf_release_cnt = 8;
3112 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3113 qdev->small_buf_index = 0;
3114 qdev->lrg_buf_index = 0;
3115 qdev->lrg_buf_free_count = 0;
3116 qdev->lrg_buf_free_head = NULL;
3117 qdev->lrg_buf_free_tail = NULL;
3119 ql_write_common_reg(qdev,
3120 &port_regs->CommonRegs.
3121 rxSmallQProducerIndex,
3122 qdev->small_buf_q_producer_index);
3123 ql_write_common_reg(qdev,
3124 &port_regs->CommonRegs.
3125 rxLargeQProducerIndex,
3126 qdev->lrg_buf_q_producer_index);
3129 * Find out if the chip has already been initialized. If it has, then
3130 * we skip some of the initialization.
3132 clear_bit(QL_LINK_MASTER, &qdev->flags);
3133 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3134 if ((value & PORT_STATUS_IC) == 0) {
3136 /* Chip has not been configured yet, so let it rip. */
3137 if (ql_init_misc_registers(qdev)) {
3142 value = qdev->nvram_data.tcpMaxWindowSize;
3143 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3145 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3147 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3148 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3153 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3154 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3155 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3156 16) | (INTERNAL_CHIP_SD |
3157 INTERNAL_CHIP_WE)));
3158 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3161 if (qdev->mac_index)
3162 ql_write_page0_reg(qdev,
3163 &port_regs->mac1MaxFrameLengthReg,
3164 qdev->max_frame_size);
3166 ql_write_page0_reg(qdev,
3167 &port_regs->mac0MaxFrameLengthReg,
3168 qdev->max_frame_size);
3170 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3171 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3178 ql_init_scan_mode(qdev);
3179 ql_get_phy_owner(qdev);
3181 /* Load the MAC Configuration */
3183 /* Program lower 32 bits of the MAC address */
3184 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3185 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3186 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3187 ((qdev->ndev->dev_addr[2] << 24)
3188 | (qdev->ndev->dev_addr[3] << 16)
3189 | (qdev->ndev->dev_addr[4] << 8)
3190 | qdev->ndev->dev_addr[5]));
3192 /* Program top 16 bits of the MAC address */
3193 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3194 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3195 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3196 ((qdev->ndev->dev_addr[0] << 8)
3197 | qdev->ndev->dev_addr[1]));
3199 /* Enable Primary MAC */
3200 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3201 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3202 MAC_ADDR_INDIRECT_PTR_REG_PE));
3204 /* Clear Primary and Secondary IP addresses */
3205 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3206 ((IP_ADDR_INDEX_REG_MASK << 16) |
3207 (qdev->mac_index << 2)));
3208 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3210 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3211 ((IP_ADDR_INDEX_REG_MASK << 16) |
3212 ((qdev->mac_index << 2) + 1)));
3213 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3215 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3217 /* Indicate Configuration Complete */
3218 ql_write_page0_reg(qdev,
3219 &port_regs->portControl,
3220 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3223 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3224 if (value & PORT_STATUS_IC)
3226 spin_unlock_irq(&qdev->hw_lock);
3228 spin_lock_irq(&qdev->hw_lock);
3232 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3237 /* Enable Ethernet Function */
3238 if (qdev->device_id == QL3032_DEVICE_ID) {
3240 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3241 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3242 QL3032_PORT_CONTROL_ET);
3243 ql_write_page0_reg(qdev, &port_regs->functionControl,
3244 ((value << 16) | value));
3247 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3249 ql_write_page0_reg(qdev, &port_regs->portControl,
3250 ((value << 16) | value));
3259 * Caller holds hw_lock.
3261 static int ql_adapter_reset(struct ql3_adapter *qdev)
3263 struct ql3xxx_port_registers __iomem *port_regs =
3264 qdev->mem_map_registers;
3269 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3270 clear_bit(QL_RESET_DONE, &qdev->flags);
3273 * Issue soft reset to chip.
3275 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3276 ql_write_common_reg(qdev,
3277 &port_regs->CommonRegs.ispControlStatus,
3278 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3280 /* Wait 3 seconds for reset to complete. */
3281 netdev_printk(KERN_DEBUG, qdev->ndev,
3282 "Wait 10 milliseconds for reset to complete\n");
3284 /* Wait until the firmware tells us the Soft Reset is done */
3288 ql_read_common_reg(qdev,
3289 &port_regs->CommonRegs.ispControlStatus);
3290 if ((value & ISP_CONTROL_SR) == 0)
3294 } while ((--max_wait_time));
3297 * Also, make sure that the Network Reset Interrupt bit has been
3298 * cleared after the soft reset has taken place.
3301 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3302 if (value & ISP_CONTROL_RI) {
3303 netdev_printk(KERN_DEBUG, qdev->ndev,
3304 "clearing RI after reset\n");
3305 ql_write_common_reg(qdev,
3306 &port_regs->CommonRegs.
3308 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3311 if (max_wait_time == 0) {
3312 /* Issue Force Soft Reset */
3313 ql_write_common_reg(qdev,
3314 &port_regs->CommonRegs.
3316 ((ISP_CONTROL_FSR << 16) |
3319 * Wait until the firmware tells us the Force Soft Reset is
3324 value = ql_read_common_reg(qdev,
3325 &port_regs->CommonRegs.
3327 if ((value & ISP_CONTROL_FSR) == 0)
3330 } while ((--max_wait_time));
3332 if (max_wait_time == 0)
3335 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3336 set_bit(QL_RESET_DONE, &qdev->flags);
3340 static void ql_set_mac_info(struct ql3_adapter *qdev)
3342 struct ql3xxx_port_registers __iomem *port_regs =
3343 qdev->mem_map_registers;
3344 u32 value, port_status;
3347 /* Get the function number */
3349 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3350 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3351 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3352 switch (value & ISP_CONTROL_FN_MASK) {
3353 case ISP_CONTROL_FN0_NET:
3354 qdev->mac_index = 0;
3355 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3356 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3357 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3358 if (port_status & PORT_STATUS_SM0)
3359 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3361 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3364 case ISP_CONTROL_FN1_NET:
3365 qdev->mac_index = 1;
3366 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3367 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3368 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3369 if (port_status & PORT_STATUS_SM1)
3370 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3372 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3375 case ISP_CONTROL_FN0_SCSI:
3376 case ISP_CONTROL_FN1_SCSI:
3378 netdev_printk(KERN_DEBUG, qdev->ndev,
3379 "Invalid function number, ispControlStatus = 0x%x\n",
3383 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3386 static void ql_display_dev_info(struct net_device *ndev)
3388 struct ql3_adapter *qdev = netdev_priv(ndev);
3389 struct pci_dev *pdev = qdev->pdev;
3392 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3393 DRV_NAME, qdev->index, qdev->chip_rev_id,
3394 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3396 netdev_info(ndev, "%s Interface\n",
3397 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3400 * Print PCI bus width/type.
3402 netdev_info(ndev, "Bus interface is %s %s\n",
3403 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3404 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3406 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3407 qdev->mem_map_registers);
3408 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3410 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3413 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3415 struct net_device *ndev = qdev->ndev;
3418 netif_stop_queue(ndev);
3419 netif_carrier_off(ndev);
3421 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3422 clear_bit(QL_LINK_MASTER, &qdev->flags);
3424 ql_disable_interrupts(qdev);
3426 free_irq(qdev->pdev->irq, ndev);
3428 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3429 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3430 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3431 pci_disable_msi(qdev->pdev);
3434 del_timer_sync(&qdev->adapter_timer);
3436 napi_disable(&qdev->napi);
3440 unsigned long hw_flags;
3442 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3443 if (ql_wait_for_drvr_lock(qdev)) {
3444 soft_reset = ql_adapter_reset(qdev);
3446 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3450 "Releasing driver lock via chip reset\n");
3453 "Could not acquire driver lock to do reset!\n");
3456 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3458 ql_free_mem_resources(qdev);
3462 static int ql_adapter_up(struct ql3_adapter *qdev)
3464 struct net_device *ndev = qdev->ndev;
3466 unsigned long irq_flags = IRQF_SHARED;
3467 unsigned long hw_flags;
3469 if (ql_alloc_mem_resources(qdev)) {
3470 netdev_err(ndev, "Unable to allocate buffers\n");
3475 if (pci_enable_msi(qdev->pdev)) {
3477 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3480 netdev_info(ndev, "MSI Enabled...\n");
3481 set_bit(QL_MSI_ENABLED, &qdev->flags);
3482 irq_flags &= ~IRQF_SHARED;
3486 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3487 irq_flags, ndev->name, ndev);
3490 "Failed to reserve interrupt %d - already in use\n",
3495 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3497 err = ql_wait_for_drvr_lock(qdev);
3499 err = ql_adapter_initialize(qdev);
3501 netdev_err(ndev, "Unable to initialize adapter\n");
3504 netdev_err(ndev, "Releasing driver lock\n");
3505 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3507 netdev_err(ndev, "Could not acquire driver lock\n");
3511 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3513 set_bit(QL_ADAPTER_UP, &qdev->flags);
3515 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3517 napi_enable(&qdev->napi);
3518 ql_enable_interrupts(qdev);
3522 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3524 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3525 free_irq(qdev->pdev->irq, ndev);
3527 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3528 netdev_info(ndev, "calling pci_disable_msi()\n");
3529 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3530 pci_disable_msi(qdev->pdev);
3535 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3537 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3538 netdev_err(qdev->ndev,
3539 "Driver up/down cycle failed, closing device\n");
3541 dev_close(qdev->ndev);
3548 static int ql3xxx_close(struct net_device *ndev)
3550 struct ql3_adapter *qdev = netdev_priv(ndev);
3553 * Wait for device to recover from a reset.
3554 * (Rarely happens, but possible.)
3556 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3559 ql_adapter_down(qdev, QL_DO_RESET);
3563 static int ql3xxx_open(struct net_device *ndev)
3565 struct ql3_adapter *qdev = netdev_priv(ndev);
3566 return ql_adapter_up(qdev);
3569 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3571 struct ql3_adapter *qdev = netdev_priv(ndev);
3572 struct ql3xxx_port_registers __iomem *port_regs =
3573 qdev->mem_map_registers;
3574 struct sockaddr *addr = p;
3575 unsigned long hw_flags;
3577 if (netif_running(ndev))
3580 if (!is_valid_ether_addr(addr->sa_data))
3581 return -EADDRNOTAVAIL;
3583 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3585 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3586 /* Program lower 32 bits of the MAC address */
3587 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3588 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3589 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3590 ((ndev->dev_addr[2] << 24) | (ndev->
3591 dev_addr[3] << 16) |
3592 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3594 /* Program top 16 bits of the MAC address */
3595 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3596 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3597 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3598 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3599 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3604 static void ql3xxx_tx_timeout(struct net_device *ndev)
3606 struct ql3_adapter *qdev = netdev_priv(ndev);
3608 netdev_err(ndev, "Resetting...\n");
3610 * Stop the queues, we've got a problem.
3612 netif_stop_queue(ndev);
3615 * Wake up the worker to process this event.
3617 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3620 static void ql_reset_work(struct work_struct *work)
3622 struct ql3_adapter *qdev =
3623 container_of(work, struct ql3_adapter, reset_work.work);
3624 struct net_device *ndev = qdev->ndev;
3626 struct ql_tx_buf_cb *tx_cb;
3627 int max_wait_time, i;
3628 struct ql3xxx_port_registers __iomem *port_regs =
3629 qdev->mem_map_registers;
3630 unsigned long hw_flags;
3632 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
3633 clear_bit(QL_LINK_MASTER, &qdev->flags);
3636 * Loop through the active list and return the skb.
3638 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3640 tx_cb = &qdev->tx_buf[i];
3642 netdev_printk(KERN_DEBUG, ndev,
3643 "Freeing lost SKB\n");
3644 pci_unmap_single(qdev->pdev,
3645 dma_unmap_addr(&tx_cb->map[0],
3647 dma_unmap_len(&tx_cb->map[0], maplen),
3649 for (j = 1; j < tx_cb->seg_count; j++) {
3650 pci_unmap_page(qdev->pdev,
3651 dma_unmap_addr(&tx_cb->map[j],
3653 dma_unmap_len(&tx_cb->map[j],
3657 dev_kfree_skb(tx_cb->skb);
3662 netdev_err(ndev, "Clearing NRI after reset\n");
3663 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3664 ql_write_common_reg(qdev,
3665 &port_regs->CommonRegs.
3667 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3669 * Wait the for Soft Reset to Complete.
3673 value = ql_read_common_reg(qdev,
3674 &port_regs->CommonRegs.
3677 if ((value & ISP_CONTROL_SR) == 0) {
3678 netdev_printk(KERN_DEBUG, ndev,
3679 "reset completed\n");
3683 if (value & ISP_CONTROL_RI) {
3684 netdev_printk(KERN_DEBUG, ndev,
3685 "clearing NRI after reset\n");
3686 ql_write_common_reg(qdev,
3691 16) | ISP_CONTROL_RI));
3694 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3696 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3697 } while (--max_wait_time);
3698 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3700 if (value & ISP_CONTROL_SR) {
3703 * Set the reset flags and clear the board again.
3704 * Nothing else to do...
3707 "Timed out waiting for reset to complete\n");
3708 netdev_err(ndev, "Do a reset\n");
3709 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3710 clear_bit(QL_RESET_START, &qdev->flags);
3711 ql_cycle_adapter(qdev, QL_DO_RESET);
3715 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3716 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3717 clear_bit(QL_RESET_START, &qdev->flags);
3718 ql_cycle_adapter(qdev, QL_NO_RESET);
3722 static void ql_tx_timeout_work(struct work_struct *work)
3724 struct ql3_adapter *qdev =
3725 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3727 ql_cycle_adapter(qdev, QL_DO_RESET);
3730 static void ql_get_board_info(struct ql3_adapter *qdev)
3732 struct ql3xxx_port_registers __iomem *port_regs =
3733 qdev->mem_map_registers;
3736 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3738 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3739 if (value & PORT_STATUS_64)
3740 qdev->pci_width = 64;
3742 qdev->pci_width = 32;
3743 if (value & PORT_STATUS_X)
3747 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3750 static void ql3xxx_timer(struct timer_list *t)
3752 struct ql3_adapter *qdev = from_timer(qdev, t, adapter_timer);
3753 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3756 static const struct net_device_ops ql3xxx_netdev_ops = {
3757 .ndo_open = ql3xxx_open,
3758 .ndo_start_xmit = ql3xxx_send,
3759 .ndo_stop = ql3xxx_close,
3760 .ndo_validate_addr = eth_validate_addr,
3761 .ndo_set_mac_address = ql3xxx_set_mac_address,
3762 .ndo_tx_timeout = ql3xxx_tx_timeout,
3765 static int ql3xxx_probe(struct pci_dev *pdev,
3766 const struct pci_device_id *pci_entry)
3768 struct net_device *ndev = NULL;
3769 struct ql3_adapter *qdev = NULL;
3770 static int cards_found;
3771 int uninitialized_var(pci_using_dac), err;
3773 err = pci_enable_device(pdev);
3775 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3779 err = pci_request_regions(pdev, DRV_NAME);
3781 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3782 goto err_out_disable_pdev;
3785 pci_set_master(pdev);
3787 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3789 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3790 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3792 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3796 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3797 goto err_out_free_regions;
3800 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3803 goto err_out_free_regions;
3806 SET_NETDEV_DEV(ndev, &pdev->dev);
3808 pci_set_drvdata(pdev, ndev);
3810 qdev = netdev_priv(ndev);
3811 qdev->index = cards_found;
3814 qdev->device_id = pci_entry->device;
3815 qdev->port_link_state = LS_DOWN;
3819 qdev->msg_enable = netif_msg_init(debug, default_msg);
3822 ndev->features |= NETIF_F_HIGHDMA;
3823 if (qdev->device_id == QL3032_DEVICE_ID)
3824 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3826 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3827 if (!qdev->mem_map_registers) {
3828 pr_err("%s: cannot map device registers\n", pci_name(pdev));
3830 goto err_out_free_ndev;
3833 spin_lock_init(&qdev->adapter_lock);
3834 spin_lock_init(&qdev->hw_lock);
3836 /* Set driver entry points */
3837 ndev->netdev_ops = &ql3xxx_netdev_ops;
3838 ndev->ethtool_ops = &ql3xxx_ethtool_ops;
3839 ndev->watchdog_timeo = 5 * HZ;
3841 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
3843 ndev->irq = pdev->irq;
3845 /* make sure the EEPROM is good */
3846 if (ql_get_nvram_params(qdev)) {
3847 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3848 __func__, qdev->index);
3850 goto err_out_iounmap;
3853 ql_set_mac_info(qdev);
3855 /* Validate and set parameters */
3856 if (qdev->mac_index) {
3857 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3858 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3860 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3861 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3864 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3866 /* Record PCI bus information. */
3867 ql_get_board_info(qdev);
3870 * Set the Maximum Memory Read Byte Count value. We do this to handle
3874 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3876 err = register_netdev(ndev);
3878 pr_err("%s: cannot register net device\n", pci_name(pdev));
3879 goto err_out_iounmap;
3882 /* we're going to reset, so assume we have no link for now */
3884 netif_carrier_off(ndev);
3885 netif_stop_queue(ndev);
3887 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3888 if (!qdev->workqueue) {
3889 unregister_netdev(ndev);
3891 goto err_out_iounmap;
3894 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3895 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3896 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3898 timer_setup(&qdev->adapter_timer, ql3xxx_timer, 0);
3899 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3902 pr_alert("%s\n", DRV_STRING);
3903 pr_alert("Driver name: %s, Version: %s\n",
3904 DRV_NAME, DRV_VERSION);
3906 ql_display_dev_info(ndev);
3912 iounmap(qdev->mem_map_registers);
3915 err_out_free_regions:
3916 pci_release_regions(pdev);
3917 err_out_disable_pdev:
3918 pci_disable_device(pdev);
3923 static void ql3xxx_remove(struct pci_dev *pdev)
3925 struct net_device *ndev = pci_get_drvdata(pdev);
3926 struct ql3_adapter *qdev = netdev_priv(ndev);
3928 unregister_netdev(ndev);
3930 ql_disable_interrupts(qdev);
3932 if (qdev->workqueue) {
3933 cancel_delayed_work(&qdev->reset_work);
3934 cancel_delayed_work(&qdev->tx_timeout_work);
3935 destroy_workqueue(qdev->workqueue);
3936 qdev->workqueue = NULL;
3939 iounmap(qdev->mem_map_registers);
3940 pci_release_regions(pdev);
3944 static struct pci_driver ql3xxx_driver = {
3947 .id_table = ql3xxx_pci_tbl,
3948 .probe = ql3xxx_probe,
3949 .remove = ql3xxx_remove,
3952 module_pci_driver(ql3xxx_driver);