drivers/net/ethernet/qlogic/qed/qed_roce.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/types.h>
  33 #include <asm/byteorder.h>
  34 #include <linux/bitops.h>
  35 #include <linux/delay.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/errno.h>
  38 #include <linux/io.h>
  39 #include <linux/kernel.h>
  40 #include <linux/list.h>
  41 #include <linux/module.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/string.h>
  47 #include "qed.h"
  48 #include "qed_cxt.h"
  49 #include "qed_hsi.h"
  50 #include "qed_hw.h"
  51 #include "qed_init_ops.h"
  52 #include "qed_int.h"
  53 #include "qed_ll2.h"
  54 #include "qed_mcp.h"
  55 #include "qed_reg_addr.h"
  56 #include <linux/qed/qed_rdma_if.h>
  57 #include "qed_rdma.h"
  58 #include "qed_roce.h"
  59 #include "qed_sp.h"
  60
  61 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid);
  62
  63 static int
  64 qed_roce_async_event(struct qed_hwfn *p_hwfn,
  65                      u8 fw_event_code,
  66                      u16 echo, union event_ring_data *data, u8 fw_return_code)
  67 {
  68         if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) {
  69                 u16 icid =
  70                     (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid);
  71
  72                 /* icid release in this async event can occur only if the icid
  73                  * was offloaded to the FW. In case it wasn't offloaded this is
  74                  * handled in qed_roce_sp_destroy_qp.
  75                  */
  76                 qed_roce_free_real_icid(p_hwfn, icid);
  77         } else {
  78                 struct qed_rdma_events *events = &p_hwfn->p_rdma_info->events;
  79
  80                 events->affiliated_event(p_hwfn->p_rdma_info->events.context,
  81                                          fw_event_code,
  82                                      (void *)&data->rdma_data.async_handle);
  83         }
  84
  85         return 0;
  86 }
  87
  88 void qed_roce_stop(struct qed_hwfn *p_hwfn)
  89 {
  90         struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map;
  91         int wait_count = 0;
  92
  93         /* when destroying a_RoCE QP the control is returned to the user after
  94          * the synchronous part. The asynchronous part may take a little longer.
  95          * We delay for a short while if an async destroy QP is still expected.
  96          * Beyond the added delay we clear the bitmap anyway.
  97          */
  98         while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) {
  99                 msleep(100);
 100                 if (wait_count++ > 20) {
 101                         DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n");
 102                         break;
 103                 }
 104         }
 105         qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_ROCE);
 106 }
 107
 108 static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid,
 109                                __le32 *dst_gid)
 110 {
 111         u32 i;
 112
 113         if (qp->roce_mode == ROCE_V2_IPV4) {
 114                 /* The IPv4 addresses shall be aligned to the highest word.
 115                  * The lower words must be zero.
 116                  */
 117                 memset(src_gid, 0, sizeof(union qed_gid));
 118                 memset(dst_gid, 0, sizeof(union qed_gid));
 119                 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr);
 120                 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr);
 121         } else {
 122                 /* GIDs and IPv6 addresses coincide in location and size */
 123                 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) {
 124                         src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]);
 125                         dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]);
 126                 }
 127         }
 128 }
 129
 130 static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode)
 131 {
 132         enum roce_flavor flavor;
 133
 134         switch (roce_mode) {
 135         case ROCE_V1:
 136                 flavor = PLAIN_ROCE;
 137                 break;
 138         case ROCE_V2_IPV4:
 139                 flavor = RROCE_IPV4;
 140                 break;
 141         case ROCE_V2_IPV6:
 142                 flavor = ROCE_V2_IPV6;
 143                 break;
 144         default:
 145                 flavor = MAX_ROCE_MODE;
 146                 break;
 147         }
 148         return flavor;
 149 }
 150
 151 void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid)
 152 {
 153         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 154         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid);
 155         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1);
 156         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 157 }
 158
 159 int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid)
 160 {
 161         struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
 162         u32 responder_icid;
 163         u32 requester_icid;
 164         int rc;
 165
 166         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 167         rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
 168                                     &responder_icid);
 169         if (rc) {
 170                 spin_unlock_bh(&p_rdma_info->lock);
 171                 return rc;
 172         }
 173
 174         rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
 175                                     &requester_icid);
 176
 177         spin_unlock_bh(&p_rdma_info->lock);
 178         if (rc)
 179                 goto err;
 180
 181         /* the two icid's should be adjacent */
 182         if ((requester_icid - responder_icid) != 1) {
 183                 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n");
 184                 rc = -EINVAL;
 185                 goto err;
 186         }
 187
 188         responder_icid += qed_cxt_get_proto_cid_start(p_hwfn,
 189                                                       p_rdma_info->proto);
 190         requester_icid += qed_cxt_get_proto_cid_start(p_hwfn,
 191                                                       p_rdma_info->proto);
 192
 193         /* If these icids require a new ILT line allocate DMA-able context for
 194          * an ILT page
 195          */
 196         rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid);
 197         if (rc)
 198                 goto err;
 199
 200         rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid);
 201         if (rc)
 202                 goto err;
 203
 204         *cid = (u16)responder_icid;
 205         return rc;
 206
 207 err:
 208         spin_lock_bh(&p_rdma_info->lock);
 209         qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid);
 210         qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid);
 211
 212         spin_unlock_bh(&p_rdma_info->lock);
 213         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 214                    "Allocate CID - failed, rc = %d\n", rc);
 215         return rc;
 216 }
 217
 218 static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid)
 219 {
 220         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 221         qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid);
 222         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 223 }
 224
 225 static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn,
 226                                         struct qed_rdma_qp *qp)
 227 {
 228         struct roce_create_qp_resp_ramrod_data *p_ramrod;
 229         struct qed_sp_init_data init_data;
 230         enum roce_flavor roce_flavor;
 231         struct qed_spq_entry *p_ent;
 232         u16 regular_latency_queue;
 233         enum protocol_type proto;
 234         int rc;
 235
 236         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
 237
 238         /* Allocate DMA-able memory for IRQ */
 239         qp->irq_num_pages = 1;
 240         qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 241                                      RDMA_RING_PAGE_SIZE,
 242                                      &qp->irq_phys_addr, GFP_KERNEL);
 243         if (!qp->irq) {
 244                 rc = -ENOMEM;
 245                 DP_NOTICE(p_hwfn,
 246                           "qed create responder failed: cannot allocate memory (irq). rc = %d\n",
 247                           rc);
 248                 return rc;
 249         }
 250
 251         /* Get SPQ entry */
 252         memset(&init_data, 0, sizeof(init_data));
 253         init_data.cid = qp->icid;
 254         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 255         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 256
 257         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP,
 258                                  PROTOCOLID_ROCE, &init_data);
 259         if (rc)
 260                 goto err;
 261
 262         p_ramrod = &p_ent->ramrod.roce_create_qp_resp;
 263
 264         p_ramrod->flags = 0;
 265
 266         roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
 267         SET_FIELD(p_ramrod->flags,
 268                   ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
 269
 270         SET_FIELD(p_ramrod->flags,
 271                   ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
 272                   qp->incoming_rdma_read_en);
 273
 274         SET_FIELD(p_ramrod->flags,
 275                   ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
 276                   qp->incoming_rdma_write_en);
 277
 278         SET_FIELD(p_ramrod->flags,
 279                   ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN,
 280                   qp->incoming_atomic_en);
 281
 282         SET_FIELD(p_ramrod->flags,
 283                   ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
 284                   qp->e2e_flow_control_en);
 285
 286         SET_FIELD(p_ramrod->flags,
 287                   ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq);
 288
 289         SET_FIELD(p_ramrod->flags,
 290                   ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN,
 291                   qp->fmr_and_reserved_lkey);
 292
 293         SET_FIELD(p_ramrod->flags,
 294                   ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
 295                   qp->min_rnr_nak_timer);
 296
 297         p_ramrod->max_ird = qp->max_rd_atomic_resp;
 298         p_ramrod->traffic_class = qp->traffic_class_tos;
 299         p_ramrod->hop_limit = qp->hop_limit_ttl;
 300         p_ramrod->irq_num_pages = qp->irq_num_pages;
 301         p_ramrod->p_key = cpu_to_le16(qp->pkey);
 302         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
 303         p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
 304         p_ramrod->mtu = cpu_to_le16(qp->mtu);
 305         p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn);
 306         p_ramrod->pd = cpu_to_le16(qp->pd);
 307         p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages);
 308         DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr);
 309         DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr);
 310         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
 311         p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
 312         p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
 313         p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
 314         p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
 315         p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) |
 316                                        qp->rq_cq_id);
 317
 318         regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 319
 320         p_ramrod->regular_latency_phy_queue =
 321             cpu_to_le16(regular_latency_queue);
 322         p_ramrod->low_latency_phy_queue =
 323             cpu_to_le16(regular_latency_queue);
 324
 325         p_ramrod->dpi = cpu_to_le16(qp->dpi);
 326
 327         qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
 328         qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
 329
 330         p_ramrod->udp_src_port = qp->udp_src_port;
 331         p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
 332         p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id);
 333         p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid);
 334
 335         p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
 336                                      qp->stats_queue;
 337
 338         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 339
 340         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 341                    "rc = %d regular physical queue = 0x%x\n", rc,
 342                    regular_latency_queue);
 343
 344         if (rc)
 345                 goto err;
 346
 347         qp->resp_offloaded = true;
 348         qp->cq_prod = 0;
 349
 350         proto = p_hwfn->p_rdma_info->proto;
 351         qed_roce_set_real_cid(p_hwfn, qp->icid -
 352                               qed_cxt_get_proto_cid_start(p_hwfn, proto));
 353
 354         return rc;
 355
 356 err:
 357         DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc);
 358         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 359                           qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
 360                           qp->irq, qp->irq_phys_addr);
 361
 362         return rc;
 363 }
 364
 365 static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn,
 366                                         struct qed_rdma_qp *qp)
 367 {
 368         struct roce_create_qp_req_ramrod_data *p_ramrod;
 369         struct qed_sp_init_data init_data;
 370         enum roce_flavor roce_flavor;
 371         struct qed_spq_entry *p_ent;
 372         u16 regular_latency_queue;
 373         enum protocol_type proto;
 374         int rc;
 375
 376         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
 377
 378         /* Allocate DMA-able memory for ORQ */
 379         qp->orq_num_pages = 1;
 380         qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 381                                      RDMA_RING_PAGE_SIZE,
 382                                      &qp->orq_phys_addr, GFP_KERNEL);
 383         if (!qp->orq) {
 384                 rc = -ENOMEM;
 385                 DP_NOTICE(p_hwfn,
 386                           "qed create requester failed: cannot allocate memory (orq). rc = %d\n",
 387                           rc);
 388                 return rc;
 389         }
 390
 391         /* Get SPQ entry */
 392         memset(&init_data, 0, sizeof(init_data));
 393         init_data.cid = qp->icid + 1;
 394         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 395         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 396
 397         rc = qed_sp_init_request(p_hwfn, &p_ent,
 398                                  ROCE_RAMROD_CREATE_QP,
 399                                  PROTOCOLID_ROCE, &init_data);
 400         if (rc)
 401                 goto err;
 402
 403         p_ramrod = &p_ent->ramrod.roce_create_qp_req;
 404
 405         p_ramrod->flags = 0;
 406
 407         roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
 408         SET_FIELD(p_ramrod->flags,
 409                   ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
 410
 411         SET_FIELD(p_ramrod->flags,
 412                   ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN,
 413                   qp->fmr_and_reserved_lkey);
 414
 415         SET_FIELD(p_ramrod->flags,
 416                   ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all);
 417
 418         SET_FIELD(p_ramrod->flags,
 419                   ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
 420
 421         SET_FIELD(p_ramrod->flags,
 422                   ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
 423                   qp->rnr_retry_cnt);
 424
 425         p_ramrod->max_ord = qp->max_rd_atomic_req;
 426         p_ramrod->traffic_class = qp->traffic_class_tos;
 427         p_ramrod->hop_limit = qp->hop_limit_ttl;
 428         p_ramrod->orq_num_pages = qp->orq_num_pages;
 429         p_ramrod->p_key = cpu_to_le16(qp->pkey);
 430         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
 431         p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
 432         p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
 433         p_ramrod->mtu = cpu_to_le16(qp->mtu);
 434         p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn);
 435         p_ramrod->pd = cpu_to_le16(qp->pd);
 436         p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages);
 437         DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr);
 438         DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr);
 439         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
 440         p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
 441         p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
 442         p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
 443         p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
 444         p_ramrod->cq_cid =
 445             cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id);
 446
 447         regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 448
 449         p_ramrod->regular_latency_phy_queue =
 450             cpu_to_le16(regular_latency_queue);
 451         p_ramrod->low_latency_phy_queue =
 452             cpu_to_le16(regular_latency_queue);
 453
 454         p_ramrod->dpi = cpu_to_le16(qp->dpi);
 455
 456         qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
 457         qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
 458
 459         p_ramrod->udp_src_port = qp->udp_src_port;
 460         p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
 461         p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
 462                                      qp->stats_queue;
 463
 464         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 465
 466         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
 467
 468         if (rc)
 469                 goto err;
 470
 471         qp->req_offloaded = true;
 472         proto = p_hwfn->p_rdma_info->proto;
 473         qed_roce_set_real_cid(p_hwfn,
 474                               qp->icid + 1 -
 475                               qed_cxt_get_proto_cid_start(p_hwfn, proto));
 476
 477         return rc;
 478
 479 err:
 480         DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc);
 481         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 482                           qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
 483                           qp->orq, qp->orq_phys_addr);
 484         return rc;
 485 }
 486
 487 static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn,
 488                                         struct qed_rdma_qp *qp,
 489                                         bool move_to_err, u32 modify_flags)
 490 {
 491         struct roce_modify_qp_resp_ramrod_data *p_ramrod;
 492         struct qed_sp_init_data init_data;
 493         struct qed_spq_entry *p_ent;
 494         int rc;
 495
 496         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
 497
 498         if (move_to_err && !qp->resp_offloaded)
 499                 return 0;
 500
 501         /* Get SPQ entry */
 502         memset(&init_data, 0, sizeof(init_data));
 503         init_data.cid = qp->icid;
 504         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 505         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 506
 507         rc = qed_sp_init_request(p_hwfn, &p_ent,
 508                                  ROCE_EVENT_MODIFY_QP,
 509                                  PROTOCOLID_ROCE, &init_data);
 510         if (rc) {
 511                 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
 512                 return rc;
 513         }
 514
 515         p_ramrod = &p_ent->ramrod.roce_modify_qp_resp;
 516
 517         p_ramrod->flags = 0;
 518
 519         SET_FIELD(p_ramrod->flags,
 520                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
 521
 522         SET_FIELD(p_ramrod->flags,
 523                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
 524                   qp->incoming_rdma_read_en);
 525
 526         SET_FIELD(p_ramrod->flags,
 527                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
 528                   qp->incoming_rdma_write_en);
 529
 530         SET_FIELD(p_ramrod->flags,
 531                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN,
 532                   qp->incoming_atomic_en);
 533
 534         SET_FIELD(p_ramrod->flags,
 535                   ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
 536                   qp->e2e_flow_control_en);
 537
 538         SET_FIELD(p_ramrod->flags,
 539                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG,
 540                   GET_FIELD(modify_flags,
 541                             QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN));
 542
 543         SET_FIELD(p_ramrod->flags,
 544                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG,
 545                   GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
 546
 547         SET_FIELD(p_ramrod->flags,
 548                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG,
 549                   GET_FIELD(modify_flags,
 550                             QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
 551
 552         SET_FIELD(p_ramrod->flags,
 553                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG,
 554                   GET_FIELD(modify_flags,
 555                             QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP));
 556
 557         SET_FIELD(p_ramrod->flags,
 558                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG,
 559                   GET_FIELD(modify_flags,
 560                             QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER));
 561
 562         p_ramrod->fields = 0;
 563         SET_FIELD(p_ramrod->fields,
 564                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
 565                   qp->min_rnr_nak_timer);
 566
 567         p_ramrod->max_ird = qp->max_rd_atomic_resp;
 568         p_ramrod->traffic_class = qp->traffic_class_tos;
 569         p_ramrod->hop_limit = qp->hop_limit_ttl;
 570         p_ramrod->p_key = cpu_to_le16(qp->pkey);
 571         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
 572         p_ramrod->mtu = cpu_to_le16(qp->mtu);
 573         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
 574         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 575
 576         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc);
 577         return rc;
 578 }
 579
 580 static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn,
 581                                         struct qed_rdma_qp *qp,
 582                                         bool move_to_sqd,
 583                                         bool move_to_err, u32 modify_flags)
 584 {
 585         struct roce_modify_qp_req_ramrod_data *p_ramrod;
 586         struct qed_sp_init_data init_data;
 587         struct qed_spq_entry *p_ent;
 588         int rc;
 589
 590         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
 591
 592         if (move_to_err && !(qp->req_offloaded))
 593                 return 0;
 594
 595         /* Get SPQ entry */
 596         memset(&init_data, 0, sizeof(init_data));
 597         init_data.cid = qp->icid + 1;
 598         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 599         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 600
 601         rc = qed_sp_init_request(p_hwfn, &p_ent,
 602                                  ROCE_EVENT_MODIFY_QP,
 603                                  PROTOCOLID_ROCE, &init_data);
 604         if (rc) {
 605                 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
 606                 return rc;
 607         }
 608
 609         p_ramrod = &p_ent->ramrod.roce_modify_qp_req;
 610
 611         p_ramrod->flags = 0;
 612
 613         SET_FIELD(p_ramrod->flags,
 614                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
 615
 616         SET_FIELD(p_ramrod->flags,
 617                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd);
 618
 619         SET_FIELD(p_ramrod->flags,
 620                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY,
 621                   qp->sqd_async);
 622
 623         SET_FIELD(p_ramrod->flags,
 624                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG,
 625                   GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
 626
 627         SET_FIELD(p_ramrod->flags,
 628                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG,
 629                   GET_FIELD(modify_flags,
 630                             QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
 631
 632         SET_FIELD(p_ramrod->flags,
 633                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG,
 634                   GET_FIELD(modify_flags,
 635                             QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ));
 636
 637         SET_FIELD(p_ramrod->flags,
 638                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG,
 639                   GET_FIELD(modify_flags,
 640                             QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT));
 641
 642         SET_FIELD(p_ramrod->flags,
 643                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG,
 644                   GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT));
 645
 646         SET_FIELD(p_ramrod->flags,
 647                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG,
 648                   GET_FIELD(modify_flags,
 649                             QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT));
 650
 651         p_ramrod->fields = 0;
 652         SET_FIELD(p_ramrod->fields,
 653                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
 654
 655         SET_FIELD(p_ramrod->fields,
 656                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
 657                   qp->rnr_retry_cnt);
 658
 659         p_ramrod->max_ord = qp->max_rd_atomic_req;
 660         p_ramrod->traffic_class = qp->traffic_class_tos;
 661         p_ramrod->hop_limit = qp->hop_limit_ttl;
 662         p_ramrod->p_key = cpu_to_le16(qp->pkey);
 663         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
 664         p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
 665         p_ramrod->mtu = cpu_to_le16(qp->mtu);
 666         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
 667         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 668
 669         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc);
 670         return rc;
 671 }
 672
 673 static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn,
 674                                             struct qed_rdma_qp *qp,
 675                                             u32 *num_invalidated_mw,
 676                                             u32 *cq_prod)
 677 {
 678         struct roce_destroy_qp_resp_output_params *p_ramrod_res;
 679         struct roce_destroy_qp_resp_ramrod_data *p_ramrod;
 680         struct qed_sp_init_data init_data;
 681         struct qed_spq_entry *p_ent;
 682         dma_addr_t ramrod_res_phys;
 683         int rc;
 684
 685         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
 686
 687         *num_invalidated_mw = 0;
 688         *cq_prod = qp->cq_prod;
 689
 690         if (!qp->resp_offloaded) {
 691                 /* If a responder was never offload, we need to free the cids
 692                  * allocated in create_qp as a FW async event will never arrive
 693                  */
 694                 u32 cid;
 695
 696                 cid = qp->icid -
 697                       qed_cxt_get_proto_cid_start(p_hwfn,
 698                                                   p_hwfn->p_rdma_info->proto);
 699                 qed_roce_free_cid_pair(p_hwfn, (u16)cid);
 700
 701                 return 0;
 702         }
 703
 704         /* Get SPQ entry */
 705         memset(&init_data, 0, sizeof(init_data));
 706         init_data.cid = qp->icid;
 707         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 708         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 709
 710         rc = qed_sp_init_request(p_hwfn, &p_ent,
 711                                  ROCE_RAMROD_DESTROY_QP,
 712                                  PROTOCOLID_ROCE, &init_data);
 713         if (rc)
 714                 return rc;
 715
 716         p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp;
 717
 718         p_ramrod_res = (struct roce_destroy_qp_resp_output_params *)
 719             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
 720                                &ramrod_res_phys, GFP_KERNEL);
 721
 722         if (!p_ramrod_res) {
 723                 rc = -ENOMEM;
 724                 DP_NOTICE(p_hwfn,
 725                           "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n",
 726                           rc);
 727                 return rc;
 728         }
 729
 730         DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
 731
 732         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 733         if (rc)
 734                 goto err;
 735
 736         *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw);
 737         *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod);
 738         qp->cq_prod = *cq_prod;
 739
 740         /* Free IRQ - only if ramrod succeeded, in case FW is still using it */
 741         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 742                           qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
 743                           qp->irq, qp->irq_phys_addr);
 744
 745         qp->resp_offloaded = false;
 746
 747         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc);
 748
 749 err:
 750         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 751                           sizeof(struct roce_destroy_qp_resp_output_params),
 752                           p_ramrod_res, ramrod_res_phys);
 753
 754         return rc;
 755 }
 756
 757 static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn,
 758                                             struct qed_rdma_qp *qp,
 759                                             u32 *num_bound_mw)
 760 {
 761         struct roce_destroy_qp_req_output_params *p_ramrod_res;
 762         struct roce_destroy_qp_req_ramrod_data *p_ramrod;
 763         struct qed_sp_init_data init_data;
 764         struct qed_spq_entry *p_ent;
 765         dma_addr_t ramrod_res_phys;
 766         int rc = -ENOMEM;
 767
 768         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
 769
 770         if (!qp->req_offloaded)
 771                 return 0;
 772
 773         p_ramrod_res = (struct roce_destroy_qp_req_output_params *)
 774                        dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 775                                           sizeof(*p_ramrod_res),
 776                                           &ramrod_res_phys, GFP_KERNEL);
 777         if (!p_ramrod_res) {
 778                 DP_NOTICE(p_hwfn,
 779                           "qed destroy requester failed: cannot allocate memory (ramrod)\n");
 780                 return rc;
 781         }
 782
 783         /* Get SPQ entry */
 784         memset(&init_data, 0, sizeof(init_data));
 785         init_data.cid = qp->icid + 1;
 786         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 787         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 788
 789         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP,
 790                                  PROTOCOLID_ROCE, &init_data);
 791         if (rc)
 792                 goto err;
 793
 794         p_ramrod = &p_ent->ramrod.roce_destroy_qp_req;
 795         DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
 796
 797         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 798         if (rc)
 799                 goto err;
 800
 801         *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw);
 802
 803         /* Free ORQ - only if ramrod succeeded, in case FW is still using it */
 804         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 805                           qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
 806                           qp->orq, qp->orq_phys_addr);
 807
 808         qp->req_offloaded = false;
 809
 810         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc);
 811
 812 err:
 813         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
 814                           p_ramrod_res, ramrod_res_phys);
 815
 816         return rc;
 817 }
 818
 819 int qed_roce_query_qp(struct qed_hwfn *p_hwfn,
 820                       struct qed_rdma_qp *qp,
 821                       struct qed_rdma_query_qp_out_params *out_params)
 822 {
 823         struct roce_query_qp_resp_output_params *p_resp_ramrod_res;
 824         struct roce_query_qp_req_output_params *p_req_ramrod_res;
 825         struct roce_query_qp_resp_ramrod_data *p_resp_ramrod;
 826         struct roce_query_qp_req_ramrod_data *p_req_ramrod;
 827         struct qed_sp_init_data init_data;
 828         dma_addr_t resp_ramrod_res_phys;
 829         dma_addr_t req_ramrod_res_phys;
 830         struct qed_spq_entry *p_ent;
 831         bool rq_err_state;
 832         bool sq_err_state;
 833         bool sq_draining;
 834         int rc = -ENOMEM;
 835
 836         if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) {
 837                 /* We can't send ramrod to the fw since this qp wasn't offloaded
 838                  * to the fw yet
 839                  */
 840                 out_params->draining = false;
 841                 out_params->rq_psn = qp->rq_psn;
 842                 out_params->sq_psn = qp->sq_psn;
 843                 out_params->state = qp->cur_state;
 844
 845                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n");
 846                 return 0;
 847         }
 848
 849         if (!(qp->resp_offloaded)) {
 850                 DP_NOTICE(p_hwfn,
 851                           "The responder's qp should be offloded before requester's\n");
 852                 return -EINVAL;
 853         }
 854
 855         /* Send a query responder ramrod to FW to get RQ-PSN and state */
 856         p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *)
 857             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 858                                sizeof(*p_resp_ramrod_res),
 859                                &resp_ramrod_res_phys, GFP_KERNEL);
 860         if (!p_resp_ramrod_res) {
 861                 DP_NOTICE(p_hwfn,
 862                           "qed query qp failed: cannot allocate memory (ramrod)\n");
 863                 return rc;
 864         }
 865
 866         /* Get SPQ entry */
 867         memset(&init_data, 0, sizeof(init_data));
 868         init_data.cid = qp->icid;
 869         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 870         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 871         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
 872                                  PROTOCOLID_ROCE, &init_data);
 873         if (rc)
 874                 goto err_resp;
 875
 876         p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp;
 877         DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys);
 878
 879         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 880         if (rc)
 881                 goto err_resp;
 882
 883         out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn);
 884         rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag),
 885                                  ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG);
 886
 887         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
 888                           p_resp_ramrod_res, resp_ramrod_res_phys);
 889
 890         if (!(qp->req_offloaded)) {
 891                 /* Don't send query qp for the requester */
 892                 out_params->sq_psn = qp->sq_psn;
 893                 out_params->draining = false;
 894
 895                 if (rq_err_state)
 896                         qp->cur_state = QED_ROCE_QP_STATE_ERR;
 897
 898                 out_params->state = qp->cur_state;
 899
 900                 return 0;
 901         }
 902
 903         /* Send a query requester ramrod to FW to get SQ-PSN and state */
 904         p_req_ramrod_res = (struct roce_query_qp_req_output_params *)
 905                            dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 906                                               sizeof(*p_req_ramrod_res),
 907                                               &req_ramrod_res_phys,
 908                                               GFP_KERNEL);
 909         if (!p_req_ramrod_res) {
 910                 rc = -ENOMEM;
 911                 DP_NOTICE(p_hwfn,
 912                           "qed query qp failed: cannot allocate memory (ramrod)\n");
 913                 return rc;
 914         }
 915
 916         /* Get SPQ entry */
 917         init_data.cid = qp->icid + 1;
 918         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
 919                                  PROTOCOLID_ROCE, &init_data);
 920         if (rc)
 921                 goto err_req;
 922
 923         p_req_ramrod = &p_ent->ramrod.roce_query_qp_req;
 924         DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys);
 925
 926         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 927         if (rc)
 928                 goto err_req;
 929
 930         out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn);
 931         sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
 932                                  ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG);
 933         sq_draining =
 934                 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
 935                           ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG);
 936
 937         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
 938                           p_req_ramrod_res, req_ramrod_res_phys);
 939
 940         out_params->draining = false;
 941
 942         if (rq_err_state || sq_err_state)
 943                 qp->cur_state = QED_ROCE_QP_STATE_ERR;
 944         else if (sq_draining)
 945                 out_params->draining = true;
 946         out_params->state = qp->cur_state;
 947
 948         return 0;
 949
 950 err_req:
 951         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
 952                           p_req_ramrod_res, req_ramrod_res_phys);
 953         return rc;
 954 err_resp:
 955         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
 956                           p_resp_ramrod_res, resp_ramrod_res_phys);
 957         return rc;
 958 }
 959
 960 int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
 961 {
 962         u32 num_invalidated_mw = 0;
 963         u32 num_bound_mw = 0;
 964         u32 cq_prod;
 965         int rc;
 966
 967         /* Destroys the specified QP */
 968         if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) &&
 969             (qp->cur_state != QED_ROCE_QP_STATE_ERR) &&
 970             (qp->cur_state != QED_ROCE_QP_STATE_INIT)) {
 971                 DP_NOTICE(p_hwfn,
 972                           "QP must be in error, reset or init state before destroying it\n");
 973                 return -EINVAL;
 974         }
 975
 976         if (qp->cur_state != QED_ROCE_QP_STATE_RESET) {
 977                 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp,
 978                                                       &num_invalidated_mw,
 979                                                       &cq_prod);
 980                 if (rc)
 981                         return rc;
 982
 983                 /* Send destroy requester ramrod */
 984                 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp,
 985                                                       &num_bound_mw);
 986                 if (rc)
 987                         return rc;
 988
 989                 if (num_invalidated_mw != num_bound_mw) {
 990                         DP_NOTICE(p_hwfn,
 991                                   "number of invalidate memory windows is different from bounded ones\n");
 992                         return -EINVAL;
 993                 }
 994         }
 995
 996         return 0;
 997 }
 998
 999 int qed_roce_modify_qp(struct qed_hwfn *p_hwfn,
1000                        struct qed_rdma_qp *qp,
1001                        enum qed_roce_qp_state prev_state,
1002                        struct qed_rdma_modify_qp_in_params *params)
1003 {
1004         u32 num_invalidated_mw = 0, num_bound_mw = 0;
1005         int rc = 0;
1006
1007         /* Perform additional operations according to the current state and the
1008          * next state
1009          */
1010         if (((prev_state == QED_ROCE_QP_STATE_INIT) ||
1011              (prev_state == QED_ROCE_QP_STATE_RESET)) &&
1012             (qp->cur_state == QED_ROCE_QP_STATE_RTR)) {
1013                 /* Init->RTR or Reset->RTR */
1014                 rc = qed_roce_sp_create_responder(p_hwfn, qp);
1015                 return rc;
1016         } else if ((prev_state == QED_ROCE_QP_STATE_RTR) &&
1017                    (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
1018                 /* RTR-> RTS */
1019                 rc = qed_roce_sp_create_requester(p_hwfn, qp);
1020                 if (rc)
1021                         return rc;
1022
1023                 /* Send modify responder ramrod */
1024                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
1025                                                   params->modify_flags);
1026                 return rc;
1027         } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
1028                    (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
1029                 /* RTS->RTS */
1030                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
1031                                                   params->modify_flags);
1032                 if (rc)
1033                         return rc;
1034
1035                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
1036                                                   params->modify_flags);
1037                 return rc;
1038         } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
1039                    (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
1040                 /* RTS->SQD */
1041                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false,
1042                                                   params->modify_flags);
1043                 return rc;
1044         } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
1045                    (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
1046                 /* SQD->SQD */
1047                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
1048                                                   params->modify_flags);
1049                 if (rc)
1050                         return rc;
1051
1052                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
1053                                                   params->modify_flags);
1054                 return rc;
1055         } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
1056                    (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
1057                 /* SQD->RTS */
1058                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
1059                                                   params->modify_flags);
1060                 if (rc)
1061                         return rc;
1062
1063                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
1064                                                   params->modify_flags);
1065
1066                 return rc;
1067         } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) {
1068                 /* ->ERR */
1069                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true,
1070                                                   params->modify_flags);
1071                 if (rc)
1072                         return rc;
1073
1074                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true,
1075                                                   params->modify_flags);
1076                 return rc;
1077         } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) {
1078                 /* Any state -> RESET */
1079                 u32 cq_prod;
1080
1081                 /* Send destroy responder ramrod */
1082                 rc = qed_roce_sp_destroy_qp_responder(p_hwfn,
1083                                                       qp,
1084                                                       &num_invalidated_mw,
1085                                                       &cq_prod);
1086
1087                 if (rc)
1088                         return rc;
1089
1090                 qp->cq_prod = cq_prod;
1091
1092                 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp,
1093                                                       &num_bound_mw);
1094
1095                 if (num_invalidated_mw != num_bound_mw) {
1096                         DP_NOTICE(p_hwfn,
1097                                   "number of invalidate memory windows is different from bounded ones\n");
1098                         return -EINVAL;
1099                 }
1100         } else {
1101                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
1102         }
1103
1104         return rc;
1105 }
1106
1107 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid)
1108 {
1109         struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
1110         u32 start_cid, cid, xcid;
1111
1112         /* an even icid belongs to a responder while an odd icid belongs to a
1113          * requester. The 'cid' received as an input can be either. We calculate
1114          * the "partner" icid and call it xcid. Only if both are free then the
1115          * "cid" map can be cleared.
1116          */
1117         start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto);
1118         cid = icid - start_cid;
1119         xcid = cid ^ 1;
1120
1121         spin_lock_bh(&p_rdma_info->lock);
1122
1123         qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid);
1124         if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) {
1125                 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid);
1126                 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid);
1127         }
1128
1129         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1130 }
1131
1132 void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1133 {
1134         u8 val;
1135
1136         /* if any QPs are already active, we want to disable DPM, since their
1137          * context information contains information from before the latest DCBx
1138          * update. Otherwise enable it.
1139          */
1140         val = qed_rdma_allocated_qps(p_hwfn) ? true : false;
1141         p_hwfn->dcbx_no_edpm = (u8)val;
1142
1143         qed_rdma_dpm_conf(p_hwfn, p_ptt);
1144 }
1145
1146 int qed_roce_setup(struct qed_hwfn *p_hwfn)
1147 {
1148         return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE,
1149                                          qed_roce_async_event);
1150 }
1151
1152 int qed_roce_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1153 {
1154         u32 ll2_ethertype_en;
1155
1156         qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
1157
1158         p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE;
1159
1160         ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
1161         qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
1162                (ll2_ethertype_en | 0x01));
1163
1164         if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) {
1165                 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n");
1166                 return -EINVAL;
1167         }
1168
1169         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n");
1170         return 0;
1171 }