1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
30 #define XSDM_REG_OPERATION_GEN \
32 #define NIG_REG_RX_BRB_OUT_EN \
34 #define NIG_REG_STORM_OUT_EN \
36 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
38 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
40 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
42 #define BAR0_MAP_REG_MSDM_RAM \
44 #define BAR0_MAP_REG_USDM_RAM \
46 #define BAR0_MAP_REG_PSDM_RAM \
48 #define BAR0_MAP_REG_TSDM_RAM \
50 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
52 #define PRS_REG_SEARCH_TCP \
54 #define PRS_REG_SEARCH_UDP \
56 #define PRS_REG_SEARCH_FCOE \
58 #define PRS_REG_SEARCH_ROCE \
60 #define PRS_REG_SEARCH_OPENFLOW \
62 #define TM_REG_PF_ENABLE_CONN \
64 #define TM_REG_PF_ENABLE_TASK \
66 #define TM_REG_PF_SCAN_ACTIVE_CONN \
68 #define TM_REG_PF_SCAN_ACTIVE_TASK \
70 #define IGU_REG_LEADING_EDGE_LATCH \
72 #define IGU_REG_TRAILING_EDGE_LATCH \
74 #define QM_REG_USG_CNT_PF_TX \
76 #define QM_REG_USG_CNT_PF_OTHER \
78 #define DORQ_REG_PF_DB_ENABLE \
80 #define QM_REG_PF_EN \
82 #define TCFC_REG_STRONG_ENABLE_PF \
84 #define CCFC_REG_STRONG_ENABLE_PF \
86 #define PGLUE_B_REG_PGL_ADDR_88_F0 \
88 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \
90 #define PGLUE_B_REG_PGL_ADDR_90_F0 \
92 #define PGLUE_B_REG_PGL_ADDR_94_F0 \
94 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
96 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
98 #define MISC_REG_GEN_PURP_CR0 \
100 #define MCP_REG_SCRATCH \
102 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
104 #define MISCS_REG_CHIP_NUM \
106 #define MISCS_REG_CHIP_REV \
108 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
110 #define MISCS_REG_CHIP_TEST_REG \
112 #define MISCS_REG_CHIP_METAL \
114 #define BRB_REG_HEADER_SIZE \
116 #define BTB_REG_HEADER_SIZE \
118 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
120 #define CCFC_REG_ACTIVITY_COUNTER \
122 #define CDU_REG_CID_ADDR_PARAMS \
124 #define DBG_REG_CLIENT_ENABLE \
126 #define DMAE_REG_INIT \
128 #define DORQ_REG_IFEN \
130 #define GRC_REG_TIMEOUT_EN \
132 #define IGU_REG_BLOCK_CONFIGURATION \
134 #define MCM_REG_INIT \
136 #define MCP2_REG_DBG_DWORD_ENABLE \
138 #define MISC_REG_PORT_MODE \
140 #define MISCS_REG_CLK_100G_MODE \
142 #define MSDM_REG_ENABLE_IN1 \
144 #define MSEM_REG_ENABLE_IN \
146 #define NIG_REG_CM_HDR \
148 #define NCSI_REG_CONFIG \
150 #define PBF_REG_INIT \
152 #define PTU_REG_ATC_INIT_ARRAY \
154 #define PCM_REG_INIT \
156 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
158 #define PRM_REG_DISABLE_PRM \
160 #define PRS_REG_SOFT_RST \
162 #define PSDM_REG_ENABLE_IN1 \
164 #define PSEM_REG_ENABLE_IN \
166 #define PSWRQ_REG_DBG_SELECT \
168 #define PSWRQ2_REG_CDUT_P_SIZE \
170 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
172 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
174 #define PSWRD_REG_DBG_SELECT \
176 #define PSWRD2_REG_CONF11 \
178 #define PSWWR_REG_USDM_FULL_TH \
180 #define PSWWR2_REG_CDU_FULL_TH2 \
182 #define QM_REG_MAXPQSIZE_0 \
184 #define RSS_REG_RSS_INIT_EN \
186 #define RDIF_REG_STOP_ON_ERROR \
188 #define SRC_REG_SOFT_RST \
190 #define TCFC_REG_ACTIVITY_COUNTER \
192 #define TCM_REG_INIT \
194 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
196 #define TSDM_REG_ENABLE_IN1 \
198 #define TSEM_REG_ENABLE_IN \
200 #define TDIF_REG_STOP_ON_ERROR \
202 #define UCM_REG_INIT \
204 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
206 #define USDM_REG_ENABLE_IN1 \
208 #define USEM_REG_ENABLE_IN \
210 #define XCM_REG_INIT \
212 #define XSDM_REG_ENABLE_IN1 \
214 #define XSEM_REG_ENABLE_IN \
216 #define YCM_REG_INIT \
218 #define YSDM_REG_ENABLE_IN1 \
220 #define YSEM_REG_ENABLE_IN \
222 #define XYLD_REG_SCBD_STRICT_PRIO \
224 #define TMLD_REG_SCBD_STRICT_PRIO \
226 #define MULD_REG_SCBD_STRICT_PRIO \
228 #define YULD_REG_SCBD_STRICT_PRIO \
230 #define MISC_REG_SHARED_MEM_ADDR \
232 #define DMAE_REG_GO_C0 \
234 #define DMAE_REG_GO_C1 \
236 #define DMAE_REG_GO_C2 \
238 #define DMAE_REG_GO_C3 \
240 #define DMAE_REG_GO_C4 \
242 #define DMAE_REG_GO_C5 \
244 #define DMAE_REG_GO_C6 \
246 #define DMAE_REG_GO_C7 \
248 #define DMAE_REG_GO_C8 \
250 #define DMAE_REG_GO_C9 \
252 #define DMAE_REG_GO_C10 \
254 #define DMAE_REG_GO_C11 \
256 #define DMAE_REG_GO_C12 \
258 #define DMAE_REG_GO_C13 \
260 #define DMAE_REG_GO_C14 \
262 #define DMAE_REG_GO_C15 \
264 #define DMAE_REG_GO_C16 \
266 #define DMAE_REG_GO_C17 \
268 #define DMAE_REG_GO_C18 \
270 #define DMAE_REG_GO_C19 \
272 #define DMAE_REG_GO_C20 \
274 #define DMAE_REG_GO_C21 \
276 #define DMAE_REG_GO_C22 \
278 #define DMAE_REG_GO_C23 \
280 #define DMAE_REG_GO_C24 \
282 #define DMAE_REG_GO_C25 \
284 #define DMAE_REG_GO_C26 \
286 #define DMAE_REG_GO_C27 \
288 #define DMAE_REG_GO_C28 \
290 #define DMAE_REG_GO_C29 \
292 #define DMAE_REG_GO_C30 \
294 #define DMAE_REG_GO_C31 \
296 #define DMAE_REG_CMD_MEM \
298 #define QM_REG_MAXPQSIZETXSEL_0 \
300 #define QM_REG_SDMCMDREADY \
302 #define QM_REG_SDMCMDADDR \
304 #define QM_REG_SDMCMDDATALSB \
306 #define QM_REG_SDMCMDDATAMSB \
308 #define QM_REG_SDMCMDGO \
310 #define QM_REG_RLPFCRD \
312 #define QM_REG_RLPFINCVAL \
314 #define QM_REG_RLGLBLCRD \
316 #define QM_REG_RLGLBLINCVAL \
318 #define IGU_REG_ATTENTION_ENABLE \
320 #define IGU_REG_ATTN_MSG_ADDR_L \
322 #define IGU_REG_ATTN_MSG_ADDR_H \
324 #define MISC_REG_AEU_GENERAL_ATTN_0 \
326 #define CAU_REG_SB_ADDR_MEMORY \
328 #define CAU_REG_SB_VAR_MEMORY \
330 #define CAU_REG_PI_MEMORY \
332 #define IGU_REG_PF_CONFIGURATION \
334 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
336 #define MISC_REG_AEU_MASK_ATTN_IGU \
338 #define IGU_REG_CLEANUP_STATUS_0 \
340 #define IGU_REG_CLEANUP_STATUS_1 \
342 #define IGU_REG_CLEANUP_STATUS_2 \
344 #define IGU_REG_CLEANUP_STATUS_3 \
346 #define IGU_REG_CLEANUP_STATUS_4 \
348 #define IGU_REG_COMMAND_REG_32LSB_DATA \
350 #define IGU_REG_COMMAND_REG_CTRL \
352 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
354 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
356 #define IGU_REG_MAPPING_MEMORY \
358 #define MISCS_REG_GENERIC_POR_0 \
360 #define MCP_REG_NVM_CFG4 \
362 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
364 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \