drivers/net/ethernet/qlogic/qed/qed_main.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 /* QLogic qed NIC Driver
   3  * Copyright (c) 2015-2017  QLogic Corporation
   4  * Copyright (c) 2019-2020 Marvell International Ltd.
   5  */
   6
   7 #include <linux/stddef.h>
   8 #include <linux/pci.h>
   9 #include <linux/kernel.h>
  10 #include <linux/slab.h>
  11 #include <linux/delay.h>
  12 #include <asm/byteorder.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/string.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/workqueue.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/crash_dump.h>
  22 #include <linux/crc32.h>
  23 #include <linux/qed/qed_if.h>
  24 #include <linux/qed/qed_ll2_if.h>
  25 #include <net/devlink.h>
  26 #include <linux/aer.h>
  27 #include <linux/phylink.h>
  28
  29 #include "qed.h"
  30 #include "qed_sriov.h"
  31 #include "qed_sp.h"
  32 #include "qed_dev_api.h"
  33 #include "qed_ll2.h"
  34 #include "qed_fcoe.h"
  35 #include "qed_iscsi.h"
  36
  37 #include "qed_mcp.h"
  38 #include "qed_reg_addr.h"
  39 #include "qed_hw.h"
  40 #include "qed_selftest.h"
  41 #include "qed_debug.h"
  42
  43 #define QED_ROCE_QPS                    (8192)
  44 #define QED_ROCE_DPIS                   (8)
  45 #define QED_RDMA_SRQS                   QED_ROCE_QPS
  46 #define QED_NVM_CFG_GET_FLAGS           0xA
  47 #define QED_NVM_CFG_GET_PF_FLAGS        0x1A
  48 #define QED_NVM_CFG_MAX_ATTRS           50
  49
  50 static char version[] =
  51         "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
  52
  53 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
  54 MODULE_LICENSE("GPL");
  55 MODULE_VERSION(DRV_MODULE_VERSION);
  56
  57 #define FW_FILE_VERSION                         \
  58         __stringify(FW_MAJOR_VERSION) "."       \
  59         __stringify(FW_MINOR_VERSION) "."       \
  60         __stringify(FW_REVISION_VERSION) "."    \
  61         __stringify(FW_ENGINEERING_VERSION)
  62
  63 #define QED_FW_FILE_NAME        \
  64         "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
  65
  66 MODULE_FIRMWARE(QED_FW_FILE_NAME);
  67
  68 /* MFW speed capabilities maps */
  69
  70 struct qed_mfw_speed_map {
  71         u32             mfw_val;
  72         __ETHTOOL_DECLARE_LINK_MODE_MASK(caps);
  73
  74         const u32       *cap_arr;
  75         u32             arr_size;
  76 };
  77
  78 #define QED_MFW_SPEED_MAP(type, arr)            \
  79 {                                               \
  80         .mfw_val        = (type),               \
  81         .cap_arr        = (arr),                \
  82         .arr_size       = ARRAY_SIZE(arr),      \
  83 }
  84
  85 static const u32 qed_mfw_ext_1g[] __initconst = {
  86         ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
  87         ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
  88         ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
  89 };
  90
  91 static const u32 qed_mfw_ext_10g[] __initconst = {
  92         ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  93         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
  94         ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
  95         ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
  96         ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
  97         ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
  98         ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
  99         ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 100 };
 101
 102 static const u32 qed_mfw_ext_20g[] __initconst = {
 103         ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
 104 };
 105
 106 static const u32 qed_mfw_ext_25g[] __initconst = {
 107         ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
 108         ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
 109         ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 110 };
 111
 112 static const u32 qed_mfw_ext_40g[] __initconst = {
 113         ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
 114         ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
 115         ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
 116         ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
 117 };
 118
 119 static const u32 qed_mfw_ext_50g_base_r[] __initconst = {
 120         ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
 121         ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
 122         ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
 123         ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
 124         ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
 125 };
 126
 127 static const u32 qed_mfw_ext_50g_base_r2[] __initconst = {
 128         ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
 129         ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
 130         ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 131 };
 132
 133 static const u32 qed_mfw_ext_100g_base_r2[] __initconst = {
 134         ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
 135         ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
 136         ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
 137         ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
 138         ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
 139 };
 140
 141 static const u32 qed_mfw_ext_100g_base_r4[] __initconst = {
 142         ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
 143         ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 144         ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
 145         ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
 146 };
 147
 148 static struct qed_mfw_speed_map qed_mfw_ext_maps[] __ro_after_init = {
 149         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_1G, qed_mfw_ext_1g),
 150         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_10G, qed_mfw_ext_10g),
 151         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_20G, qed_mfw_ext_20g),
 152         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_25G, qed_mfw_ext_25g),
 153         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_40G, qed_mfw_ext_40g),
 154         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_50G_BASE_R,
 155                           qed_mfw_ext_50g_base_r),
 156         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_50G_BASE_R2,
 157                           qed_mfw_ext_50g_base_r2),
 158         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_100G_BASE_R2,
 159                           qed_mfw_ext_100g_base_r2),
 160         QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_100G_BASE_R4,
 161                           qed_mfw_ext_100g_base_r4),
 162 };
 163
 164 static const u32 qed_mfw_legacy_1g[] __initconst = {
 165         ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 166         ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 167         ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 168 };
 169
 170 static const u32 qed_mfw_legacy_10g[] __initconst = {
 171         ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 172         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 173         ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 174         ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
 175         ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
 176         ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 177         ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 178         ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 179 };
 180
 181 static const u32 qed_mfw_legacy_20g[] __initconst = {
 182         ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
 183 };
 184
 185 static const u32 qed_mfw_legacy_25g[] __initconst = {
 186         ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
 187         ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
 188         ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 189 };
 190
 191 static const u32 qed_mfw_legacy_40g[] __initconst = {
 192         ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
 193         ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
 194         ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
 195         ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
 196 };
 197
 198 static const u32 qed_mfw_legacy_50g[] __initconst = {
 199         ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
 200         ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
 201         ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 202 };
 203
 204 static const u32 qed_mfw_legacy_bb_100g[] __initconst = {
 205         ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
 206         ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 207         ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
 208         ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
 209 };
 210
 211 static struct qed_mfw_speed_map qed_mfw_legacy_maps[] __ro_after_init = {
 212         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G,
 213                           qed_mfw_legacy_1g),
 214         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G,
 215                           qed_mfw_legacy_10g),
 216         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G,
 217                           qed_mfw_legacy_20g),
 218         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G,
 219                           qed_mfw_legacy_25g),
 220         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G,
 221                           qed_mfw_legacy_40g),
 222         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G,
 223                           qed_mfw_legacy_50g),
 224         QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G,
 225                           qed_mfw_legacy_bb_100g),
 226 };
 227
 228 static void __init qed_mfw_speed_map_populate(struct qed_mfw_speed_map *map)
 229 {
 230         linkmode_set_bit_array(map->cap_arr, map->arr_size, map->caps);
 231
 232         map->cap_arr = NULL;
 233         map->arr_size = 0;
 234 }
 235
 236 static void __init qed_mfw_speed_maps_init(void)
 237 {
 238         u32 i;
 239
 240         for (i = 0; i < ARRAY_SIZE(qed_mfw_ext_maps); i++)
 241                 qed_mfw_speed_map_populate(qed_mfw_ext_maps + i);
 242
 243         for (i = 0; i < ARRAY_SIZE(qed_mfw_legacy_maps); i++)
 244                 qed_mfw_speed_map_populate(qed_mfw_legacy_maps + i);
 245 }
 246
 247 static int __init qed_init(void)
 248 {
 249         pr_info("%s", version);
 250
 251         qed_mfw_speed_maps_init();
 252
 253         return 0;
 254 }
 255 module_init(qed_init);
 256
 257 static void __exit qed_exit(void)
 258 {
 259         /* To prevent marking this module as "permanent" */
 260 }
 261 module_exit(qed_exit);
 262
 263 /* Check if the DMA controller on the machine can properly handle the DMA
 264  * addressing required by the device.
 265 */
 266 static int qed_set_coherency_mask(struct qed_dev *cdev)
 267 {
 268         struct device *dev = &cdev->pdev->dev;
 269
 270         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
 271                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
 272                         DP_NOTICE(cdev,
 273                                   "Can't request 64-bit consistent allocations\n");
 274                         return -EIO;
 275                 }
 276         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
 277                 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
 278                 return -EIO;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static void qed_free_pci(struct qed_dev *cdev)
 285 {
 286         struct pci_dev *pdev = cdev->pdev;
 287
 288         pci_disable_pcie_error_reporting(pdev);
 289
 290         if (cdev->doorbells && cdev->db_size)
 291                 iounmap(cdev->doorbells);
 292         if (cdev->regview)
 293                 iounmap(cdev->regview);
 294         if (atomic_read(&pdev->enable_cnt) == 1)
 295                 pci_release_regions(pdev);
 296
 297         pci_disable_device(pdev);
 298 }
 299
 300 #define PCI_REVISION_ID_ERROR_VAL       0xff
 301
 302 /* Performs PCI initializations as well as initializing PCI-related parameters
 303  * in the device structrue. Returns 0 in case of success.
 304  */
 305 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
 306 {
 307         u8 rev_id;
 308         int rc;
 309
 310         cdev->pdev = pdev;
 311
 312         rc = pci_enable_device(pdev);
 313         if (rc) {
 314                 DP_NOTICE(cdev, "Cannot enable PCI device\n");
 315                 goto err0;
 316         }
 317
 318         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 319                 DP_NOTICE(cdev, "No memory region found in bar #0\n");
 320                 rc = -EIO;
 321                 goto err1;
 322         }
 323
 324         if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
 325                 DP_NOTICE(cdev, "No memory region found in bar #2\n");
 326                 rc = -EIO;
 327                 goto err1;
 328         }
 329
 330         if (atomic_read(&pdev->enable_cnt) == 1) {
 331                 rc = pci_request_regions(pdev, "qed");
 332                 if (rc) {
 333                         DP_NOTICE(cdev,
 334                                   "Failed to request PCI memory resources\n");
 335                         goto err1;
 336                 }
 337                 pci_set_master(pdev);
 338                 pci_save_state(pdev);
 339         }
 340
 341         pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
 342         if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
 343                 DP_NOTICE(cdev,
 344                           "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
 345                           rev_id);
 346                 rc = -ENODEV;
 347                 goto err2;
 348         }
 349         if (!pci_is_pcie(pdev)) {
 350                 DP_NOTICE(cdev, "The bus is not PCI Express\n");
 351                 rc = -EIO;
 352                 goto err2;
 353         }
 354
 355         cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
 356         if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
 357                 DP_NOTICE(cdev, "Cannot find power management capability\n");
 358
 359         rc = qed_set_coherency_mask(cdev);
 360         if (rc)
 361                 goto err2;
 362
 363         cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
 364         cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
 365         cdev->pci_params.irq = pdev->irq;
 366
 367         cdev->regview = pci_ioremap_bar(pdev, 0);
 368         if (!cdev->regview) {
 369                 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
 370                 rc = -ENOMEM;
 371                 goto err2;
 372         }
 373
 374         cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
 375         cdev->db_size = pci_resource_len(cdev->pdev, 2);
 376         if (!cdev->db_size) {
 377                 if (IS_PF(cdev)) {
 378                         DP_NOTICE(cdev, "No Doorbell bar available\n");
 379                         return -EINVAL;
 380                 } else {
 381                         return 0;
 382                 }
 383         }
 384
 385         cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
 386
 387         if (!cdev->doorbells) {
 388                 DP_NOTICE(cdev, "Cannot map doorbell space\n");
 389                 return -ENOMEM;
 390         }
 391
 392         /* AER (Advanced Error reporting) configuration */
 393         rc = pci_enable_pcie_error_reporting(pdev);
 394         if (rc)
 395                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
 396                            "Failed to configure PCIe AER [%d]\n", rc);
 397
 398         return 0;
 399
 400 err2:
 401         pci_release_regions(pdev);
 402 err1:
 403         pci_disable_device(pdev);
 404 err0:
 405         return rc;
 406 }
 407
 408 int qed_fill_dev_info(struct qed_dev *cdev,
 409                       struct qed_dev_info *dev_info)
 410 {
 411         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 412         struct qed_hw_info *hw_info = &p_hwfn->hw_info;
 413         struct qed_tunnel_info *tun = &cdev->tunnel;
 414         struct qed_ptt  *ptt;
 415
 416         memset(dev_info, 0, sizeof(struct qed_dev_info));
 417
 418         if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 419             tun->vxlan.b_mode_enabled)
 420                 dev_info->vxlan_enable = true;
 421
 422         if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
 423             tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 424             tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
 425                 dev_info->gre_enable = true;
 426
 427         if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
 428             tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 429             tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
 430                 dev_info->geneve_enable = true;
 431
 432         dev_info->num_hwfns = cdev->num_hwfns;
 433         dev_info->pci_mem_start = cdev->pci_params.mem_start;
 434         dev_info->pci_mem_end = cdev->pci_params.mem_end;
 435         dev_info->pci_irq = cdev->pci_params.irq;
 436         dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
 437         dev_info->dev_type = cdev->type;
 438         ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
 439
 440         if (IS_PF(cdev)) {
 441                 dev_info->fw_major = FW_MAJOR_VERSION;
 442                 dev_info->fw_minor = FW_MINOR_VERSION;
 443                 dev_info->fw_rev = FW_REVISION_VERSION;
 444                 dev_info->fw_eng = FW_ENGINEERING_VERSION;
 445                 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,
 446                                                        &cdev->mf_bits);
 447                 dev_info->tx_switching = true;
 448
 449                 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
 450                         dev_info->wol_support = true;
 451
 452                 dev_info->smart_an = qed_mcp_is_smart_an_supported(p_hwfn);
 453
 454                 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id;
 455         } else {
 456                 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
 457                                       &dev_info->fw_minor, &dev_info->fw_rev,
 458                                       &dev_info->fw_eng);
 459         }
 460
 461         if (IS_PF(cdev)) {
 462                 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
 463                 if (ptt) {
 464                         qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
 465                                             &dev_info->mfw_rev, NULL);
 466
 467                         qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt,
 468                                             &dev_info->mbi_version);
 469
 470                         qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
 471                                                &dev_info->flash_size);
 472
 473                         qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
 474                 }
 475         } else {
 476                 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
 477                                     &dev_info->mfw_rev, NULL);
 478         }
 479
 480         dev_info->mtu = hw_info->mtu;
 481
 482         return 0;
 483 }
 484
 485 static void qed_free_cdev(struct qed_dev *cdev)
 486 {
 487         kfree((void *)cdev);
 488 }
 489
 490 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
 491 {
 492         struct qed_dev *cdev;
 493
 494         cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
 495         if (!cdev)
 496                 return cdev;
 497
 498         qed_init_struct(cdev);
 499
 500         return cdev;
 501 }
 502
 503 /* Sets the requested power state */
 504 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
 505 {
 506         if (!cdev)
 507                 return -ENODEV;
 508
 509         DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
 510         return 0;
 511 }
 512
 513 struct qed_devlink {
 514         struct qed_dev *cdev;
 515 };
 516
 517 enum qed_devlink_param_id {
 518         QED_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
 519         QED_DEVLINK_PARAM_ID_IWARP_CMT,
 520 };
 521
 522 static int qed_dl_param_get(struct devlink *dl, u32 id,
 523                             struct devlink_param_gset_ctx *ctx)
 524 {
 525         struct qed_devlink *qed_dl;
 526         struct qed_dev *cdev;
 527
 528         qed_dl = devlink_priv(dl);
 529         cdev = qed_dl->cdev;
 530         ctx->val.vbool = cdev->iwarp_cmt;
 531
 532         return 0;
 533 }
 534
 535 static int qed_dl_param_set(struct devlink *dl, u32 id,
 536                             struct devlink_param_gset_ctx *ctx)
 537 {
 538         struct qed_devlink *qed_dl;
 539         struct qed_dev *cdev;
 540
 541         qed_dl = devlink_priv(dl);
 542         cdev = qed_dl->cdev;
 543         cdev->iwarp_cmt = ctx->val.vbool;
 544
 545         return 0;
 546 }
 547
 548 static const struct devlink_param qed_devlink_params[] = {
 549         DEVLINK_PARAM_DRIVER(QED_DEVLINK_PARAM_ID_IWARP_CMT,
 550                              "iwarp_cmt", DEVLINK_PARAM_TYPE_BOOL,
 551                              BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 552                              qed_dl_param_get, qed_dl_param_set, NULL),
 553 };
 554
 555 static const struct devlink_ops qed_dl_ops;
 556
 557 static int qed_devlink_register(struct qed_dev *cdev)
 558 {
 559         union devlink_param_value value;
 560         struct qed_devlink *qed_dl;
 561         struct devlink *dl;
 562         int rc;
 563
 564         dl = devlink_alloc(&qed_dl_ops, sizeof(*qed_dl));
 565         if (!dl)
 566                 return -ENOMEM;
 567
 568         qed_dl = devlink_priv(dl);
 569
 570         cdev->dl = dl;
 571         qed_dl->cdev = cdev;
 572
 573         rc = devlink_register(dl, &cdev->pdev->dev);
 574         if (rc)
 575                 goto err_free;
 576
 577         rc = devlink_params_register(dl, qed_devlink_params,
 578                                      ARRAY_SIZE(qed_devlink_params));
 579         if (rc)
 580                 goto err_unregister;
 581
 582         value.vbool = false;
 583         devlink_param_driverinit_value_set(dl,
 584                                            QED_DEVLINK_PARAM_ID_IWARP_CMT,
 585                                            value);
 586
 587         devlink_params_publish(dl);
 588         cdev->iwarp_cmt = false;
 589
 590         return 0;
 591
 592 err_unregister:
 593         devlink_unregister(dl);
 594
 595 err_free:
 596         cdev->dl = NULL;
 597         devlink_free(dl);
 598
 599         return rc;
 600 }
 601
 602 static void qed_devlink_unregister(struct qed_dev *cdev)
 603 {
 604         if (!cdev->dl)
 605                 return;
 606
 607         devlink_params_unregister(cdev->dl, qed_devlink_params,
 608                                   ARRAY_SIZE(qed_devlink_params));
 609
 610         devlink_unregister(cdev->dl);
 611         devlink_free(cdev->dl);
 612 }
 613
 614 /* probing */
 615 static struct qed_dev *qed_probe(struct pci_dev *pdev,
 616                                  struct qed_probe_params *params)
 617 {
 618         struct qed_dev *cdev;
 619         int rc;
 620
 621         cdev = qed_alloc_cdev(pdev);
 622         if (!cdev)
 623                 goto err0;
 624
 625         cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
 626         cdev->protocol = params->protocol;
 627
 628         if (params->is_vf)
 629                 cdev->b_is_vf = true;
 630
 631         qed_init_dp(cdev, params->dp_module, params->dp_level);
 632
 633         cdev->recov_in_prog = params->recov_in_prog;
 634
 635         rc = qed_init_pci(cdev, pdev);
 636         if (rc) {
 637                 DP_ERR(cdev, "init pci failed\n");
 638                 goto err1;
 639         }
 640         DP_INFO(cdev, "PCI init completed successfully\n");
 641
 642         rc = qed_devlink_register(cdev);
 643         if (rc) {
 644                 DP_INFO(cdev, "Failed to register devlink.\n");
 645                 goto err2;
 646         }
 647
 648         rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
 649         if (rc) {
 650                 DP_ERR(cdev, "hw prepare failed\n");
 651                 goto err2;
 652         }
 653
 654         DP_INFO(cdev, "qed_probe completed successfully\n");
 655
 656         return cdev;
 657
 658 err2:
 659         qed_free_pci(cdev);
 660 err1:
 661         qed_free_cdev(cdev);
 662 err0:
 663         return NULL;
 664 }
 665
 666 static void qed_remove(struct qed_dev *cdev)
 667 {
 668         if (!cdev)
 669                 return;
 670
 671         qed_hw_remove(cdev);
 672
 673         qed_free_pci(cdev);
 674
 675         qed_set_power_state(cdev, PCI_D3hot);
 676
 677         qed_devlink_unregister(cdev);
 678
 679         qed_free_cdev(cdev);
 680 }
 681
 682 static void qed_disable_msix(struct qed_dev *cdev)
 683 {
 684         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 685                 pci_disable_msix(cdev->pdev);
 686                 kfree(cdev->int_params.msix_table);
 687         } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
 688                 pci_disable_msi(cdev->pdev);
 689         }
 690
 691         memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
 692 }
 693
 694 static int qed_enable_msix(struct qed_dev *cdev,
 695                            struct qed_int_params *int_params)
 696 {
 697         int i, rc, cnt;
 698
 699         cnt = int_params->in.num_vectors;
 700
 701         for (i = 0; i < cnt; i++)
 702                 int_params->msix_table[i].entry = i;
 703
 704         rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
 705                                    int_params->in.min_msix_cnt, cnt);
 706         if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
 707             (rc % cdev->num_hwfns)) {
 708                 pci_disable_msix(cdev->pdev);
 709
 710                 /* If fastpath is initialized, we need at least one interrupt
 711                  * per hwfn [and the slow path interrupts]. New requested number
 712                  * should be a multiple of the number of hwfns.
 713                  */
 714                 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
 715                 DP_NOTICE(cdev,
 716                           "Trying to enable MSI-X with less vectors (%d out of %d)\n",
 717                           cnt, int_params->in.num_vectors);
 718                 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
 719                                            cnt);
 720                 if (!rc)
 721                         rc = cnt;
 722         }
 723
 724         if (rc > 0) {
 725                 /* MSI-x configuration was achieved */
 726                 int_params->out.int_mode = QED_INT_MODE_MSIX;
 727                 int_params->out.num_vectors = rc;
 728                 rc = 0;
 729         } else {
 730                 DP_NOTICE(cdev,
 731                           "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
 732                           cnt, rc);
 733         }
 734
 735         return rc;
 736 }
 737
 738 /* This function outputs the int mode and the number of enabled msix vector */
 739 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
 740 {
 741         struct qed_int_params *int_params = &cdev->int_params;
 742         struct msix_entry *tbl;
 743         int rc = 0, cnt;
 744
 745         switch (int_params->in.int_mode) {
 746         case QED_INT_MODE_MSIX:
 747                 /* Allocate MSIX table */
 748                 cnt = int_params->in.num_vectors;
 749                 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
 750                 if (!int_params->msix_table) {
 751                         rc = -ENOMEM;
 752                         goto out;
 753                 }
 754
 755                 /* Enable MSIX */
 756                 rc = qed_enable_msix(cdev, int_params);
 757                 if (!rc)
 758                         goto out;
 759
 760                 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
 761                 kfree(int_params->msix_table);
 762                 if (force_mode)
 763                         goto out;
 764                 fallthrough;
 765
 766         case QED_INT_MODE_MSI:
 767                 if (cdev->num_hwfns == 1) {
 768                         rc = pci_enable_msi(cdev->pdev);
 769                         if (!rc) {
 770                                 int_params->out.int_mode = QED_INT_MODE_MSI;
 771                                 goto out;
 772                         }
 773
 774                         DP_NOTICE(cdev, "Failed to enable MSI\n");
 775                         if (force_mode)
 776                                 goto out;
 777                 }
 778                 fallthrough;
 779
 780         case QED_INT_MODE_INTA:
 781                         int_params->out.int_mode = QED_INT_MODE_INTA;
 782                         rc = 0;
 783                         goto out;
 784         default:
 785                 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
 786                           int_params->in.int_mode);
 787                 rc = -EINVAL;
 788         }
 789
 790 out:
 791         if (!rc)
 792                 DP_INFO(cdev, "Using %s interrupts\n",
 793                         int_params->out.int_mode == QED_INT_MODE_INTA ?
 794                         "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
 795                         "MSI" : "MSIX");
 796         cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
 797
 798         return rc;
 799 }
 800
 801 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
 802                                     int index, void(*handler)(void *))
 803 {
 804         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 805         int relative_idx = index / cdev->num_hwfns;
 806
 807         hwfn->simd_proto_handler[relative_idx].func = handler;
 808         hwfn->simd_proto_handler[relative_idx].token = token;
 809 }
 810
 811 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
 812 {
 813         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 814         int relative_idx = index / cdev->num_hwfns;
 815
 816         memset(&hwfn->simd_proto_handler[relative_idx], 0,
 817                sizeof(struct qed_simd_fp_handler));
 818 }
 819
 820 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
 821 {
 822         tasklet_schedule((struct tasklet_struct *)tasklet);
 823         return IRQ_HANDLED;
 824 }
 825
 826 static irqreturn_t qed_single_int(int irq, void *dev_instance)
 827 {
 828         struct qed_dev *cdev = (struct qed_dev *)dev_instance;
 829         struct qed_hwfn *hwfn;
 830         irqreturn_t rc = IRQ_NONE;
 831         u64 status;
 832         int i, j;
 833
 834         for (i = 0; i < cdev->num_hwfns; i++) {
 835                 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
 836
 837                 if (!status)
 838                         continue;
 839
 840                 hwfn = &cdev->hwfns[i];
 841
 842                 /* Slowpath interrupt */
 843                 if (unlikely(status & 0x1)) {
 844                         tasklet_schedule(hwfn->sp_dpc);
 845                         status &= ~0x1;
 846                         rc = IRQ_HANDLED;
 847                 }
 848
 849                 /* Fastpath interrupts */
 850                 for (j = 0; j < 64; j++) {
 851                         if ((0x2ULL << j) & status) {
 852                                 struct qed_simd_fp_handler *p_handler =
 853                                         &hwfn->simd_proto_handler[j];
 854
 855                                 if (p_handler->func)
 856                                         p_handler->func(p_handler->token);
 857                                 else
 858                                         DP_NOTICE(hwfn,
 859                                                   "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
 860                                                   j, status);
 861
 862                                 status &= ~(0x2ULL << j);
 863                                 rc = IRQ_HANDLED;
 864                         }
 865                 }
 866
 867                 if (unlikely(status))
 868                         DP_VERBOSE(hwfn, NETIF_MSG_INTR,
 869                                    "got an unknown interrupt status 0x%llx\n",
 870                                    status);
 871         }
 872
 873         return rc;
 874 }
 875
 876 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
 877 {
 878         struct qed_dev *cdev = hwfn->cdev;
 879         u32 int_mode;
 880         int rc = 0;
 881         u8 id;
 882
 883         int_mode = cdev->int_params.out.int_mode;
 884         if (int_mode == QED_INT_MODE_MSIX) {
 885                 id = hwfn->my_id;
 886                 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
 887                          id, cdev->pdev->bus->number,
 888                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
 889                 rc = request_irq(cdev->int_params.msix_table[id].vector,
 890                                  qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
 891         } else {
 892                 unsigned long flags = 0;
 893
 894                 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
 895                          cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
 896                          PCI_FUNC(cdev->pdev->devfn));
 897
 898                 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
 899                         flags |= IRQF_SHARED;
 900
 901                 rc = request_irq(cdev->pdev->irq, qed_single_int,
 902                                  flags, cdev->name, cdev);
 903         }
 904
 905         if (rc)
 906                 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
 907         else
 908                 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
 909                            "Requested slowpath %s\n",
 910                            (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
 911
 912         return rc;
 913 }
 914
 915 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn)
 916 {
 917         /* Calling the disable function will make sure that any
 918          * currently-running function is completed. The following call to the
 919          * enable function makes this sequence a flush-like operation.
 920          */
 921         if (p_hwfn->b_sp_dpc_enabled) {
 922                 tasklet_disable(p_hwfn->sp_dpc);
 923                 tasklet_enable(p_hwfn->sp_dpc);
 924         }
 925 }
 926
 927 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
 928 {
 929         struct qed_dev *cdev = p_hwfn->cdev;
 930         u8 id = p_hwfn->my_id;
 931         u32 int_mode;
 932
 933         int_mode = cdev->int_params.out.int_mode;
 934         if (int_mode == QED_INT_MODE_MSIX)
 935                 synchronize_irq(cdev->int_params.msix_table[id].vector);
 936         else
 937                 synchronize_irq(cdev->pdev->irq);
 938
 939         qed_slowpath_tasklet_flush(p_hwfn);
 940 }
 941
 942 static void qed_slowpath_irq_free(struct qed_dev *cdev)
 943 {
 944         int i;
 945
 946         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 947                 for_each_hwfn(cdev, i) {
 948                         if (!cdev->hwfns[i].b_int_requested)
 949                                 break;
 950                         synchronize_irq(cdev->int_params.msix_table[i].vector);
 951                         free_irq(cdev->int_params.msix_table[i].vector,
 952                                  cdev->hwfns[i].sp_dpc);
 953                 }
 954         } else {
 955                 if (QED_LEADING_HWFN(cdev)->b_int_requested)
 956                         free_irq(cdev->pdev->irq, cdev);
 957         }
 958         qed_int_disable_post_isr_release(cdev);
 959 }
 960
 961 static int qed_nic_stop(struct qed_dev *cdev)
 962 {
 963         int i, rc;
 964
 965         rc = qed_hw_stop(cdev);
 966
 967         for (i = 0; i < cdev->num_hwfns; i++) {
 968                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 969
 970                 if (p_hwfn->b_sp_dpc_enabled) {
 971                         tasklet_disable(p_hwfn->sp_dpc);
 972                         p_hwfn->b_sp_dpc_enabled = false;
 973                         DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
 974                                    "Disabled sp tasklet [hwfn %d] at %p\n",
 975                                    i, p_hwfn->sp_dpc);
 976                 }
 977         }
 978
 979         qed_dbg_pf_exit(cdev);
 980
 981         return rc;
 982 }
 983
 984 static int qed_nic_setup(struct qed_dev *cdev)
 985 {
 986         int rc, i;
 987
 988         /* Determine if interface is going to require LL2 */
 989         if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
 990                 for (i = 0; i < cdev->num_hwfns; i++) {
 991                         struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 992
 993                         p_hwfn->using_ll2 = true;
 994                 }
 995         }
 996
 997         rc = qed_resc_alloc(cdev);
 998         if (rc)
 999                 return rc;
1000
1001         DP_INFO(cdev, "Allocated qed resources\n");
1002
1003         qed_resc_setup(cdev);
1004
1005         return rc;
1006 }
1007
1008 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
1009 {
1010         int limit = 0;
1011
1012         /* Mark the fastpath as free/used */
1013         cdev->int_params.fp_initialized = cnt ? true : false;
1014
1015         if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
1016                 limit = cdev->num_hwfns * 63;
1017         else if (cdev->int_params.fp_msix_cnt)
1018                 limit = cdev->int_params.fp_msix_cnt;
1019
1020         if (!limit)
1021                 return -ENOMEM;
1022
1023         return min_t(int, cnt, limit);
1024 }
1025
1026 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
1027 {
1028         memset(info, 0, sizeof(struct qed_int_info));
1029
1030         if (!cdev->int_params.fp_initialized) {
1031                 DP_INFO(cdev,
1032                         "Protocol driver requested interrupt information, but its support is not yet configured\n");
1033                 return -EINVAL;
1034         }
1035
1036         /* Need to expose only MSI-X information; Single IRQ is handled solely
1037          * by qed.
1038          */
1039         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1040                 int msix_base = cdev->int_params.fp_msix_base;
1041
1042                 info->msix_cnt = cdev->int_params.fp_msix_cnt;
1043                 info->msix = &cdev->int_params.msix_table[msix_base];
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int qed_slowpath_setup_int(struct qed_dev *cdev,
1050                                   enum qed_int_mode int_mode)
1051 {
1052         struct qed_sb_cnt_info sb_cnt_info;
1053         int num_l2_queues = 0;
1054         int rc;
1055         int i;
1056
1057         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1058                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1059                 return -EINVAL;
1060         }
1061
1062         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
1063         cdev->int_params.in.int_mode = int_mode;
1064         for_each_hwfn(cdev, i) {
1065                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1066                 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
1067                 cdev->int_params.in.num_vectors += sb_cnt_info.cnt;
1068                 cdev->int_params.in.num_vectors++; /* slowpath */
1069         }
1070
1071         /* We want a minimum of one slowpath and one fastpath vector per hwfn */
1072         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
1073
1074         if (is_kdump_kernel()) {
1075                 DP_INFO(cdev,
1076                         "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
1077                         cdev->int_params.in.min_msix_cnt);
1078                 cdev->int_params.in.num_vectors =
1079                         cdev->int_params.in.min_msix_cnt;
1080         }
1081
1082         rc = qed_set_int_mode(cdev, false);
1083         if (rc)  {
1084                 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
1085                 return rc;
1086         }
1087
1088         cdev->int_params.fp_msix_base = cdev->num_hwfns;
1089         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
1090                                        cdev->num_hwfns;
1091
1092         if (!IS_ENABLED(CONFIG_QED_RDMA) ||
1093             !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev)))
1094                 return 0;
1095
1096         for_each_hwfn(cdev, i)
1097                 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
1098
1099         DP_VERBOSE(cdev, QED_MSG_RDMA,
1100                    "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
1101                    cdev->int_params.fp_msix_cnt, num_l2_queues);
1102
1103         if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
1104                 cdev->int_params.rdma_msix_cnt =
1105                         (cdev->int_params.fp_msix_cnt - num_l2_queues)
1106                         / cdev->num_hwfns;
1107                 cdev->int_params.rdma_msix_base =
1108                         cdev->int_params.fp_msix_base + num_l2_queues;
1109                 cdev->int_params.fp_msix_cnt = num_l2_queues;
1110         } else {
1111                 cdev->int_params.rdma_msix_cnt = 0;
1112         }
1113
1114         DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
1115                    cdev->int_params.rdma_msix_cnt,
1116                    cdev->int_params.rdma_msix_base);
1117
1118         return 0;
1119 }
1120
1121 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
1122 {
1123         int rc;
1124
1125         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
1126         cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
1127
1128         qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
1129                             &cdev->int_params.in.num_vectors);
1130         if (cdev->num_hwfns > 1) {
1131                 u8 vectors = 0;
1132
1133                 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
1134                 cdev->int_params.in.num_vectors += vectors;
1135         }
1136
1137         /* We want a minimum of one fastpath vector per vf hwfn */
1138         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
1139
1140         rc = qed_set_int_mode(cdev, true);
1141         if (rc)
1142                 return rc;
1143
1144         cdev->int_params.fp_msix_base = 0;
1145         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
1146
1147         return 0;
1148 }
1149
1150 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
1151                    u8 *input_buf, u32 max_size, u8 *unzip_buf)
1152 {
1153         int rc;
1154
1155         p_hwfn->stream->next_in = input_buf;
1156         p_hwfn->stream->avail_in = input_len;
1157         p_hwfn->stream->next_out = unzip_buf;
1158         p_hwfn->stream->avail_out = max_size;
1159
1160         rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
1161
1162         if (rc != Z_OK) {
1163                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
1164                            rc);
1165                 return 0;
1166         }
1167
1168         rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
1169         zlib_inflateEnd(p_hwfn->stream);
1170
1171         if (rc != Z_OK && rc != Z_STREAM_END) {
1172                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
1173                            p_hwfn->stream->msg, rc);
1174                 return 0;
1175         }
1176
1177         return p_hwfn->stream->total_out / 4;
1178 }
1179
1180 static int qed_alloc_stream_mem(struct qed_dev *cdev)
1181 {
1182         int i;
1183         void *workspace;
1184
1185         for_each_hwfn(cdev, i) {
1186                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1187
1188                 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
1189                 if (!p_hwfn->stream)
1190                         return -ENOMEM;
1191
1192                 workspace = vzalloc(zlib_inflate_workspacesize());
1193                 if (!workspace)
1194                         return -ENOMEM;
1195                 p_hwfn->stream->workspace = workspace;
1196         }
1197
1198         return 0;
1199 }
1200
1201 static void qed_free_stream_mem(struct qed_dev *cdev)
1202 {
1203         int i;
1204
1205         for_each_hwfn(cdev, i) {
1206                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1207
1208                 if (!p_hwfn->stream)
1209                         return;
1210
1211                 vfree(p_hwfn->stream->workspace);
1212                 kfree(p_hwfn->stream);
1213         }
1214 }
1215
1216 static void qed_update_pf_params(struct qed_dev *cdev,
1217                                  struct qed_pf_params *params)
1218 {
1219         int i;
1220
1221         if (IS_ENABLED(CONFIG_QED_RDMA)) {
1222                 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
1223                 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
1224                 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS;
1225                 /* divide by 3 the MRs to avoid MF ILT overflow */
1226                 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
1227         }
1228
1229         if (cdev->num_hwfns > 1 || IS_VF(cdev))
1230                 params->eth_pf_params.num_arfs_filters = 0;
1231
1232         /* In case we might support RDMA, don't allow qede to be greedy
1233          * with the L2 contexts. Allow for 64 queues [rx, tx cos, xdp]
1234          * per hwfn.
1235          */
1236         if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) {
1237                 u16 *num_cons;
1238
1239                 num_cons = &params->eth_pf_params.num_cons;
1240                 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS);
1241         }
1242
1243         for (i = 0; i < cdev->num_hwfns; i++) {
1244                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1245
1246                 p_hwfn->pf_params = *params;
1247         }
1248 }
1249
1250 #define QED_PERIODIC_DB_REC_COUNT               10
1251 #define QED_PERIODIC_DB_REC_INTERVAL_MS         100
1252 #define QED_PERIODIC_DB_REC_INTERVAL \
1253         msecs_to_jiffies(QED_PERIODIC_DB_REC_INTERVAL_MS)
1254
1255 static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn,
1256                                      enum qed_slowpath_wq_flag wq_flag,
1257                                      unsigned long delay)
1258 {
1259         if (!hwfn->slowpath_wq_active)
1260                 return -EINVAL;
1261
1262         /* Memory barrier for setting atomic bit */
1263         smp_mb__before_atomic();
1264         set_bit(wq_flag, &hwfn->slowpath_task_flags);
1265         smp_mb__after_atomic();
1266         queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, delay);
1267
1268         return 0;
1269 }
1270
1271 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn)
1272 {
1273         /* Reset periodic Doorbell Recovery counter */
1274         p_hwfn->periodic_db_rec_count = QED_PERIODIC_DB_REC_COUNT;
1275
1276         /* Don't schedule periodic Doorbell Recovery if already scheduled */
1277         if (test_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1278                      &p_hwfn->slowpath_task_flags))
1279                 return;
1280
1281         qed_slowpath_delayed_work(p_hwfn, QED_SLOWPATH_PERIODIC_DB_REC,
1282                                   QED_PERIODIC_DB_REC_INTERVAL);
1283 }
1284
1285 static void qed_slowpath_wq_stop(struct qed_dev *cdev)
1286 {
1287         int i;
1288
1289         if (IS_VF(cdev))
1290                 return;
1291
1292         for_each_hwfn(cdev, i) {
1293                 if (!cdev->hwfns[i].slowpath_wq)
1294                         continue;
1295
1296                 /* Stop queuing new delayed works */
1297                 cdev->hwfns[i].slowpath_wq_active = false;
1298
1299                 cancel_delayed_work(&cdev->hwfns[i].slowpath_task);
1300                 destroy_workqueue(cdev->hwfns[i].slowpath_wq);
1301         }
1302 }
1303
1304 static void qed_slowpath_task(struct work_struct *work)
1305 {
1306         struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1307                                              slowpath_task.work);
1308         struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
1309
1310         if (!ptt) {
1311                 if (hwfn->slowpath_wq_active)
1312                         queue_delayed_work(hwfn->slowpath_wq,
1313                                            &hwfn->slowpath_task, 0);
1314
1315                 return;
1316         }
1317
1318         if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ,
1319                                &hwfn->slowpath_task_flags))
1320                 qed_mfw_process_tlv_req(hwfn, ptt);
1321
1322         if (test_and_clear_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1323                                &hwfn->slowpath_task_flags)) {
1324                 qed_db_rec_handler(hwfn, ptt);
1325                 if (hwfn->periodic_db_rec_count--)
1326                         qed_slowpath_delayed_work(hwfn,
1327                                                   QED_SLOWPATH_PERIODIC_DB_REC,
1328                                                   QED_PERIODIC_DB_REC_INTERVAL);
1329         }
1330
1331         qed_ptt_release(hwfn, ptt);
1332 }
1333
1334 static int qed_slowpath_wq_start(struct qed_dev *cdev)
1335 {
1336         struct qed_hwfn *hwfn;
1337         char name[NAME_SIZE];
1338         int i;
1339
1340         if (IS_VF(cdev))
1341                 return 0;
1342
1343         for_each_hwfn(cdev, i) {
1344                 hwfn = &cdev->hwfns[i];
1345
1346                 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x",
1347                          cdev->pdev->bus->number,
1348                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
1349
1350                 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0);
1351                 if (!hwfn->slowpath_wq) {
1352                         DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n");
1353                         return -ENOMEM;
1354                 }
1355
1356                 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task);
1357                 hwfn->slowpath_wq_active = true;
1358         }
1359
1360         return 0;
1361 }
1362
1363 static int qed_slowpath_start(struct qed_dev *cdev,
1364                               struct qed_slowpath_params *params)
1365 {
1366         struct qed_drv_load_params drv_load_params;
1367         struct qed_hw_init_params hw_init_params;
1368         struct qed_mcp_drv_version drv_version;
1369         struct qed_tunnel_info tunn_info;
1370         const u8 *data = NULL;
1371         struct qed_hwfn *hwfn;
1372         struct qed_ptt *p_ptt;
1373         int rc = -EINVAL;
1374
1375         if (qed_iov_wq_start(cdev))
1376                 goto err;
1377
1378         if (qed_slowpath_wq_start(cdev))
1379                 goto err;
1380
1381         if (IS_PF(cdev)) {
1382                 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
1383                                       &cdev->pdev->dev);
1384                 if (rc) {
1385                         DP_NOTICE(cdev,
1386                                   "Failed to find fw file - /lib/firmware/%s\n",
1387                                   QED_FW_FILE_NAME);
1388                         goto err;
1389                 }
1390
1391                 if (cdev->num_hwfns == 1) {
1392                         p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1393                         if (p_ptt) {
1394                                 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
1395                         } else {
1396                                 DP_NOTICE(cdev,
1397                                           "Failed to acquire PTT for aRFS\n");
1398                                 goto err;
1399                         }
1400                 }
1401         }
1402
1403         cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
1404         rc = qed_nic_setup(cdev);
1405         if (rc)
1406                 goto err;
1407
1408         if (IS_PF(cdev))
1409                 rc = qed_slowpath_setup_int(cdev, params->int_mode);
1410         else
1411                 rc = qed_slowpath_vf_setup_int(cdev);
1412         if (rc)
1413                 goto err1;
1414
1415         if (IS_PF(cdev)) {
1416                 /* Allocate stream for unzipping */
1417                 rc = qed_alloc_stream_mem(cdev);
1418                 if (rc)
1419                         goto err2;
1420
1421                 /* First Dword used to differentiate between various sources */
1422                 data = cdev->firmware->data + sizeof(u32);
1423
1424                 qed_dbg_pf_init(cdev);
1425         }
1426
1427         /* Start the slowpath */
1428         memset(&hw_init_params, 0, sizeof(hw_init_params));
1429         memset(&tunn_info, 0, sizeof(tunn_info));
1430         tunn_info.vxlan.b_mode_enabled = true;
1431         tunn_info.l2_gre.b_mode_enabled = true;
1432         tunn_info.ip_gre.b_mode_enabled = true;
1433         tunn_info.l2_geneve.b_mode_enabled = true;
1434         tunn_info.ip_geneve.b_mode_enabled = true;
1435         tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1436         tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1437         tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1438         tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1439         tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1440         hw_init_params.p_tunn = &tunn_info;
1441         hw_init_params.b_hw_start = true;
1442         hw_init_params.int_mode = cdev->int_params.out.int_mode;
1443         hw_init_params.allow_npar_tx_switch = true;
1444         hw_init_params.bin_fw_data = data;
1445
1446         memset(&drv_load_params, 0, sizeof(drv_load_params));
1447         drv_load_params.is_crash_kernel = is_kdump_kernel();
1448         drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1449         drv_load_params.avoid_eng_reset = false;
1450         drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1451         hw_init_params.p_drv_load_params = &drv_load_params;
1452
1453         rc = qed_hw_init(cdev, &hw_init_params);
1454         if (rc)
1455                 goto err2;
1456
1457         DP_INFO(cdev,
1458                 "HW initialization and function start completed successfully\n");
1459
1460         if (IS_PF(cdev)) {
1461                 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1462                                            BIT(QED_MODE_L2GENEVE_TUNN) |
1463                                            BIT(QED_MODE_IPGENEVE_TUNN) |
1464                                            BIT(QED_MODE_L2GRE_TUNN) |
1465                                            BIT(QED_MODE_IPGRE_TUNN));
1466         }
1467
1468         /* Allocate LL2 interface if needed */
1469         if (QED_LEADING_HWFN(cdev)->using_ll2) {
1470                 rc = qed_ll2_alloc_if(cdev);
1471                 if (rc)
1472                         goto err3;
1473         }
1474         if (IS_PF(cdev)) {
1475                 hwfn = QED_LEADING_HWFN(cdev);
1476                 drv_version.version = (params->drv_major << 24) |
1477                                       (params->drv_minor << 16) |
1478                                       (params->drv_rev << 8) |
1479                                       (params->drv_eng);
1480                 strlcpy(drv_version.name, params->name,
1481                         MCP_DRV_VER_STR_SIZE - 4);
1482                 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1483                                               &drv_version);
1484                 if (rc) {
1485                         DP_NOTICE(cdev, "Failed sending drv version command\n");
1486                         goto err4;
1487                 }
1488         }
1489
1490         qed_reset_vport_stats(cdev);
1491
1492         return 0;
1493
1494 err4:
1495         qed_ll2_dealloc_if(cdev);
1496 err3:
1497         qed_hw_stop(cdev);
1498 err2:
1499         qed_hw_timers_stop_all(cdev);
1500         if (IS_PF(cdev))
1501                 qed_slowpath_irq_free(cdev);
1502         qed_free_stream_mem(cdev);
1503         qed_disable_msix(cdev);
1504 err1:
1505         qed_resc_free(cdev);
1506 err:
1507         if (IS_PF(cdev))
1508                 release_firmware(cdev->firmware);
1509
1510         if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1511             QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1512                 qed_ptt_release(QED_LEADING_HWFN(cdev),
1513                                 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1514
1515         qed_iov_wq_stop(cdev, false);
1516
1517         qed_slowpath_wq_stop(cdev);
1518
1519         return rc;
1520 }
1521
1522 static int qed_slowpath_stop(struct qed_dev *cdev)
1523 {
1524         if (!cdev)
1525                 return -ENODEV;
1526
1527         qed_slowpath_wq_stop(cdev);
1528
1529         qed_ll2_dealloc_if(cdev);
1530
1531         if (IS_PF(cdev)) {
1532                 if (cdev->num_hwfns == 1)
1533                         qed_ptt_release(QED_LEADING_HWFN(cdev),
1534                                         QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1535                 qed_free_stream_mem(cdev);
1536                 if (IS_QED_ETH_IF(cdev))
1537                         qed_sriov_disable(cdev, true);
1538         }
1539
1540         qed_nic_stop(cdev);
1541
1542         if (IS_PF(cdev))
1543                 qed_slowpath_irq_free(cdev);
1544
1545         qed_disable_msix(cdev);
1546
1547         qed_resc_free(cdev);
1548
1549         qed_iov_wq_stop(cdev, true);
1550
1551         if (IS_PF(cdev))
1552                 release_firmware(cdev->firmware);
1553
1554         return 0;
1555 }
1556
1557 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE])
1558 {
1559         int i;
1560
1561         memcpy(cdev->name, name, NAME_SIZE);
1562         for_each_hwfn(cdev, i)
1563                 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1564 }
1565
1566 static u32 qed_sb_init(struct qed_dev *cdev,
1567                        struct qed_sb_info *sb_info,
1568                        void *sb_virt_addr,
1569                        dma_addr_t sb_phy_addr, u16 sb_id,
1570                        enum qed_sb_type type)
1571 {
1572         struct qed_hwfn *p_hwfn;
1573         struct qed_ptt *p_ptt;
1574         u16 rel_sb_id;
1575         u32 rc;
1576
1577         /* RoCE/Storage use a single engine in CMT mode while L2 uses both */
1578         if (type == QED_SB_TYPE_L2_QUEUE) {
1579                 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns];
1580                 rel_sb_id = sb_id / cdev->num_hwfns;
1581         } else {
1582                 p_hwfn = QED_AFFIN_HWFN(cdev);
1583                 rel_sb_id = sb_id;
1584         }
1585
1586         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1587                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1588                    IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id);
1589
1590         if (IS_PF(p_hwfn->cdev)) {
1591                 p_ptt = qed_ptt_acquire(p_hwfn);
1592                 if (!p_ptt)
1593                         return -EBUSY;
1594
1595                 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1596                                      sb_phy_addr, rel_sb_id);
1597                 qed_ptt_release(p_hwfn, p_ptt);
1598         } else {
1599                 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1600                                      sb_phy_addr, rel_sb_id);
1601         }
1602
1603         return rc;
1604 }
1605
1606 static u32 qed_sb_release(struct qed_dev *cdev,
1607                           struct qed_sb_info *sb_info,
1608                           u16 sb_id,
1609                           enum qed_sb_type type)
1610 {
1611         struct qed_hwfn *p_hwfn;
1612         u16 rel_sb_id;
1613         u32 rc;
1614
1615         /* RoCE/Storage use a single engine in CMT mode while L2 uses both */
1616         if (type == QED_SB_TYPE_L2_QUEUE) {
1617                 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns];
1618                 rel_sb_id = sb_id / cdev->num_hwfns;
1619         } else {
1620                 p_hwfn = QED_AFFIN_HWFN(cdev);
1621                 rel_sb_id = sb_id;
1622         }
1623
1624         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1625                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1626                    IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id);
1627
1628         rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1629
1630         return rc;
1631 }
1632
1633 static bool qed_can_link_change(struct qed_dev *cdev)
1634 {
1635         return true;
1636 }
1637
1638 static void qed_set_ext_speed_params(struct qed_mcp_link_params *link_params,
1639                                      const struct qed_link_params *params)
1640 {
1641         struct qed_mcp_link_speed_params *ext_speed = &link_params->ext_speed;
1642         const struct qed_mfw_speed_map *map;
1643         u32 i;
1644
1645         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1646                 ext_speed->autoneg = !!params->autoneg;
1647
1648         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1649                 ext_speed->advertised_speeds = 0;
1650
1651                 for (i = 0; i < ARRAY_SIZE(qed_mfw_ext_maps); i++) {
1652                         map = qed_mfw_ext_maps + i;
1653
1654                         if (linkmode_intersects(params->adv_speeds, map->caps))
1655                                 ext_speed->advertised_speeds |= map->mfw_val;
1656                 }
1657         }
1658
1659         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) {
1660                 switch (params->forced_speed) {
1661                 case SPEED_1000:
1662                         ext_speed->forced_speed = QED_EXT_SPEED_1G;
1663                         break;
1664                 case SPEED_10000:
1665                         ext_speed->forced_speed = QED_EXT_SPEED_10G;
1666                         break;
1667                 case SPEED_20000:
1668                         ext_speed->forced_speed = QED_EXT_SPEED_20G;
1669                         break;
1670                 case SPEED_25000:
1671                         ext_speed->forced_speed = QED_EXT_SPEED_25G;
1672                         break;
1673                 case SPEED_40000:
1674                         ext_speed->forced_speed = QED_EXT_SPEED_40G;
1675                         break;
1676                 case SPEED_50000:
1677                         ext_speed->forced_speed = QED_EXT_SPEED_50G_R |
1678                                                   QED_EXT_SPEED_50G_R2;
1679                         break;
1680                 case SPEED_100000:
1681                         ext_speed->forced_speed = QED_EXT_SPEED_100G_R2 |
1682                                                   QED_EXT_SPEED_100G_R4 |
1683                                                   QED_EXT_SPEED_100G_P4;
1684                         break;
1685                 default:
1686                         break;
1687                 }
1688         }
1689
1690         if (!(params->override_flags & QED_LINK_OVERRIDE_FEC_CONFIG))
1691                 return;
1692
1693         switch (params->forced_speed) {
1694         case SPEED_25000:
1695                 switch (params->fec) {
1696                 case FEC_FORCE_MODE_NONE:
1697                         link_params->ext_fec_mode = ETH_EXT_FEC_25G_NONE;
1698                         break;
1699                 case FEC_FORCE_MODE_FIRECODE:
1700                         link_params->ext_fec_mode = ETH_EXT_FEC_25G_BASE_R;
1701                         break;
1702                 case FEC_FORCE_MODE_RS:
1703                         link_params->ext_fec_mode = ETH_EXT_FEC_25G_RS528;
1704                         break;
1705                 case FEC_FORCE_MODE_AUTO:
1706                         link_params->ext_fec_mode = ETH_EXT_FEC_25G_RS528 |
1707                                                     ETH_EXT_FEC_25G_BASE_R |
1708                                                     ETH_EXT_FEC_25G_NONE;
1709                         break;
1710                 default:
1711                         break;
1712                 }
1713
1714                 break;
1715         case SPEED_40000:
1716                 switch (params->fec) {
1717                 case FEC_FORCE_MODE_NONE:
1718                         link_params->ext_fec_mode = ETH_EXT_FEC_40G_NONE;
1719                         break;
1720                 case FEC_FORCE_MODE_FIRECODE:
1721                         link_params->ext_fec_mode = ETH_EXT_FEC_40G_BASE_R;
1722                         break;
1723                 case FEC_FORCE_MODE_AUTO:
1724                         link_params->ext_fec_mode = ETH_EXT_FEC_40G_BASE_R |
1725                                                     ETH_EXT_FEC_40G_NONE;
1726                         break;
1727                 default:
1728                         break;
1729                 }
1730
1731                 break;
1732         case SPEED_50000:
1733                 switch (params->fec) {
1734                 case FEC_FORCE_MODE_NONE:
1735                         link_params->ext_fec_mode = ETH_EXT_FEC_50G_NONE;
1736                         break;
1737                 case FEC_FORCE_MODE_FIRECODE:
1738                         link_params->ext_fec_mode = ETH_EXT_FEC_50G_BASE_R;
1739                         break;
1740                 case FEC_FORCE_MODE_RS:
1741                         link_params->ext_fec_mode = ETH_EXT_FEC_50G_RS528;
1742                         break;
1743                 case FEC_FORCE_MODE_AUTO:
1744                         link_params->ext_fec_mode = ETH_EXT_FEC_50G_RS528 |
1745                                                     ETH_EXT_FEC_50G_BASE_R |
1746                                                     ETH_EXT_FEC_50G_NONE;
1747                         break;
1748                 default:
1749                         break;
1750                 }
1751
1752                 break;
1753         case SPEED_100000:
1754                 switch (params->fec) {
1755                 case FEC_FORCE_MODE_NONE:
1756                         link_params->ext_fec_mode = ETH_EXT_FEC_100G_NONE;
1757                         break;
1758                 case FEC_FORCE_MODE_FIRECODE:
1759                         link_params->ext_fec_mode = ETH_EXT_FEC_100G_BASE_R;
1760                         break;
1761                 case FEC_FORCE_MODE_RS:
1762                         link_params->ext_fec_mode = ETH_EXT_FEC_100G_RS528;
1763                         break;
1764                 case FEC_FORCE_MODE_AUTO:
1765                         link_params->ext_fec_mode = ETH_EXT_FEC_100G_RS528 |
1766                                                     ETH_EXT_FEC_100G_BASE_R |
1767                                                     ETH_EXT_FEC_100G_NONE;
1768                         break;
1769                 default:
1770                         break;
1771                 }
1772
1773                 break;
1774         default:
1775                 break;
1776         }
1777 }
1778
1779 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1780 {
1781         struct qed_mcp_link_params *link_params;
1782         struct qed_mcp_link_speed_params *speed;
1783         const struct qed_mfw_speed_map *map;
1784         struct qed_hwfn *hwfn;
1785         struct qed_ptt *ptt;
1786         int rc;
1787         u32 i;
1788
1789         if (!cdev)
1790                 return -ENODEV;
1791
1792         /* The link should be set only once per PF */
1793         hwfn = &cdev->hwfns[0];
1794
1795         /* When VF wants to set link, force it to read the bulletin instead.
1796          * This mimics the PF behavior, where a noitification [both immediate
1797          * and possible later] would be generated when changing properties.
1798          */
1799         if (IS_VF(cdev)) {
1800                 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1801                 return 0;
1802         }
1803
1804         ptt = qed_ptt_acquire(hwfn);
1805         if (!ptt)
1806                 return -EBUSY;
1807
1808         link_params = qed_mcp_get_link_params(hwfn);
1809         if (!link_params)
1810                 return -ENODATA;
1811
1812         speed = &link_params->speed;
1813
1814         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1815                 speed->autoneg = !!params->autoneg;
1816
1817         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1818                 speed->advertised_speeds = 0;
1819
1820                 for (i = 0; i < ARRAY_SIZE(qed_mfw_legacy_maps); i++) {
1821                         map = qed_mfw_legacy_maps + i;
1822
1823                         if (linkmode_intersects(params->adv_speeds, map->caps))
1824                                 speed->advertised_speeds |= map->mfw_val;
1825                 }
1826         }
1827
1828         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1829                 speed->forced_speed = params->forced_speed;
1830
1831         if (qed_mcp_is_ext_speed_supported(hwfn))
1832                 qed_set_ext_speed_params(link_params, params);
1833
1834         if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1835                 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1836                         link_params->pause.autoneg = true;
1837                 else
1838                         link_params->pause.autoneg = false;
1839                 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1840                         link_params->pause.forced_rx = true;
1841                 else
1842                         link_params->pause.forced_rx = false;
1843                 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1844                         link_params->pause.forced_tx = true;
1845                 else
1846                         link_params->pause.forced_tx = false;
1847         }
1848
1849         if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1850                 switch (params->loopback_mode) {
1851                 case QED_LINK_LOOPBACK_INT_PHY:
1852                         link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1853                         break;
1854                 case QED_LINK_LOOPBACK_EXT_PHY:
1855                         link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1856                         break;
1857                 case QED_LINK_LOOPBACK_EXT:
1858                         link_params->loopback_mode = ETH_LOOPBACK_EXT;
1859                         break;
1860                 case QED_LINK_LOOPBACK_MAC:
1861                         link_params->loopback_mode = ETH_LOOPBACK_MAC;
1862                         break;
1863                 case QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123:
1864                         link_params->loopback_mode =
1865                                 ETH_LOOPBACK_CNIG_AH_ONLY_0123;
1866                         break;
1867                 case QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301:
1868                         link_params->loopback_mode =
1869                                 ETH_LOOPBACK_CNIG_AH_ONLY_2301;
1870                         break;
1871                 case QED_LINK_LOOPBACK_PCS_AH_ONLY:
1872                         link_params->loopback_mode = ETH_LOOPBACK_PCS_AH_ONLY;
1873                         break;
1874                 case QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY:
1875                         link_params->loopback_mode =
1876                                 ETH_LOOPBACK_REVERSE_MAC_AH_ONLY;
1877                         break;
1878                 case QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY:
1879                         link_params->loopback_mode =
1880                                 ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY;
1881                         break;
1882                 default:
1883                         link_params->loopback_mode = ETH_LOOPBACK_NONE;
1884                         break;
1885                 }
1886         }
1887
1888         if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
1889                 memcpy(&link_params->eee, &params->eee,
1890                        sizeof(link_params->eee));
1891
1892         if (params->override_flags & QED_LINK_OVERRIDE_FEC_CONFIG)
1893                 link_params->fec = params->fec;
1894
1895         rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1896
1897         qed_ptt_release(hwfn, ptt);
1898
1899         return rc;
1900 }
1901
1902 static int qed_get_port_type(u32 media_type)
1903 {
1904         int port_type;
1905
1906         switch (media_type) {
1907         case MEDIA_SFPP_10G_FIBER:
1908         case MEDIA_SFP_1G_FIBER:
1909         case MEDIA_XFP_FIBER:
1910         case MEDIA_MODULE_FIBER:
1911                 port_type = PORT_FIBRE;
1912                 break;
1913         case MEDIA_DA_TWINAX:
1914                 port_type = PORT_DA;
1915                 break;
1916         case MEDIA_BASE_T:
1917                 port_type = PORT_TP;
1918                 break;
1919         case MEDIA_KR:
1920         case MEDIA_NOT_PRESENT:
1921                 port_type = PORT_NONE;
1922                 break;
1923         case MEDIA_UNSPECIFIED:
1924         default:
1925                 port_type = PORT_OTHER;
1926                 break;
1927         }
1928         return port_type;
1929 }
1930
1931 static int qed_get_link_data(struct qed_hwfn *hwfn,
1932                              struct qed_mcp_link_params *params,
1933                              struct qed_mcp_link_state *link,
1934                              struct qed_mcp_link_capabilities *link_caps)
1935 {
1936         void *p;
1937
1938         if (!IS_PF(hwfn->cdev)) {
1939                 qed_vf_get_link_params(hwfn, params);
1940                 qed_vf_get_link_state(hwfn, link);
1941                 qed_vf_get_link_caps(hwfn, link_caps);
1942
1943                 return 0;
1944         }
1945
1946         p = qed_mcp_get_link_params(hwfn);
1947         if (!p)
1948                 return -ENXIO;
1949         memcpy(params, p, sizeof(*params));
1950
1951         p = qed_mcp_get_link_state(hwfn);
1952         if (!p)
1953                 return -ENXIO;
1954         memcpy(link, p, sizeof(*link));
1955
1956         p = qed_mcp_get_link_capabilities(hwfn);
1957         if (!p)
1958                 return -ENXIO;
1959         memcpy(link_caps, p, sizeof(*link_caps));
1960
1961         return 0;
1962 }
1963
1964 static void qed_fill_link_capability(struct qed_hwfn *hwfn,
1965                                      struct qed_ptt *ptt, u32 capability,
1966                                      unsigned long *if_caps)
1967 {
1968         u32 media_type, tcvr_state, tcvr_type;
1969         u32 speed_mask, board_cfg;
1970
1971         if (qed_mcp_get_media_type(hwfn, ptt, &media_type))
1972                 media_type = MEDIA_UNSPECIFIED;
1973
1974         if (qed_mcp_get_transceiver_data(hwfn, ptt, &tcvr_state, &tcvr_type))
1975                 tcvr_type = ETH_TRANSCEIVER_STATE_UNPLUGGED;
1976
1977         if (qed_mcp_trans_speed_mask(hwfn, ptt, &speed_mask))
1978                 speed_mask = 0xFFFFFFFF;
1979
1980         if (qed_mcp_get_board_config(hwfn, ptt, &board_cfg))
1981                 board_cfg = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
1982
1983         DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
1984                    "Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n",
1985                    media_type, tcvr_state, tcvr_type, speed_mask, board_cfg);
1986
1987         switch (media_type) {
1988         case MEDIA_DA_TWINAX:
1989                 phylink_set(if_caps, FIBRE);
1990
1991                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1992                         phylink_set(if_caps, 20000baseKR2_Full);
1993
1994                 /* For DAC media multiple speed capabilities are supported */
1995                 capability |= speed_mask;
1996
1997                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1998                         phylink_set(if_caps, 1000baseKX_Full);
1999                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
2000                         phylink_set(if_caps, 10000baseCR_Full);
2001
2002                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
2003                         switch (tcvr_type) {
2004                         case ETH_TRANSCEIVER_TYPE_40G_CR4:
2005                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
2006                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
2007                                 phylink_set(if_caps, 40000baseCR4_Full);
2008                                 break;
2009                         default:
2010                                 break;
2011                         }
2012
2013                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
2014                         phylink_set(if_caps, 25000baseCR_Full);
2015                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
2016                         phylink_set(if_caps, 50000baseCR2_Full);
2017
2018                 if (capability &
2019                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
2020                         switch (tcvr_type) {
2021                         case ETH_TRANSCEIVER_TYPE_100G_CR4:
2022                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
2023                                 phylink_set(if_caps, 100000baseCR4_Full);
2024                                 break;
2025                         default:
2026                                 break;
2027                         }
2028
2029                 break;
2030         case MEDIA_BASE_T:
2031                 phylink_set(if_caps, TP);
2032
2033                 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
2034                         if (capability &
2035                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
2036                                 phylink_set(if_caps, 1000baseT_Full);
2037                         if (capability &
2038                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
2039                                 phylink_set(if_caps, 10000baseT_Full);
2040                 }
2041
2042                 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
2043                         phylink_set(if_caps, FIBRE);
2044
2045                         switch (tcvr_type) {
2046                         case ETH_TRANSCEIVER_TYPE_1000BASET:
2047                                 phylink_set(if_caps, 1000baseT_Full);
2048                                 break;
2049                         case ETH_TRANSCEIVER_TYPE_10G_BASET:
2050                                 phylink_set(if_caps, 10000baseT_Full);
2051                                 break;
2052                         default:
2053                                 break;
2054                         }
2055                 }
2056
2057                 break;
2058         case MEDIA_SFP_1G_FIBER:
2059         case MEDIA_SFPP_10G_FIBER:
2060         case MEDIA_XFP_FIBER:
2061         case MEDIA_MODULE_FIBER:
2062                 phylink_set(if_caps, FIBRE);
2063                 capability |= speed_mask;
2064
2065                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
2066                         switch (tcvr_type) {
2067                         case ETH_TRANSCEIVER_TYPE_1G_LX:
2068                         case ETH_TRANSCEIVER_TYPE_1G_SX:
2069                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
2070                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
2071                                 phylink_set(if_caps, 1000baseKX_Full);
2072                                 break;
2073                         default:
2074                                 break;
2075                         }
2076
2077                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
2078                         switch (tcvr_type) {
2079                         case ETH_TRANSCEIVER_TYPE_10G_SR:
2080                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
2081                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
2082                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
2083                                 phylink_set(if_caps, 10000baseSR_Full);
2084                                 break;
2085                         case ETH_TRANSCEIVER_TYPE_10G_LR:
2086                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
2087                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR:
2088                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
2089                                 phylink_set(if_caps, 10000baseLR_Full);
2090                                 break;
2091                         case ETH_TRANSCEIVER_TYPE_10G_LRM:
2092                                 phylink_set(if_caps, 10000baseLRM_Full);
2093                                 break;
2094                         case ETH_TRANSCEIVER_TYPE_10G_ER:
2095                                 phylink_set(if_caps, 10000baseR_FEC);
2096                                 break;
2097                         default:
2098                                 break;
2099                         }
2100
2101                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
2102                         phylink_set(if_caps, 20000baseKR2_Full);
2103
2104                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
2105                         switch (tcvr_type) {
2106                         case ETH_TRANSCEIVER_TYPE_25G_SR:
2107                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
2108                                 phylink_set(if_caps, 25000baseSR_Full);
2109                                 break;
2110                         default:
2111                                 break;
2112                         }
2113
2114                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
2115                         switch (tcvr_type) {
2116                         case ETH_TRANSCEIVER_TYPE_40G_LR4:
2117                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
2118                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
2119                                 phylink_set(if_caps, 40000baseLR4_Full);
2120                                 break;
2121                         case ETH_TRANSCEIVER_TYPE_40G_SR4:
2122                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
2123                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
2124                                 phylink_set(if_caps, 40000baseSR4_Full);
2125                                 break;
2126                         default:
2127                                 break;
2128                         }
2129
2130                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
2131                         phylink_set(if_caps, 50000baseKR2_Full);
2132
2133                 if (capability &
2134                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
2135                         switch (tcvr_type) {
2136                         case ETH_TRANSCEIVER_TYPE_100G_SR4:
2137                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
2138                                 phylink_set(if_caps, 100000baseSR4_Full);
2139                                 break;
2140                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
2141                                 phylink_set(if_caps, 100000baseLR4_ER4_Full);
2142                                 break;
2143                         default:
2144                                 break;
2145                         }
2146
2147                 break;
2148         case MEDIA_KR:
2149                 phylink_set(if_caps, Backplane);
2150
2151                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
2152                         phylink_set(if_caps, 20000baseKR2_Full);
2153                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
2154                         phylink_set(if_caps, 1000baseKX_Full);
2155                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
2156                         phylink_set(if_caps, 10000baseKR_Full);
2157                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
2158                         phylink_set(if_caps, 25000baseKR_Full);
2159                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
2160                         phylink_set(if_caps, 40000baseKR4_Full);
2161                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
2162                         phylink_set(if_caps, 50000baseKR2_Full);
2163                 if (capability &
2164                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
2165                         phylink_set(if_caps, 100000baseKR4_Full);
2166
2167                 break;
2168         case MEDIA_UNSPECIFIED:
2169         case MEDIA_NOT_PRESENT:
2170         default:
2171                 DP_VERBOSE(hwfn->cdev, QED_MSG_DEBUG,
2172                            "Unknown media and transceiver type;\n");
2173                 break;
2174         }
2175 }
2176
2177 static void qed_lp_caps_to_speed_mask(u32 caps, u32 *speed_mask)
2178 {
2179         *speed_mask = 0;
2180
2181         if (caps &
2182             (QED_LINK_PARTNER_SPEED_1G_FD | QED_LINK_PARTNER_SPEED_1G_HD))
2183                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2184         if (caps & QED_LINK_PARTNER_SPEED_10G)
2185                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2186         if (caps & QED_LINK_PARTNER_SPEED_20G)
2187                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
2188         if (caps & QED_LINK_PARTNER_SPEED_25G)
2189                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2190         if (caps & QED_LINK_PARTNER_SPEED_40G)
2191                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
2192         if (caps & QED_LINK_PARTNER_SPEED_50G)
2193                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
2194         if (caps & QED_LINK_PARTNER_SPEED_100G)
2195                 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
2196 }
2197
2198 static void qed_fill_link(struct qed_hwfn *hwfn,
2199                           struct qed_ptt *ptt,
2200                           struct qed_link_output *if_link)
2201 {
2202         struct qed_mcp_link_capabilities link_caps;
2203         struct qed_mcp_link_params params;
2204         struct qed_mcp_link_state link;
2205         u32 media_type, speed_mask;
2206
2207         memset(if_link, 0, sizeof(*if_link));
2208
2209         /* Prepare source inputs */
2210         if (qed_get_link_data(hwfn, &params, &link, &link_caps)) {
2211                 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
2212                 return;
2213         }
2214
2215         /* Set the link parameters to pass to protocol driver */
2216         if (link.link_up)
2217                 if_link->link_up = true;
2218
2219         if (IS_PF(hwfn->cdev) && qed_mcp_is_ext_speed_supported(hwfn)) {
2220                 if (link_caps.default_ext_autoneg)
2221                         phylink_set(if_link->supported_caps, Autoneg);
2222
2223                 linkmode_copy(if_link->advertised_caps, if_link->supported_caps);
2224
2225                 if (params.ext_speed.autoneg)
2226                         phylink_set(if_link->advertised_caps, Autoneg);
2227                 else
2228                         phylink_clear(if_link->advertised_caps, Autoneg);
2229
2230                 qed_fill_link_capability(hwfn, ptt,
2231                                          params.ext_speed.advertised_speeds,
2232                                          if_link->advertised_caps);
2233         } else {
2234                 if (link_caps.default_speed_autoneg)
2235                         phylink_set(if_link->supported_caps, Autoneg);
2236
2237                 linkmode_copy(if_link->advertised_caps, if_link->supported_caps);
2238
2239                 if (params.speed.autoneg)
2240                         phylink_set(if_link->advertised_caps, Autoneg);
2241                 else
2242                         phylink_clear(if_link->advertised_caps, Autoneg);
2243         }
2244
2245         if (params.pause.autoneg ||
2246             (params.pause.forced_rx && params.pause.forced_tx))
2247                 phylink_set(if_link->supported_caps, Asym_Pause);
2248         if (params.pause.autoneg || params.pause.forced_rx ||
2249             params.pause.forced_tx)
2250                 phylink_set(if_link->supported_caps, Pause);
2251
2252         if_link->sup_fec = link_caps.fec_default;
2253         if_link->active_fec = params.fec;
2254
2255         /* Fill link advertised capability */
2256         qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds,
2257                                  if_link->advertised_caps);
2258
2259         /* Fill link supported capability */
2260         qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities,
2261                                  if_link->supported_caps);
2262
2263         /* Fill partner advertised capability */
2264         qed_lp_caps_to_speed_mask(link.partner_adv_speed, &speed_mask);
2265         qed_fill_link_capability(hwfn, ptt, speed_mask, if_link->lp_caps);
2266
2267         if (link.link_up)
2268                 if_link->speed = link.speed;
2269
2270         /* TODO - fill duplex properly */
2271         if_link->duplex = DUPLEX_FULL;
2272         qed_mcp_get_media_type(hwfn, ptt, &media_type);
2273         if_link->port = qed_get_port_type(media_type);
2274
2275         if_link->autoneg = params.speed.autoneg;
2276
2277         if (params.pause.autoneg)
2278                 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2279         if (params.pause.forced_rx)
2280                 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2281         if (params.pause.forced_tx)
2282                 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2283
2284         if (link.an_complete)
2285                 phylink_set(if_link->lp_caps, Autoneg);
2286         if (link.partner_adv_pause)
2287                 phylink_set(if_link->lp_caps, Pause);
2288         if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
2289             link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
2290                 phylink_set(if_link->lp_caps, Asym_Pause);
2291
2292         if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
2293                 if_link->eee_supported = false;
2294         } else {
2295                 if_link->eee_supported = true;
2296                 if_link->eee_active = link.eee_active;
2297                 if_link->sup_caps = link_caps.eee_speed_caps;
2298                 /* MFW clears adv_caps on eee disable; use configured value */
2299                 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
2300                                         params.eee.adv_caps;
2301                 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
2302                 if_link->eee.enable = params.eee.enable;
2303                 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
2304                 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
2305         }
2306 }
2307
2308 static void qed_get_current_link(struct qed_dev *cdev,
2309                                  struct qed_link_output *if_link)
2310 {
2311         struct qed_hwfn *hwfn;
2312         struct qed_ptt *ptt;
2313         int i;
2314
2315         hwfn = &cdev->hwfns[0];
2316         if (IS_PF(cdev)) {
2317                 ptt = qed_ptt_acquire(hwfn);
2318                 if (ptt) {
2319                         qed_fill_link(hwfn, ptt, if_link);
2320                         qed_ptt_release(hwfn, ptt);
2321                 } else {
2322                         DP_NOTICE(hwfn, "Failed to fill link; No PTT\n");
2323                 }
2324         } else {
2325                 qed_fill_link(hwfn, NULL, if_link);
2326         }
2327
2328         for_each_hwfn(cdev, i)
2329                 qed_inform_vf_link_state(&cdev->hwfns[i]);
2330 }
2331
2332 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
2333 {
2334         void *cookie = hwfn->cdev->ops_cookie;
2335         struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
2336         struct qed_link_output if_link;
2337
2338         qed_fill_link(hwfn, ptt, &if_link);
2339         qed_inform_vf_link_state(hwfn);
2340
2341         if (IS_LEAD_HWFN(hwfn) && cookie)
2342                 op->link_update(cookie, &if_link);
2343 }
2344
2345 void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
2346 {
2347         void *cookie = hwfn->cdev->ops_cookie;
2348         struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
2349
2350         if (IS_LEAD_HWFN(hwfn) && cookie && op && op->bw_update)
2351                 op->bw_update(cookie);
2352 }
2353
2354 static int qed_drain(struct qed_dev *cdev)
2355 {
2356         struct qed_hwfn *hwfn;
2357         struct qed_ptt *ptt;
2358         int i, rc;
2359
2360         if (IS_VF(cdev))
2361                 return 0;
2362
2363         for_each_hwfn(cdev, i) {
2364                 hwfn = &cdev->hwfns[i];
2365                 ptt = qed_ptt_acquire(hwfn);
2366                 if (!ptt) {
2367                         DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
2368                         return -EBUSY;
2369                 }
2370                 rc = qed_mcp_drain(hwfn, ptt);
2371                 qed_ptt_release(hwfn, ptt);
2372                 if (rc)
2373                         return rc;
2374         }
2375
2376         return 0;
2377 }
2378
2379 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev,
2380                                           struct qed_nvm_image_att *nvm_image,
2381                                           u32 *crc)
2382 {
2383         u8 *buf = NULL;
2384         int rc;
2385
2386         /* Allocate a buffer for holding the nvram image */
2387         buf = kzalloc(nvm_image->length, GFP_KERNEL);
2388         if (!buf)
2389                 return -ENOMEM;
2390
2391         /* Read image into buffer */
2392         rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr,
2393                               buf, nvm_image->length);
2394         if (rc) {
2395                 DP_ERR(cdev, "Failed reading image from nvm\n");
2396                 goto out;
2397         }
2398
2399         /* Convert the buffer into big-endian format (excluding the
2400          * closing 4 bytes of CRC).
2401          */
2402         cpu_to_be32_array((__force __be32 *)buf, (const u32 *)buf,
2403                           DIV_ROUND_UP(nvm_image->length - 4, 4));
2404
2405         /* Calc CRC for the "actual" image buffer, i.e. not including
2406          * the last 4 CRC bytes.
2407          */
2408         *crc = ~crc32(~0U, buf, nvm_image->length - 4);
2409         *crc = (__force u32)cpu_to_be32p(crc);
2410
2411 out:
2412         kfree(buf);
2413
2414         return rc;
2415 }
2416
2417 /* Binary file format -
2418  *     /----------------------------------------------------------------------\
2419  * 0B  |                       0x4 [command index]                            |
2420  * 4B  | image_type     | Options        |  Number of register settings       |
2421  * 8B  |                       Value                                          |
2422  * 12B |                       Mask                                           |
2423  * 16B |                       Offset                                         |
2424  *     \----------------------------------------------------------------------/
2425  * There can be several Value-Mask-Offset sets as specified by 'Number of...'.
2426  * Options - 0'b - Calculate & Update CRC for image
2427  */
2428 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data,
2429                                       bool *check_resp)
2430 {
2431         struct qed_nvm_image_att nvm_image;
2432         struct qed_hwfn *p_hwfn;
2433         bool is_crc = false;
2434         u32 image_type;
2435         int rc = 0, i;
2436         u16 len;
2437
2438         *data += 4;
2439         image_type = **data;
2440         p_hwfn = QED_LEADING_HWFN(cdev);
2441         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2442                 if (image_type == p_hwfn->nvm_info.image_att[i].image_type)
2443                         break;
2444         if (i == p_hwfn->nvm_info.num_images) {
2445                 DP_ERR(cdev, "Failed to find nvram image of type %08x\n",
2446                        image_type);
2447                 return -ENOENT;
2448         }
2449
2450         nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2451         nvm_image.length = p_hwfn->nvm_info.image_att[i].len;
2452
2453         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2454                    "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n",
2455                    **data, image_type, nvm_image.start_addr,
2456                    nvm_image.start_addr + nvm_image.length - 1);
2457         (*data)++;
2458         is_crc = !!(**data & BIT(0));
2459         (*data)++;
2460         len = *((u16 *)*data);
2461         *data += 2;
2462         if (is_crc) {
2463                 u32 crc = 0;
2464
2465                 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc);
2466                 if (rc) {
2467                         DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc);
2468                         goto exit;
2469                 }
2470
2471                 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
2472                                        (nvm_image.start_addr +
2473                                         nvm_image.length - 4), (u8 *)&crc, 4);
2474                 if (rc)
2475                         DP_ERR(cdev, "Failed writing to %08x, rc = %d\n",
2476                                nvm_image.start_addr + nvm_image.length - 4, rc);
2477                 goto exit;
2478         }
2479
2480         /* Iterate over the values for setting */
2481         while (len) {
2482                 u32 offset, mask, value, cur_value;
2483                 u8 buf[4];
2484
2485                 value = *((u32 *)*data);
2486                 *data += 4;
2487                 mask = *((u32 *)*data);
2488                 *data += 4;
2489                 offset = *((u32 *)*data);
2490                 *data += 4;
2491
2492                 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf,
2493                                       4);
2494                 if (rc) {
2495                         DP_ERR(cdev, "Failed reading from %08x\n",
2496                                nvm_image.start_addr + offset);
2497                         goto exit;
2498                 }
2499
2500                 cur_value = le32_to_cpu(*((__le32 *)buf));
2501                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2502                            "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n",
2503                            nvm_image.start_addr + offset, cur_value,
2504                            (cur_value & ~mask) | (value & mask), value, mask);
2505                 value = (value & mask) | (cur_value & ~mask);
2506                 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
2507                                        nvm_image.start_addr + offset,
2508                                        (u8 *)&value, 4);
2509                 if (rc) {
2510                         DP_ERR(cdev, "Failed writing to %08x\n",
2511                                nvm_image.start_addr + offset);
2512                         goto exit;
2513                 }
2514
2515                 len--;
2516         }
2517 exit:
2518         return rc;
2519 }
2520
2521 /* Binary file format -
2522  *     /----------------------------------------------------------------------\
2523  * 0B  |                       0x3 [command index]                            |
2524  * 4B  | b'0: check_response?   | b'1-31  reserved                            |
2525  * 8B  | File-type |                   reserved                               |
2526  * 12B |                    Image length in bytes                             |
2527  *     \----------------------------------------------------------------------/
2528  *     Start a new file of the provided type
2529  */
2530 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev,
2531                                           const u8 **data, bool *check_resp)
2532 {
2533         u32 file_type, file_size = 0;
2534         int rc;
2535
2536         *data += 4;
2537         *check_resp = !!(**data & BIT(0));
2538         *data += 4;
2539         file_type = **data;
2540
2541         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2542                    "About to start a new file of type %02x\n", file_type);
2543         if (file_type == DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI) {
2544                 *data += 4;
2545                 file_size = *((u32 *)(*data));
2546         }
2547
2548         rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_BEGIN, file_type,
2549                                (u8 *)(&file_size), 4);
2550         *data += 4;
2551
2552         return rc;
2553 }
2554
2555 /* Binary file format -
2556  *     /----------------------------------------------------------------------\
2557  * 0B  |                       0x2 [command index]                            |
2558  * 4B  |                       Length in bytes                                |
2559  * 8B  | b'0: check_response?   | b'1-31  reserved                            |
2560  * 12B |                       Offset in bytes                                |
2561  * 16B |                       Data ...                                       |
2562  *     \----------------------------------------------------------------------/
2563  *     Write data as part of a file that was previously started. Data should be
2564  *     of length equal to that provided in the message
2565  */
2566 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev,
2567                                          const u8 **data, bool *check_resp)
2568 {
2569         u32 offset, len;
2570         int rc;
2571
2572         *data += 4;
2573         len = *((u32 *)(*data));
2574         *data += 4;
2575         *check_resp = !!(**data & BIT(0));
2576         *data += 4;
2577         offset = *((u32 *)(*data));
2578         *data += 4;
2579
2580         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2581                    "About to write File-data: %08x bytes to offset %08x\n",
2582                    len, offset);
2583
2584         rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset,
2585                                (char *)(*data), len);
2586         *data += len;
2587
2588         return rc;
2589 }
2590
2591 /* Binary file format [General header] -
2592  *     /----------------------------------------------------------------------\
2593  * 0B  |                       QED_NVM_SIGNATURE                              |
2594  * 4B  |                       Length in bytes                                |
2595  * 8B  | Highest command in this batchfile |          Reserved                |
2596  *     \----------------------------------------------------------------------/
2597  */
2598 static int qed_nvm_flash_image_validate(struct qed_dev *cdev,
2599                                         const struct firmware *image,
2600                                         const u8 **data)
2601 {
2602         u32 signature, len;
2603
2604         /* Check minimum size */
2605         if (image->size < 12) {
2606                 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size);
2607                 return -EINVAL;
2608         }
2609
2610         /* Check signature */
2611         signature = *((u32 *)(*data));
2612         if (signature != QED_NVM_SIGNATURE) {
2613                 DP_ERR(cdev, "Wrong signature '%08x'\n", signature);
2614                 return -EINVAL;
2615         }
2616
2617         *data += 4;
2618         /* Validate internal size equals the image-size */
2619         len = *((u32 *)(*data));
2620         if (len != image->size) {
2621                 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n",
2622                        len, (u32)image->size);
2623                 return -EINVAL;
2624         }
2625
2626         *data += 4;
2627         /* Make sure driver familiar with all commands necessary for this */
2628         if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) {
2629                 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n",
2630                        *((u16 *)(*data)));
2631                 return -EINVAL;
2632         }
2633
2634         *data += 4;
2635
2636         return 0;
2637 }
2638
2639 /* Binary file format -
2640  *     /----------------------------------------------------------------------\
2641  * 0B  |                       0x5 [command index]                            |
2642  * 4B  | Number of config attributes     |          Reserved                  |
2643  * 4B  | Config ID                       | Entity ID      | Length            |
2644  * 4B  | Value                                                                |
2645  *     |                                                                      |
2646  *     \----------------------------------------------------------------------/
2647  * There can be several cfg_id-entity_id-Length-Value sets as specified by
2648  * 'Number of config attributes'.
2649  *
2650  * The API parses config attributes from the user provided buffer and flashes
2651  * them to the respective NVM path using Management FW inerface.
2652  */
2653 static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data)
2654 {
2655         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2656         u8 entity_id, len, buf[32];
2657         bool need_nvm_init = true;
2658         struct qed_ptt *ptt;
2659         u16 cfg_id, count;
2660         int rc = 0, i;
2661         u32 flags;
2662
2663         ptt = qed_ptt_acquire(hwfn);
2664         if (!ptt)
2665                 return -EAGAIN;
2666
2667         /* NVM CFG ID attribute header */
2668         *data += 4;
2669         count = *((u16 *)*data);
2670         *data += 4;
2671
2672         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2673                    "Read config ids: num_attrs = %0d\n", count);
2674         /* NVM CFG ID attributes. Start loop index from 1 to avoid additional
2675          * arithmetic operations in the implementation.
2676          */
2677         for (i = 1; i <= count; i++) {
2678                 cfg_id = *((u16 *)*data);
2679                 *data += 2;
2680                 entity_id = **data;
2681                 (*data)++;
2682                 len = **data;
2683                 (*data)++;
2684                 memcpy(buf, *data, len);
2685                 *data += len;
2686
2687                 flags = 0;
2688                 if (need_nvm_init) {
2689                         flags |= QED_NVM_CFG_OPTION_INIT;
2690                         need_nvm_init = false;
2691                 }
2692
2693                 /* Commit to flash and free the resources */
2694                 if (!(i % QED_NVM_CFG_MAX_ATTRS) || i == count) {
2695                         flags |= QED_NVM_CFG_OPTION_COMMIT |
2696                                  QED_NVM_CFG_OPTION_FREE;
2697                         need_nvm_init = true;
2698                 }
2699
2700                 if (entity_id)
2701                         flags |= QED_NVM_CFG_OPTION_ENTITY_SEL;
2702
2703                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2704                            "cfg_id = %d entity = %d len = %d\n", cfg_id,
2705                            entity_id, len);
2706                 rc = qed_mcp_nvm_set_cfg(hwfn, ptt, cfg_id, entity_id, flags,
2707                                          buf, len);
2708                 if (rc) {
2709                         DP_ERR(cdev, "Error %d configuring %d\n", rc, cfg_id);
2710                         break;
2711                 }
2712         }
2713
2714         qed_ptt_release(hwfn, ptt);
2715
2716         return rc;
2717 }
2718
2719 #define QED_MAX_NVM_BUF_LEN     32
2720 static int qed_nvm_flash_cfg_len(struct qed_dev *cdev, u32 cmd)
2721 {
2722         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2723         u8 buf[QED_MAX_NVM_BUF_LEN];
2724         struct qed_ptt *ptt;
2725         u32 len;
2726         int rc;
2727
2728         ptt = qed_ptt_acquire(hwfn);
2729         if (!ptt)
2730                 return QED_MAX_NVM_BUF_LEN;
2731
2732         rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, 0, QED_NVM_CFG_GET_FLAGS, buf,
2733                                  &len);
2734         if (rc || !len) {
2735                 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
2736                 len = QED_MAX_NVM_BUF_LEN;
2737         }
2738
2739         qed_ptt_release(hwfn, ptt);
2740
2741         return len;
2742 }
2743
2744 static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data,
2745                                   u32 cmd, u32 entity_id)
2746 {
2747         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2748         struct qed_ptt *ptt;
2749         u32 flags, len;
2750         int rc = 0;
2751
2752         ptt = qed_ptt_acquire(hwfn);
2753         if (!ptt)
2754                 return -EAGAIN;
2755
2756         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2757                    "Read config cmd = %d entity id %d\n", cmd, entity_id);
2758         flags = entity_id ? QED_NVM_CFG_GET_PF_FLAGS : QED_NVM_CFG_GET_FLAGS;
2759         rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, entity_id, flags, *data, &len);
2760         if (rc)
2761                 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
2762
2763         qed_ptt_release(hwfn, ptt);
2764
2765         return rc;
2766 }
2767
2768 static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
2769 {
2770         const struct firmware *image;
2771         const u8 *data, *data_end;
2772         u32 cmd_type;
2773         int rc;
2774
2775         rc = request_firmware(&image, name, &cdev->pdev->dev);
2776         if (rc) {
2777                 DP_ERR(cdev, "Failed to find '%s'\n", name);
2778                 return rc;
2779         }
2780
2781         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2782                    "Flashing '%s' - firmware's data at %p, size is %08x\n",
2783                    name, image->data, (u32)image->size);
2784         data = image->data;
2785         data_end = data + image->size;
2786
2787         rc = qed_nvm_flash_image_validate(cdev, image, &data);
2788         if (rc)
2789                 goto exit;
2790
2791         while (data < data_end) {
2792                 bool check_resp = false;
2793
2794                 /* Parse the actual command */
2795                 cmd_type = *((u32 *)data);
2796                 switch (cmd_type) {
2797                 case QED_NVM_FLASH_CMD_FILE_DATA:
2798                         rc = qed_nvm_flash_image_file_data(cdev, &data,
2799                                                            &check_resp);
2800                         break;
2801                 case QED_NVM_FLASH_CMD_FILE_START:
2802                         rc = qed_nvm_flash_image_file_start(cdev, &data,
2803                                                             &check_resp);
2804                         break;
2805                 case QED_NVM_FLASH_CMD_NVM_CHANGE:
2806                         rc = qed_nvm_flash_image_access(cdev, &data,
2807                                                         &check_resp);
2808                         break;
2809                 case QED_NVM_FLASH_CMD_NVM_CFG_ID:
2810                         rc = qed_nvm_flash_cfg_write(cdev, &data);
2811                         break;
2812                 default:
2813                         DP_ERR(cdev, "Unknown command %08x\n", cmd_type);
2814                         rc = -EINVAL;
2815                         goto exit;
2816                 }
2817
2818                 if (rc) {
2819                         DP_ERR(cdev, "Command %08x failed\n", cmd_type);
2820                         goto exit;
2821                 }
2822
2823                 /* Check response if needed */
2824                 if (check_resp) {
2825                         u32 mcp_response = 0;
2826
2827                         if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) {
2828                                 DP_ERR(cdev, "Failed getting MCP response\n");
2829                                 rc = -EINVAL;
2830                                 goto exit;
2831                         }
2832
2833                         switch (mcp_response & FW_MSG_CODE_MASK) {
2834                         case FW_MSG_CODE_OK:
2835                         case FW_MSG_CODE_NVM_OK:
2836                         case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK:
2837                         case FW_MSG_CODE_PHY_OK:
2838                                 break;
2839                         default:
2840                                 DP_ERR(cdev, "MFW returns error: %08x\n",
2841                                        mcp_response);
2842                                 rc = -EINVAL;
2843                                 goto exit;
2844                         }
2845                 }
2846         }
2847
2848 exit:
2849         release_firmware(image);
2850
2851         return rc;
2852 }
2853
2854 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type,
2855                              u8 *buf, u16 len)
2856 {
2857         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2858
2859         return qed_mcp_get_nvm_image(hwfn, type, buf, len);
2860 }
2861
2862 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn)
2863 {
2864         struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common;
2865         void *cookie = p_hwfn->cdev->ops_cookie;
2866
2867         if (ops && ops->schedule_recovery_handler)
2868                 ops->schedule_recovery_handler(cookie);
2869 }
2870
2871 static const char * const qed_hw_err_type_descr[] = {
2872         [QED_HW_ERR_FAN_FAIL]           = "Fan Failure",
2873         [QED_HW_ERR_MFW_RESP_FAIL]      = "MFW Response Failure",
2874         [QED_HW_ERR_HW_ATTN]            = "HW Attention",
2875         [QED_HW_ERR_DMAE_FAIL]          = "DMAE Failure",
2876         [QED_HW_ERR_RAMROD_FAIL]        = "Ramrod Failure",
2877         [QED_HW_ERR_FW_ASSERT]          = "FW Assertion",
2878         [QED_HW_ERR_LAST]               = "Unknown",
2879 };
2880
2881 void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
2882                            enum qed_hw_err_type err_type)
2883 {
2884         struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common;
2885         void *cookie = p_hwfn->cdev->ops_cookie;
2886         const char *err_str;
2887
2888         if (err_type > QED_HW_ERR_LAST)
2889                 err_type = QED_HW_ERR_LAST;
2890         err_str = qed_hw_err_type_descr[err_type];
2891
2892         DP_NOTICE(p_hwfn, "HW error occurred [%s]\n", err_str);
2893
2894         /* Call the HW error handler of the protocol driver.
2895          * If it is not available - perform a minimal handling of preventing
2896          * HW attentions from being reasserted.
2897          */
2898         if (ops && ops->schedule_hw_err_handler)
2899                 ops->schedule_hw_err_handler(cookie, err_type);
2900         else
2901                 qed_int_attn_clr_enable(p_hwfn->cdev, true);
2902 }
2903
2904 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
2905                             void *handle)
2906 {
2907                 return qed_set_queue_coalesce(rx_coal, tx_coal, handle);
2908 }
2909
2910 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
2911 {
2912         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2913         struct qed_ptt *ptt;
2914         int status = 0;
2915
2916         ptt = qed_ptt_acquire(hwfn);
2917         if (!ptt)
2918                 return -EAGAIN;
2919
2920         status = qed_mcp_set_led(hwfn, ptt, mode);
2921
2922         qed_ptt_release(hwfn, ptt);
2923
2924         return status;
2925 }
2926
2927 static int qed_recovery_process(struct qed_dev *cdev)
2928 {
2929         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2930         struct qed_ptt *p_ptt;
2931         int rc = 0;
2932
2933         p_ptt = qed_ptt_acquire(p_hwfn);
2934         if (!p_ptt)
2935                 return -EAGAIN;
2936
2937         rc = qed_start_recovery_process(p_hwfn, p_ptt);
2938
2939         qed_ptt_release(p_hwfn, p_ptt);
2940
2941         return rc;
2942 }
2943
2944 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
2945 {
2946         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2947         struct qed_ptt *ptt;
2948         int rc = 0;
2949
2950         if (IS_VF(cdev))
2951                 return 0;
2952
2953         ptt = qed_ptt_acquire(hwfn);
2954         if (!ptt)
2955                 return -EAGAIN;
2956
2957         rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
2958                                    : QED_OV_WOL_DISABLED);
2959         if (rc)
2960                 goto out;
2961         rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2962
2963 out:
2964         qed_ptt_release(hwfn, ptt);
2965         return rc;
2966 }
2967
2968 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
2969 {
2970         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2971         struct qed_ptt *ptt;
2972         int status = 0;
2973
2974         if (IS_VF(cdev))
2975                 return 0;
2976
2977         ptt = qed_ptt_acquire(hwfn);
2978         if (!ptt)
2979                 return -EAGAIN;
2980
2981         status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
2982                                                 QED_OV_DRIVER_STATE_ACTIVE :
2983                                                 QED_OV_DRIVER_STATE_DISABLED);
2984
2985         qed_ptt_release(hwfn, ptt);
2986
2987         return status;
2988 }
2989
2990 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
2991 {
2992         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2993         struct qed_ptt *ptt;
2994         int status = 0;
2995
2996         if (IS_VF(cdev))
2997                 return 0;
2998
2999         ptt = qed_ptt_acquire(hwfn);
3000         if (!ptt)
3001                 return -EAGAIN;
3002
3003         status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
3004         if (status)
3005                 goto out;
3006
3007         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
3008
3009 out:
3010         qed_ptt_release(hwfn, ptt);
3011         return status;
3012 }
3013
3014 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
3015 {
3016         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
3017         struct qed_ptt *ptt;
3018         int status = 0;
3019
3020         if (IS_VF(cdev))
3021                 return 0;
3022
3023         ptt = qed_ptt_acquire(hwfn);
3024         if (!ptt)
3025                 return -EAGAIN;
3026
3027         status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
3028         if (status)
3029                 goto out;
3030
3031         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
3032
3033 out:
3034         qed_ptt_release(hwfn, ptt);
3035         return status;
3036 }
3037
3038 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
3039                                   u8 dev_addr, u32 offset, u32 len)
3040 {
3041         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
3042         struct qed_ptt *ptt;
3043         int rc = 0;
3044
3045         if (IS_VF(cdev))
3046                 return 0;
3047
3048         ptt = qed_ptt_acquire(hwfn);
3049         if (!ptt)
3050                 return -EAGAIN;
3051
3052         rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr,
3053                                   offset, len, buf);
3054
3055         qed_ptt_release(hwfn, ptt);
3056
3057         return rc;
3058 }
3059
3060 static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val)
3061 {
3062         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
3063         struct qed_ptt *ptt;
3064         int rc = 0;
3065
3066         if (IS_VF(cdev))
3067                 return 0;
3068
3069         ptt = qed_ptt_acquire(hwfn);
3070         if (!ptt)
3071                 return -EAGAIN;
3072
3073         rc = qed_dbg_grc_config(hwfn, cfg_id, val);
3074
3075         qed_ptt_release(hwfn, ptt);
3076
3077         return rc;
3078 }
3079
3080 static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev)
3081 {
3082         return QED_AFFIN_HWFN_IDX(cdev);
3083 }
3084
3085 static struct qed_selftest_ops qed_selftest_ops_pass = {
3086         .selftest_memory = &qed_selftest_memory,
3087         .selftest_interrupt = &qed_selftest_interrupt,
3088         .selftest_register = &qed_selftest_register,
3089         .selftest_clock = &qed_selftest_clock,
3090         .selftest_nvram = &qed_selftest_nvram,
3091 };
3092
3093 const struct qed_common_ops qed_common_ops_pass = {
3094         .selftest = &qed_selftest_ops_pass,
3095         .probe = &qed_probe,
3096         .remove = &qed_remove,
3097         .set_power_state = &qed_set_power_state,
3098         .set_name = &qed_set_name,
3099         .update_pf_params = &qed_update_pf_params,
3100         .slowpath_start = &qed_slowpath_start,
3101         .slowpath_stop = &qed_slowpath_stop,
3102         .set_fp_int = &qed_set_int_fp,
3103         .get_fp_int = &qed_get_int_fp,
3104         .sb_init = &qed_sb_init,
3105         .sb_release = &qed_sb_release,
3106         .simd_handler_config = &qed_simd_handler_config,
3107         .simd_handler_clean = &qed_simd_handler_clean,
3108         .dbg_grc = &qed_dbg_grc,
3109         .dbg_grc_size = &qed_dbg_grc_size,
3110         .can_link_change = &qed_can_link_change,
3111         .set_link = &qed_set_link,
3112         .get_link = &qed_get_current_link,
3113         .drain = &qed_drain,
3114         .update_msglvl = &qed_init_dp,
3115         .dbg_all_data = &qed_dbg_all_data,
3116         .dbg_all_data_size = &qed_dbg_all_data_size,
3117         .chain_alloc = &qed_chain_alloc,
3118         .chain_free = &qed_chain_free,
3119         .nvm_flash = &qed_nvm_flash,
3120         .nvm_get_image = &qed_nvm_get_image,
3121         .set_coalesce = &qed_set_coalesce,
3122         .set_led = &qed_set_led,
3123         .recovery_process = &qed_recovery_process,
3124         .recovery_prolog = &qed_recovery_prolog,
3125         .attn_clr_enable = &qed_int_attn_clr_enable,
3126         .update_drv_state = &qed_update_drv_state,
3127         .update_mac = &qed_update_mac,
3128         .update_mtu = &qed_update_mtu,
3129         .update_wol = &qed_update_wol,
3130         .db_recovery_add = &qed_db_recovery_add,
3131         .db_recovery_del = &qed_db_recovery_del,
3132         .read_module_eeprom = &qed_read_module_eeprom,
3133         .get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
3134         .read_nvm_cfg = &qed_nvm_flash_cfg_read,
3135         .read_nvm_cfg_len = &qed_nvm_flash_cfg_len,
3136         .set_grc_config = &qed_set_grc_config,
3137 };
3138
3139 void qed_get_protocol_stats(struct qed_dev *cdev,
3140                             enum qed_mcp_protocol_type type,
3141                             union qed_mcp_protocol_stats *stats)
3142 {
3143         struct qed_eth_stats eth_stats;
3144
3145         memset(stats, 0, sizeof(*stats));
3146
3147         switch (type) {
3148         case QED_MCP_LAN_STATS:
3149                 qed_get_vport_stats(cdev, &eth_stats);
3150                 stats->lan_stats.ucast_rx_pkts =
3151                                         eth_stats.common.rx_ucast_pkts;
3152                 stats->lan_stats.ucast_tx_pkts =
3153                                         eth_stats.common.tx_ucast_pkts;
3154                 stats->lan_stats.fcs_err = -1;
3155                 break;
3156         case QED_MCP_FCOE_STATS:
3157                 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
3158                 break;
3159         case QED_MCP_ISCSI_STATS:
3160                 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
3161                 break;
3162         default:
3163                 DP_VERBOSE(cdev, QED_MSG_SP,
3164                            "Invalid protocol type = %d\n", type);
3165                 return;
3166         }
3167 }
3168
3169 int qed_mfw_tlv_req(struct qed_hwfn *hwfn)
3170 {
3171         DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
3172                    "Scheduling slowpath task [Flag: %d]\n",
3173                    QED_SLOWPATH_MFW_TLV_REQ);
3174         smp_mb__before_atomic();
3175         set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags);
3176         smp_mb__after_atomic();
3177         queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
3178
3179         return 0;
3180 }
3181
3182 static void
3183 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv)
3184 {
3185         struct qed_common_cb_ops *op = cdev->protocol_ops.common;
3186         struct qed_eth_stats_common *p_common;
3187         struct qed_generic_tlvs gen_tlvs;
3188         struct qed_eth_stats stats;
3189         int i;
3190
3191         memset(&gen_tlvs, 0, sizeof(gen_tlvs));
3192         op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs);
3193
3194         if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM)
3195                 tlv->flags.ipv4_csum_offload = true;
3196         if (gen_tlvs.feat_flags & QED_TLV_LSO)
3197                 tlv->flags.lso_supported = true;
3198         tlv->flags.b_set = true;
3199
3200         for (i = 0; i < QED_TLV_MAC_COUNT; i++) {
3201                 if (is_valid_ether_addr(gen_tlvs.mac[i])) {
3202                         ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]);
3203                         tlv->mac_set[i] = true;
3204                 }
3205         }
3206
3207         qed_get_vport_stats(cdev, &stats);
3208         p_common = &stats.common;
3209         tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
3210                          p_common->rx_bcast_pkts;
3211         tlv->rx_frames_set = true;
3212         tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
3213                         p_common->rx_bcast_bytes;
3214         tlv->rx_bytes_set = true;
3215         tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
3216                          p_common->tx_bcast_pkts;
3217         tlv->tx_frames_set = true;
3218         tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
3219                         p_common->tx_bcast_bytes;
3220         tlv->rx_bytes_set = true;
3221 }
3222
3223 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type,
3224                           union qed_mfw_tlv_data *tlv_buf)
3225 {
3226         struct qed_dev *cdev = hwfn->cdev;
3227         struct qed_common_cb_ops *ops;
3228
3229         ops = cdev->protocol_ops.common;
3230         if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) {
3231                 DP_NOTICE(hwfn, "Can't collect TLV management info\n");
3232                 return -EINVAL;
3233         }
3234
3235         switch (type) {
3236         case QED_MFW_TLV_GENERIC:
3237                 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic);
3238                 break;
3239         case QED_MFW_TLV_ETH:
3240                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth);
3241                 break;
3242         case QED_MFW_TLV_FCOE:
3243                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe);
3244                 break;
3245         case QED_MFW_TLV_ISCSI:
3246                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi);
3247                 break;
3248         default:
3249                 break;
3250         }
3251
3252         return 0;
3253 }