drivers/net/ethernet/qlogic/qed/qed_main.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/stddef.h>
  34 #include <linux/pci.h>
  35 #include <linux/kernel.h>
  36 #include <linux/slab.h>
  37 #include <linux/version.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/string.h>
  42 #include <linux/module.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/ethtool.h>
  46 #include <linux/etherdevice.h>
  47 #include <linux/vmalloc.h>
  48 #include <linux/qed/qed_if.h>
  49 #include <linux/qed/qed_ll2_if.h>
  50
  51 #include "qed.h"
  52 #include "qed_sriov.h"
  53 #include "qed_sp.h"
  54 #include "qed_dev_api.h"
  55 #include "qed_ll2.h"
  56 #include "qed_mcp.h"
  57 #include "qed_hw.h"
  58 #include "qed_selftest.h"
  59
  60 #define QED_ROCE_QPS                    (8192)
  61 #define QED_ROCE_DPIS                   (8)
  62
  63 static char version[] =
  64         "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
  65
  66 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
  67 MODULE_LICENSE("GPL");
  68 MODULE_VERSION(DRV_MODULE_VERSION);
  69
  70 #define FW_FILE_VERSION                         \
  71         __stringify(FW_MAJOR_VERSION) "."       \
  72         __stringify(FW_MINOR_VERSION) "."       \
  73         __stringify(FW_REVISION_VERSION) "."    \
  74         __stringify(FW_ENGINEERING_VERSION)
  75
  76 #define QED_FW_FILE_NAME        \
  77         "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
  78
  79 MODULE_FIRMWARE(QED_FW_FILE_NAME);
  80
  81 static int __init qed_init(void)
  82 {
  83         pr_info("%s", version);
  84
  85         return 0;
  86 }
  87
  88 static void __exit qed_cleanup(void)
  89 {
  90         pr_notice("qed_cleanup called\n");
  91 }
  92
  93 module_init(qed_init);
  94 module_exit(qed_cleanup);
  95
  96 /* Check if the DMA controller on the machine can properly handle the DMA
  97  * addressing required by the device.
  98 */
  99 static int qed_set_coherency_mask(struct qed_dev *cdev)
 100 {
 101         struct device *dev = &cdev->pdev->dev;
 102
 103         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
 104                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
 105                         DP_NOTICE(cdev,
 106                                   "Can't request 64-bit consistent allocations\n");
 107                         return -EIO;
 108                 }
 109         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
 110                 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
 111                 return -EIO;
 112         }
 113
 114         return 0;
 115 }
 116
 117 static void qed_free_pci(struct qed_dev *cdev)
 118 {
 119         struct pci_dev *pdev = cdev->pdev;
 120
 121         if (cdev->doorbells)
 122                 iounmap(cdev->doorbells);
 123         if (cdev->regview)
 124                 iounmap(cdev->regview);
 125         if (atomic_read(&pdev->enable_cnt) == 1)
 126                 pci_release_regions(pdev);
 127
 128         pci_disable_device(pdev);
 129 }
 130
 131 #define PCI_REVISION_ID_ERROR_VAL       0xff
 132
 133 /* Performs PCI initializations as well as initializing PCI-related parameters
 134  * in the device structrue. Returns 0 in case of success.
 135  */
 136 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
 137 {
 138         u8 rev_id;
 139         int rc;
 140
 141         cdev->pdev = pdev;
 142
 143         rc = pci_enable_device(pdev);
 144         if (rc) {
 145                 DP_NOTICE(cdev, "Cannot enable PCI device\n");
 146                 goto err0;
 147         }
 148
 149         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 150                 DP_NOTICE(cdev, "No memory region found in bar #0\n");
 151                 rc = -EIO;
 152                 goto err1;
 153         }
 154
 155         if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
 156                 DP_NOTICE(cdev, "No memory region found in bar #2\n");
 157                 rc = -EIO;
 158                 goto err1;
 159         }
 160
 161         if (atomic_read(&pdev->enable_cnt) == 1) {
 162                 rc = pci_request_regions(pdev, "qed");
 163                 if (rc) {
 164                         DP_NOTICE(cdev,
 165                                   "Failed to request PCI memory resources\n");
 166                         goto err1;
 167                 }
 168                 pci_set_master(pdev);
 169                 pci_save_state(pdev);
 170         }
 171
 172         pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
 173         if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
 174                 DP_NOTICE(cdev,
 175                           "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
 176                           rev_id);
 177                 rc = -ENODEV;
 178                 goto err2;
 179         }
 180         if (!pci_is_pcie(pdev)) {
 181                 DP_NOTICE(cdev, "The bus is not PCI Express\n");
 182                 rc = -EIO;
 183                 goto err2;
 184         }
 185
 186         cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
 187         if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
 188                 DP_NOTICE(cdev, "Cannot find power management capability\n");
 189
 190         rc = qed_set_coherency_mask(cdev);
 191         if (rc)
 192                 goto err2;
 193
 194         cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
 195         cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
 196         cdev->pci_params.irq = pdev->irq;
 197
 198         cdev->regview = pci_ioremap_bar(pdev, 0);
 199         if (!cdev->regview) {
 200                 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
 201                 rc = -ENOMEM;
 202                 goto err2;
 203         }
 204
 205         if (IS_PF(cdev)) {
 206                 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
 207                 cdev->db_size = pci_resource_len(cdev->pdev, 2);
 208                 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
 209                 if (!cdev->doorbells) {
 210                         DP_NOTICE(cdev, "Cannot map doorbell space\n");
 211                         return -ENOMEM;
 212                 }
 213         }
 214
 215         return 0;
 216
 217 err2:
 218         pci_release_regions(pdev);
 219 err1:
 220         pci_disable_device(pdev);
 221 err0:
 222         return rc;
 223 }
 224
 225 int qed_fill_dev_info(struct qed_dev *cdev,
 226                       struct qed_dev_info *dev_info)
 227 {
 228         struct qed_ptt  *ptt;
 229
 230         memset(dev_info, 0, sizeof(struct qed_dev_info));
 231
 232         dev_info->num_hwfns = cdev->num_hwfns;
 233         dev_info->pci_mem_start = cdev->pci_params.mem_start;
 234         dev_info->pci_mem_end = cdev->pci_params.mem_end;
 235         dev_info->pci_irq = cdev->pci_params.irq;
 236         dev_info->rdma_supported = (cdev->hwfns[0].hw_info.personality ==
 237                                     QED_PCI_ETH_ROCE);
 238         dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
 239         ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
 240
 241         if (IS_PF(cdev)) {
 242                 dev_info->fw_major = FW_MAJOR_VERSION;
 243                 dev_info->fw_minor = FW_MINOR_VERSION;
 244                 dev_info->fw_rev = FW_REVISION_VERSION;
 245                 dev_info->fw_eng = FW_ENGINEERING_VERSION;
 246                 dev_info->mf_mode = cdev->mf_mode;
 247                 dev_info->tx_switching = true;
 248
 249                 if (QED_LEADING_HWFN(cdev)->hw_info.b_wol_support ==
 250                     QED_WOL_SUPPORT_PME)
 251                         dev_info->wol_support = true;
 252         } else {
 253                 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
 254                                       &dev_info->fw_minor, &dev_info->fw_rev,
 255                                       &dev_info->fw_eng);
 256         }
 257
 258         if (IS_PF(cdev)) {
 259                 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
 260                 if (ptt) {
 261                         qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
 262                                             &dev_info->mfw_rev, NULL);
 263
 264                         qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
 265                                                &dev_info->flash_size);
 266
 267                         qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
 268                 }
 269         } else {
 270                 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
 271                                     &dev_info->mfw_rev, NULL);
 272         }
 273
 274         dev_info->mtu = QED_LEADING_HWFN(cdev)->hw_info.mtu;
 275
 276         return 0;
 277 }
 278
 279 static void qed_free_cdev(struct qed_dev *cdev)
 280 {
 281         kfree((void *)cdev);
 282 }
 283
 284 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
 285 {
 286         struct qed_dev *cdev;
 287
 288         cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
 289         if (!cdev)
 290                 return cdev;
 291
 292         qed_init_struct(cdev);
 293
 294         return cdev;
 295 }
 296
 297 /* Sets the requested power state */
 298 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
 299 {
 300         if (!cdev)
 301                 return -ENODEV;
 302
 303         DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
 304         return 0;
 305 }
 306
 307 /* probing */
 308 static struct qed_dev *qed_probe(struct pci_dev *pdev,
 309                                  struct qed_probe_params *params)
 310 {
 311         struct qed_dev *cdev;
 312         int rc;
 313
 314         cdev = qed_alloc_cdev(pdev);
 315         if (!cdev)
 316                 goto err0;
 317
 318         cdev->protocol = params->protocol;
 319
 320         if (params->is_vf)
 321                 cdev->b_is_vf = true;
 322
 323         qed_init_dp(cdev, params->dp_module, params->dp_level);
 324
 325         rc = qed_init_pci(cdev, pdev);
 326         if (rc) {
 327                 DP_ERR(cdev, "init pci failed\n");
 328                 goto err1;
 329         }
 330         DP_INFO(cdev, "PCI init completed successfully\n");
 331
 332         rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
 333         if (rc) {
 334                 DP_ERR(cdev, "hw prepare failed\n");
 335                 goto err2;
 336         }
 337
 338         DP_INFO(cdev, "qed_probe completed successffuly\n");
 339
 340         return cdev;
 341
 342 err2:
 343         qed_free_pci(cdev);
 344 err1:
 345         qed_free_cdev(cdev);
 346 err0:
 347         return NULL;
 348 }
 349
 350 static void qed_remove(struct qed_dev *cdev)
 351 {
 352         if (!cdev)
 353                 return;
 354
 355         qed_hw_remove(cdev);
 356
 357         qed_free_pci(cdev);
 358
 359         qed_set_power_state(cdev, PCI_D3hot);
 360
 361         qed_free_cdev(cdev);
 362 }
 363
 364 static void qed_disable_msix(struct qed_dev *cdev)
 365 {
 366         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 367                 pci_disable_msix(cdev->pdev);
 368                 kfree(cdev->int_params.msix_table);
 369         } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
 370                 pci_disable_msi(cdev->pdev);
 371         }
 372
 373         memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
 374 }
 375
 376 static int qed_enable_msix(struct qed_dev *cdev,
 377                            struct qed_int_params *int_params)
 378 {
 379         int i, rc, cnt;
 380
 381         cnt = int_params->in.num_vectors;
 382
 383         for (i = 0; i < cnt; i++)
 384                 int_params->msix_table[i].entry = i;
 385
 386         rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
 387                                    int_params->in.min_msix_cnt, cnt);
 388         if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
 389             (rc % cdev->num_hwfns)) {
 390                 pci_disable_msix(cdev->pdev);
 391
 392                 /* If fastpath is initialized, we need at least one interrupt
 393                  * per hwfn [and the slow path interrupts]. New requested number
 394                  * should be a multiple of the number of hwfns.
 395                  */
 396                 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
 397                 DP_NOTICE(cdev,
 398                           "Trying to enable MSI-X with less vectors (%d out of %d)\n",
 399                           cnt, int_params->in.num_vectors);
 400                 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
 401                                            cnt);
 402                 if (!rc)
 403                         rc = cnt;
 404         }
 405
 406         if (rc > 0) {
 407                 /* MSI-x configuration was achieved */
 408                 int_params->out.int_mode = QED_INT_MODE_MSIX;
 409                 int_params->out.num_vectors = rc;
 410                 rc = 0;
 411         } else {
 412                 DP_NOTICE(cdev,
 413                           "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
 414                           cnt, rc);
 415         }
 416
 417         return rc;
 418 }
 419
 420 /* This function outputs the int mode and the number of enabled msix vector */
 421 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
 422 {
 423         struct qed_int_params *int_params = &cdev->int_params;
 424         struct msix_entry *tbl;
 425         int rc = 0, cnt;
 426
 427         switch (int_params->in.int_mode) {
 428         case QED_INT_MODE_MSIX:
 429                 /* Allocate MSIX table */
 430                 cnt = int_params->in.num_vectors;
 431                 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
 432                 if (!int_params->msix_table) {
 433                         rc = -ENOMEM;
 434                         goto out;
 435                 }
 436
 437                 /* Enable MSIX */
 438                 rc = qed_enable_msix(cdev, int_params);
 439                 if (!rc)
 440                         goto out;
 441
 442                 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
 443                 kfree(int_params->msix_table);
 444                 if (force_mode)
 445                         goto out;
 446                 /* Fallthrough */
 447
 448         case QED_INT_MODE_MSI:
 449                 if (cdev->num_hwfns == 1) {
 450                         rc = pci_enable_msi(cdev->pdev);
 451                         if (!rc) {
 452                                 int_params->out.int_mode = QED_INT_MODE_MSI;
 453                                 goto out;
 454                         }
 455
 456                         DP_NOTICE(cdev, "Failed to enable MSI\n");
 457                         if (force_mode)
 458                                 goto out;
 459                 }
 460                 /* Fallthrough */
 461
 462         case QED_INT_MODE_INTA:
 463                         int_params->out.int_mode = QED_INT_MODE_INTA;
 464                         rc = 0;
 465                         goto out;
 466         default:
 467                 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
 468                           int_params->in.int_mode);
 469                 rc = -EINVAL;
 470         }
 471
 472 out:
 473         if (!rc)
 474                 DP_INFO(cdev, "Using %s interrupts\n",
 475                         int_params->out.int_mode == QED_INT_MODE_INTA ?
 476                         "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
 477                         "MSI" : "MSIX");
 478         cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
 479
 480         return rc;
 481 }
 482
 483 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
 484                                     int index, void(*handler)(void *))
 485 {
 486         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 487         int relative_idx = index / cdev->num_hwfns;
 488
 489         hwfn->simd_proto_handler[relative_idx].func = handler;
 490         hwfn->simd_proto_handler[relative_idx].token = token;
 491 }
 492
 493 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
 494 {
 495         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 496         int relative_idx = index / cdev->num_hwfns;
 497
 498         memset(&hwfn->simd_proto_handler[relative_idx], 0,
 499                sizeof(struct qed_simd_fp_handler));
 500 }
 501
 502 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
 503 {
 504         tasklet_schedule((struct tasklet_struct *)tasklet);
 505         return IRQ_HANDLED;
 506 }
 507
 508 static irqreturn_t qed_single_int(int irq, void *dev_instance)
 509 {
 510         struct qed_dev *cdev = (struct qed_dev *)dev_instance;
 511         struct qed_hwfn *hwfn;
 512         irqreturn_t rc = IRQ_NONE;
 513         u64 status;
 514         int i, j;
 515
 516         for (i = 0; i < cdev->num_hwfns; i++) {
 517                 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
 518
 519                 if (!status)
 520                         continue;
 521
 522                 hwfn = &cdev->hwfns[i];
 523
 524                 /* Slowpath interrupt */
 525                 if (unlikely(status & 0x1)) {
 526                         tasklet_schedule(hwfn->sp_dpc);
 527                         status &= ~0x1;
 528                         rc = IRQ_HANDLED;
 529                 }
 530
 531                 /* Fastpath interrupts */
 532                 for (j = 0; j < 64; j++) {
 533                         if ((0x2ULL << j) & status) {
 534                                 hwfn->simd_proto_handler[j].func(
 535                                         hwfn->simd_proto_handler[j].token);
 536                                 status &= ~(0x2ULL << j);
 537                                 rc = IRQ_HANDLED;
 538                         }
 539                 }
 540
 541                 if (unlikely(status))
 542                         DP_VERBOSE(hwfn, NETIF_MSG_INTR,
 543                                    "got an unknown interrupt status 0x%llx\n",
 544                                    status);
 545         }
 546
 547         return rc;
 548 }
 549
 550 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
 551 {
 552         struct qed_dev *cdev = hwfn->cdev;
 553         u32 int_mode;
 554         int rc = 0;
 555         u8 id;
 556
 557         int_mode = cdev->int_params.out.int_mode;
 558         if (int_mode == QED_INT_MODE_MSIX) {
 559                 id = hwfn->my_id;
 560                 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
 561                          id, cdev->pdev->bus->number,
 562                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
 563                 rc = request_irq(cdev->int_params.msix_table[id].vector,
 564                                  qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
 565         } else {
 566                 unsigned long flags = 0;
 567
 568                 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
 569                          cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
 570                          PCI_FUNC(cdev->pdev->devfn));
 571
 572                 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
 573                         flags |= IRQF_SHARED;
 574
 575                 rc = request_irq(cdev->pdev->irq, qed_single_int,
 576                                  flags, cdev->name, cdev);
 577         }
 578
 579         if (rc)
 580                 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
 581         else
 582                 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
 583                            "Requested slowpath %s\n",
 584                            (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
 585
 586         return rc;
 587 }
 588
 589 static void qed_slowpath_irq_free(struct qed_dev *cdev)
 590 {
 591         int i;
 592
 593         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 594                 for_each_hwfn(cdev, i) {
 595                         if (!cdev->hwfns[i].b_int_requested)
 596                                 break;
 597                         synchronize_irq(cdev->int_params.msix_table[i].vector);
 598                         free_irq(cdev->int_params.msix_table[i].vector,
 599                                  cdev->hwfns[i].sp_dpc);
 600                 }
 601         } else {
 602                 if (QED_LEADING_HWFN(cdev)->b_int_requested)
 603                         free_irq(cdev->pdev->irq, cdev);
 604         }
 605         qed_int_disable_post_isr_release(cdev);
 606 }
 607
 608 static int qed_nic_stop(struct qed_dev *cdev)
 609 {
 610         int i, rc;
 611
 612         rc = qed_hw_stop(cdev);
 613
 614         for (i = 0; i < cdev->num_hwfns; i++) {
 615                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 616
 617                 if (p_hwfn->b_sp_dpc_enabled) {
 618                         tasklet_disable(p_hwfn->sp_dpc);
 619                         p_hwfn->b_sp_dpc_enabled = false;
 620                         DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
 621                                    "Disabled sp taskelt [hwfn %d] at %p\n",
 622                                    i, p_hwfn->sp_dpc);
 623                 }
 624         }
 625
 626         qed_dbg_pf_exit(cdev);
 627
 628         return rc;
 629 }
 630
 631 static int qed_nic_reset(struct qed_dev *cdev)
 632 {
 633         int rc;
 634
 635         rc = qed_hw_reset(cdev);
 636         if (rc)
 637                 return rc;
 638
 639         qed_resc_free(cdev);
 640
 641         return 0;
 642 }
 643
 644 static int qed_nic_setup(struct qed_dev *cdev)
 645 {
 646         int rc, i;
 647
 648         /* Determine if interface is going to require LL2 */
 649         if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
 650                 for (i = 0; i < cdev->num_hwfns; i++) {
 651                         struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 652
 653                         p_hwfn->using_ll2 = true;
 654                 }
 655         }
 656
 657         rc = qed_resc_alloc(cdev);
 658         if (rc)
 659                 return rc;
 660
 661         DP_INFO(cdev, "Allocated qed resources\n");
 662
 663         qed_resc_setup(cdev);
 664
 665         return rc;
 666 }
 667
 668 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
 669 {
 670         int limit = 0;
 671
 672         /* Mark the fastpath as free/used */
 673         cdev->int_params.fp_initialized = cnt ? true : false;
 674
 675         if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
 676                 limit = cdev->num_hwfns * 63;
 677         else if (cdev->int_params.fp_msix_cnt)
 678                 limit = cdev->int_params.fp_msix_cnt;
 679
 680         if (!limit)
 681                 return -ENOMEM;
 682
 683         return min_t(int, cnt, limit);
 684 }
 685
 686 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
 687 {
 688         memset(info, 0, sizeof(struct qed_int_info));
 689
 690         if (!cdev->int_params.fp_initialized) {
 691                 DP_INFO(cdev,
 692                         "Protocol driver requested interrupt information, but its support is not yet configured\n");
 693                 return -EINVAL;
 694         }
 695
 696         /* Need to expose only MSI-X information; Single IRQ is handled solely
 697          * by qed.
 698          */
 699         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 700                 int msix_base = cdev->int_params.fp_msix_base;
 701
 702                 info->msix_cnt = cdev->int_params.fp_msix_cnt;
 703                 info->msix = &cdev->int_params.msix_table[msix_base];
 704         }
 705
 706         return 0;
 707 }
 708
 709 static int qed_slowpath_setup_int(struct qed_dev *cdev,
 710                                   enum qed_int_mode int_mode)
 711 {
 712         struct qed_sb_cnt_info sb_cnt_info;
 713         int num_l2_queues = 0;
 714         int rc;
 715         int i;
 716
 717         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
 718                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
 719                 return -EINVAL;
 720         }
 721
 722         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
 723         cdev->int_params.in.int_mode = int_mode;
 724         for_each_hwfn(cdev, i) {
 725                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
 726                 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
 727                 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;
 728                 cdev->int_params.in.num_vectors++; /* slowpath */
 729         }
 730
 731         /* We want a minimum of one slowpath and one fastpath vector per hwfn */
 732         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
 733
 734         rc = qed_set_int_mode(cdev, false);
 735         if (rc)  {
 736                 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
 737                 return rc;
 738         }
 739
 740         cdev->int_params.fp_msix_base = cdev->num_hwfns;
 741         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
 742                                        cdev->num_hwfns;
 743
 744         if (!IS_ENABLED(CONFIG_QED_RDMA))
 745                 return 0;
 746
 747         for_each_hwfn(cdev, i)
 748                 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
 749
 750         DP_VERBOSE(cdev, QED_MSG_RDMA,
 751                    "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
 752                    cdev->int_params.fp_msix_cnt, num_l2_queues);
 753
 754         if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
 755                 cdev->int_params.rdma_msix_cnt =
 756                         (cdev->int_params.fp_msix_cnt - num_l2_queues)
 757                         / cdev->num_hwfns;
 758                 cdev->int_params.rdma_msix_base =
 759                         cdev->int_params.fp_msix_base + num_l2_queues;
 760                 cdev->int_params.fp_msix_cnt = num_l2_queues;
 761         } else {
 762                 cdev->int_params.rdma_msix_cnt = 0;
 763         }
 764
 765         DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
 766                    cdev->int_params.rdma_msix_cnt,
 767                    cdev->int_params.rdma_msix_base);
 768
 769         return 0;
 770 }
 771
 772 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
 773 {
 774         int rc;
 775
 776         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
 777         cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
 778
 779         qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
 780                             &cdev->int_params.in.num_vectors);
 781         if (cdev->num_hwfns > 1) {
 782                 u8 vectors = 0;
 783
 784                 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
 785                 cdev->int_params.in.num_vectors += vectors;
 786         }
 787
 788         /* We want a minimum of one fastpath vector per vf hwfn */
 789         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
 790
 791         rc = qed_set_int_mode(cdev, true);
 792         if (rc)
 793                 return rc;
 794
 795         cdev->int_params.fp_msix_base = 0;
 796         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
 797
 798         return 0;
 799 }
 800
 801 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
 802                    u8 *input_buf, u32 max_size, u8 *unzip_buf)
 803 {
 804         int rc;
 805
 806         p_hwfn->stream->next_in = input_buf;
 807         p_hwfn->stream->avail_in = input_len;
 808         p_hwfn->stream->next_out = unzip_buf;
 809         p_hwfn->stream->avail_out = max_size;
 810
 811         rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
 812
 813         if (rc != Z_OK) {
 814                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
 815                            rc);
 816                 return 0;
 817         }
 818
 819         rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
 820         zlib_inflateEnd(p_hwfn->stream);
 821
 822         if (rc != Z_OK && rc != Z_STREAM_END) {
 823                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
 824                            p_hwfn->stream->msg, rc);
 825                 return 0;
 826         }
 827
 828         return p_hwfn->stream->total_out / 4;
 829 }
 830
 831 static int qed_alloc_stream_mem(struct qed_dev *cdev)
 832 {
 833         int i;
 834         void *workspace;
 835
 836         for_each_hwfn(cdev, i) {
 837                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 838
 839                 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
 840                 if (!p_hwfn->stream)
 841                         return -ENOMEM;
 842
 843                 workspace = vzalloc(zlib_inflate_workspacesize());
 844                 if (!workspace)
 845                         return -ENOMEM;
 846                 p_hwfn->stream->workspace = workspace;
 847         }
 848
 849         return 0;
 850 }
 851
 852 static void qed_free_stream_mem(struct qed_dev *cdev)
 853 {
 854         int i;
 855
 856         for_each_hwfn(cdev, i) {
 857                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 858
 859                 if (!p_hwfn->stream)
 860                         return;
 861
 862                 vfree(p_hwfn->stream->workspace);
 863                 kfree(p_hwfn->stream);
 864         }
 865 }
 866
 867 static void qed_update_pf_params(struct qed_dev *cdev,
 868                                  struct qed_pf_params *params)
 869 {
 870         int i;
 871
 872         if (IS_ENABLED(CONFIG_QED_RDMA)) {
 873                 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
 874                 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
 875                 /* divide by 3 the MRs to avoid MF ILT overflow */
 876                 params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS;
 877                 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
 878         }
 879
 880         /* In case we might support RDMA, don't allow qede to be greedy
 881          * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn.
 882          */
 883         if (QED_LEADING_HWFN(cdev)->hw_info.personality ==
 884             QED_PCI_ETH_ROCE) {
 885                 u16 *num_cons;
 886
 887                 num_cons = &params->eth_pf_params.num_cons;
 888                 *num_cons = min_t(u16, *num_cons, 192);
 889         }
 890
 891         for (i = 0; i < cdev->num_hwfns; i++) {
 892                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 893
 894                 p_hwfn->pf_params = *params;
 895         }
 896 }
 897
 898 static int qed_slowpath_start(struct qed_dev *cdev,
 899                               struct qed_slowpath_params *params)
 900 {
 901         struct qed_tunn_start_params tunn_info;
 902         struct qed_mcp_drv_version drv_version;
 903         const u8 *data = NULL;
 904         struct qed_hwfn *hwfn;
 905         struct qed_ptt *p_ptt;
 906         int rc = -EINVAL;
 907
 908         if (qed_iov_wq_start(cdev))
 909                 goto err;
 910
 911         if (IS_PF(cdev)) {
 912                 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
 913                                       &cdev->pdev->dev);
 914                 if (rc) {
 915                         DP_NOTICE(cdev,
 916                                   "Failed to find fw file - /lib/firmware/%s\n",
 917                                   QED_FW_FILE_NAME);
 918                         goto err;
 919                 }
 920
 921                 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
 922                 if (p_ptt) {
 923                         QED_LEADING_HWFN(cdev)->p_ptp_ptt = p_ptt;
 924                 } else {
 925                         DP_NOTICE(cdev, "Failed to acquire PTT for PTP\n");
 926                         goto err;
 927                 }
 928         }
 929
 930         cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
 931         rc = qed_nic_setup(cdev);
 932         if (rc)
 933                 goto err;
 934
 935         if (IS_PF(cdev))
 936                 rc = qed_slowpath_setup_int(cdev, params->int_mode);
 937         else
 938                 rc = qed_slowpath_vf_setup_int(cdev);
 939         if (rc)
 940                 goto err1;
 941
 942         if (IS_PF(cdev)) {
 943                 /* Allocate stream for unzipping */
 944                 rc = qed_alloc_stream_mem(cdev);
 945                 if (rc)
 946                         goto err2;
 947
 948                 /* First Dword used to diffrentiate between various sources */
 949                 data = cdev->firmware->data + sizeof(u32);
 950
 951                 qed_dbg_pf_init(cdev);
 952         }
 953
 954         memset(&tunn_info, 0, sizeof(tunn_info));
 955         tunn_info.tunn_mode |=  1 << QED_MODE_VXLAN_TUNN |
 956                                 1 << QED_MODE_L2GRE_TUNN |
 957                                 1 << QED_MODE_IPGRE_TUNN |
 958                                 1 << QED_MODE_L2GENEVE_TUNN |
 959                                 1 << QED_MODE_IPGENEVE_TUNN;
 960
 961         tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN;
 962         tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN;
 963         tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN;
 964
 965         /* Start the slowpath */
 966         rc = qed_hw_init(cdev, &tunn_info, true,
 967                          cdev->int_params.out.int_mode,
 968                          true, data);
 969         if (rc)
 970                 goto err2;
 971
 972         DP_INFO(cdev,
 973                 "HW initialization and function start completed successfully\n");
 974
 975         /* Allocate LL2 interface if needed */
 976         if (QED_LEADING_HWFN(cdev)->using_ll2) {
 977                 rc = qed_ll2_alloc_if(cdev);
 978                 if (rc)
 979                         goto err3;
 980         }
 981         if (IS_PF(cdev)) {
 982                 hwfn = QED_LEADING_HWFN(cdev);
 983                 drv_version.version = (params->drv_major << 24) |
 984                                       (params->drv_minor << 16) |
 985                                       (params->drv_rev << 8) |
 986                                       (params->drv_eng);
 987                 strlcpy(drv_version.name, params->name,
 988                         MCP_DRV_VER_STR_SIZE - 4);
 989                 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
 990                                               &drv_version);
 991                 if (rc) {
 992                         DP_NOTICE(cdev, "Failed sending drv version command\n");
 993                         return rc;
 994                 }
 995         }
 996
 997         qed_reset_vport_stats(cdev);
 998
 999         return 0;
1000
1001 err3:
1002         qed_hw_stop(cdev);
1003 err2:
1004         qed_hw_timers_stop_all(cdev);
1005         if (IS_PF(cdev))
1006                 qed_slowpath_irq_free(cdev);
1007         qed_free_stream_mem(cdev);
1008         qed_disable_msix(cdev);
1009 err1:
1010         qed_resc_free(cdev);
1011 err:
1012         if (IS_PF(cdev))
1013                 release_firmware(cdev->firmware);
1014
1015         if (IS_PF(cdev) && QED_LEADING_HWFN(cdev)->p_ptp_ptt)
1016                 qed_ptt_release(QED_LEADING_HWFN(cdev),
1017                                 QED_LEADING_HWFN(cdev)->p_ptp_ptt);
1018
1019         qed_iov_wq_stop(cdev, false);
1020
1021         return rc;
1022 }
1023
1024 static int qed_slowpath_stop(struct qed_dev *cdev)
1025 {
1026         if (!cdev)
1027                 return -ENODEV;
1028
1029         qed_ll2_dealloc_if(cdev);
1030
1031         if (IS_PF(cdev)) {
1032                 qed_ptt_release(QED_LEADING_HWFN(cdev),
1033                                 QED_LEADING_HWFN(cdev)->p_ptp_ptt);
1034                 qed_free_stream_mem(cdev);
1035                 if (IS_QED_ETH_IF(cdev))
1036                         qed_sriov_disable(cdev, true);
1037
1038                 qed_nic_stop(cdev);
1039                 qed_slowpath_irq_free(cdev);
1040         }
1041
1042         qed_disable_msix(cdev);
1043         qed_nic_reset(cdev);
1044
1045         qed_iov_wq_stop(cdev, true);
1046
1047         if (IS_PF(cdev))
1048                 release_firmware(cdev->firmware);
1049
1050         return 0;
1051 }
1052
1053 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
1054                        char ver_str[VER_SIZE])
1055 {
1056         int i;
1057
1058         memcpy(cdev->name, name, NAME_SIZE);
1059         for_each_hwfn(cdev, i)
1060                 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1061
1062         memcpy(cdev->ver_str, ver_str, VER_SIZE);
1063         cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
1064 }
1065
1066 static u32 qed_sb_init(struct qed_dev *cdev,
1067                        struct qed_sb_info *sb_info,
1068                        void *sb_virt_addr,
1069                        dma_addr_t sb_phy_addr, u16 sb_id,
1070                        enum qed_sb_type type)
1071 {
1072         struct qed_hwfn *p_hwfn;
1073         int hwfn_index;
1074         u16 rel_sb_id;
1075         u8 n_hwfns;
1076         u32 rc;
1077
1078         /* RoCE uses single engine and CMT uses two engines. When using both
1079          * we force only a single engine. Storage uses only engine 0 too.
1080          */
1081         if (type == QED_SB_TYPE_L2_QUEUE)
1082                 n_hwfns = cdev->num_hwfns;
1083         else
1084                 n_hwfns = 1;
1085
1086         hwfn_index = sb_id % n_hwfns;
1087         p_hwfn = &cdev->hwfns[hwfn_index];
1088         rel_sb_id = sb_id / n_hwfns;
1089
1090         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1091                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1092                    hwfn_index, rel_sb_id, sb_id);
1093
1094         rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
1095                              sb_virt_addr, sb_phy_addr, rel_sb_id);
1096
1097         return rc;
1098 }
1099
1100 static u32 qed_sb_release(struct qed_dev *cdev,
1101                           struct qed_sb_info *sb_info, u16 sb_id)
1102 {
1103         struct qed_hwfn *p_hwfn;
1104         int hwfn_index;
1105         u16 rel_sb_id;
1106         u32 rc;
1107
1108         hwfn_index = sb_id % cdev->num_hwfns;
1109         p_hwfn = &cdev->hwfns[hwfn_index];
1110         rel_sb_id = sb_id / cdev->num_hwfns;
1111
1112         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1113                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1114                    hwfn_index, rel_sb_id, sb_id);
1115
1116         rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1117
1118         return rc;
1119 }
1120
1121 static bool qed_can_link_change(struct qed_dev *cdev)
1122 {
1123         return true;
1124 }
1125
1126 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1127 {
1128         struct qed_hwfn *hwfn;
1129         struct qed_mcp_link_params *link_params;
1130         struct qed_ptt *ptt;
1131         int rc;
1132
1133         if (!cdev)
1134                 return -ENODEV;
1135
1136         if (IS_VF(cdev))
1137                 return 0;
1138
1139         /* The link should be set only once per PF */
1140         hwfn = &cdev->hwfns[0];
1141
1142         ptt = qed_ptt_acquire(hwfn);
1143         if (!ptt)
1144                 return -EBUSY;
1145
1146         link_params = qed_mcp_get_link_params(hwfn);
1147         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1148                 link_params->speed.autoneg = params->autoneg;
1149         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1150                 link_params->speed.advertised_speeds = 0;
1151                 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) ||
1152                     (params->adv_speeds & QED_LM_1000baseT_Full_BIT))
1153                         link_params->speed.advertised_speeds |=
1154                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1155                 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
1156                         link_params->speed.advertised_speeds |=
1157                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1158                 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
1159                         link_params->speed.advertised_speeds |=
1160                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1161                 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
1162                         link_params->speed.advertised_speeds |=
1163                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1164                 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
1165                         link_params->speed.advertised_speeds |=
1166                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1167                 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
1168                         link_params->speed.advertised_speeds |=
1169                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1170         }
1171         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1172                 link_params->speed.forced_speed = params->forced_speed;
1173         if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1174                 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1175                         link_params->pause.autoneg = true;
1176                 else
1177                         link_params->pause.autoneg = false;
1178                 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1179                         link_params->pause.forced_rx = true;
1180                 else
1181                         link_params->pause.forced_rx = false;
1182                 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1183                         link_params->pause.forced_tx = true;
1184                 else
1185                         link_params->pause.forced_tx = false;
1186         }
1187         if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1188                 switch (params->loopback_mode) {
1189                 case QED_LINK_LOOPBACK_INT_PHY:
1190                         link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1191                         break;
1192                 case QED_LINK_LOOPBACK_EXT_PHY:
1193                         link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1194                         break;
1195                 case QED_LINK_LOOPBACK_EXT:
1196                         link_params->loopback_mode = ETH_LOOPBACK_EXT;
1197                         break;
1198                 case QED_LINK_LOOPBACK_MAC:
1199                         link_params->loopback_mode = ETH_LOOPBACK_MAC;
1200                         break;
1201                 default:
1202                         link_params->loopback_mode = ETH_LOOPBACK_NONE;
1203                         break;
1204                 }
1205         }
1206
1207         rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1208
1209         qed_ptt_release(hwfn, ptt);
1210
1211         return rc;
1212 }
1213
1214 static int qed_get_port_type(u32 media_type)
1215 {
1216         int port_type;
1217
1218         switch (media_type) {
1219         case MEDIA_SFPP_10G_FIBER:
1220         case MEDIA_SFP_1G_FIBER:
1221         case MEDIA_XFP_FIBER:
1222         case MEDIA_MODULE_FIBER:
1223         case MEDIA_KR:
1224                 port_type = PORT_FIBRE;
1225                 break;
1226         case MEDIA_DA_TWINAX:
1227                 port_type = PORT_DA;
1228                 break;
1229         case MEDIA_BASE_T:
1230                 port_type = PORT_TP;
1231                 break;
1232         case MEDIA_NOT_PRESENT:
1233                 port_type = PORT_NONE;
1234                 break;
1235         case MEDIA_UNSPECIFIED:
1236         default:
1237                 port_type = PORT_OTHER;
1238                 break;
1239         }
1240         return port_type;
1241 }
1242
1243 static int qed_get_link_data(struct qed_hwfn *hwfn,
1244                              struct qed_mcp_link_params *params,
1245                              struct qed_mcp_link_state *link,
1246                              struct qed_mcp_link_capabilities *link_caps)
1247 {
1248         void *p;
1249
1250         if (!IS_PF(hwfn->cdev)) {
1251                 qed_vf_get_link_params(hwfn, params);
1252                 qed_vf_get_link_state(hwfn, link);
1253                 qed_vf_get_link_caps(hwfn, link_caps);
1254
1255                 return 0;
1256         }
1257
1258         p = qed_mcp_get_link_params(hwfn);
1259         if (!p)
1260                 return -ENXIO;
1261         memcpy(params, p, sizeof(*params));
1262
1263         p = qed_mcp_get_link_state(hwfn);
1264         if (!p)
1265                 return -ENXIO;
1266         memcpy(link, p, sizeof(*link));
1267
1268         p = qed_mcp_get_link_capabilities(hwfn);
1269         if (!p)
1270                 return -ENXIO;
1271         memcpy(link_caps, p, sizeof(*link_caps));
1272
1273         return 0;
1274 }
1275
1276 static void qed_fill_link(struct qed_hwfn *hwfn,
1277                           struct qed_link_output *if_link)
1278 {
1279         struct qed_mcp_link_params params;
1280         struct qed_mcp_link_state link;
1281         struct qed_mcp_link_capabilities link_caps;
1282         u32 media_type;
1283
1284         memset(if_link, 0, sizeof(*if_link));
1285
1286         /* Prepare source inputs */
1287         if (qed_get_link_data(hwfn, &params, &link, &link_caps)) {
1288                 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1289                 return;
1290         }
1291
1292         /* Set the link parameters to pass to protocol driver */
1293         if (link.link_up)
1294                 if_link->link_up = true;
1295
1296         /* TODO - at the moment assume supported and advertised speed equal */
1297         if_link->supported_caps = QED_LM_FIBRE_BIT;
1298         if (params.speed.autoneg)
1299                 if_link->supported_caps |= QED_LM_Autoneg_BIT;
1300         if (params.pause.autoneg ||
1301             (params.pause.forced_rx && params.pause.forced_tx))
1302                 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
1303         if (params.pause.autoneg || params.pause.forced_rx ||
1304             params.pause.forced_tx)
1305                 if_link->supported_caps |= QED_LM_Pause_BIT;
1306
1307         if_link->advertised_caps = if_link->supported_caps;
1308         if (params.speed.advertised_speeds &
1309             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1310                 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT |
1311                     QED_LM_1000baseT_Full_BIT;
1312         if (params.speed.advertised_speeds &
1313             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1314                 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
1315         if (params.speed.advertised_speeds &
1316             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1317                 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
1318         if (params.speed.advertised_speeds &
1319             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1320                 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT;
1321         if (params.speed.advertised_speeds &
1322             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1323                 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT;
1324         if (params.speed.advertised_speeds &
1325             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1326                 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT;
1327
1328         if (link_caps.speed_capabilities &
1329             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1330                 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT |
1331                     QED_LM_1000baseT_Full_BIT;
1332         if (link_caps.speed_capabilities &
1333             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1334                 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
1335         if (link_caps.speed_capabilities &
1336             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1337                 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
1338         if (link_caps.speed_capabilities &
1339             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1340                 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT;
1341         if (link_caps.speed_capabilities &
1342             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1343                 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT;
1344         if (link_caps.speed_capabilities &
1345             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1346                 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT;
1347
1348         if (link.link_up)
1349                 if_link->speed = link.speed;
1350
1351         /* TODO - fill duplex properly */
1352         if_link->duplex = DUPLEX_FULL;
1353         qed_mcp_get_media_type(hwfn->cdev, &media_type);
1354         if_link->port = qed_get_port_type(media_type);
1355
1356         if_link->autoneg = params.speed.autoneg;
1357
1358         if (params.pause.autoneg)
1359                 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1360         if (params.pause.forced_rx)
1361                 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1362         if (params.pause.forced_tx)
1363                 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1364
1365         /* Link partner capabilities */
1366         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD)
1367                 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT;
1368         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
1369                 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1370         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1371                 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1372         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1373                 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1374         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1375                 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1376         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1377                 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1378         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1379                 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
1380
1381         if (link.an_complete)
1382                 if_link->lp_caps |= QED_LM_Autoneg_BIT;
1383
1384         if (link.partner_adv_pause)
1385                 if_link->lp_caps |= QED_LM_Pause_BIT;
1386         if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1387             link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1388                 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
1389 }
1390
1391 static void qed_get_current_link(struct qed_dev *cdev,
1392                                  struct qed_link_output *if_link)
1393 {
1394         int i;
1395
1396         qed_fill_link(&cdev->hwfns[0], if_link);
1397
1398         for_each_hwfn(cdev, i)
1399                 qed_inform_vf_link_state(&cdev->hwfns[i]);
1400 }
1401
1402 void qed_link_update(struct qed_hwfn *hwfn)
1403 {
1404         void *cookie = hwfn->cdev->ops_cookie;
1405         struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1406         struct qed_link_output if_link;
1407
1408         qed_fill_link(hwfn, &if_link);
1409         qed_inform_vf_link_state(hwfn);
1410
1411         if (IS_LEAD_HWFN(hwfn) && cookie)
1412                 op->link_update(cookie, &if_link);
1413 }
1414
1415 static int qed_drain(struct qed_dev *cdev)
1416 {
1417         struct qed_hwfn *hwfn;
1418         struct qed_ptt *ptt;
1419         int i, rc;
1420
1421         if (IS_VF(cdev))
1422                 return 0;
1423
1424         for_each_hwfn(cdev, i) {
1425                 hwfn = &cdev->hwfns[i];
1426                 ptt = qed_ptt_acquire(hwfn);
1427                 if (!ptt) {
1428                         DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1429                         return -EBUSY;
1430                 }
1431                 rc = qed_mcp_drain(hwfn, ptt);
1432                 if (rc)
1433                         return rc;
1434                 qed_ptt_release(hwfn, ptt);
1435         }
1436
1437         return 0;
1438 }
1439
1440 static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal)
1441 {
1442         *rx_coal = cdev->rx_coalesce_usecs;
1443         *tx_coal = cdev->tx_coalesce_usecs;
1444 }
1445
1446 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
1447                             u8 qid, u16 sb_id)
1448 {
1449         struct qed_hwfn *hwfn;
1450         struct qed_ptt *ptt;
1451         int hwfn_index;
1452         int status = 0;
1453
1454         hwfn_index = qid % cdev->num_hwfns;
1455         hwfn = &cdev->hwfns[hwfn_index];
1456         ptt = qed_ptt_acquire(hwfn);
1457         if (!ptt)
1458                 return -EAGAIN;
1459
1460         status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal,
1461                                       qid / cdev->num_hwfns, sb_id);
1462         if (status)
1463                 goto out;
1464         status = qed_set_txq_coalesce(hwfn, ptt, tx_coal,
1465                                       qid / cdev->num_hwfns, sb_id);
1466 out:
1467         qed_ptt_release(hwfn, ptt);
1468
1469         return status;
1470 }
1471
1472 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1473 {
1474         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1475         struct qed_ptt *ptt;
1476         int status = 0;
1477
1478         ptt = qed_ptt_acquire(hwfn);
1479         if (!ptt)
1480                 return -EAGAIN;
1481
1482         status = qed_mcp_set_led(hwfn, ptt, mode);
1483
1484         qed_ptt_release(hwfn, ptt);
1485
1486         return status;
1487 }
1488
1489 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
1490 {
1491         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1492         struct qed_ptt *ptt;
1493         int rc = 0;
1494
1495         if (IS_VF(cdev))
1496                 return 0;
1497
1498         ptt = qed_ptt_acquire(hwfn);
1499         if (!ptt)
1500                 return -EAGAIN;
1501
1502         rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
1503                                    : QED_OV_WOL_DISABLED);
1504         if (rc)
1505                 goto out;
1506         rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1507
1508 out:
1509         qed_ptt_release(hwfn, ptt);
1510         return rc;
1511 }
1512
1513 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
1514 {
1515         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1516         struct qed_ptt *ptt;
1517         int status = 0;
1518
1519         if (IS_VF(cdev))
1520                 return 0;
1521
1522         ptt = qed_ptt_acquire(hwfn);
1523         if (!ptt)
1524                 return -EAGAIN;
1525
1526         status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
1527                                                 QED_OV_DRIVER_STATE_ACTIVE :
1528                                                 QED_OV_DRIVER_STATE_DISABLED);
1529
1530         qed_ptt_release(hwfn, ptt);
1531
1532         return status;
1533 }
1534
1535 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
1536 {
1537         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1538         struct qed_ptt *ptt;
1539         int status = 0;
1540
1541         if (IS_VF(cdev))
1542                 return 0;
1543
1544         ptt = qed_ptt_acquire(hwfn);
1545         if (!ptt)
1546                 return -EAGAIN;
1547
1548         status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
1549         if (status)
1550                 goto out;
1551
1552         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1553
1554 out:
1555         qed_ptt_release(hwfn, ptt);
1556         return status;
1557 }
1558
1559 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
1560 {
1561         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1562         struct qed_ptt *ptt;
1563         int status = 0;
1564
1565         if (IS_VF(cdev))
1566                 return 0;
1567
1568         ptt = qed_ptt_acquire(hwfn);
1569         if (!ptt)
1570                 return -EAGAIN;
1571
1572         status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
1573         if (status)
1574                 goto out;
1575
1576         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1577
1578 out:
1579         qed_ptt_release(hwfn, ptt);
1580         return status;
1581 }
1582
1583 static struct qed_selftest_ops qed_selftest_ops_pass = {
1584         .selftest_memory = &qed_selftest_memory,
1585         .selftest_interrupt = &qed_selftest_interrupt,
1586         .selftest_register = &qed_selftest_register,
1587         .selftest_clock = &qed_selftest_clock,
1588         .selftest_nvram = &qed_selftest_nvram,
1589 };
1590
1591 const struct qed_common_ops qed_common_ops_pass = {
1592         .selftest = &qed_selftest_ops_pass,
1593         .probe = &qed_probe,
1594         .remove = &qed_remove,
1595         .set_power_state = &qed_set_power_state,
1596         .set_id = &qed_set_id,
1597         .update_pf_params = &qed_update_pf_params,
1598         .slowpath_start = &qed_slowpath_start,
1599         .slowpath_stop = &qed_slowpath_stop,
1600         .set_fp_int = &qed_set_int_fp,
1601         .get_fp_int = &qed_get_int_fp,
1602         .sb_init = &qed_sb_init,
1603         .sb_release = &qed_sb_release,
1604         .simd_handler_config = &qed_simd_handler_config,
1605         .simd_handler_clean = &qed_simd_handler_clean,
1606         .can_link_change = &qed_can_link_change,
1607         .set_link = &qed_set_link,
1608         .get_link = &qed_get_current_link,
1609         .drain = &qed_drain,
1610         .update_msglvl = &qed_init_dp,
1611         .dbg_all_data = &qed_dbg_all_data,
1612         .dbg_all_data_size = &qed_dbg_all_data_size,
1613         .chain_alloc = &qed_chain_alloc,
1614         .chain_free = &qed_chain_free,
1615         .get_coalesce = &qed_get_coalesce,
1616         .set_coalesce = &qed_set_coalesce,
1617         .set_led = &qed_set_led,
1618         .update_drv_state = &qed_update_drv_state,
1619         .update_mac = &qed_update_mac,
1620         .update_mtu = &qed_update_mtu,
1621         .update_wol = &qed_update_wol,
1622 };
1623
1624 void qed_get_protocol_stats(struct qed_dev *cdev,
1625                             enum qed_mcp_protocol_type type,
1626                             union qed_mcp_protocol_stats *stats)
1627 {
1628         struct qed_eth_stats eth_stats;
1629
1630         memset(stats, 0, sizeof(*stats));
1631
1632         switch (type) {
1633         case QED_MCP_LAN_STATS:
1634                 qed_get_vport_stats(cdev, &eth_stats);
1635                 stats->lan_stats.ucast_rx_pkts = eth_stats.rx_ucast_pkts;
1636                 stats->lan_stats.ucast_tx_pkts = eth_stats.tx_ucast_pkts;
1637                 stats->lan_stats.fcs_err = -1;
1638                 break;
1639         default:
1640                 DP_ERR(cdev, "Invalid protocol type = %d\n", type);
1641                 return;
1642         }
1643 }