1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <linux/bitops.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/errno.h>
37 #include <linux/kernel.h>
38 #include <linux/list.h>
39 #include <linux/log2.h>
40 #include <linux/pci.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/bitops.h>
46 #include "qed_dev_api.h"
49 #include "qed_init_ops.h"
50 #include "qed_reg_addr.h"
51 #include "qed_sriov.h"
53 /* Max number of connection types in HW (DQ/CDU etc.) */
54 #define MAX_CONN_TYPES PROTOCOLID_COMMON
55 #define NUM_TASK_TYPES 2
56 #define NUM_TASK_PF_SEGMENTS 4
57 #define NUM_TASK_VF_SEGMENTS 1
60 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */
62 /* Doorbell-Queue constants */
63 #define DQ_RANGE_SHIFT 4
64 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT)
66 /* Searcher constants */
67 #define SRC_MIN_NUM_ELEMS 256
69 /* Timers constants */
71 #define TM_ALIGN BIT(TM_SHIFT)
72 #define TM_ELEM_SIZE 4
74 #define ILT_DEFAULT_HW_P_SIZE 4
76 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
77 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
79 /* ILT entry structure */
80 #define ILT_ENTRY_PHY_ADDR_MASK (~0ULL >> 12)
81 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
82 #define ILT_ENTRY_VALID_MASK 0x1ULL
83 #define ILT_ENTRY_VALID_SHIFT 52
84 #define ILT_ENTRY_IN_REGS 2
85 #define ILT_REG_SIZE_IN_BYTES 4
87 /* connection context union */
89 struct e4_core_conn_context core_ctx;
90 struct e4_eth_conn_context eth_ctx;
91 struct e4_iscsi_conn_context iscsi_ctx;
92 struct e4_fcoe_conn_context fcoe_ctx;
93 struct e4_roce_conn_context roce_ctx;
96 /* TYPE-0 task context - iSCSI, FCOE */
97 union type0_task_context {
98 struct e4_iscsi_task_context iscsi_ctx;
99 struct e4_fcoe_task_context fcoe_ctx;
102 /* TYPE-1 task context - ROCE */
103 union type1_task_context {
104 struct e4_rdma_task_context roce_ctx;
112 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
113 #define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12)
115 #define CONN_CXT_SIZE(p_hwfn) \
116 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
118 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
120 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
121 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
123 /* Alignment is inherent to the type1_task_context structure */
124 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
126 /* PF per protocl configuration object */
127 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
128 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
136 struct qed_conn_type_cfg {
139 struct qed_tid_seg tid_seg[TASK_SEGMENTS];
142 /* ILT Client configuration, Per connection type (protocol) resources. */
143 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
144 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
147 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
148 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
160 struct ilt_cfg_pair {
165 struct qed_ilt_cli_blk {
166 u32 total_size; /* 0 means not active */
167 u32 real_size_in_page;
169 u32 dynamic_line_cnt;
172 struct qed_ilt_client_cfg {
176 struct ilt_cfg_pair first;
177 struct ilt_cfg_pair last;
178 struct ilt_cfg_pair p_size;
180 /* ILT client blocks for PF */
181 struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
184 /* ILT client blocks for VFs */
185 struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
191 * Protocol acquired CID lists
192 * PF start line in ILT
200 struct qed_cid_acquired_map {
203 unsigned long *cid_map;
206 struct qed_cxt_mngr {
207 /* Per protocl configuration */
208 struct qed_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
210 /* computed ILT structure */
211 struct qed_ilt_client_cfg clients[ILT_CLI_MAX];
213 /* Task type sizes */
214 u32 task_type_size[NUM_TASK_TYPES];
216 /* total number of VFs for this hwfn -
217 * ALL VFs are symmetric in terms of HW resources
222 struct qed_cid_acquired_map acquired[MAX_CONN_TYPES];
224 struct qed_cid_acquired_map
225 acquired_vf[MAX_CONN_TYPES][MAX_NUM_VFS];
227 /* ILT shadow table */
228 struct qed_dma_mem *ilt_shadow;
231 /* Mutex for a dynamic ILT allocation */
235 struct qed_dma_mem *t2;
240 /* total number of SRQ's for this hwfn */
243 /* Maximal number of L2 steering filters */
246 static bool src_proto(enum protocol_type type)
248 return type == PROTOCOLID_ISCSI ||
249 type == PROTOCOLID_FCOE ||
250 type == PROTOCOLID_IWARP;
253 static bool tm_cid_proto(enum protocol_type type)
255 return type == PROTOCOLID_ISCSI ||
256 type == PROTOCOLID_FCOE ||
257 type == PROTOCOLID_ROCE ||
258 type == PROTOCOLID_IWARP;
261 static bool tm_tid_proto(enum protocol_type type)
263 return type == PROTOCOLID_FCOE;
266 /* counts the iids for the CDU/CDUC ILT client configuration */
267 struct qed_cdu_iids {
272 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
273 struct qed_cdu_iids *iids)
277 for (type = 0; type < MAX_CONN_TYPES; type++) {
278 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
279 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
283 /* counts the iids for the Searcher block configuration */
284 struct qed_src_iids {
289 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
290 struct qed_src_iids *iids)
294 for (i = 0; i < MAX_CONN_TYPES; i++) {
298 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
299 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
302 /* Add L2 filtering filters in addition */
303 iids->pf_cids += p_mngr->arfs_count;
306 /* counts the iids for the Timers block configuration */
309 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
315 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn,
316 struct qed_cxt_mngr *p_mngr,
317 struct qed_tm_iids *iids)
319 bool tm_vf_required = false;
320 bool tm_required = false;
323 /* Timers is a special case -> we don't count how many cids require
324 * timers but what's the max cid that will be used by the timer block.
325 * therefore we traverse in reverse order, and once we hit a protocol
326 * that requires the timers memory, we'll sum all the protocols up
329 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) {
330 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
332 if (tm_cid_proto(i) || tm_required) {
333 if (p_cfg->cid_count)
336 iids->pf_cids += p_cfg->cid_count;
339 if (tm_cid_proto(i) || tm_vf_required) {
340 if (p_cfg->cids_per_vf)
341 tm_vf_required = true;
343 iids->per_vf_cids += p_cfg->cids_per_vf;
346 if (tm_tid_proto(i)) {
347 struct qed_tid_seg *segs = p_cfg->tid_seg;
349 /* for each segment there is at most one
350 * protocol for which count is not 0.
352 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
353 iids->pf_tids[j] += segs[j].count;
355 /* The last array elelment is for the VFs. As for PF
356 * segments there can be only one protocol for
357 * which this value is not 0.
359 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
363 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
364 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
365 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
367 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
368 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
369 iids->pf_tids_total += iids->pf_tids[j];
373 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
374 struct qed_qm_iids *iids)
376 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
377 struct qed_tid_seg *segs;
378 u32 vf_cids = 0, type, j;
381 for (type = 0; type < MAX_CONN_TYPES; type++) {
382 iids->cids += p_mngr->conn_cfg[type].cid_count;
383 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
385 segs = p_mngr->conn_cfg[type].tid_seg;
386 /* for each segment there is at most one
387 * protocol for which count is not 0.
389 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
390 iids->tids += segs[j].count;
392 /* The last array elelment is for the VFs. As for PF
393 * segments there can be only one protocol for
394 * which this value is not 0.
396 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
399 iids->vf_cids += vf_cids * p_mngr->vf_count;
400 iids->tids += vf_tids * p_mngr->vf_count;
402 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
403 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
404 iids->cids, iids->vf_cids, iids->tids, vf_tids);
407 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
410 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
413 /* Find the protocol with tid count > 0 for this segment.
414 * Note: there can only be one and this is already validated.
416 for (i = 0; i < MAX_CONN_TYPES; i++)
417 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
418 return &p_cfg->conn_cfg[i].tid_seg[seg];
422 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
424 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
426 p_mgr->srq_count = num_srqs;
429 static u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
431 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
433 return p_mgr->srq_count;
436 /* set the iids count per protocol */
437 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
438 enum protocol_type type,
439 u32 cid_count, u32 vf_cid_cnt)
441 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
442 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
444 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
445 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
447 if (type == PROTOCOLID_ROCE) {
448 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
449 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
450 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
451 u32 align = elems_per_page * DQ_RANGE_ALIGN;
453 p_conn->cid_count = roundup(p_conn->cid_count, align);
457 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
458 enum protocol_type type, u32 *vf_cid)
461 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
463 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
466 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
467 enum protocol_type type)
469 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
472 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
473 enum protocol_type type)
478 for (i = 0; i < TASK_SEGMENTS; i++)
479 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
484 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
485 enum protocol_type proto,
487 u8 seg_type, u32 count, bool has_fl)
489 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
490 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
492 p_seg->count = count;
493 p_seg->has_fl_mem = has_fl;
494 p_seg->type = seg_type;
497 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
498 struct qed_ilt_cli_blk *p_blk,
499 u32 start_line, u32 total_size, u32 elem_size)
501 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
503 /* verify thatits called only once for each block */
504 if (p_blk->total_size)
507 p_blk->total_size = total_size;
508 p_blk->real_size_in_page = 0;
510 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
511 p_blk->start_line = start_line;
514 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
515 struct qed_ilt_client_cfg *p_cli,
516 struct qed_ilt_cli_blk *p_blk,
517 u32 *p_line, enum ilt_clients client_id)
519 if (!p_blk->total_size)
523 p_cli->first.val = *p_line;
525 p_cli->active = true;
526 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
527 p_cli->last.val = *p_line - 1;
529 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
530 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
531 client_id, p_cli->first.val,
532 p_cli->last.val, p_blk->total_size,
533 p_blk->real_size_in_page, p_blk->start_line);
536 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
537 enum ilt_clients ilt_client)
539 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
540 struct qed_ilt_client_cfg *p_cli;
541 u32 lines_to_skip = 0;
544 if (ilt_client == ILT_CLI_CDUC) {
545 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
547 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
548 (u32) CONN_CXT_SIZE(p_hwfn);
550 lines_to_skip = cid_count / cxts_per_p;
553 return lines_to_skip;
556 static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg
559 p_cli->active = false;
560 p_cli->first.val = 0;
565 static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk)
567 p_blk->total_size = 0;
571 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count)
573 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
574 u32 curr_line, total, i, task_size, line;
575 struct qed_ilt_client_cfg *p_cli;
576 struct qed_ilt_cli_blk *p_blk;
577 struct qed_cdu_iids cdu_iids;
578 struct qed_src_iids src_iids;
579 struct qed_qm_iids qm_iids;
580 struct qed_tm_iids tm_iids;
581 struct qed_tid_seg *p_seg;
583 memset(&qm_iids, 0, sizeof(qm_iids));
584 memset(&cdu_iids, 0, sizeof(cdu_iids));
585 memset(&src_iids, 0, sizeof(src_iids));
586 memset(&tm_iids, 0, sizeof(tm_iids));
588 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
590 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
591 "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
592 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
595 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]);
597 curr_line = p_mngr->pf_start_line;
600 p_cli->pf_total_lines = 0;
602 /* get the counters for the CDUC and QM clients */
603 qed_cxt_cdu_iids(p_mngr, &cdu_iids);
605 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]);
607 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
609 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
610 total, CONN_CXT_SIZE(p_hwfn));
612 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
613 p_cli->pf_total_lines = curr_line - p_blk->start_line;
615 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
619 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]);
620 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
622 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
623 total, CONN_CXT_SIZE(p_hwfn));
625 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
626 p_cli->vf_total_lines = curr_line - p_blk->start_line;
628 for (i = 1; i < p_mngr->vf_count; i++)
629 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
633 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]);
634 p_cli->first.val = curr_line;
636 /* first the 'working' task memory */
637 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
638 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
639 if (!p_seg || p_seg->count == 0)
642 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]);
643 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
644 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
645 p_mngr->task_type_size[p_seg->type]);
647 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
651 /* next the 'init' task memory (forced load memory) */
652 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
653 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
654 if (!p_seg || p_seg->count == 0)
658 qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]);
660 if (!p_seg->has_fl_mem) {
661 /* The segment is active (total size pf 'working'
662 * memory is > 0) but has no FL (forced-load, Init)
665 * 1. The total-size in the corrsponding FL block of
666 * the ILT client is set to 0 - No ILT line are
667 * provisioned and no ILT memory allocated.
669 * 2. The start-line of said block is set to the
670 * start line of the matching working memory
671 * block in the ILT client. This is later used to
672 * configure the CDU segment offset registers and
673 * results in an FL command for TIDs of this
674 * segement behaves as regular load commands
675 * (loading TIDs from the working memory).
677 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
679 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
682 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
684 qed_ilt_cli_blk_fill(p_cli, p_blk,
686 p_mngr->task_type_size[p_seg->type]);
688 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
691 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
694 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
695 if (p_seg && p_seg->count) {
696 /* Stricly speaking we need to iterate over all VF
697 * task segment types, but a VF has only 1 segment
700 /* 'working' memory */
701 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
703 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]);
704 qed_ilt_cli_blk_fill(p_cli, p_blk,
706 p_mngr->task_type_size[p_seg->type]);
708 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
713 qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]);
714 if (!p_seg->has_fl_mem) {
715 /* see comment above */
716 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
717 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
719 task_size = p_mngr->task_type_size[p_seg->type];
720 qed_ilt_cli_blk_fill(p_cli, p_blk,
721 curr_line, total, task_size);
722 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
725 p_cli->vf_total_lines = curr_line -
726 p_cli->vf_blks[0].start_line;
728 /* Now for the rest of the VFs */
729 for (i = 1; i < p_mngr->vf_count; i++) {
730 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
731 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
734 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
735 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
741 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]);
742 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
744 qed_cxt_qm_iids(p_hwfn, &qm_iids);
745 total = qed_qm_pf_mem_size(qm_iids.cids,
746 qm_iids.vf_cids, qm_iids.tids,
747 p_hwfn->qm_info.num_pqs,
748 p_hwfn->qm_info.num_vf_pqs);
752 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
756 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
758 qed_ilt_cli_blk_fill(p_cli, p_blk,
759 curr_line, total * 0x1000,
762 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
763 p_cli->pf_total_lines = curr_line - p_blk->start_line;
766 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]);
767 qed_cxt_src_iids(p_mngr, &src_iids);
769 /* Both the PF and VFs searcher connections are stored in the per PF
770 * database. Thus sum the PF searcher cids and all the VFs searcher
773 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
775 u32 local_max = max_t(u32, total,
778 total = roundup_pow_of_two(local_max);
780 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
781 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
782 total * sizeof(struct src_ent),
783 sizeof(struct src_ent));
785 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
787 p_cli->pf_total_lines = curr_line - p_blk->start_line;
791 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]);
792 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
793 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
795 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
796 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
797 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
799 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
801 p_cli->pf_total_lines = curr_line - p_blk->start_line;
805 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
807 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]);
808 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
809 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
811 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
814 p_cli->vf_total_lines = curr_line - p_blk->start_line;
815 for (i = 1; i < p_mngr->vf_count; i++)
816 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
820 /* TSDM (SRQ CONTEXT) */
821 total = qed_cxt_get_srq_count(p_hwfn);
824 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]);
825 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]);
826 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
827 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
829 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
831 p_cli->pf_total_lines = curr_line - p_blk->start_line;
834 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line;
836 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
837 RESC_NUM(p_hwfn, QED_ILT))
843 u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines)
845 struct qed_ilt_client_cfg *p_cli;
846 u32 excess_lines, available_lines;
847 struct qed_cxt_mngr *p_mngr;
848 u32 ilt_page_size, elem_size;
849 struct qed_tid_seg *p_seg;
852 available_lines = RESC_NUM(p_hwfn, QED_ILT);
853 excess_lines = used_lines - available_lines;
858 if (!QED_IS_RDMA_PERSONALITY(p_hwfn))
861 p_mngr = p_hwfn->p_cxt_mngr;
862 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
863 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
865 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
866 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
867 if (!p_seg || p_seg->count == 0)
870 elem_size = p_mngr->task_type_size[p_seg->type];
874 return (ilt_page_size / elem_size) * excess_lines;
877 DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n");
881 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
883 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
889 for (i = 0; i < p_mngr->t2_num_pages; i++)
890 if (p_mngr->t2[i].p_virt)
891 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
893 p_mngr->t2[i].p_virt,
894 p_mngr->t2[i].p_phys);
900 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
902 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
903 u32 conn_num, total_size, ent_per_page, psz, i;
904 struct qed_ilt_client_cfg *p_src;
905 struct qed_src_iids src_iids;
906 struct qed_dma_mem *p_t2;
909 memset(&src_iids, 0, sizeof(src_iids));
911 /* if the SRC ILT client is inactive - there are no connection
912 * requiring the searcer, leave.
914 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
918 qed_cxt_src_iids(p_mngr, &src_iids);
919 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
920 total_size = conn_num * sizeof(struct src_ent);
922 /* use the same page size as the SRC ILT client */
923 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
924 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
927 p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
934 /* allocate t2 pages */
935 for (i = 0; i < p_mngr->t2_num_pages; i++) {
936 u32 size = min_t(u32, total_size, psz);
937 void **p_virt = &p_mngr->t2[i].p_virt;
939 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
941 &p_mngr->t2[i].p_phys, GFP_KERNEL);
942 if (!p_mngr->t2[i].p_virt) {
946 memset(*p_virt, 0, size);
947 p_mngr->t2[i].size = size;
951 /* Set the t2 pointers */
953 /* entries per page - must be a power of two */
954 ent_per_page = psz / sizeof(struct src_ent);
956 p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
958 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
959 p_mngr->last_free = (u64) p_t2->p_phys +
960 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
962 for (i = 0; i < p_mngr->t2_num_pages; i++) {
963 u32 ent_num = min_t(u32,
966 struct src_ent *entries = p_mngr->t2[i].p_virt;
967 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
970 for (j = 0; j < ent_num - 1; j++) {
971 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
972 entries[j].next = cpu_to_be64(val);
975 if (i < p_mngr->t2_num_pages - 1)
976 val = (u64) p_mngr->t2[i + 1].p_phys;
979 entries[j].next = cpu_to_be64(val);
987 qed_cxt_src_t2_free(p_hwfn);
991 #define for_each_ilt_valid_client(pos, clients) \
992 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
993 if (!clients[pos].active) { \
997 /* Total number of ILT lines used by this PF */
998 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
1003 for_each_ilt_valid_client(i, ilt_clients)
1004 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
1009 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
1011 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
1012 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1015 ilt_size = qed_cxt_ilt_shadow_size(p_cli);
1017 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
1018 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
1021 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1022 p_dma->size, p_dma->p_virt,
1024 p_dma->p_virt = NULL;
1026 kfree(p_mngr->ilt_shadow);
1029 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
1030 struct qed_ilt_cli_blk *p_blk,
1031 enum ilt_clients ilt_client,
1032 u32 start_line_offset)
1034 struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
1035 u32 lines, line, sz_left, lines_to_skip = 0;
1037 /* Special handling for RoCE that supports dynamic allocation */
1038 if (QED_IS_RDMA_PERSONALITY(p_hwfn) &&
1039 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
1042 lines_to_skip = p_blk->dynamic_line_cnt;
1044 if (!p_blk->total_size)
1047 sz_left = p_blk->total_size;
1048 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
1049 line = p_blk->start_line + start_line_offset -
1050 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
1052 for (; lines; lines--) {
1057 size = min_t(u32, sz_left, p_blk->real_size_in_page);
1058 p_virt = dma_zalloc_coherent(&p_hwfn->cdev->pdev->dev, size,
1059 &p_phys, GFP_KERNEL);
1063 ilt_shadow[line].p_phys = p_phys;
1064 ilt_shadow[line].p_virt = p_virt;
1065 ilt_shadow[line].size = size;
1067 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1068 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
1069 line, (u64)p_phys, p_virt, size);
1078 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
1080 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1081 struct qed_ilt_client_cfg *clients = p_mngr->clients;
1082 struct qed_ilt_cli_blk *p_blk;
1086 size = qed_cxt_ilt_shadow_size(clients);
1087 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
1089 if (!p_mngr->ilt_shadow) {
1091 goto ilt_shadow_fail;
1094 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1095 "Allocated 0x%x bytes for ilt shadow\n",
1096 (u32)(size * sizeof(struct qed_dma_mem)));
1098 for_each_ilt_valid_client(i, clients) {
1099 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1100 p_blk = &clients[i].pf_blks[j];
1101 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1103 goto ilt_shadow_fail;
1105 for (k = 0; k < p_mngr->vf_count; k++) {
1106 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1107 u32 lines = clients[i].vf_total_lines * k;
1109 p_blk = &clients[i].vf_blks[j];
1110 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
1112 goto ilt_shadow_fail;
1120 qed_ilt_shadow_free(p_hwfn);
1124 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
1126 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1129 for (type = 0; type < MAX_CONN_TYPES; type++) {
1130 kfree(p_mngr->acquired[type].cid_map);
1131 p_mngr->acquired[type].max_count = 0;
1132 p_mngr->acquired[type].start_cid = 0;
1134 for (vf = 0; vf < MAX_NUM_VFS; vf++) {
1135 kfree(p_mngr->acquired_vf[type][vf].cid_map);
1136 p_mngr->acquired_vf[type][vf].max_count = 0;
1137 p_mngr->acquired_vf[type][vf].start_cid = 0;
1143 qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn,
1146 u32 cid_count, struct qed_cid_acquired_map *p_map)
1153 size = DIV_ROUND_UP(cid_count,
1154 sizeof(unsigned long) * BITS_PER_BYTE) *
1155 sizeof(unsigned long);
1156 p_map->cid_map = kzalloc(size, GFP_KERNEL);
1157 if (!p_map->cid_map)
1160 p_map->max_count = cid_count;
1161 p_map->start_cid = cid_start;
1163 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1164 "Type %08x start: %08x count %08x\n",
1165 type, p_map->start_cid, p_map->max_count);
1170 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1172 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1173 u32 start_cid = 0, vf_start_cid = 0;
1176 for (type = 0; type < MAX_CONN_TYPES; type++) {
1177 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1178 struct qed_cid_acquired_map *p_map;
1180 /* Handle PF maps */
1181 p_map = &p_mngr->acquired[type];
1182 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid,
1183 p_cfg->cid_count, p_map))
1186 /* Handle VF maps */
1187 for (vf = 0; vf < MAX_NUM_VFS; vf++) {
1188 p_map = &p_mngr->acquired_vf[type][vf];
1189 if (qed_cid_map_alloc_single(p_hwfn, type,
1191 p_cfg->cids_per_vf, p_map))
1195 start_cid += p_cfg->cid_count;
1196 vf_start_cid += p_cfg->cids_per_vf;
1202 qed_cid_map_free(p_hwfn);
1206 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1208 struct qed_ilt_client_cfg *clients;
1209 struct qed_cxt_mngr *p_mngr;
1212 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1216 /* Initialize ILT client registers */
1217 clients = p_mngr->clients;
1218 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1219 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1220 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1222 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1223 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1224 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1226 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1227 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1228 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1230 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1231 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1232 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1234 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1235 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1236 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1238 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1239 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1240 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1241 /* default ILT page size for all clients is 64K */
1242 for (i = 0; i < ILT_CLI_MAX; i++)
1243 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1245 /* Initialize task sizes */
1246 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1247 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1249 if (p_hwfn->cdev->p_iov_info)
1250 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1251 /* Initialize the dynamic ILT allocation mutex */
1252 mutex_init(&p_mngr->mutex);
1254 /* Set the cxt mangr pointer priori to further allocations */
1255 p_hwfn->p_cxt_mngr = p_mngr;
1260 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1264 /* Allocate the ILT shadow table */
1265 rc = qed_ilt_shadow_alloc(p_hwfn);
1267 goto tables_alloc_fail;
1269 /* Allocate the T2 table */
1270 rc = qed_cxt_src_t2_alloc(p_hwfn);
1272 goto tables_alloc_fail;
1274 /* Allocate and initialize the acquired cids bitmaps */
1275 rc = qed_cid_map_alloc(p_hwfn);
1277 goto tables_alloc_fail;
1282 qed_cxt_mngr_free(p_hwfn);
1286 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1288 if (!p_hwfn->p_cxt_mngr)
1291 qed_cid_map_free(p_hwfn);
1292 qed_cxt_src_t2_free(p_hwfn);
1293 qed_ilt_shadow_free(p_hwfn);
1294 kfree(p_hwfn->p_cxt_mngr);
1296 p_hwfn->p_cxt_mngr = NULL;
1299 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1301 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1302 struct qed_cid_acquired_map *p_map;
1303 struct qed_conn_type_cfg *p_cfg;
1307 /* Reset acquired cids */
1308 for (type = 0; type < MAX_CONN_TYPES; type++) {
1311 p_cfg = &p_mngr->conn_cfg[type];
1312 if (p_cfg->cid_count) {
1313 p_map = &p_mngr->acquired[type];
1314 len = DIV_ROUND_UP(p_map->max_count,
1315 sizeof(unsigned long) *
1317 sizeof(unsigned long);
1318 memset(p_map->cid_map, 0, len);
1321 if (!p_cfg->cids_per_vf)
1324 for (vf = 0; vf < MAX_NUM_VFS; vf++) {
1325 p_map = &p_mngr->acquired_vf[type][vf];
1326 len = DIV_ROUND_UP(p_map->max_count,
1327 sizeof(unsigned long) *
1329 sizeof(unsigned long);
1330 memset(p_map->cid_map, 0, len);
1336 #define CDUC_CXT_SIZE_SHIFT \
1337 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1339 #define CDUC_CXT_SIZE_MASK \
1340 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1342 #define CDUC_BLOCK_WASTE_SHIFT \
1343 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1345 #define CDUC_BLOCK_WASTE_MASK \
1346 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1348 #define CDUC_NCIB_SHIFT \
1349 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1351 #define CDUC_NCIB_MASK \
1352 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1354 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1355 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1357 #define CDUT_TYPE0_CXT_SIZE_MASK \
1358 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1359 CDUT_TYPE0_CXT_SIZE_SHIFT)
1361 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1362 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1364 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1365 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1366 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1368 #define CDUT_TYPE0_NCIB_SHIFT \
1369 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1371 #define CDUT_TYPE0_NCIB_MASK \
1372 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1373 CDUT_TYPE0_NCIB_SHIFT)
1375 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1376 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1378 #define CDUT_TYPE1_CXT_SIZE_MASK \
1379 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1380 CDUT_TYPE1_CXT_SIZE_SHIFT)
1382 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1383 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1385 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1386 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1387 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1389 #define CDUT_TYPE1_NCIB_SHIFT \
1390 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1392 #define CDUT_TYPE1_NCIB_MASK \
1393 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1394 CDUT_TYPE1_NCIB_SHIFT)
1396 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1398 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1400 /* CDUC - connection configuration */
1401 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1402 cxt_size = CONN_CXT_SIZE(p_hwfn);
1403 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1404 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1406 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1407 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1408 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1409 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1411 /* CDUT - type-0 tasks configuration */
1412 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1413 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1414 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1415 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1417 /* cxt size and block-waste are multipes of 8 */
1419 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1420 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1421 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1422 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1424 /* CDUT - type-1 tasks configuration */
1425 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1426 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1427 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1429 /* cxt size and block-waste are multipes of 8 */
1431 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1432 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1433 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1434 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1438 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1439 #define CDU_SEG_REG_TYPE_MASK 0x1
1440 #define CDU_SEG_REG_OFFSET_SHIFT 0
1441 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1443 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1445 struct qed_ilt_client_cfg *p_cli;
1446 struct qed_tid_seg *p_seg;
1447 u32 cdu_seg_params, offset;
1450 static const u32 rt_type_offset_arr[] = {
1451 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1452 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1453 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1454 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1457 static const u32 rt_type_offset_fl_arr[] = {
1458 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1459 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1460 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1461 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1464 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1466 /* There are initializations only for CDUT during pf Phase */
1467 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1469 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1473 /* Note: start_line is already adjusted for the CDU
1474 * segment register granularity, so we just need to
1475 * divide. Adjustment is implicit as we assume ILT
1476 * Page size is larger than 32K!
1478 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1479 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1480 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1483 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1484 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1485 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1487 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1488 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1489 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1492 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1493 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1494 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1498 void qed_qm_init_pf(struct qed_hwfn *p_hwfn,
1499 struct qed_ptt *p_ptt, bool is_pf_loading)
1501 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1502 struct qed_qm_pf_rt_init_params params;
1503 struct qed_mcp_link_state *p_link;
1504 struct qed_qm_iids iids;
1506 memset(&iids, 0, sizeof(iids));
1507 qed_cxt_qm_iids(p_hwfn, &iids);
1509 p_link = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output;
1511 memset(¶ms, 0, sizeof(params));
1512 params.port_id = p_hwfn->port_id;
1513 params.pf_id = p_hwfn->rel_pf_id;
1514 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1515 params.is_pf_loading = is_pf_loading;
1516 params.num_pf_cids = iids.cids;
1517 params.num_vf_cids = iids.vf_cids;
1518 params.num_tids = iids.tids;
1519 params.start_pq = qm_info->start_pq;
1520 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1521 params.num_vf_pqs = qm_info->num_vf_pqs;
1522 params.start_vport = qm_info->start_vport;
1523 params.num_vports = qm_info->num_vports;
1524 params.pf_wfq = qm_info->pf_wfq;
1525 params.pf_rl = qm_info->pf_rl;
1526 params.link_speed = p_link->speed;
1527 params.pq_params = qm_info->qm_pq_params;
1528 params.vport_params = qm_info->qm_vport_params;
1530 qed_qm_pf_rt_init(p_hwfn, p_ptt, ¶ms);
1534 void qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1536 /* XCM pure-LB queue */
1537 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1538 qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1542 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1544 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1545 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1547 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1548 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1550 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1551 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1553 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1554 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1556 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1557 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1559 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1560 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1562 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1563 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1565 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1566 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1568 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1569 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1571 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1572 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1574 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1575 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1577 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1578 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1580 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1581 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1583 /* Connection types 6 & 7 are not in use, yet they must be configured
1584 * as the highest possible connection. Not configuring them means the
1585 * defaults will be used, and with a large number of cids a bug may
1586 * occur, if the defaults will be smaller than dq_pf_max_cid /
1589 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1590 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1592 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1593 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1596 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1598 struct qed_ilt_client_cfg *ilt_clients;
1601 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1602 for_each_ilt_valid_client(i, ilt_clients) {
1603 STORE_RT_REG(p_hwfn,
1604 ilt_clients[i].first.reg,
1605 ilt_clients[i].first.val);
1606 STORE_RT_REG(p_hwfn,
1607 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1608 STORE_RT_REG(p_hwfn,
1609 ilt_clients[i].p_size.reg,
1610 ilt_clients[i].p_size.val);
1614 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1616 struct qed_ilt_client_cfg *p_cli;
1619 /* For simplicty we set the 'block' to be an ILT page */
1620 if (p_hwfn->cdev->p_iov_info) {
1621 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1623 STORE_RT_REG(p_hwfn,
1624 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1625 p_iov->first_vf_in_pf);
1626 STORE_RT_REG(p_hwfn,
1627 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1628 p_iov->first_vf_in_pf + p_iov->total_vfs);
1631 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1632 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1633 if (p_cli->active) {
1634 STORE_RT_REG(p_hwfn,
1635 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1637 STORE_RT_REG(p_hwfn,
1638 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1639 p_cli->pf_total_lines);
1640 STORE_RT_REG(p_hwfn,
1641 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1642 p_cli->vf_total_lines);
1645 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1646 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1647 if (p_cli->active) {
1648 STORE_RT_REG(p_hwfn,
1649 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1651 STORE_RT_REG(p_hwfn,
1652 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1653 p_cli->pf_total_lines);
1654 STORE_RT_REG(p_hwfn,
1655 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1656 p_cli->vf_total_lines);
1659 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1660 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1661 if (p_cli->active) {
1662 STORE_RT_REG(p_hwfn,
1663 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1664 STORE_RT_REG(p_hwfn,
1665 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1666 p_cli->pf_total_lines);
1667 STORE_RT_REG(p_hwfn,
1668 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1669 p_cli->vf_total_lines);
1673 /* ILT (PSWRQ2) PF */
1674 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1676 struct qed_ilt_client_cfg *clients;
1677 struct qed_cxt_mngr *p_mngr;
1678 struct qed_dma_mem *p_shdw;
1679 u32 line, rt_offst, i;
1681 qed_ilt_bounds_init(p_hwfn);
1682 qed_ilt_vf_bounds_init(p_hwfn);
1684 p_mngr = p_hwfn->p_cxt_mngr;
1685 p_shdw = p_mngr->ilt_shadow;
1686 clients = p_hwfn->p_cxt_mngr->clients;
1688 for_each_ilt_valid_client(i, clients) {
1689 /** Client's 1st val and RT array are absolute, ILT shadows'
1690 * lines are relative.
1692 line = clients[i].first.val - p_mngr->pf_start_line;
1693 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1694 clients[i].first.val * ILT_ENTRY_IN_REGS;
1696 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1697 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1698 u64 ilt_hw_entry = 0;
1700 /** p_virt could be NULL incase of dynamic
1703 if (p_shdw[line].p_virt) {
1704 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1705 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1706 (p_shdw[line].p_phys >> 12));
1708 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1709 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1711 (u64)(p_shdw[line].p_phys >> 12));
1714 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1719 /* SRC (Searcher) PF */
1720 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1722 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1723 u32 rounded_conn_num, conn_num, conn_max;
1724 struct qed_src_iids src_iids;
1726 memset(&src_iids, 0, sizeof(src_iids));
1727 qed_cxt_src_iids(p_mngr, &src_iids);
1728 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1732 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1733 rounded_conn_num = roundup_pow_of_two(conn_max);
1735 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1736 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1737 ilog2(rounded_conn_num));
1739 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1740 p_hwfn->p_cxt_mngr->first_free);
1741 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1742 p_hwfn->p_cxt_mngr->last_free);
1746 #define TM_CFG_NUM_IDS_SHIFT 0
1747 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1748 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1749 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1750 #define TM_CFG_PARENT_PF_SHIFT 25
1751 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1753 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1754 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1756 #define TM_CFG_TID_OFFSET_SHIFT 30
1757 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1758 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1759 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1761 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1763 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1764 u32 active_seg_mask = 0, tm_offset, rt_reg;
1765 struct qed_tm_iids tm_iids;
1769 memset(&tm_iids, 0, sizeof(tm_iids));
1770 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
1772 /* @@@TBD No pre-scan for now */
1774 /* Note: We assume consecutive VFs for a PF */
1775 for (i = 0; i < p_mngr->vf_count; i++) {
1777 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1778 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1779 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1780 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1781 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1782 (sizeof(cfg_word) / sizeof(u32)) *
1783 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1784 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1788 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1789 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1790 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1791 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1793 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1794 (sizeof(cfg_word) / sizeof(u32)) *
1795 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1796 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1799 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1800 tm_iids.pf_cids ? 0x1 : 0x0);
1802 /* @@@TBD how to enable the scan for the VFs */
1804 tm_offset = tm_iids.per_vf_cids;
1806 /* Note: We assume consecutive VFs for a PF */
1807 for (i = 0; i < p_mngr->vf_count; i++) {
1809 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1810 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1811 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1812 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1813 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1815 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1816 (sizeof(cfg_word) / sizeof(u32)) *
1817 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1819 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1822 tm_offset = tm_iids.pf_cids;
1823 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1825 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1826 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1827 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1828 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1829 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1831 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1832 (sizeof(cfg_word) / sizeof(u32)) *
1833 (NUM_OF_VFS(p_hwfn->cdev) +
1834 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1836 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1837 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1839 tm_offset += tm_iids.pf_tids[i];
1842 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
1843 active_seg_mask = 0;
1845 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1847 /* @@@TBD how to enable the scan for the VFs */
1850 static void qed_prs_init_common(struct qed_hwfn *p_hwfn)
1852 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) &&
1853 p_hwfn->pf_params.fcoe_pf_params.is_target)
1854 STORE_RT_REG(p_hwfn,
1855 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
1858 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn)
1860 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1861 struct qed_conn_type_cfg *p_fcoe;
1862 struct qed_tid_seg *p_tid;
1864 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1866 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1867 if (!p_fcoe->cid_count)
1870 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG];
1871 if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
1872 STORE_RT_REG_AGG(p_hwfn,
1873 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
1876 STORE_RT_REG_AGG(p_hwfn,
1877 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1882 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1884 qed_cdu_init_common(p_hwfn);
1885 qed_prs_init_common(p_hwfn);
1888 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1890 qed_qm_init_pf(p_hwfn, p_ptt, true);
1891 qed_cm_init_pf(p_hwfn);
1892 qed_dq_init_pf(p_hwfn);
1893 qed_cdu_init_pf(p_hwfn);
1894 qed_ilt_init_pf(p_hwfn);
1895 qed_src_init_pf(p_hwfn);
1896 qed_tm_init_pf(p_hwfn);
1897 qed_prs_init_pf(p_hwfn);
1900 int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1901 enum protocol_type type, u32 *p_cid, u8 vfid)
1903 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1904 struct qed_cid_acquired_map *p_map;
1907 if (type >= MAX_CONN_TYPES) {
1908 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1912 if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) {
1913 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid);
1917 /* Determine the right map to take this CID from */
1918 if (vfid == QED_CXT_PF_CID)
1919 p_map = &p_mngr->acquired[type];
1921 p_map = &p_mngr->acquired_vf[type][vfid];
1923 if (!p_map->cid_map) {
1924 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1928 rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count);
1930 if (rel_cid >= p_map->max_count) {
1931 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1935 __set_bit(rel_cid, p_map->cid_map);
1937 *p_cid = rel_cid + p_map->start_cid;
1939 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1940 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1941 *p_cid, rel_cid, vfid, type);
1946 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1947 enum protocol_type type, u32 *p_cid)
1949 return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID);
1952 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1955 enum protocol_type *p_type,
1956 struct qed_cid_acquired_map **pp_map)
1958 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1961 /* Iterate over protocols and find matching cid range */
1962 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1963 if (vfid == QED_CXT_PF_CID)
1964 *pp_map = &p_mngr->acquired[*p_type];
1966 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1968 if (!((*pp_map)->cid_map))
1970 if (cid >= (*pp_map)->start_cid &&
1971 cid < (*pp_map)->start_cid + (*pp_map)->max_count)
1975 if (*p_type == MAX_CONN_TYPES) {
1976 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid);
1980 rel_cid = cid - (*pp_map)->start_cid;
1981 if (!test_bit(rel_cid, (*pp_map)->cid_map)) {
1982 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired",
1989 *p_type = MAX_CONN_TYPES;
1994 void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid)
1996 struct qed_cid_acquired_map *p_map = NULL;
1997 enum protocol_type type;
2001 if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) {
2003 "Trying to return incorrect CID belonging to VF %02x\n",
2008 /* Test acquired and find matching per-protocol map */
2009 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid,
2015 rel_cid = cid - p_map->start_cid;
2016 clear_bit(rel_cid, p_map->cid_map);
2018 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
2019 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
2020 cid, rel_cid, vfid, type);
2023 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
2025 _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID);
2028 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
2030 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2031 struct qed_cid_acquired_map *p_map = NULL;
2032 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
2033 enum protocol_type type;
2036 /* Test acquired and find matching per-protocol map */
2037 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid,
2038 QED_CXT_PF_CID, &type, &p_map);
2043 /* set the protocl type */
2044 p_info->type = type;
2046 /* compute context virtual pointer */
2047 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
2049 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
2050 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
2051 line = p_info->iid / cxts_per_p;
2053 /* Make sure context is allocated (dynamic allocation) */
2054 if (!p_mngr->ilt_shadow[line].p_virt)
2057 p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
2058 p_info->iid % cxts_per_p * conn_cxt_size;
2060 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
2061 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
2062 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
2067 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
2068 struct qed_rdma_pf_params *p_params,
2071 u32 num_cons, num_qps, num_srqs;
2072 enum protocol_type proto;
2074 num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
2076 if (p_hwfn->mcp_info->func_info.protocol == QED_PCI_ETH_RDMA) {
2078 "Current day drivers don't support RoCE & iWARP simultaneously on the same PF. Default to RoCE-only\n");
2079 p_hwfn->hw_info.personality = QED_PCI_ETH_ROCE;
2082 switch (p_hwfn->hw_info.personality) {
2083 case QED_PCI_ETH_IWARP:
2084 /* Each QP requires one connection */
2085 num_cons = min_t(u32, IWARP_MAX_QPS, p_params->num_qps);
2086 proto = PROTOCOLID_IWARP;
2088 case QED_PCI_ETH_ROCE:
2089 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
2090 num_cons = num_qps * 2; /* each QP requires two connections */
2091 proto = PROTOCOLID_ROCE;
2097 if (num_cons && num_tasks) {
2098 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
2100 /* Deliberatly passing ROCE for tasks id. This is because
2101 * iWARP / RoCE share the task id.
2103 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
2104 QED_CXT_ROCE_TID_SEG, 1,
2106 qed_cxt_set_srq_count(p_hwfn, num_srqs);
2108 DP_INFO(p_hwfn->cdev,
2109 "RDMA personality used without setting params!\n");
2113 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks)
2115 /* Set the number of required CORE connections */
2116 u32 core_cids = 1; /* SPQ */
2118 if (p_hwfn->using_ll2)
2120 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
2122 switch (p_hwfn->hw_info.personality) {
2123 case QED_PCI_ETH_RDMA:
2124 case QED_PCI_ETH_IWARP:
2125 case QED_PCI_ETH_ROCE:
2127 qed_rdma_set_pf_params(p_hwfn,
2129 pf_params.rdma_pf_params,
2131 /* no need for break since RoCE coexist with Ethernet */
2135 struct qed_eth_pf_params *p_params =
2136 &p_hwfn->pf_params.eth_pf_params;
2138 if (!p_params->num_vf_cons)
2139 p_params->num_vf_cons =
2140 ETH_PF_PARAMS_VF_CONS_DEFAULT;
2141 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2143 p_params->num_vf_cons);
2144 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2149 struct qed_fcoe_pf_params *p_params;
2151 p_params = &p_hwfn->pf_params.fcoe_pf_params;
2153 if (p_params->num_cons && p_params->num_tasks) {
2154 qed_cxt_set_proto_cid_count(p_hwfn,
2159 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
2160 QED_CXT_FCOE_TID_SEG, 0,
2161 p_params->num_tasks, true);
2163 DP_INFO(p_hwfn->cdev,
2164 "Fcoe personality used without setting params!\n");
2170 struct qed_iscsi_pf_params *p_params;
2172 p_params = &p_hwfn->pf_params.iscsi_pf_params;
2174 if (p_params->num_cons && p_params->num_tasks) {
2175 qed_cxt_set_proto_cid_count(p_hwfn,
2180 qed_cxt_set_proto_tid_count(p_hwfn,
2182 QED_CXT_ISCSI_TID_SEG,
2184 p_params->num_tasks,
2187 DP_INFO(p_hwfn->cdev,
2188 "Iscsi personality used without setting params!\n");
2199 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
2200 struct qed_tid_mem *p_info)
2202 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2203 u32 proto, seg, total_lines, i, shadow_line;
2204 struct qed_ilt_client_cfg *p_cli;
2205 struct qed_ilt_cli_blk *p_fl_seg;
2206 struct qed_tid_seg *p_seg_info;
2208 /* Verify the personality */
2209 switch (p_hwfn->hw_info.personality) {
2211 proto = PROTOCOLID_FCOE;
2212 seg = QED_CXT_FCOE_TID_SEG;
2215 proto = PROTOCOLID_ISCSI;
2216 seg = QED_CXT_ISCSI_TID_SEG;
2222 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2226 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2227 if (!p_seg_info->has_fl_mem)
2230 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2231 total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2232 p_fl_seg->real_size_in_page);
2234 for (i = 0; i < total_lines; i++) {
2235 shadow_line = i + p_fl_seg->start_line -
2236 p_hwfn->p_cxt_mngr->pf_start_line;
2237 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2239 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2240 p_fl_seg->real_size_in_page;
2241 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2242 p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2248 /* This function is very RoCE oriented, if another protocol in the future
2249 * will want this feature we'll need to modify the function to be more generic
2252 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
2253 enum qed_cxt_elem_type elem_type, u32 iid)
2255 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2256 struct qed_ilt_client_cfg *p_cli;
2257 struct qed_ilt_cli_blk *p_blk;
2258 struct qed_ptt *p_ptt;
2264 switch (elem_type) {
2266 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2267 elem_size = CONN_CXT_SIZE(p_hwfn);
2268 p_blk = &p_cli->pf_blks[CDUC_BLK];
2271 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2272 elem_size = SRQ_CXT_SIZE;
2273 p_blk = &p_cli->pf_blks[SRQ_BLK];
2276 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2277 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2278 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2281 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2285 /* Calculate line in ilt */
2286 hw_p_size = p_cli->p_size.val;
2287 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2288 line = p_blk->start_line + (iid / elems_per_p);
2289 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2291 /* If line is already allocated, do nothing, otherwise allocate it and
2292 * write it to the PSWRQ2 registers.
2293 * This section can be run in parallel from different contexts and thus
2294 * a mutex protection is needed.
2297 mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
2299 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2302 p_ptt = qed_ptt_acquire(p_hwfn);
2305 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2310 p_virt = dma_zalloc_coherent(&p_hwfn->cdev->pdev->dev,
2311 p_blk->real_size_in_page, &p_phys,
2318 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2319 * to compensate for a HW bug, but it is configured even if DIF is not
2320 * enabled. This is harmless and allows us to avoid a dedicated API. We
2321 * configure the field for all of the contexts on the newly allocated
2324 if (elem_type == QED_ELEM_TASK) {
2326 u8 *elem_start = (u8 *)p_virt;
2327 union type1_task_context *elem;
2329 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2330 elem = (union type1_task_context *)elem_start;
2331 SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2332 TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);
2333 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2337 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2338 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2339 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2340 p_blk->real_size_in_page;
2342 /* compute absolute offset */
2343 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2344 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2347 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2348 SET_FIELD(ilt_hw_entry,
2350 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2352 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2353 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2354 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2356 if (elem_type == QED_ELEM_CXT) {
2357 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2360 /* Update the relevant register in the parser */
2361 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2362 last_cid_allocated - 1);
2364 if (!p_hwfn->b_rdma_enabled_in_prs) {
2365 /* Enable RDMA search */
2366 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2367 p_hwfn->b_rdma_enabled_in_prs = true;
2372 qed_ptt_release(p_hwfn, p_ptt);
2374 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2379 /* This function is very RoCE oriented, if another protocol in the future
2380 * will want this feature we'll need to modify the function to be more generic
2383 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2384 enum qed_cxt_elem_type elem_type,
2385 u32 start_iid, u32 count)
2387 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2388 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2389 struct qed_ilt_client_cfg *p_cli;
2390 struct qed_ilt_cli_blk *p_blk;
2391 u32 end_iid = start_iid + count;
2392 struct qed_ptt *p_ptt;
2393 u64 ilt_hw_entry = 0;
2396 switch (elem_type) {
2398 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2399 elem_size = CONN_CXT_SIZE(p_hwfn);
2400 p_blk = &p_cli->pf_blks[CDUC_BLK];
2403 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2404 elem_size = SRQ_CXT_SIZE;
2405 p_blk = &p_cli->pf_blks[SRQ_BLK];
2408 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2409 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2410 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2413 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2417 /* Calculate line in ilt */
2418 hw_p_size = p_cli->p_size.val;
2419 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2420 start_line = p_blk->start_line + (start_iid / elems_per_p);
2421 end_line = p_blk->start_line + (end_iid / elems_per_p);
2422 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2425 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2426 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2428 p_ptt = qed_ptt_acquire(p_hwfn);
2431 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2435 for (i = shadow_start_line; i < shadow_end_line; i++) {
2436 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2439 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2440 p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2441 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2442 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2444 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2445 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2446 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2448 /* compute absolute offset */
2449 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2450 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2453 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2456 qed_dmae_host2grc(p_hwfn, p_ptt,
2457 (u64) (uintptr_t) &ilt_hw_entry,
2459 sizeof(ilt_hw_entry) / sizeof(u32),
2463 qed_ptt_release(p_hwfn, p_ptt);
2468 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2473 /* Free Connection CXT */
2474 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2475 qed_cxt_get_proto_cid_start(p_hwfn,
2477 qed_cxt_get_proto_cid_count(p_hwfn,
2483 /* Free Task CXT ( Intentionally RoCE as task-id is shared between
2486 proto = PROTOCOLID_ROCE;
2487 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2488 qed_cxt_get_proto_tid_count(p_hwfn, proto));
2493 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2494 qed_cxt_get_srq_count(p_hwfn));
2499 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2500 u32 tid, u8 ctx_type, void **pp_task_ctx)
2502 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2503 struct qed_ilt_client_cfg *p_cli;
2504 struct qed_tid_seg *p_seg_info;
2505 struct qed_ilt_cli_blk *p_seg;
2506 u32 num_tids_per_block;
2507 u32 tid_size, ilt_idx;
2511 /* Verify the personality */
2512 switch (p_hwfn->hw_info.personality) {
2514 proto = PROTOCOLID_FCOE;
2515 seg = QED_CXT_FCOE_TID_SEG;
2518 proto = PROTOCOLID_ISCSI;
2519 seg = QED_CXT_ISCSI_TID_SEG;
2525 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2529 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2531 if (ctx_type == QED_CTX_WORKING_MEM) {
2532 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2533 } else if (ctx_type == QED_CTX_FL_MEM) {
2534 if (!p_seg_info->has_fl_mem)
2536 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2540 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2541 tid_size = p_mngr->task_type_size[p_seg_info->type];
2542 num_tids_per_block = p_seg->real_size_in_page / tid_size;
2544 if (total_lines < tid / num_tids_per_block)
2547 ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2548 p_mngr->pf_start_line;
2549 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2550 (tid % num_tids_per_block) * tid_size;