1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
5 #include <linux/ipv6.h>
6 #include <linux/if_vlan.h>
7 #include <net/ip6_checksum.h>
10 #include "ionic_lif.h"
11 #include "ionic_txrx.h"
13 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell,
14 ionic_desc_cb cb_func, void *cb_arg)
16 ionic_q_post(q, ring_dbell, cb_func, cb_arg);
19 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell,
20 ionic_desc_cb cb_func, void *cb_arg)
22 ionic_q_post(q, ring_dbell, cb_func, cb_arg);
25 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q)
27 return netdev_get_tx_queue(q->lif->netdev, q->index);
30 static int ionic_rx_page_alloc(struct ionic_queue *q,
31 struct ionic_buf_info *buf_info)
33 struct net_device *netdev = q->lif->netdev;
34 struct ionic_rx_stats *stats;
39 stats = q_to_rx_stats(q);
41 if (unlikely(!buf_info)) {
42 net_err_ratelimited("%s: %s invalid buf_info in alloc\n",
43 netdev->name, q->name);
47 page = alloc_pages(IONIC_PAGE_GFP_MASK, 0);
48 if (unlikely(!page)) {
49 net_err_ratelimited("%s: %s page alloc failed\n",
50 netdev->name, q->name);
55 buf_info->dma_addr = dma_map_page(dev, page, 0,
56 IONIC_PAGE_SIZE, DMA_FROM_DEVICE);
57 if (unlikely(dma_mapping_error(dev, buf_info->dma_addr))) {
58 __free_pages(page, 0);
59 net_err_ratelimited("%s: %s dma map failed\n",
60 netdev->name, q->name);
65 buf_info->page = page;
66 buf_info->page_offset = 0;
71 static void ionic_rx_page_free(struct ionic_queue *q,
72 struct ionic_buf_info *buf_info)
74 struct net_device *netdev = q->lif->netdev;
75 struct device *dev = q->dev;
77 if (unlikely(!buf_info)) {
78 net_err_ratelimited("%s: %s invalid buf_info in free\n",
79 netdev->name, q->name);
86 dma_unmap_page(dev, buf_info->dma_addr, IONIC_PAGE_SIZE, DMA_FROM_DEVICE);
87 __free_pages(buf_info->page, 0);
88 buf_info->page = NULL;
91 static bool ionic_rx_buf_recycle(struct ionic_queue *q,
92 struct ionic_buf_info *buf_info, u32 used)
96 /* don't re-use pages allocated in low-mem condition */
97 if (page_is_pfmemalloc(buf_info->page))
100 /* don't re-use buffers from non-local numa nodes */
101 if (page_to_nid(buf_info->page) != numa_mem_id())
104 size = ALIGN(used, IONIC_PAGE_SPLIT_SZ);
105 buf_info->page_offset += size;
106 if (buf_info->page_offset >= IONIC_PAGE_SIZE)
109 get_page(buf_info->page);
114 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q,
115 struct ionic_desc_info *desc_info,
116 struct ionic_rxq_comp *comp)
118 struct net_device *netdev = q->lif->netdev;
119 struct ionic_buf_info *buf_info;
120 struct ionic_rx_stats *stats;
121 struct device *dev = q->dev;
127 stats = q_to_rx_stats(q);
129 buf_info = &desc_info->bufs[0];
130 len = le16_to_cpu(comp->len);
132 prefetchw(buf_info->page);
134 skb = napi_get_frags(&q_to_qcq(q)->napi);
135 if (unlikely(!skb)) {
136 net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
137 netdev->name, q->name);
142 i = comp->num_sg_elems + 1;
144 if (unlikely(!buf_info->page)) {
149 frag_len = min_t(u16, len, IONIC_PAGE_SIZE - buf_info->page_offset);
152 dma_sync_single_for_cpu(dev,
153 buf_info->dma_addr + buf_info->page_offset,
154 frag_len, DMA_FROM_DEVICE);
156 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
157 buf_info->page, buf_info->page_offset, frag_len,
160 if (!ionic_rx_buf_recycle(q, buf_info, frag_len)) {
161 dma_unmap_page(dev, buf_info->dma_addr,
162 IONIC_PAGE_SIZE, DMA_FROM_DEVICE);
163 buf_info->page = NULL;
174 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q,
175 struct ionic_desc_info *desc_info,
176 struct ionic_rxq_comp *comp)
178 struct net_device *netdev = q->lif->netdev;
179 struct ionic_buf_info *buf_info;
180 struct ionic_rx_stats *stats;
181 struct device *dev = q->dev;
185 stats = q_to_rx_stats(q);
187 buf_info = &desc_info->bufs[0];
188 len = le16_to_cpu(comp->len);
190 skb = napi_alloc_skb(&q_to_qcq(q)->napi, len);
191 if (unlikely(!skb)) {
192 net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
193 netdev->name, q->name);
198 if (unlikely(!buf_info->page)) {
203 dma_sync_single_for_cpu(dev, buf_info->dma_addr + buf_info->page_offset,
204 len, DMA_FROM_DEVICE);
205 skb_copy_to_linear_data(skb, page_address(buf_info->page) + buf_info->page_offset, len);
206 dma_sync_single_for_device(dev, buf_info->dma_addr + buf_info->page_offset,
207 len, DMA_FROM_DEVICE);
210 skb->protocol = eth_type_trans(skb, q->lif->netdev);
215 static void ionic_rx_clean(struct ionic_queue *q,
216 struct ionic_desc_info *desc_info,
217 struct ionic_cq_info *cq_info,
220 struct net_device *netdev = q->lif->netdev;
221 struct ionic_qcq *qcq = q_to_qcq(q);
222 struct ionic_rx_stats *stats;
223 struct ionic_rxq_comp *comp;
226 comp = cq_info->cq_desc + qcq->cq.desc_size - sizeof(*comp);
228 stats = q_to_rx_stats(q);
236 stats->bytes += le16_to_cpu(comp->len);
238 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak)
239 skb = ionic_rx_copybreak(q, desc_info, comp);
241 skb = ionic_rx_frags(q, desc_info, comp);
243 if (unlikely(!skb)) {
248 skb_record_rx_queue(skb, q->index);
250 if (likely(netdev->features & NETIF_F_RXHASH)) {
251 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
252 case IONIC_PKT_TYPE_IPV4:
253 case IONIC_PKT_TYPE_IPV6:
254 skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
257 case IONIC_PKT_TYPE_IPV4_TCP:
258 case IONIC_PKT_TYPE_IPV6_TCP:
259 case IONIC_PKT_TYPE_IPV4_UDP:
260 case IONIC_PKT_TYPE_IPV6_UDP:
261 skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
267 if (likely(netdev->features & NETIF_F_RXCSUM) &&
268 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC)) {
269 skb->ip_summed = CHECKSUM_COMPLETE;
270 skb->csum = (__force __wsum)le16_to_cpu(comp->csum);
271 stats->csum_complete++;
276 if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
277 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) ||
278 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)))
281 if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
282 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) {
283 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
284 le16_to_cpu(comp->vlan_tci));
285 stats->vlan_stripped++;
288 if (unlikely(q->features & IONIC_RXQ_F_HWSTAMP)) {
289 __le64 *cq_desc_hwstamp;
295 sizeof(struct ionic_rxq_comp) -
296 IONIC_HWSTAMP_CQ_NEGOFFSET;
298 hwstamp = le64_to_cpu(*cq_desc_hwstamp);
300 if (hwstamp != IONIC_HWSTAMP_INVALID) {
301 skb_hwtstamps(skb)->hwtstamp = ionic_lif_phc_ktime(q->lif, hwstamp);
302 stats->hwstamp_valid++;
304 stats->hwstamp_invalid++;
308 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak)
309 napi_gro_receive(&qcq->napi, skb);
311 napi_gro_frags(&qcq->napi);
314 bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)
316 struct ionic_queue *q = cq->bound_q;
317 struct ionic_desc_info *desc_info;
318 struct ionic_rxq_comp *comp;
320 comp = cq_info->cq_desc + cq->desc_size - sizeof(*comp);
322 if (!color_match(comp->pkt_type_color, cq->done_color))
325 /* check for empty queue */
326 if (q->tail_idx == q->head_idx)
329 if (q->tail_idx != le16_to_cpu(comp->comp_index))
332 desc_info = &q->info[q->tail_idx];
333 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
335 /* clean the related q entry, only one per qc completion */
336 ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg);
338 desc_info->cb = NULL;
339 desc_info->cb_arg = NULL;
344 void ionic_rx_fill(struct ionic_queue *q)
346 struct net_device *netdev = q->lif->netdev;
347 struct ionic_desc_info *desc_info;
348 struct ionic_rxq_sg_desc *sg_desc;
349 struct ionic_rxq_sg_elem *sg_elem;
350 struct ionic_buf_info *buf_info;
351 struct ionic_rxq_desc *desc;
352 unsigned int remain_len;
353 unsigned int frag_len;
358 len = netdev->mtu + ETH_HLEN + VLAN_HLEN;
360 for (i = ionic_q_space_avail(q); i; i--) {
363 desc_info = &q->info[q->head_idx];
364 desc = desc_info->desc;
365 buf_info = &desc_info->bufs[0];
367 if (!buf_info->page) { /* alloc a new buffer? */
368 if (unlikely(ionic_rx_page_alloc(q, buf_info))) {
375 /* fill main descriptor - buf[0] */
376 desc->addr = cpu_to_le64(buf_info->dma_addr + buf_info->page_offset);
377 frag_len = min_t(u16, len, IONIC_PAGE_SIZE - buf_info->page_offset);
378 desc->len = cpu_to_le16(frag_len);
379 remain_len -= frag_len;
383 /* fill sg descriptors - buf[1..n] */
384 sg_desc = desc_info->sg_desc;
385 for (j = 0; remain_len > 0 && j < q->max_sg_elems; j++) {
386 sg_elem = &sg_desc->elems[j];
387 if (!buf_info->page) { /* alloc a new sg buffer? */
388 if (unlikely(ionic_rx_page_alloc(q, buf_info))) {
395 sg_elem->addr = cpu_to_le64(buf_info->dma_addr + buf_info->page_offset);
396 frag_len = min_t(u16, remain_len, IONIC_PAGE_SIZE - buf_info->page_offset);
397 sg_elem->len = cpu_to_le16(frag_len);
398 remain_len -= frag_len;
403 /* clear end sg element as a sentinel */
404 if (j < q->max_sg_elems) {
405 sg_elem = &sg_desc->elems[j];
406 memset(sg_elem, 0, sizeof(*sg_elem));
409 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
410 IONIC_RXQ_DESC_OPCODE_SIMPLE;
411 desc_info->nbufs = nfrags;
413 ionic_rxq_post(q, false, ionic_rx_clean, NULL);
416 ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type,
417 q->dbval | q->head_idx);
420 void ionic_rx_empty(struct ionic_queue *q)
422 struct ionic_desc_info *desc_info;
423 struct ionic_buf_info *buf_info;
426 for (i = 0; i < q->num_descs; i++) {
427 desc_info = &q->info[i];
428 for (j = 0; j < IONIC_RX_MAX_SG_ELEMS + 1; j++) {
429 buf_info = &desc_info->bufs[j];
431 ionic_rx_page_free(q, buf_info);
434 desc_info->nbufs = 0;
435 desc_info->cb = NULL;
436 desc_info->cb_arg = NULL;
443 static void ionic_dim_update(struct ionic_qcq *qcq, int napi_mode)
445 struct dim_sample dim_sample;
446 struct ionic_lif *lif;
450 if (!qcq->intr.dim_coal_hw)
454 qi = qcq->cq.bound_q->index;
457 case IONIC_LIF_F_TX_DIM_INTR:
458 pkts = lif->txqstats[qi].pkts;
459 bytes = lif->txqstats[qi].bytes;
461 case IONIC_LIF_F_RX_DIM_INTR:
462 pkts = lif->rxqstats[qi].pkts;
463 bytes = lif->rxqstats[qi].bytes;
466 pkts = lif->txqstats[qi].pkts + lif->rxqstats[qi].pkts;
467 bytes = lif->txqstats[qi].bytes + lif->rxqstats[qi].bytes;
471 dim_update_sample(qcq->cq.bound_intr->rearm_count,
472 pkts, bytes, &dim_sample);
474 net_dim(&qcq->dim, dim_sample);
477 int ionic_tx_napi(struct napi_struct *napi, int budget)
479 struct ionic_qcq *qcq = napi_to_qcq(napi);
480 struct ionic_cq *cq = napi_to_cq(napi);
481 struct ionic_dev *idev;
482 struct ionic_lif *lif;
486 lif = cq->bound_q->lif;
487 idev = &lif->ionic->idev;
489 work_done = ionic_cq_service(cq, budget,
490 ionic_tx_service, NULL, NULL);
492 if (work_done < budget && napi_complete_done(napi, work_done)) {
493 ionic_dim_update(qcq, IONIC_LIF_F_TX_DIM_INTR);
494 flags |= IONIC_INTR_CRED_UNMASK;
495 cq->bound_intr->rearm_count++;
498 if (work_done || flags) {
499 flags |= IONIC_INTR_CRED_RESET_COALESCE;
500 ionic_intr_credits(idev->intr_ctrl,
501 cq->bound_intr->index,
508 int ionic_rx_napi(struct napi_struct *napi, int budget)
510 struct ionic_qcq *qcq = napi_to_qcq(napi);
511 struct ionic_cq *cq = napi_to_cq(napi);
512 struct ionic_dev *idev;
513 struct ionic_lif *lif;
514 u16 rx_fill_threshold;
518 lif = cq->bound_q->lif;
519 idev = &lif->ionic->idev;
521 work_done = ionic_cq_service(cq, budget,
522 ionic_rx_service, NULL, NULL);
524 rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD,
525 cq->num_descs / IONIC_RX_FILL_DIV);
526 if (work_done && ionic_q_space_avail(cq->bound_q) >= rx_fill_threshold)
527 ionic_rx_fill(cq->bound_q);
529 if (work_done < budget && napi_complete_done(napi, work_done)) {
530 ionic_dim_update(qcq, IONIC_LIF_F_RX_DIM_INTR);
531 flags |= IONIC_INTR_CRED_UNMASK;
532 cq->bound_intr->rearm_count++;
535 if (work_done || flags) {
536 flags |= IONIC_INTR_CRED_RESET_COALESCE;
537 ionic_intr_credits(idev->intr_ctrl,
538 cq->bound_intr->index,
545 int ionic_txrx_napi(struct napi_struct *napi, int budget)
547 struct ionic_qcq *qcq = napi_to_qcq(napi);
548 struct ionic_cq *rxcq = napi_to_cq(napi);
549 unsigned int qi = rxcq->bound_q->index;
550 struct ionic_dev *idev;
551 struct ionic_lif *lif;
552 struct ionic_cq *txcq;
553 u16 rx_fill_threshold;
554 u32 rx_work_done = 0;
555 u32 tx_work_done = 0;
558 lif = rxcq->bound_q->lif;
559 idev = &lif->ionic->idev;
560 txcq = &lif->txqcqs[qi]->cq;
562 tx_work_done = ionic_cq_service(txcq, IONIC_TX_BUDGET_DEFAULT,
563 ionic_tx_service, NULL, NULL);
565 rx_work_done = ionic_cq_service(rxcq, budget,
566 ionic_rx_service, NULL, NULL);
568 rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD,
569 rxcq->num_descs / IONIC_RX_FILL_DIV);
570 if (rx_work_done && ionic_q_space_avail(rxcq->bound_q) >= rx_fill_threshold)
571 ionic_rx_fill(rxcq->bound_q);
573 if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) {
574 ionic_dim_update(qcq, 0);
575 flags |= IONIC_INTR_CRED_UNMASK;
576 rxcq->bound_intr->rearm_count++;
579 if (rx_work_done || flags) {
580 flags |= IONIC_INTR_CRED_RESET_COALESCE;
581 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index,
582 tx_work_done + rx_work_done, flags);
588 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q,
589 void *data, size_t len)
591 struct ionic_tx_stats *stats = q_to_tx_stats(q);
592 struct device *dev = q->dev;
595 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE);
596 if (dma_mapping_error(dev, dma_addr)) {
597 net_warn_ratelimited("%s: DMA single map failed on %s!\n",
598 q->lif->netdev->name, q->name);
599 stats->dma_map_err++;
605 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q,
606 const skb_frag_t *frag,
607 size_t offset, size_t len)
609 struct ionic_tx_stats *stats = q_to_tx_stats(q);
610 struct device *dev = q->dev;
613 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE);
614 if (dma_mapping_error(dev, dma_addr)) {
615 net_warn_ratelimited("%s: DMA frag map failed on %s!\n",
616 q->lif->netdev->name, q->name);
617 stats->dma_map_err++;
622 static int ionic_tx_map_skb(struct ionic_queue *q, struct sk_buff *skb,
623 struct ionic_desc_info *desc_info)
625 struct ionic_buf_info *buf_info = desc_info->bufs;
626 struct ionic_tx_stats *stats = q_to_tx_stats(q);
627 struct device *dev = q->dev;
633 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
634 if (dma_mapping_error(dev, dma_addr)) {
635 stats->dma_map_err++;
638 buf_info->dma_addr = dma_addr;
639 buf_info->len = skb_headlen(skb);
642 frag = skb_shinfo(skb)->frags;
643 nfrags = skb_shinfo(skb)->nr_frags;
644 for (frag_idx = 0; frag_idx < nfrags; frag_idx++, frag++) {
645 dma_addr = ionic_tx_map_frag(q, frag, 0, skb_frag_size(frag));
646 if (dma_mapping_error(dev, dma_addr)) {
647 stats->dma_map_err++;
650 buf_info->dma_addr = dma_addr;
651 buf_info->len = skb_frag_size(frag);
655 desc_info->nbufs = 1 + nfrags;
660 /* unwind the frag mappings and the head mapping */
661 while (frag_idx > 0) {
664 dma_unmap_page(dev, buf_info->dma_addr,
665 buf_info->len, DMA_TO_DEVICE);
667 dma_unmap_single(dev, buf_info->dma_addr, buf_info->len, DMA_TO_DEVICE);
671 static void ionic_tx_desc_unmap_bufs(struct ionic_queue *q,
672 struct ionic_desc_info *desc_info)
674 struct ionic_buf_info *buf_info = desc_info->bufs;
675 struct device *dev = q->dev;
678 if (!desc_info->nbufs)
681 dma_unmap_single(dev, (dma_addr_t)buf_info->dma_addr,
682 buf_info->len, DMA_TO_DEVICE);
684 for (i = 1; i < desc_info->nbufs; i++, buf_info++)
685 dma_unmap_page(dev, (dma_addr_t)buf_info->dma_addr,
686 buf_info->len, DMA_TO_DEVICE);
688 desc_info->nbufs = 0;
691 static void ionic_tx_clean(struct ionic_queue *q,
692 struct ionic_desc_info *desc_info,
693 struct ionic_cq_info *cq_info,
696 struct ionic_tx_stats *stats = q_to_tx_stats(q);
697 struct ionic_qcq *qcq = q_to_qcq(q);
698 struct sk_buff *skb = cb_arg;
701 ionic_tx_desc_unmap_bufs(q, desc_info);
706 qi = skb_get_queue_mapping(skb);
708 if (unlikely(q->features & IONIC_TXQ_F_HWSTAMP)) {
710 struct skb_shared_hwtstamps hwts = {};
711 __le64 *cq_desc_hwstamp;
717 sizeof(struct ionic_txq_comp) -
718 IONIC_HWSTAMP_CQ_NEGOFFSET;
720 hwstamp = le64_to_cpu(*cq_desc_hwstamp);
722 if (hwstamp != IONIC_HWSTAMP_INVALID) {
723 hwts.hwtstamp = ionic_lif_phc_ktime(q->lif, hwstamp);
725 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
726 skb_tstamp_tx(skb, &hwts);
728 stats->hwstamp_valid++;
730 stats->hwstamp_invalid++;
734 } else if (unlikely(__netif_subqueue_stopped(q->lif->netdev, qi))) {
735 netif_wake_subqueue(q->lif->netdev, qi);
738 desc_info->bytes = skb->len;
741 dev_consume_skb_any(skb);
744 bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)
746 struct ionic_queue *q = cq->bound_q;
747 struct ionic_desc_info *desc_info;
748 struct ionic_txq_comp *comp;
753 comp = cq_info->cq_desc + cq->desc_size - sizeof(*comp);
755 if (!color_match(comp->color, cq->done_color))
758 /* clean the related q entries, there could be
759 * several q entries completed for each cq completion
762 desc_info = &q->info[q->tail_idx];
763 desc_info->bytes = 0;
765 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
766 ionic_tx_clean(q, desc_info, cq_info, desc_info->cb_arg);
767 if (desc_info->cb_arg) {
769 bytes += desc_info->bytes;
771 desc_info->cb = NULL;
772 desc_info->cb_arg = NULL;
773 } while (index != le16_to_cpu(comp->comp_index));
775 if (pkts && bytes && !unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
776 netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes);
781 void ionic_tx_flush(struct ionic_cq *cq)
783 struct ionic_dev *idev = &cq->lif->ionic->idev;
786 work_done = ionic_cq_service(cq, cq->num_descs,
787 ionic_tx_service, NULL, NULL);
789 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
790 work_done, IONIC_INTR_CRED_RESET_COALESCE);
793 void ionic_tx_empty(struct ionic_queue *q)
795 struct ionic_desc_info *desc_info;
799 /* walk the not completed tx entries, if any */
800 while (q->head_idx != q->tail_idx) {
801 desc_info = &q->info[q->tail_idx];
802 desc_info->bytes = 0;
803 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
804 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg);
805 if (desc_info->cb_arg) {
807 bytes += desc_info->bytes;
809 desc_info->cb = NULL;
810 desc_info->cb_arg = NULL;
813 if (pkts && bytes && !unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
814 netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes);
817 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb)
821 err = skb_cow_head(skb, 0);
825 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
826 inner_ip_hdr(skb)->check = 0;
827 inner_tcp_hdr(skb)->check =
828 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
829 inner_ip_hdr(skb)->daddr,
831 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
832 inner_tcp_hdr(skb)->check =
833 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
834 &inner_ipv6_hdr(skb)->daddr,
841 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb)
845 err = skb_cow_head(skb, 0);
849 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
850 ip_hdr(skb)->check = 0;
851 tcp_hdr(skb)->check =
852 ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
855 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
856 tcp_v6_gso_csum_prep(skb);
862 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
864 dma_addr_t addr, u8 nsge, u16 len,
865 unsigned int hdrlen, unsigned int mss,
867 u16 vlan_tci, bool has_vlan,
868 bool start, bool done)
873 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
874 flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
875 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
876 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
878 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr);
879 desc->cmd = cpu_to_le64(cmd);
880 desc->len = cpu_to_le16(len);
881 desc->vlan_tci = cpu_to_le16(vlan_tci);
882 desc->hdr_len = cpu_to_le16(hdrlen);
883 desc->mss = cpu_to_le16(mss);
886 skb_tx_timestamp(skb);
887 if (!unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
888 netdev_tx_sent_queue(q_to_ndq(q), skb->len);
889 ionic_txq_post(q, false, ionic_tx_clean, skb);
891 ionic_txq_post(q, done, NULL, NULL);
895 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb)
897 struct ionic_tx_stats *stats = q_to_tx_stats(q);
898 struct ionic_desc_info *desc_info;
899 struct ionic_buf_info *buf_info;
900 struct ionic_txq_sg_elem *elem;
901 struct ionic_txq_desc *desc;
902 unsigned int chunk_len;
903 unsigned int frag_rem;
904 unsigned int tso_rem;
905 unsigned int seg_rem;
906 dma_addr_t desc_addr;
907 dma_addr_t frag_addr;
920 desc_info = &q->info[q->head_idx];
921 buf_info = desc_info->bufs;
923 if (unlikely(ionic_tx_map_skb(q, skb, desc_info)))
927 mss = skb_shinfo(skb)->gso_size;
928 outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) ||
929 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM);
930 has_vlan = !!skb_vlan_tag_present(skb);
931 vlan_tci = skb_vlan_tag_get(skb);
932 encap = skb->encapsulation;
934 /* Preload inner-most TCP csum field with IP pseudo hdr
935 * calculated with IP length set to zero. HW will later
936 * add in length to each TCP segment resulting from the TSO.
940 err = ionic_tx_tcp_inner_pseudo_csum(skb);
942 err = ionic_tx_tcp_pseudo_csum(skb);
944 /* clean up mapping from ionic_tx_map_skb */
945 ionic_tx_desc_unmap_bufs(q, desc_info);
950 hdrlen = skb_inner_tcp_all_headers(skb);
952 hdrlen = skb_tcp_all_headers(skb);
955 seg_rem = min(tso_rem, hdrlen + mss);
962 while (tso_rem > 0) {
968 /* use fragments until we have enough to post a single descriptor */
969 while (seg_rem > 0) {
970 /* if the fragment is exhausted then move to the next one */
972 /* grab the next fragment */
973 frag_addr = buf_info->dma_addr;
974 frag_rem = buf_info->len;
977 chunk_len = min(frag_rem, seg_rem);
979 /* fill main descriptor */
980 desc = desc_info->txq_desc;
981 elem = desc_info->txq_sg_desc->elems;
982 desc_addr = frag_addr;
983 desc_len = chunk_len;
985 /* fill sg descriptor */
986 elem->addr = cpu_to_le64(frag_addr);
987 elem->len = cpu_to_le16(chunk_len);
991 frag_addr += chunk_len;
992 frag_rem -= chunk_len;
993 tso_rem -= chunk_len;
994 seg_rem -= chunk_len;
996 seg_rem = min(tso_rem, mss);
997 done = (tso_rem == 0);
998 /* post descriptor */
999 ionic_tx_tso_post(q, desc, skb,
1000 desc_addr, desc_nsge, desc_len,
1001 hdrlen, mss, outer_csum, vlan_tci, has_vlan,
1004 /* Buffer information is stored with the first tso descriptor */
1005 desc_info = &q->info[q->head_idx];
1006 desc_info->nbufs = 0;
1009 stats->pkts += DIV_ROUND_UP(len - hdrlen, mss);
1010 stats->bytes += len;
1012 stats->tso_bytes = len;
1017 static void ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb,
1018 struct ionic_desc_info *desc_info)
1020 struct ionic_txq_desc *desc = desc_info->txq_desc;
1021 struct ionic_buf_info *buf_info = desc_info->bufs;
1022 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1028 has_vlan = !!skb_vlan_tag_present(skb);
1029 encap = skb->encapsulation;
1031 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
1032 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
1034 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL,
1035 flags, skb_shinfo(skb)->nr_frags,
1036 buf_info->dma_addr);
1037 desc->cmd = cpu_to_le64(cmd);
1038 desc->len = cpu_to_le16(buf_info->len);
1040 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
1041 stats->vlan_inserted++;
1045 desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb));
1046 desc->csum_offset = cpu_to_le16(skb->csum_offset);
1048 if (skb_csum_is_sctp(skb))
1049 stats->crc32_csum++;
1054 static void ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb,
1055 struct ionic_desc_info *desc_info)
1057 struct ionic_txq_desc *desc = desc_info->txq_desc;
1058 struct ionic_buf_info *buf_info = desc_info->bufs;
1059 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1065 has_vlan = !!skb_vlan_tag_present(skb);
1066 encap = skb->encapsulation;
1068 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
1069 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
1071 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE,
1072 flags, skb_shinfo(skb)->nr_frags,
1073 buf_info->dma_addr);
1074 desc->cmd = cpu_to_le64(cmd);
1075 desc->len = cpu_to_le16(buf_info->len);
1077 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
1078 stats->vlan_inserted++;
1082 desc->csum_start = 0;
1083 desc->csum_offset = 0;
1088 static void ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb,
1089 struct ionic_desc_info *desc_info)
1091 struct ionic_txq_sg_desc *sg_desc = desc_info->txq_sg_desc;
1092 struct ionic_buf_info *buf_info = &desc_info->bufs[1];
1093 struct ionic_txq_sg_elem *elem = sg_desc->elems;
1094 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1097 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, buf_info++, elem++) {
1098 elem->addr = cpu_to_le64(buf_info->dma_addr);
1099 elem->len = cpu_to_le16(buf_info->len);
1102 stats->frags += skb_shinfo(skb)->nr_frags;
1105 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb)
1107 struct ionic_desc_info *desc_info = &q->info[q->head_idx];
1108 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1110 if (unlikely(ionic_tx_map_skb(q, skb, desc_info)))
1113 /* set up the initial descriptor */
1114 if (skb->ip_summed == CHECKSUM_PARTIAL)
1115 ionic_tx_calc_csum(q, skb, desc_info);
1117 ionic_tx_calc_no_csum(q, skb, desc_info);
1120 ionic_tx_skb_frags(q, skb, desc_info);
1122 skb_tx_timestamp(skb);
1124 stats->bytes += skb->len;
1126 if (!unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
1127 netdev_tx_sent_queue(q_to_ndq(q), skb->len);
1128 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
1133 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb)
1135 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1139 /* Each desc is mss long max, so a descriptor for each gso_seg */
1140 if (skb_is_gso(skb))
1141 ndescs = skb_shinfo(skb)->gso_segs;
1145 /* If non-TSO, just need 1 desc and nr_frags sg elems */
1146 if (skb_shinfo(skb)->nr_frags <= q->max_sg_elems)
1149 /* Too many frags, so linearize */
1150 err = skb_linearize(skb);
1159 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs)
1163 if (unlikely(!ionic_q_has_space(q, ndescs))) {
1164 netif_stop_subqueue(q->lif->netdev, q->index);
1167 /* Might race with ionic_tx_clean, check again */
1169 if (ionic_q_has_space(q, ndescs)) {
1170 netif_wake_subqueue(q->lif->netdev, q->index);
1178 static netdev_tx_t ionic_start_hwstamp_xmit(struct sk_buff *skb,
1179 struct net_device *netdev)
1181 struct ionic_lif *lif = netdev_priv(netdev);
1182 struct ionic_queue *q = &lif->hwstamp_txq->q;
1185 /* Does not stop/start txq, because we post to a separate tx queue
1186 * for timestamping, and if a packet can't be posted immediately to
1187 * the timestamping queue, it is dropped.
1190 ndescs = ionic_tx_descs_needed(q, skb);
1191 if (unlikely(ndescs < 0))
1194 if (unlikely(!ionic_q_has_space(q, ndescs)))
1197 skb_shinfo(skb)->tx_flags |= SKBTX_HW_TSTAMP;
1198 if (skb_is_gso(skb))
1199 err = ionic_tx_tso(q, skb);
1201 err = ionic_tx(q, skb);
1206 return NETDEV_TX_OK;
1211 return NETDEV_TX_OK;
1214 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1216 u16 queue_index = skb_get_queue_mapping(skb);
1217 struct ionic_lif *lif = netdev_priv(netdev);
1218 struct ionic_queue *q;
1222 if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) {
1224 return NETDEV_TX_OK;
1227 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
1228 if (lif->hwstamp_txq && lif->phc->ts_config_tx_mode)
1229 return ionic_start_hwstamp_xmit(skb, netdev);
1231 if (unlikely(queue_index >= lif->nxqs))
1233 q = &lif->txqcqs[queue_index]->q;
1235 ndescs = ionic_tx_descs_needed(q, skb);
1239 if (unlikely(ionic_maybe_stop_tx(q, ndescs)))
1240 return NETDEV_TX_BUSY;
1242 if (skb_is_gso(skb))
1243 err = ionic_tx_tso(q, skb);
1245 err = ionic_tx(q, skb);
1250 /* Stop the queue if there aren't descriptors for the next packet.
1251 * Since our SG lists per descriptor take care of most of the possible
1252 * fragmentation, we don't need to have many descriptors available.
1254 ionic_maybe_stop_tx(q, 4);
1256 return NETDEV_TX_OK;
1261 return NETDEV_TX_OK;