drivers/net/ethernet/pensando/ionic/ionic_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
   2 /* Copyright (c) 2018-2019 Pensando Systems, Inc.  All rights reserved. */
   3
   4 #ifndef IONIC_REGS_H
   5 #define IONIC_REGS_H
   6
   7 #include <linux/io.h>
   8
   9 /** struct ionic_intr - interrupt control register set.
  10  * @coal_init:                  coalesce timer initial value.
  11  * @mask:                       interrupt mask value.
  12  * @credits:                    interrupt credit count and return.
  13  * @mask_assert:                interrupt mask value on assert.
  14  * @coal:                       coalesce timer time remaining.
  15  */
  16 struct ionic_intr {
  17         u32 coal_init;
  18         u32 mask;
  19         u32 credits;
  20         u32 mask_assert;
  21         u32 coal;
  22         u32 rsvd[3];
  23 };
  24
  25 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
  26  * @IONIC_INTR_MASK_CLEAR:      unmask interrupt.
  27  * @IONIC_INTR_MASK_SET:        mask interrupt.
  28  */
  29 enum ionic_intr_mask_vals {
  30         IONIC_INTR_MASK_CLEAR           = 0,
  31         IONIC_INTR_MASK_SET             = 1,
  32 };
  33
  34 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
  35  * @IONIC_INTR_CRED_COUNT:      bit mask of credit count, no shift needed.
  36  * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
  37  * @IONIC_INTR_CRED_UNMASK:     unmask the interrupt.
  38  * @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
  39  * @IONIC_INTR_CRED_REARM:      unmask the and reset the timer.
  40  */
  41 enum ionic_intr_credits_bits {
  42         IONIC_INTR_CRED_COUNT           = 0x7fffu,
  43         IONIC_INTR_CRED_COUNT_SIGNED    = 0xffffu,
  44         IONIC_INTR_CRED_UNMASK          = 0x10000u,
  45         IONIC_INTR_CRED_RESET_COALESCE  = 0x20000u,
  46         IONIC_INTR_CRED_REARM           = (IONIC_INTR_CRED_UNMASK |
  47                                            IONIC_INTR_CRED_RESET_COALESCE),
  48 };
  49
  50 static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,
  51                                         int intr_idx, u32 coal)
  52 {
  53         iowrite32(coal, &intr_ctrl[intr_idx].coal_init);
  54 }
  55
  56 static inline void ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl,
  57                                    int intr_idx, u32 mask)
  58 {
  59         iowrite32(mask, &intr_ctrl[intr_idx].mask);
  60 }
  61
  62 static inline void ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,
  63                                       int intr_idx, u32 cred, u32 flags)
  64 {
  65         if (WARN_ON_ONCE(cred > IONIC_INTR_CRED_COUNT)) {
  66                 cred = ioread32(&intr_ctrl[intr_idx].credits);
  67                 cred &= IONIC_INTR_CRED_COUNT_SIGNED;
  68         }
  69
  70         iowrite32(cred | flags, &intr_ctrl[intr_idx].credits);
  71 }
  72
  73 static inline void ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl,
  74                                     int intr_idx)
  75 {
  76         u32 cred;
  77
  78         cred = ioread32(&intr_ctrl[intr_idx].credits);
  79         cred &= IONIC_INTR_CRED_COUNT_SIGNED;
  80         cred |= IONIC_INTR_CRED_RESET_COALESCE;
  81         iowrite32(cred, &intr_ctrl[intr_idx].credits);
  82 }
  83
  84 static inline void ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl,
  85                                           int intr_idx, u32 mask)
  86 {
  87         iowrite32(mask, &intr_ctrl[intr_idx].mask_assert);
  88 }
  89
  90 /** enum ionic_dbell_bits - bitwise composition of dbell values.
  91  *
  92  * @IONIC_DBELL_QID_MASK:       unshifted mask of valid queue id bits.
  93  * @IONIC_DBELL_QID_SHIFT:      queue id shift amount in dbell value.
  94  * @IONIC_DBELL_QID:            macro to build QID component of dbell value.
  95  *
  96  * @IONIC_DBELL_RING_MASK:      unshifted mask of valid ring bits.
  97  * @IONIC_DBELL_RING_SHIFT:     ring shift amount in dbell value.
  98  * @IONIC_DBELL_RING:           macro to build ring component of dbell value.
  99  *
 100  * @IONIC_DBELL_RING_0:         ring zero dbell component value.
 101  * @IONIC_DBELL_RING_1:         ring one dbell component value.
 102  * @IONIC_DBELL_RING_2:         ring two dbell component value.
 103  * @IONIC_DBELL_RING_3:         ring three dbell component value.
 104  *
 105  * @IONIC_DBELL_INDEX_MASK:     bit mask of valid index bits, no shift needed.
 106  */
 107 enum ionic_dbell_bits {
 108         IONIC_DBELL_QID_MASK            = 0xffffff,
 109         IONIC_DBELL_QID_SHIFT           = 24,
 110
 111 #define IONIC_DBELL_QID(n) \
 112         (((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT)
 113
 114         IONIC_DBELL_RING_MASK           = 0x7,
 115         IONIC_DBELL_RING_SHIFT          = 16,
 116
 117 #define IONIC_DBELL_RING(n) \
 118         (((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT)
 119
 120         IONIC_DBELL_RING_0              = 0,
 121         IONIC_DBELL_RING_1              = IONIC_DBELL_RING(1),
 122         IONIC_DBELL_RING_2              = IONIC_DBELL_RING(2),
 123         IONIC_DBELL_RING_3              = IONIC_DBELL_RING(3),
 124
 125         IONIC_DBELL_INDEX_MASK          = 0xffff,
 126 };
 127
 128 static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val)
 129 {
 130         writeq(val, &db_page[qtype]);
 131 }
 132
 133 #endif /* IONIC_REGS_H */