1 /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
3 Written 1997-2001 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28 #define DRV_NAME "yellowfin"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sep 11, 2006"
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37 static int max_interrupt_work = 20;
39 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40 /* System-wide count of bogus-rx frames. */
42 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44 #elif defined(YF_NEW) /* A future perfect board :->. */
45 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46 static int fifo_cfg = 0x0028;
48 static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49 static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
52 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54 static int rx_copybreak;
56 /* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
60 #define MAX_UNITS 8 /* More are supported, limit only on options */
61 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
64 /* Do ugly workaround for GX server chipset errata. */
67 /* Operational parameters that are set at compile time. */
69 /* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73 #define TX_RING_SIZE 16
74 #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75 #define RX_RING_SIZE 64
76 #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77 #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
80 /* Operational parameters that usually are not changed. */
81 /* Time in jiffies before concluding the transmitter is hung. */
82 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
85 #define yellowfin_debug debug
87 #include <linux/module.h>
88 #include <linux/kernel.h>
89 #include <linux/string.h>
90 #include <linux/timer.h>
91 #include <linux/errno.h>
92 #include <linux/ioport.h>
93 #include <linux/interrupt.h>
94 #include <linux/pci.h>
95 #include <linux/init.h>
96 #include <linux/mii.h>
97 #include <linux/netdevice.h>
98 #include <linux/etherdevice.h>
99 #include <linux/skbuff.h>
100 #include <linux/ethtool.h>
101 #include <linux/crc32.h>
102 #include <linux/bitops.h>
103 #include <asm/uaccess.h>
104 #include <asm/processor.h> /* Processor type for cache alignment. */
105 #include <asm/unaligned.h>
108 /* These identify the driver base version and may not be removed. */
109 static const char version[] __devinitconst =
110 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
111 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
113 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
114 MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
115 MODULE_LICENSE("GPL");
117 module_param(max_interrupt_work, int, 0);
118 module_param(mtu, int, 0);
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(options, int, NULL, 0);
122 module_param_array(full_duplex, int, NULL, 0);
123 module_param(gx_fix, int, 0);
124 MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
125 MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
126 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
127 MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
128 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
129 MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
130 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
135 I. Board Compatibility
137 This device driver is designed for the Packet Engines "Yellowfin" Gigabit
138 Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
139 Symbios 53C885E dual function chip.
141 II. Board-specific settings
143 PCI bus devices are configured by the system at boot time, so no jumpers
144 need to be set on the board. The system BIOS preferably should assign the
145 PCI INTA signal to an otherwise unused system IRQ line.
146 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
149 III. Driver operation
153 The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
154 This is a descriptor list scheme similar to that used by the EEPro100 and
155 Tulip. This driver uses two statically allocated fixed-size descriptor lists
156 formed into rings by a branch from the final descriptor to the beginning of
157 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
159 The driver allocates full frame size skbuffs for the Rx ring buffers at
160 open() time and passes the skb->data field to the Yellowfin as receive data
161 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
162 a fresh skbuff is allocated and the frame is copied to the new skbuff.
163 When the incoming frame is larger, the skbuff is passed directly up the
164 protocol stack and replaced by a newly allocated skbuff.
166 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
167 using a full-sized skbuff for small frames vs. the copying costs of larger
168 frames. For small frames the copying cost is negligible (esp. considering
169 that we are pre-loading the cache with immediately useful header
170 information). For large frames the copying cost is non-trivial, and the
171 larger copy might flush the cache of useful data.
173 IIIC. Synchronization
175 The driver runs as two independent, single-threaded flows of control. One
176 is the send-packet routine, which enforces single-threaded use by the
177 dev->tbusy flag. The other thread is the interrupt handler, which is single
178 threaded by the hardware and other software.
180 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
181 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
182 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
183 the 'yp->tx_full' flag.
185 The interrupt handler has exclusive control over the Rx ring and records stats
186 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
187 empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
188 clears both the tx_full and tbusy flags.
192 Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
193 Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
194 and an AlphaStation to verifty the Alpha port!
198 Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
199 Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
201 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
202 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
206 See Packet Engines confidential appendix (prototype chips only).
211 enum capability_flags {
212 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
213 HasMACAddrBug=32, /* Only on early revs. */
214 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
217 /* The PCI I/O space extent. */
219 YELLOWFIN_SIZE = 0x100,
225 int pci, pci_mask, subsystem, subsystem_mask;
226 int revision, revision_mask; /* Only 8 bits. */
228 int drv_flags; /* Driver use, intended as capability flags. */
231 static const struct pci_id_info pci_id_tbl[] = {
232 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
233 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
234 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
235 HasMII | DontUseEeprom },
239 static DEFINE_PCI_DEVICE_TABLE(yellowfin_pci_tbl) = {
240 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
241 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
244 MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
247 /* Offsets to the Yellowfin registers. Various sizes and alignments. */
248 enum yellowfin_offsets {
249 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
250 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
251 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
252 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
253 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
254 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
255 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
256 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
258 RxDepth=0xB8, FlowCtrl=0xBC,
259 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
260 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
264 /* The Yellowfin Rx and Tx buffer descriptors.
265 Elements are written as 32 bit for endian portability. */
266 struct yellowfin_desc {
270 __le32 result_status;
273 struct tx_status_words {
279 #else /* Little endian chips. */
284 #endif /* __BIG_ENDIAN */
287 /* Bits in yellowfin_desc.cmd */
289 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
290 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
291 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
292 BRANCH_IFTRUE=0x040000,
295 /* Bits in yellowfin_desc.status */
296 enum desc_status_bits { RX_EOP=0x0040, };
298 /* Bits in the interrupt status/mask registers. */
299 enum intr_status_bits {
300 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
301 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
302 IntrEarlyRx=0x100, IntrWakeup=0x200, };
304 #define PRIV_ALIGN 31 /* Required alignment mask */
306 struct yellowfin_private {
307 /* Descriptor rings first for alignment.
308 Tx requires a second descriptor for status. */
309 struct yellowfin_desc *rx_ring;
310 struct yellowfin_desc *tx_ring;
311 struct sk_buff* rx_skbuff[RX_RING_SIZE];
312 struct sk_buff* tx_skbuff[TX_RING_SIZE];
313 dma_addr_t rx_ring_dma;
314 dma_addr_t tx_ring_dma;
316 struct tx_status_words *tx_status;
317 dma_addr_t tx_status_dma;
319 struct timer_list timer; /* Media selection timer. */
320 /* Frequently used and paired value: keep adjacent for cache effect. */
321 int chip_id, drv_flags;
322 struct pci_dev *pci_dev;
323 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
324 unsigned int rx_buf_sz; /* Based on MTU+slack. */
325 struct tx_status_words *tx_tail_desc;
326 unsigned int cur_tx, dirty_tx;
328 unsigned int tx_full:1; /* The Tx queue is full. */
329 unsigned int full_duplex:1; /* Full-duplex operation requested. */
330 unsigned int duplex_lock:1;
331 unsigned int medialock:1; /* Do not sense media. */
332 unsigned int default_port:4; /* Last dev->if_port value. */
333 /* MII transceiver section. */
334 int mii_cnt; /* MII device addresses. */
335 u16 advertising; /* NWay media advertisement */
336 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
341 static int read_eeprom(void __iomem *ioaddr, int location);
342 static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
343 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
344 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
345 static int yellowfin_open(struct net_device *dev);
346 static void yellowfin_timer(unsigned long data);
347 static void yellowfin_tx_timeout(struct net_device *dev);
348 static int yellowfin_init_ring(struct net_device *dev);
349 static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
350 struct net_device *dev);
351 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
352 static int yellowfin_rx(struct net_device *dev);
353 static void yellowfin_error(struct net_device *dev, int intr_status);
354 static int yellowfin_close(struct net_device *dev);
355 static void set_rx_mode(struct net_device *dev);
356 static const struct ethtool_ops ethtool_ops;
358 static const struct net_device_ops netdev_ops = {
359 .ndo_open = yellowfin_open,
360 .ndo_stop = yellowfin_close,
361 .ndo_start_xmit = yellowfin_start_xmit,
362 .ndo_set_rx_mode = set_rx_mode,
363 .ndo_change_mtu = eth_change_mtu,
364 .ndo_validate_addr = eth_validate_addr,
365 .ndo_set_mac_address = eth_mac_addr,
366 .ndo_do_ioctl = netdev_ioctl,
367 .ndo_tx_timeout = yellowfin_tx_timeout,
370 static int __devinit yellowfin_init_one(struct pci_dev *pdev,
371 const struct pci_device_id *ent)
373 struct net_device *dev;
374 struct yellowfin_private *np;
376 int chip_idx = ent->driver_data;
378 void __iomem *ioaddr;
379 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
380 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
389 /* when built into the kernel, we only print version if device is found */
391 static int printed_version;
392 if (!printed_version++)
396 i = pci_enable_device(pdev);
399 dev = alloc_etherdev(sizeof(*np));
403 SET_NETDEV_DEV(dev, &pdev->dev);
405 np = netdev_priv(dev);
407 if (pci_request_regions(pdev, DRV_NAME))
408 goto err_out_free_netdev;
410 pci_set_master (pdev);
412 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
414 goto err_out_free_res;
418 if (drv_flags & DontUseEeprom)
419 for (i = 0; i < 6; i++)
420 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
422 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
423 for (i = 0; i < 6; i++)
424 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
427 /* Reset the chip. */
428 iowrite32(0x80000000, ioaddr + DMACtrl);
430 dev->base_addr = (unsigned long)ioaddr;
433 pci_set_drvdata(pdev, dev);
434 spin_lock_init(&np->lock);
437 np->chip_id = chip_idx;
438 np->drv_flags = drv_flags;
441 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
443 goto err_out_cleardev;
444 np->tx_ring = ring_space;
445 np->tx_ring_dma = ring_dma;
447 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
449 goto err_out_unmap_tx;
450 np->rx_ring = ring_space;
451 np->rx_ring_dma = ring_dma;
453 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
455 goto err_out_unmap_rx;
456 np->tx_status = ring_space;
457 np->tx_status_dma = ring_dma;
460 option = dev->mem_start;
462 /* The lower four bits are the media type. */
466 np->default_port = option & 15;
467 if (np->default_port)
470 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
476 /* The Yellowfin-specific entries in the device structure. */
477 dev->netdev_ops = &netdev_ops;
478 SET_ETHTOOL_OPS(dev, ðtool_ops);
479 dev->watchdog_timeo = TX_TIMEOUT;
484 i = register_netdev(dev);
486 goto err_out_unmap_status;
488 netdev_info(dev, "%s type %8x at %p, %pM, IRQ %d\n",
489 pci_id_tbl[chip_idx].name,
490 ioread32(ioaddr + ChipRev), ioaddr,
493 if (np->drv_flags & HasMII) {
494 int phy, phy_idx = 0;
495 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
496 int mii_status = mdio_read(ioaddr, phy, 1);
497 if (mii_status != 0xffff && mii_status != 0x0000) {
498 np->phys[phy_idx++] = phy;
499 np->advertising = mdio_read(ioaddr, phy, 4);
500 netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",
501 phy, mii_status, np->advertising);
504 np->mii_cnt = phy_idx;
511 err_out_unmap_status:
512 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
515 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
517 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
519 pci_set_drvdata(pdev, NULL);
520 pci_iounmap(pdev, ioaddr);
522 pci_release_regions(pdev);
528 static int __devinit read_eeprom(void __iomem *ioaddr, int location)
530 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
532 iowrite8(location, ioaddr + EEAddr);
533 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
534 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
536 return ioread8(ioaddr + EERead);
539 /* MII Managemen Data I/O accesses.
540 These routines assume the MDIO controller is idle, and do not exit until
541 the command is finished. */
543 static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
547 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
548 iowrite16(1, ioaddr + MII_Cmd);
549 for (i = 10000; i >= 0; i--)
550 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
552 return ioread16(ioaddr + MII_Rd_Data);
555 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
559 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
560 iowrite16(value, ioaddr + MII_Wr_Data);
562 /* Wait for the command to finish. */
563 for (i = 10000; i >= 0; i--)
564 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
569 static int yellowfin_open(struct net_device *dev)
571 struct yellowfin_private *yp = netdev_priv(dev);
572 void __iomem *ioaddr = yp->base;
575 /* Reset the chip. */
576 iowrite32(0x80000000, ioaddr + DMACtrl);
578 ret = request_irq(dev->irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
582 if (yellowfin_debug > 1)
583 netdev_printk(KERN_DEBUG, dev, "%s() irq %d\n",
586 ret = yellowfin_init_ring(dev);
588 free_irq(dev->irq, dev);
592 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
593 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
595 for (i = 0; i < 6; i++)
596 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
598 /* Set up various condition 'select' registers.
599 There are no options here. */
600 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
601 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
602 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
603 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
604 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
605 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
607 /* Initialize other registers: with so many this eventually this will
608 converted to an offset/value list. */
609 iowrite32(dma_ctrl, ioaddr + DMACtrl);
610 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
611 /* Enable automatic generation of flow control frames, period 0xffff. */
612 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
614 yp->tx_threshold = 32;
615 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
617 if (dev->if_port == 0)
618 dev->if_port = yp->default_port;
620 netif_start_queue(dev);
622 /* Setting the Rx mode will start the Rx process. */
623 if (yp->drv_flags & IsGigabit) {
624 /* We are always in full-duplex mode with gigabit! */
626 iowrite16(0x01CF, ioaddr + Cnfg);
628 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
629 iowrite16(0x1018, ioaddr + FrameGap1);
630 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
634 /* Enable interrupts by setting the interrupt mask. */
635 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
636 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
637 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
638 iowrite32(0x80008000, ioaddr + TxCtrl);
640 if (yellowfin_debug > 2) {
641 netdev_printk(KERN_DEBUG, dev, "Done %s()\n", __func__);
644 /* Set the timer to check for link beat. */
645 init_timer(&yp->timer);
646 yp->timer.expires = jiffies + 3*HZ;
647 yp->timer.data = (unsigned long)dev;
648 yp->timer.function = yellowfin_timer; /* timer handler */
649 add_timer(&yp->timer);
654 static void yellowfin_timer(unsigned long data)
656 struct net_device *dev = (struct net_device *)data;
657 struct yellowfin_private *yp = netdev_priv(dev);
658 void __iomem *ioaddr = yp->base;
659 int next_tick = 60*HZ;
661 if (yellowfin_debug > 3) {
662 netdev_printk(KERN_DEBUG, dev, "Yellowfin timer tick, status %08x\n",
663 ioread16(ioaddr + IntrStatus));
667 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
668 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
669 int negotiated = lpa & yp->advertising;
670 if (yellowfin_debug > 1)
671 netdev_printk(KERN_DEBUG, dev, "MII #%d status register is %04x, link partner capability %04x\n",
672 yp->phys[0], bmsr, lpa);
674 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
676 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
678 if (bmsr & BMSR_LSTATUS)
684 yp->timer.expires = jiffies + next_tick;
685 add_timer(&yp->timer);
688 static void yellowfin_tx_timeout(struct net_device *dev)
690 struct yellowfin_private *yp = netdev_priv(dev);
691 void __iomem *ioaddr = yp->base;
693 netdev_warn(dev, "Yellowfin transmit timed out at %d/%d Tx status %04x, Rx status %04x, resetting...\n",
694 yp->cur_tx, yp->dirty_tx,
695 ioread32(ioaddr + TxStatus),
696 ioread32(ioaddr + RxStatus));
698 /* Note: these should be KERN_DEBUG. */
699 if (yellowfin_debug) {
701 pr_warning(" Rx ring %p: ", yp->rx_ring);
702 for (i = 0; i < RX_RING_SIZE; i++)
703 pr_cont(" %08x", yp->rx_ring[i].result_status);
705 pr_warning(" Tx ring %p: ", yp->tx_ring);
706 for (i = 0; i < TX_RING_SIZE; i++)
707 pr_cont(" %04x /%08x",
708 yp->tx_status[i].tx_errs,
709 yp->tx_ring[i].result_status);
713 /* If the hardware is found to hang regularly, we will update the code
714 to reinitialize the chip here. */
717 /* Wake the potentially-idle transmit channel. */
718 iowrite32(0x10001000, yp->base + TxCtrl);
719 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
720 netif_wake_queue (dev); /* Typical path */
722 dev->trans_start = jiffies; /* prevent tx timeout */
723 dev->stats.tx_errors++;
726 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
727 static int yellowfin_init_ring(struct net_device *dev)
729 struct yellowfin_private *yp = netdev_priv(dev);
733 yp->cur_rx = yp->cur_tx = 0;
736 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
738 for (i = 0; i < RX_RING_SIZE; i++) {
739 yp->rx_ring[i].dbdma_cmd =
740 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
741 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
742 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
745 for (i = 0; i < RX_RING_SIZE; i++) {
746 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz + 2);
747 yp->rx_skbuff[i] = skb;
750 skb->dev = dev; /* Mark as being used by this device. */
751 skb_reserve(skb, 2); /* 16 byte align the IP header. */
752 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
753 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
755 if (i != RX_RING_SIZE) {
756 for (j = 0; j < i; j++)
757 dev_kfree_skb(yp->rx_skbuff[j]);
760 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
761 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
765 /* In this mode the Tx ring needs only a single descriptor. */
766 for (i = 0; i < TX_RING_SIZE; i++) {
767 yp->tx_skbuff[i] = NULL;
768 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
769 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
770 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
773 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
776 /* Tx ring needs a pair of descriptors, the second for the status. */
777 for (i = 0; i < TX_RING_SIZE; i++) {
779 yp->tx_skbuff[i] = 0;
780 /* Branch on Tx error. */
781 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
782 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
783 (j+1)*sizeof(struct yellowfin_desc));
785 if (yp->flags & FullTxStatus) {
786 yp->tx_ring[j].dbdma_cmd =
787 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
788 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
789 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
790 i*sizeof(struct tx_status_words));
792 /* Symbios chips write only tx_errs word. */
793 yp->tx_ring[j].dbdma_cmd =
794 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
795 yp->tx_ring[j].request_cnt = 2;
796 /* Om pade ummmmm... */
797 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
798 i*sizeof(struct tx_status_words) +
799 &(yp->tx_status[0].tx_errs) -
800 &(yp->tx_status[0]));
802 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
803 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
806 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
809 yp->tx_tail_desc = &yp->tx_status[0];
813 static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
814 struct net_device *dev)
816 struct yellowfin_private *yp = netdev_priv(dev);
820 netif_stop_queue (dev);
822 /* Note: Ordering is important here, set the field with the
823 "ownership" bit last, and only then increment cur_tx. */
825 /* Calculate the next Tx descriptor entry. */
826 entry = yp->cur_tx % TX_RING_SIZE;
828 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
829 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
830 /* Fix GX chipset errata. */
831 if (cacheline_end > 24 || cacheline_end == 0) {
832 len = skb->len + 32 - cacheline_end + 1;
833 if (skb_padto(skb, len)) {
834 yp->tx_skbuff[entry] = NULL;
835 netif_wake_queue(dev);
840 yp->tx_skbuff[entry] = skb;
843 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
844 skb->data, len, PCI_DMA_TODEVICE));
845 yp->tx_ring[entry].result_status = 0;
846 if (entry >= TX_RING_SIZE-1) {
847 /* New stop command. */
848 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
849 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
850 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
852 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
853 yp->tx_ring[entry].dbdma_cmd =
854 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
858 yp->tx_ring[entry<<1].request_cnt = len;
859 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
860 skb->data, len, PCI_DMA_TODEVICE));
861 /* The input_last (status-write) command is constant, but we must
862 rewrite the subsequent 'stop' command. */
866 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
867 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
869 /* Final step -- overwrite the old 'stop' command. */
871 yp->tx_ring[entry<<1].dbdma_cmd =
872 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
873 CMD_TX_PKT | BRANCH_IFTRUE) | len);
876 /* Non-x86 Todo: explicitly flush cache lines here. */
878 /* Wake the potentially-idle transmit channel. */
879 iowrite32(0x10001000, yp->base + TxCtrl);
881 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
882 netif_start_queue (dev); /* Typical path */
886 if (yellowfin_debug > 4) {
887 netdev_printk(KERN_DEBUG, dev, "Yellowfin transmit frame #%d queued in slot %d\n",
893 /* The interrupt handler does all of the Rx thread work and cleans up
894 after the Tx thread. */
895 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
897 struct net_device *dev = dev_instance;
898 struct yellowfin_private *yp;
899 void __iomem *ioaddr;
900 int boguscnt = max_interrupt_work;
901 unsigned int handled = 0;
903 yp = netdev_priv(dev);
906 spin_lock (&yp->lock);
909 u16 intr_status = ioread16(ioaddr + IntrClear);
911 if (yellowfin_debug > 4)
912 netdev_printk(KERN_DEBUG, dev, "Yellowfin interrupt, status %04x\n",
915 if (intr_status == 0)
919 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
921 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
925 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
926 int entry = yp->dirty_tx % TX_RING_SIZE;
929 if (yp->tx_ring[entry].result_status == 0)
931 skb = yp->tx_skbuff[entry];
932 dev->stats.tx_packets++;
933 dev->stats.tx_bytes += skb->len;
934 /* Free the original skb. */
935 pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
936 skb->len, PCI_DMA_TODEVICE);
937 dev_kfree_skb_irq(skb);
938 yp->tx_skbuff[entry] = NULL;
941 yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
942 /* The ring is no longer full, clear tbusy. */
944 netif_wake_queue(dev);
947 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
948 unsigned dirty_tx = yp->dirty_tx;
950 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
952 /* Todo: optimize this. */
953 int entry = dirty_tx % TX_RING_SIZE;
954 u16 tx_errs = yp->tx_status[entry].tx_errs;
957 #ifndef final_version
958 if (yellowfin_debug > 5)
959 netdev_printk(KERN_DEBUG, dev, "Tx queue %d check, Tx status %04x %04x %04x %04x\n",
961 yp->tx_status[entry].tx_cnt,
962 yp->tx_status[entry].tx_errs,
963 yp->tx_status[entry].total_tx_cnt,
964 yp->tx_status[entry].paused);
967 break; /* It still hasn't been Txed */
968 skb = yp->tx_skbuff[entry];
969 if (tx_errs & 0xF810) {
970 /* There was an major error, log it. */
971 #ifndef final_version
972 if (yellowfin_debug > 1)
973 netdev_printk(KERN_DEBUG, dev, "Transmit error, Tx status %04x\n",
976 dev->stats.tx_errors++;
977 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
978 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
979 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
980 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
982 #ifndef final_version
983 if (yellowfin_debug > 4)
984 netdev_printk(KERN_DEBUG, dev, "Normal transmit, Tx status %04x\n",
987 dev->stats.tx_bytes += skb->len;
988 dev->stats.collisions += tx_errs & 15;
989 dev->stats.tx_packets++;
991 /* Free the original skb. */
992 pci_unmap_single(yp->pci_dev,
993 yp->tx_ring[entry<<1].addr, skb->len,
995 dev_kfree_skb_irq(skb);
996 yp->tx_skbuff[entry] = 0;
997 /* Mark status as empty. */
998 yp->tx_status[entry].tx_errs = 0;
1001 #ifndef final_version
1002 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1003 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1004 dirty_tx, yp->cur_tx, yp->tx_full);
1005 dirty_tx += TX_RING_SIZE;
1010 yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1011 /* The ring is no longer full, clear tbusy. */
1013 netif_wake_queue(dev);
1016 yp->dirty_tx = dirty_tx;
1017 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1021 /* Log errors and other uncommon events. */
1022 if (intr_status & 0x2ee) /* Abnormal error summary. */
1023 yellowfin_error(dev, intr_status);
1025 if (--boguscnt < 0) {
1026 netdev_warn(dev, "Too much work at interrupt, status=%#04x\n",
1032 if (yellowfin_debug > 3)
1033 netdev_printk(KERN_DEBUG, dev, "exiting interrupt, status=%#04x\n",
1034 ioread16(ioaddr + IntrStatus));
1036 spin_unlock (&yp->lock);
1037 return IRQ_RETVAL(handled);
1040 /* This routine is logically part of the interrupt handler, but separated
1041 for clarity and better register allocation. */
1042 static int yellowfin_rx(struct net_device *dev)
1044 struct yellowfin_private *yp = netdev_priv(dev);
1045 int entry = yp->cur_rx % RX_RING_SIZE;
1046 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1048 if (yellowfin_debug > 4) {
1049 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %08x\n",
1050 entry, yp->rx_ring[entry].result_status);
1051 printk(KERN_DEBUG " #%d desc. %08x %08x %08x\n",
1052 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1053 yp->rx_ring[entry].result_status);
1056 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1058 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1059 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1065 if(!desc->result_status)
1067 pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1068 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1069 desc_status = le32_to_cpu(desc->result_status) >> 16;
1070 buf_addr = rx_skb->data;
1071 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1072 le32_to_cpu(desc->result_status)) & 0xffff;
1073 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1074 if (yellowfin_debug > 4)
1075 printk(KERN_DEBUG " %s() status was %04x\n",
1076 __func__, frame_status);
1079 if ( ! (desc_status & RX_EOP)) {
1081 netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %04x, data_size %d!\n",
1082 desc_status, data_size);
1083 dev->stats.rx_length_errors++;
1084 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1085 /* There was a error. */
1086 if (yellowfin_debug > 3)
1087 printk(KERN_DEBUG " %s() Rx error was %04x\n",
1088 __func__, frame_status);
1089 dev->stats.rx_errors++;
1090 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1091 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1092 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1093 if (frame_status < 0) dev->stats.rx_dropped++;
1094 } else if ( !(yp->drv_flags & IsGigabit) &&
1095 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1096 u8 status1 = buf_addr[data_size-2];
1097 u8 status2 = buf_addr[data_size-1];
1098 dev->stats.rx_errors++;
1099 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1100 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1101 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1102 if (status2 & 0x80) dev->stats.rx_dropped++;
1103 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1104 } else if ((yp->flags & HasMACAddrBug) &&
1105 memcmp(le32_to_cpu(yp->rx_ring_dma +
1106 entry*sizeof(struct yellowfin_desc)),
1107 dev->dev_addr, 6) != 0 &&
1108 memcmp(le32_to_cpu(yp->rx_ring_dma +
1109 entry*sizeof(struct yellowfin_desc)),
1110 "\377\377\377\377\377\377", 6) != 0) {
1111 if (bogus_rx++ == 0)
1112 netdev_warn(dev, "Bad frame to %pM\n",
1116 struct sk_buff *skb;
1117 int pkt_len = data_size -
1118 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1119 /* To verify: Yellowfin Length should omit the CRC! */
1121 #ifndef final_version
1122 if (yellowfin_debug > 4)
1123 printk(KERN_DEBUG " %s() normal Rx pkt length %d of %d, bogus_cnt %d\n",
1124 __func__, pkt_len, data_size, boguscnt);
1126 /* Check if the packet is long enough to just pass up the skbuff
1127 without copying to a properly sized skbuff. */
1128 if (pkt_len > rx_copybreak) {
1129 skb_put(skb = rx_skb, pkt_len);
1130 pci_unmap_single(yp->pci_dev,
1131 le32_to_cpu(yp->rx_ring[entry].addr),
1133 PCI_DMA_FROMDEVICE);
1134 yp->rx_skbuff[entry] = NULL;
1136 skb = dev_alloc_skb(pkt_len + 2);
1139 skb_reserve(skb, 2); /* 16 byte align the IP header */
1140 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1141 skb_put(skb, pkt_len);
1142 pci_dma_sync_single_for_device(yp->pci_dev,
1143 le32_to_cpu(desc->addr),
1145 PCI_DMA_FROMDEVICE);
1147 skb->protocol = eth_type_trans(skb, dev);
1149 dev->stats.rx_packets++;
1150 dev->stats.rx_bytes += pkt_len;
1152 entry = (++yp->cur_rx) % RX_RING_SIZE;
1155 /* Refill the Rx ring buffers. */
1156 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1157 entry = yp->dirty_rx % RX_RING_SIZE;
1158 if (yp->rx_skbuff[entry] == NULL) {
1159 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz + 2);
1161 break; /* Better luck next round. */
1162 yp->rx_skbuff[entry] = skb;
1163 skb->dev = dev; /* Mark as being used by this device. */
1164 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1165 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1166 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1168 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1169 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1171 yp->rx_ring[entry - 1].dbdma_cmd =
1172 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1174 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1175 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1182 static void yellowfin_error(struct net_device *dev, int intr_status)
1184 netdev_err(dev, "Something Wicked happened! %04x\n", intr_status);
1185 /* Hmmmmm, it's not clear what to do here. */
1186 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1187 dev->stats.tx_errors++;
1188 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1189 dev->stats.rx_errors++;
1192 static int yellowfin_close(struct net_device *dev)
1194 struct yellowfin_private *yp = netdev_priv(dev);
1195 void __iomem *ioaddr = yp->base;
1198 netif_stop_queue (dev);
1200 if (yellowfin_debug > 1) {
1201 netdev_printk(KERN_DEBUG, dev, "Shutting down ethercard, status was Tx %04x Rx %04x Int %02x\n",
1202 ioread16(ioaddr + TxStatus),
1203 ioread16(ioaddr + RxStatus),
1204 ioread16(ioaddr + IntrStatus));
1205 netdev_printk(KERN_DEBUG, dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1206 yp->cur_tx, yp->dirty_tx,
1207 yp->cur_rx, yp->dirty_rx);
1210 /* Disable interrupts by clearing the interrupt mask. */
1211 iowrite16(0x0000, ioaddr + IntrEnb);
1213 /* Stop the chip's Tx and Rx processes. */
1214 iowrite32(0x80000000, ioaddr + RxCtrl);
1215 iowrite32(0x80000000, ioaddr + TxCtrl);
1217 del_timer(&yp->timer);
1219 #if defined(__i386__)
1220 if (yellowfin_debug > 2) {
1221 printk(KERN_DEBUG " Tx ring at %08llx:\n",
1222 (unsigned long long)yp->tx_ring_dma);
1223 for (i = 0; i < TX_RING_SIZE*2; i++)
1224 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x %08x\n",
1225 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1226 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1227 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1228 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1229 for (i = 0; i < TX_RING_SIZE; i++)
1230 printk(KERN_DEBUG " #%d status %04x %04x %04x %04x\n",
1231 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1232 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1234 printk(KERN_DEBUG " Rx ring %08llx:\n",
1235 (unsigned long long)yp->rx_ring_dma);
1236 for (i = 0; i < RX_RING_SIZE; i++) {
1237 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x\n",
1238 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1239 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1240 yp->rx_ring[i].result_status);
1241 if (yellowfin_debug > 6) {
1242 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1246 for (j = 0; j < 0x50; j++)
1248 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1254 #endif /* __i386__ debugging only */
1256 free_irq(dev->irq, dev);
1258 /* Free all the skbuffs in the Rx queue. */
1259 for (i = 0; i < RX_RING_SIZE; i++) {
1260 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1261 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1262 if (yp->rx_skbuff[i]) {
1263 dev_kfree_skb(yp->rx_skbuff[i]);
1265 yp->rx_skbuff[i] = NULL;
1267 for (i = 0; i < TX_RING_SIZE; i++) {
1268 if (yp->tx_skbuff[i])
1269 dev_kfree_skb(yp->tx_skbuff[i]);
1270 yp->tx_skbuff[i] = NULL;
1273 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1274 if (yellowfin_debug > 0) {
1275 netdev_printk(KERN_DEBUG, dev, "Received %d frames that we should not have\n",
1283 /* Set or clear the multicast filter for this adaptor. */
1285 static void set_rx_mode(struct net_device *dev)
1287 struct yellowfin_private *yp = netdev_priv(dev);
1288 void __iomem *ioaddr = yp->base;
1289 u16 cfg_value = ioread16(ioaddr + Cnfg);
1291 /* Stop the Rx process to change any value. */
1292 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1293 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1294 iowrite16(0x000F, ioaddr + AddrMode);
1295 } else if ((netdev_mc_count(dev) > 64) ||
1296 (dev->flags & IFF_ALLMULTI)) {
1297 /* Too many to filter well, or accept all multicasts. */
1298 iowrite16(0x000B, ioaddr + AddrMode);
1299 } else if (!netdev_mc_empty(dev)) { /* Must use the multicast hash table. */
1300 struct netdev_hw_addr *ha;
1304 memset(hash_table, 0, sizeof(hash_table));
1305 netdev_for_each_mc_addr(ha, dev) {
1308 /* Due to a bug in the early chip versions, multiple filter
1309 slots must be set for each address. */
1310 if (yp->drv_flags & HasMulticastBug) {
1311 bit = (ether_crc_le(3, ha->addr) >> 3) & 0x3f;
1312 hash_table[bit >> 4] |= (1 << bit);
1313 bit = (ether_crc_le(4, ha->addr) >> 3) & 0x3f;
1314 hash_table[bit >> 4] |= (1 << bit);
1315 bit = (ether_crc_le(5, ha->addr) >> 3) & 0x3f;
1316 hash_table[bit >> 4] |= (1 << bit);
1318 bit = (ether_crc_le(6, ha->addr) >> 3) & 0x3f;
1319 hash_table[bit >> 4] |= (1 << bit);
1321 /* Copy the hash table to the chip. */
1322 for (i = 0; i < 4; i++)
1323 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1324 iowrite16(0x0003, ioaddr + AddrMode);
1325 } else { /* Normal, unicast/broadcast-only mode. */
1326 iowrite16(0x0001, ioaddr + AddrMode);
1328 /* Restart the Rx process. */
1329 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1332 static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1334 struct yellowfin_private *np = netdev_priv(dev);
1335 strcpy(info->driver, DRV_NAME);
1336 strcpy(info->version, DRV_VERSION);
1337 strcpy(info->bus_info, pci_name(np->pci_dev));
1340 static const struct ethtool_ops ethtool_ops = {
1341 .get_drvinfo = yellowfin_get_drvinfo
1344 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1346 struct yellowfin_private *np = netdev_priv(dev);
1347 void __iomem *ioaddr = np->base;
1348 struct mii_ioctl_data *data = if_mii(rq);
1351 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1352 data->phy_id = np->phys[0] & 0x1f;
1355 case SIOCGMIIREG: /* Read MII PHY register. */
1356 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1359 case SIOCSMIIREG: /* Write MII PHY register. */
1360 if (data->phy_id == np->phys[0]) {
1361 u16 value = data->val_in;
1362 switch (data->reg_num) {
1364 /* Check for autonegotiation on or reset. */
1365 np->medialock = (value & 0x9000) ? 0 : 1;
1367 np->full_duplex = (value & 0x0100) ? 1 : 0;
1369 case 4: np->advertising = value; break;
1371 /* Perhaps check_duplex(dev), depending on chip semantics. */
1373 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1381 static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1383 struct net_device *dev = pci_get_drvdata(pdev);
1384 struct yellowfin_private *np;
1387 np = netdev_priv(dev);
1389 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1391 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1392 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1393 unregister_netdev (dev);
1395 pci_iounmap(pdev, np->base);
1397 pci_release_regions (pdev);
1400 pci_set_drvdata(pdev, NULL);
1404 static struct pci_driver yellowfin_driver = {
1406 .id_table = yellowfin_pci_tbl,
1407 .probe = yellowfin_init_one,
1408 .remove = __devexit_p(yellowfin_remove_one),
1412 static int __init yellowfin_init (void)
1414 /* when a module, this is printed whether or not devices are found in probe */
1418 return pci_register_driver(&yellowfin_driver);
1422 static void __exit yellowfin_cleanup (void)
1424 pci_unregister_driver (&yellowfin_driver);
1428 module_init(yellowfin_init);
1429 module_exit(yellowfin_cleanup);