1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
6 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
7 * Jason McMullan <jason.mcmullan@netronome.com>
8 * Rolf Neugebauer <rolf.neugebauer@netronome.com>
10 * Multiplexes the NFP BARs between NFP internal resources and
11 * implements the PCIe specific interface for generic CPP bus access.
13 * The BARs are managed with refcounts and are allocated/acquired
14 * using target, token and offset/size matching. The generic CPP bus
15 * abstraction builds upon this BAR interface.
18 #include <asm/unaligned.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/kref.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/sort.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/pci.h>
32 #include "nfp6000/nfp6000.h"
34 #include "nfp6000_pcie.h"
36 #define NFP_PCIE_BAR(_pf) (0x30000 + ((_pf) & 7) * 0xc0)
37 #define NFP_PCIE_BAR_EXPLICIT_BAR0(_x, _y) \
38 (0x00000080 + (0x40 * ((_x) & 0x3)) + (0x10 * ((_y) & 0x3)))
39 #define NFP_PCIE_BAR_EXPLICIT_BAR0_SignalType(_x) (((_x) & 0x3) << 30)
40 #define NFP_PCIE_BAR_EXPLICIT_BAR0_SignalType_of(_x) (((_x) >> 30) & 0x3)
41 #define NFP_PCIE_BAR_EXPLICIT_BAR0_Token(_x) (((_x) & 0x3) << 28)
42 #define NFP_PCIE_BAR_EXPLICIT_BAR0_Token_of(_x) (((_x) >> 28) & 0x3)
43 #define NFP_PCIE_BAR_EXPLICIT_BAR0_Address(_x) (((_x) & 0xffffff) << 0)
44 #define NFP_PCIE_BAR_EXPLICIT_BAR0_Address_of(_x) (((_x) >> 0) & 0xffffff)
45 #define NFP_PCIE_BAR_EXPLICIT_BAR1(_x, _y) \
46 (0x00000084 + (0x40 * ((_x) & 0x3)) + (0x10 * ((_y) & 0x3)))
47 #define NFP_PCIE_BAR_EXPLICIT_BAR1_SignalRef(_x) (((_x) & 0x7f) << 24)
48 #define NFP_PCIE_BAR_EXPLICIT_BAR1_SignalRef_of(_x) (((_x) >> 24) & 0x7f)
49 #define NFP_PCIE_BAR_EXPLICIT_BAR1_DataMaster(_x) (((_x) & 0x3ff) << 14)
50 #define NFP_PCIE_BAR_EXPLICIT_BAR1_DataMaster_of(_x) (((_x) >> 14) & 0x3ff)
51 #define NFP_PCIE_BAR_EXPLICIT_BAR1_DataRef(_x) (((_x) & 0x3fff) << 0)
52 #define NFP_PCIE_BAR_EXPLICIT_BAR1_DataRef_of(_x) (((_x) >> 0) & 0x3fff)
53 #define NFP_PCIE_BAR_EXPLICIT_BAR2(_x, _y) \
54 (0x00000088 + (0x40 * ((_x) & 0x3)) + (0x10 * ((_y) & 0x3)))
55 #define NFP_PCIE_BAR_EXPLICIT_BAR2_Target(_x) (((_x) & 0xf) << 28)
56 #define NFP_PCIE_BAR_EXPLICIT_BAR2_Target_of(_x) (((_x) >> 28) & 0xf)
57 #define NFP_PCIE_BAR_EXPLICIT_BAR2_Action(_x) (((_x) & 0x1f) << 23)
58 #define NFP_PCIE_BAR_EXPLICIT_BAR2_Action_of(_x) (((_x) >> 23) & 0x1f)
59 #define NFP_PCIE_BAR_EXPLICIT_BAR2_Length(_x) (((_x) & 0x1f) << 18)
60 #define NFP_PCIE_BAR_EXPLICIT_BAR2_Length_of(_x) (((_x) >> 18) & 0x1f)
61 #define NFP_PCIE_BAR_EXPLICIT_BAR2_ByteMask(_x) (((_x) & 0xff) << 10)
62 #define NFP_PCIE_BAR_EXPLICIT_BAR2_ByteMask_of(_x) (((_x) >> 10) & 0xff)
63 #define NFP_PCIE_BAR_EXPLICIT_BAR2_SignalMaster(_x) (((_x) & 0x3ff) << 0)
64 #define NFP_PCIE_BAR_EXPLICIT_BAR2_SignalMaster_of(_x) (((_x) >> 0) & 0x3ff)
66 #define NFP_PCIE_BAR_PCIE2CPP_Action_BaseAddress(_x) (((_x) & 0x1f) << 16)
67 #define NFP_PCIE_BAR_PCIE2CPP_Action_BaseAddress_of(_x) (((_x) >> 16) & 0x1f)
68 #define NFP_PCIE_BAR_PCIE2CPP_BaseAddress(_x) (((_x) & 0xffff) << 0)
69 #define NFP_PCIE_BAR_PCIE2CPP_BaseAddress_of(_x) (((_x) >> 0) & 0xffff)
70 #define NFP_PCIE_BAR_PCIE2CPP_LengthSelect(_x) (((_x) & 0x3) << 27)
71 #define NFP_PCIE_BAR_PCIE2CPP_LengthSelect_of(_x) (((_x) >> 27) & 0x3)
72 #define NFP_PCIE_BAR_PCIE2CPP_LengthSelect_32BIT 0
73 #define NFP_PCIE_BAR_PCIE2CPP_LengthSelect_64BIT 1
74 #define NFP_PCIE_BAR_PCIE2CPP_LengthSelect_0BYTE 3
75 #define NFP_PCIE_BAR_PCIE2CPP_MapType(_x) (((_x) & 0x7) << 29)
76 #define NFP_PCIE_BAR_PCIE2CPP_MapType_of(_x) (((_x) >> 29) & 0x7)
77 #define NFP_PCIE_BAR_PCIE2CPP_MapType_FIXED 0
78 #define NFP_PCIE_BAR_PCIE2CPP_MapType_BULK 1
79 #define NFP_PCIE_BAR_PCIE2CPP_MapType_TARGET 2
80 #define NFP_PCIE_BAR_PCIE2CPP_MapType_GENERAL 3
81 #define NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT0 4
82 #define NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT1 5
83 #define NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT2 6
84 #define NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT3 7
85 #define NFP_PCIE_BAR_PCIE2CPP_Target_BaseAddress(_x) (((_x) & 0xf) << 23)
86 #define NFP_PCIE_BAR_PCIE2CPP_Target_BaseAddress_of(_x) (((_x) >> 23) & 0xf)
87 #define NFP_PCIE_BAR_PCIE2CPP_Token_BaseAddress(_x) (((_x) & 0x3) << 21)
88 #define NFP_PCIE_BAR_PCIE2CPP_Token_BaseAddress_of(_x) (((_x) >> 21) & 0x3)
89 #define NFP_PCIE_EM 0x020000
90 #define NFP_PCIE_SRAM 0x000000
92 /* Minimal size of the PCIe cfg memory we depend on being mapped,
93 * queue controller and DMA controller don't have to be covered.
95 #define NFP_PCI_MIN_MAP_SIZE 0x080000
97 #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize)
98 #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize)
99 #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2))
100 #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4))
101 #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4))
103 #define NFP_PCIE_CFG_BAR_PCIETOCPPEXPANSIONBAR(bar, slot) \
104 (0x400 + ((bar) * 8 + (slot)) * 4)
106 #define NFP_PCIE_CPP_BAR_PCIETOCPPEXPANSIONBAR(bar, slot) \
107 (((bar) * 8 + (slot)) * 4)
109 /* The number of explicit BARs to reserve.
110 * Minimum is 0, maximum is 4 on the NFP6000.
111 * The NFP3800 can have only one per PF.
113 #define NFP_PCIE_EXPLICIT_BARS 2
116 struct nfp6000_area_priv;
119 * struct nfp_bar - describes BAR configuration and usage
120 * @nfp: backlink to owner
121 * @barcfg: cached contents of BAR config CSR
122 * @base: the BAR's base CPP offset
123 * @mask: mask for the BAR aperture (read only)
124 * @bitsize: bitsize of BAR aperture (read only)
125 * @index: index of the BAR
126 * @refcnt: number of current users
127 * @iomem: mapped IO memory
128 * @resource: iomem resource window
131 struct nfp6000_pcie *nfp;
133 u64 base; /* CPP address base */
134 u64 mask; /* Bit mask of the bar */
135 u32 bitsize; /* Bit size of the bar */
140 struct resource *resource;
143 #define NFP_PCI_BAR_MAX (PCI_64BIT_BAR_COUNT * 8)
145 struct nfp6000_pcie {
146 struct pci_dev *pdev;
149 /* PCI BAR management */
150 spinlock_t bar_lock; /* Protect the PCI2CPP BAR cache */
152 struct nfp_bar bar[NFP_PCI_BAR_MAX];
153 wait_queue_head_t bar_waiters;
155 /* Reserved BAR access */
159 void __iomem *expl[4];
162 /* Explicit IO access */
164 struct mutex mutex; /* Lock access to this explicit group */
176 static u32 nfp_bar_maptype(struct nfp_bar *bar)
178 return NFP_PCIE_BAR_PCIE2CPP_MapType_of(bar->barcfg);
181 static resource_size_t nfp_bar_resource_len(struct nfp_bar *bar)
183 return pci_resource_len(bar->nfp->pdev, (bar->index / 8) * 2) / 8;
186 static resource_size_t nfp_bar_resource_start(struct nfp_bar *bar)
188 return pci_resource_start(bar->nfp->pdev, (bar->index / 8) * 2)
189 + nfp_bar_resource_len(bar) * (bar->index & 7);
192 #define TARGET_WIDTH_32 4
193 #define TARGET_WIDTH_64 8
196 compute_bar(const struct nfp6000_pcie *nfp, const struct nfp_bar *bar,
197 u32 *bar_config, u64 *bar_base,
198 int tgt, int act, int tok, u64 offset, size_t size, int width)
203 if (tgt >= NFP_CPP_NUM_TARGETS)
208 newcfg = NFP_PCIE_BAR_PCIE2CPP_LengthSelect(
209 NFP_PCIE_BAR_PCIE2CPP_LengthSelect_64BIT);
212 newcfg = NFP_PCIE_BAR_PCIE2CPP_LengthSelect(
213 NFP_PCIE_BAR_PCIE2CPP_LengthSelect_32BIT);
216 newcfg = NFP_PCIE_BAR_PCIE2CPP_LengthSelect(
217 NFP_PCIE_BAR_PCIE2CPP_LengthSelect_0BYTE);
223 if (act != NFP_CPP_ACTION_RW && act != 0) {
224 /* Fixed CPP mapping with specific action */
225 u64 mask = ~(NFP_PCIE_P2C_FIXED_SIZE(bar) - 1);
227 newcfg |= NFP_PCIE_BAR_PCIE2CPP_MapType(
228 NFP_PCIE_BAR_PCIE2CPP_MapType_FIXED);
229 newcfg |= NFP_PCIE_BAR_PCIE2CPP_Target_BaseAddress(tgt);
230 newcfg |= NFP_PCIE_BAR_PCIE2CPP_Action_BaseAddress(act);
231 newcfg |= NFP_PCIE_BAR_PCIE2CPP_Token_BaseAddress(tok);
233 if ((offset & mask) != ((offset + size - 1) & mask))
239 u64 mask = ~(NFP_PCIE_P2C_BULK_SIZE(bar) - 1);
242 newcfg |= NFP_PCIE_BAR_PCIE2CPP_MapType(
243 NFP_PCIE_BAR_PCIE2CPP_MapType_BULK);
244 newcfg |= NFP_PCIE_BAR_PCIE2CPP_Target_BaseAddress(tgt);
245 newcfg |= NFP_PCIE_BAR_PCIE2CPP_Token_BaseAddress(tok);
247 if ((offset & mask) != ((offset + size - 1) & mask))
255 if (bar->bitsize < bitsize)
258 newcfg |= offset >> bitsize;
264 *bar_config = newcfg;
270 nfp6000_bar_write(struct nfp6000_pcie *nfp, struct nfp_bar *bar, u32 newcfg)
275 base = bar->index >> 3;
276 slot = bar->index & 7;
278 if (nfp->iomem.csr) {
279 xbar = NFP_PCIE_CPP_BAR_PCIETOCPPEXPANSIONBAR(base, slot);
280 writel(newcfg, nfp->iomem.csr + xbar);
281 /* Readback to ensure BAR is flushed */
282 readl(nfp->iomem.csr + xbar);
284 xbar = NFP_PCIE_CFG_BAR_PCIETOCPPEXPANSIONBAR(base, slot);
285 pci_write_config_dword(nfp->pdev, xbar, newcfg);
288 bar->barcfg = newcfg;
294 reconfigure_bar(struct nfp6000_pcie *nfp, struct nfp_bar *bar,
295 int tgt, int act, int tok, u64 offset, size_t size, int width)
301 err = compute_bar(nfp, bar, &newcfg, &newbase,
302 tgt, act, tok, offset, size, width);
308 return nfp6000_bar_write(nfp, bar, newcfg);
311 /* Check if BAR can be used with the given parameters. */
312 static int matching_bar(struct nfp_bar *bar, u32 tgt, u32 act, u32 tok,
313 u64 offset, size_t size, int width)
315 int bartgt, baract, bartok;
319 maptype = NFP_PCIE_BAR_PCIE2CPP_MapType_of(bar->barcfg);
320 bartgt = NFP_PCIE_BAR_PCIE2CPP_Target_BaseAddress_of(bar->barcfg);
321 bartok = NFP_PCIE_BAR_PCIE2CPP_Token_BaseAddress_of(bar->barcfg);
322 baract = NFP_PCIE_BAR_PCIE2CPP_Action_BaseAddress_of(bar->barcfg);
324 barwidth = NFP_PCIE_BAR_PCIE2CPP_LengthSelect_of(bar->barcfg);
326 case NFP_PCIE_BAR_PCIE2CPP_LengthSelect_32BIT:
329 case NFP_PCIE_BAR_PCIE2CPP_LengthSelect_64BIT:
332 case NFP_PCIE_BAR_PCIE2CPP_LengthSelect_0BYTE:
341 case NFP_PCIE_BAR_PCIE2CPP_MapType_TARGET:
344 case NFP_PCIE_BAR_PCIE2CPP_MapType_BULK:
345 baract = NFP_CPP_ACTION_RW;
347 act = NFP_CPP_ACTION_RW;
349 case NFP_PCIE_BAR_PCIE2CPP_MapType_FIXED:
352 /* We don't match explicit bars through the area interface */
356 /* Make sure to match up the width */
357 if (barwidth != width)
360 if ((bartgt < 0 || bartgt == tgt) &&
361 (bartok < 0 || bartok == tok) &&
363 bar->base <= offset &&
364 (bar->base + (1 << bar->bitsize)) >= (offset + size))
372 find_matching_bar(struct nfp6000_pcie *nfp,
373 u32 tgt, u32 act, u32 tok, u64 offset, size_t size, int width)
377 for (n = 0; n < nfp->bars; n++) {
378 struct nfp_bar *bar = &nfp->bar[n];
380 if (matching_bar(bar, tgt, act, tok, offset, size, width))
387 /* Return EAGAIN if no resource is available */
389 find_unused_bar_noblock(const struct nfp6000_pcie *nfp,
390 int tgt, int act, int tok,
391 u64 offset, size_t size, int width)
395 for (n = 0; n < nfp->bars; n++) {
396 const struct nfp_bar *bar = &nfp->bar[n];
402 /* Just check to see if we can make it fit... */
403 err = compute_bar(nfp, bar, NULL, NULL,
404 tgt, act, tok, offset, size, width);
408 if (!atomic_read(&bar->refcnt))
414 if (WARN(!busy, "No suitable BAR found for request tgt:0x%x act:0x%x tok:0x%x off:0x%llx size:%zd width:%d\n",
415 tgt, act, tok, offset, size, width))
422 find_unused_bar_and_lock(struct nfp6000_pcie *nfp,
423 int tgt, int act, int tok,
424 u64 offset, size_t size, int width)
429 spin_lock_irqsave(&nfp->bar_lock, flags);
431 n = find_unused_bar_noblock(nfp, tgt, act, tok, offset, size, width);
433 spin_unlock_irqrestore(&nfp->bar_lock, flags);
435 __release(&nfp->bar_lock);
440 static void nfp_bar_get(struct nfp6000_pcie *nfp, struct nfp_bar *bar)
442 atomic_inc(&bar->refcnt);
445 static void nfp_bar_put(struct nfp6000_pcie *nfp, struct nfp_bar *bar)
447 if (atomic_dec_and_test(&bar->refcnt))
448 wake_up_interruptible(&nfp->bar_waiters);
452 nfp_wait_for_bar(struct nfp6000_pcie *nfp, int *barnum,
453 u32 tgt, u32 act, u32 tok, u64 offset, size_t size, int width)
455 return wait_event_interruptible(nfp->bar_waiters,
456 (*barnum = find_unused_bar_and_lock(nfp, tgt, act, tok,
457 offset, size, width))
462 nfp_alloc_bar(struct nfp6000_pcie *nfp,
463 u32 tgt, u32 act, u32 tok,
464 u64 offset, size_t size, int width, int nonblocking)
466 unsigned long irqflags;
469 if (size > (1 << 24))
472 spin_lock_irqsave(&nfp->bar_lock, irqflags);
473 barnum = find_matching_bar(nfp, tgt, act, tok, offset, size, width);
475 /* Found a perfect match. */
476 nfp_bar_get(nfp, &nfp->bar[barnum]);
477 spin_unlock_irqrestore(&nfp->bar_lock, irqflags);
481 barnum = find_unused_bar_noblock(nfp, tgt, act, tok,
482 offset, size, width);
487 /* Wait until a BAR becomes available. The
488 * find_unused_bar function will reclaim the bar_lock
489 * if a free BAR is found.
491 spin_unlock_irqrestore(&nfp->bar_lock, irqflags);
492 retval = nfp_wait_for_bar(nfp, &barnum, tgt, act, tok,
493 offset, size, width);
496 __acquire(&nfp->bar_lock);
499 nfp_bar_get(nfp, &nfp->bar[barnum]);
500 retval = reconfigure_bar(nfp, &nfp->bar[barnum],
501 tgt, act, tok, offset, size, width);
503 nfp_bar_put(nfp, &nfp->bar[barnum]);
508 spin_unlock_irqrestore(&nfp->bar_lock, irqflags);
512 static void disable_bars(struct nfp6000_pcie *nfp);
514 static int bar_cmp(const void *aptr, const void *bptr)
516 const struct nfp_bar *a = aptr, *b = bptr;
518 if (a->bitsize == b->bitsize)
519 return a->index - b->index;
521 return a->bitsize - b->bitsize;
524 /* Map all PCI bars and fetch the actual BAR configurations from the
525 * board. We assume that the BAR with the PCIe config block is
528 * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM)
529 * BAR0.1: Reserved for XPB access (for MSI-X access to PCIe PBA)
532 * BAR0.4: Reserved for Explicit 0.0-0.3 access
533 * BAR0.5: Reserved for Explicit 1.0-1.3 access
534 * BAR0.6: Reserved for Explicit 2.0-2.3 access
535 * BAR0.7: Reserved for Explicit 3.0-3.3 access
540 static int enable_bars(struct nfp6000_pcie *nfp, u16 interface)
542 const u32 barcfg_msix_general =
543 NFP_PCIE_BAR_PCIE2CPP_MapType(
544 NFP_PCIE_BAR_PCIE2CPP_MapType_GENERAL) |
545 NFP_PCIE_BAR_PCIE2CPP_LengthSelect_32BIT;
546 const u32 barcfg_msix_xpb =
547 NFP_PCIE_BAR_PCIE2CPP_MapType(
548 NFP_PCIE_BAR_PCIE2CPP_MapType_BULK) |
549 NFP_PCIE_BAR_PCIE2CPP_LengthSelect_32BIT |
550 NFP_PCIE_BAR_PCIE2CPP_Target_BaseAddress(
551 NFP_CPP_TARGET_ISLAND_XPB);
552 const u32 barcfg_explicit[4] = {
553 NFP_PCIE_BAR_PCIE2CPP_MapType(
554 NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT0),
555 NFP_PCIE_BAR_PCIE2CPP_MapType(
556 NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT1),
557 NFP_PCIE_BAR_PCIE2CPP_MapType(
558 NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT2),
559 NFP_PCIE_BAR_PCIE2CPP_MapType(
560 NFP_PCIE_BAR_PCIE2CPP_MapType_EXPLICIT3),
562 char status_msg[196] = {};
563 int i, err, bars_free;
569 snprintf(status_msg, sizeof(status_msg) - 1, "RESERVED BARs: ");
570 end = status_msg + sizeof(status_msg) - 1;
573 for (i = 0; i < ARRAY_SIZE(nfp->bar); i++, bar++) {
574 struct resource *res;
576 res = &nfp->pdev->resource[(i >> 3) * 2];
578 /* Skip over BARs that are not IORESOURCE_MEM */
579 if (!(resource_type(res) & IORESOURCE_MEM)) {
589 bar->mask = nfp_bar_resource_len(bar) - 1;
590 bar->bitsize = fls(bar->mask);
595 nfp->bars = bar - &nfp->bar[0];
597 dev_err(nfp->dev, "No usable BARs found!\n");
601 bars_free = nfp->bars;
603 /* Convert unit ID (0..3) to signal master/data master ID (0x40..0x70)
605 mutex_init(&nfp->expl.mutex);
607 nfp->expl.master_id = ((NFP_CPP_INTERFACE_UNIT_of(interface) & 3) + 4)
609 nfp->expl.signal_ref = 0x10;
611 /* Configure, and lock, BAR0.0 for General Target use (MSI-X SRAM) */
613 if (nfp_bar_resource_len(bar) >= NFP_PCI_MIN_MAP_SIZE)
614 bar->iomem = ioremap(nfp_bar_resource_start(bar),
615 nfp_bar_resource_len(bar));
619 msg += scnprintf(msg, end - msg, "0.0: General/MSI-X SRAM, ");
620 atomic_inc(&bar->refcnt);
623 nfp6000_bar_write(nfp, bar, barcfg_msix_general);
625 nfp->expl.data = bar->iomem + NFP_PCIE_SRAM + 0x1000;
627 switch (nfp->pdev->device) {
628 case PCI_DEVICE_ID_NETRONOME_NFP3800:
629 pf = nfp->pdev->devfn & 7;
630 nfp->iomem.csr = bar->iomem + NFP_PCIE_BAR(pf);
632 case PCI_DEVICE_ID_NETRONOME_NFP4000:
633 case PCI_DEVICE_ID_NETRONOME_NFP5000:
634 case PCI_DEVICE_ID_NETRONOME_NFP6000:
635 nfp->iomem.csr = bar->iomem + NFP_PCIE_BAR(0);
638 dev_err(nfp->dev, "Unsupported device ID: %04hx!\n",
643 nfp->iomem.em = bar->iomem + NFP_PCIE_EM;
646 switch (nfp->pdev->device) {
647 case PCI_DEVICE_ID_NETRONOME_NFP3800:
650 case PCI_DEVICE_ID_NETRONOME_NFP4000:
651 case PCI_DEVICE_ID_NETRONOME_NFP5000:
652 case PCI_DEVICE_ID_NETRONOME_NFP6000:
656 dev_err(nfp->dev, "Unsupported device ID: %04hx!\n",
662 /* Configure, and lock, BAR0.1 for PCIe XPB (MSI-X PBA) */
664 msg += scnprintf(msg, end - msg, "0.1: PCIe XPB/MSI-X PBA, ");
665 atomic_inc(&bar->refcnt);
668 nfp6000_bar_write(nfp, bar, barcfg_msix_xpb);
670 /* Use BAR0.4..BAR0.7 for EXPL IO */
671 for (i = 0; i < 4; i++) {
674 if (i >= NFP_PCIE_EXPLICIT_BARS || i >= expl_groups) {
675 nfp->expl.group[i].bitsize = 0;
679 bar = &nfp->bar[4 + i];
680 bar->iomem = ioremap(nfp_bar_resource_start(bar),
681 nfp_bar_resource_len(bar));
683 msg += scnprintf(msg, end - msg,
684 "0.%d: Explicit%d, ", 4 + i, i);
685 atomic_inc(&bar->refcnt);
688 nfp->expl.group[i].bitsize = bar->bitsize;
689 nfp->expl.group[i].addr = bar->iomem;
690 nfp6000_bar_write(nfp, bar, barcfg_explicit[i]);
692 for (j = 0; j < 4; j++)
693 nfp->expl.group[i].free[j] = true;
695 nfp->iomem.expl[i] = bar->iomem;
698 /* Sort bars by bit size - use the smallest possible first. */
699 sort(&nfp->bar[0], nfp->bars, sizeof(nfp->bar[0]),
702 dev_info(nfp->dev, "%sfree: %d/%d\n", status_msg, bars_free, nfp->bars);
707 if (nfp->bar[0].iomem)
708 iounmap(nfp->bar[0].iomem);
712 static void disable_bars(struct nfp6000_pcie *nfp)
714 struct nfp_bar *bar = &nfp->bar[0];
717 for (n = 0; n < nfp->bars; n++, bar++) {
726 * Generic CPP bus access interface.
729 struct nfp6000_area_priv {
748 struct resource resource;
751 static int nfp6000_area_init(struct nfp_cpp_area *area, u32 dest,
752 unsigned long long address, unsigned long size)
754 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
755 u32 target = NFP_CPP_ID_TARGET_of(dest);
756 u32 action = NFP_CPP_ID_ACTION_of(dest);
757 u32 token = NFP_CPP_ID_TOKEN_of(dest);
760 pp = nfp_target_pushpull(NFP_CPP_ID(target, action, token), address);
764 priv->width.read = PUSH_WIDTH(pp);
765 priv->width.write = PULL_WIDTH(pp);
766 if (priv->width.read > 0 &&
767 priv->width.write > 0 &&
768 priv->width.read != priv->width.write) {
772 if (priv->width.read > 0)
773 priv->width.bar = priv->width.read;
775 priv->width.bar = priv->width.write;
777 atomic_set(&priv->refcnt, 0);
780 priv->target = target;
781 priv->action = action;
783 priv->offset = address;
785 memset(&priv->resource, 0, sizeof(priv->resource));
790 static void nfp6000_area_cleanup(struct nfp_cpp_area *area)
794 static void priv_area_get(struct nfp_cpp_area *area)
796 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
798 atomic_inc(&priv->refcnt);
801 static int priv_area_put(struct nfp_cpp_area *area)
803 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
805 if (WARN_ON(!atomic_read(&priv->refcnt)))
808 return atomic_dec_and_test(&priv->refcnt);
811 static int nfp6000_area_acquire(struct nfp_cpp_area *area)
813 struct nfp6000_pcie *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area));
814 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
818 /* Already allocated. */
823 barnum = nfp_alloc_bar(nfp, priv->target, priv->action, priv->token,
824 priv->offset, priv->size, priv->width.bar, 1);
830 priv->bar = &nfp->bar[barnum];
832 /* Calculate offset into BAR. */
833 if (nfp_bar_maptype(priv->bar) ==
834 NFP_PCIE_BAR_PCIE2CPP_MapType_GENERAL) {
835 priv->bar_offset = priv->offset &
836 (NFP_PCIE_P2C_GENERAL_SIZE(priv->bar) - 1);
837 priv->bar_offset += NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(
838 priv->bar, priv->target);
839 priv->bar_offset += NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(
840 priv->bar, priv->token);
842 priv->bar_offset = priv->offset & priv->bar->mask;
845 /* We don't actually try to acquire the resource area using
846 * request_resource. This would prevent sharing the mapped
847 * BAR between multiple CPP areas and prevent us from
848 * effectively utilizing the limited amount of BAR resources.
850 priv->phys = nfp_bar_resource_start(priv->bar) + priv->bar_offset;
851 priv->resource.name = nfp_cpp_area_name(area);
852 priv->resource.start = priv->phys;
853 priv->resource.end = priv->resource.start + priv->size - 1;
854 priv->resource.flags = IORESOURCE_MEM;
856 /* If the bar is already mapped in, use its mapping */
857 if (priv->bar->iomem)
858 priv->iomem = priv->bar->iomem + priv->bar_offset;
860 /* Must have been too big. Sub-allocate. */
861 priv->iomem = ioremap(priv->phys, priv->size);
863 if (IS_ERR_OR_NULL(priv->iomem)) {
864 dev_err(nfp->dev, "Can't ioremap() a %d byte region of BAR %d\n",
865 (int)priv->size, priv->bar->index);
866 err = !priv->iomem ? -ENOMEM : PTR_ERR(priv->iomem);
868 goto err_iomem_remap;
875 nfp_bar_put(nfp, priv->bar);
881 static void nfp6000_area_release(struct nfp_cpp_area *area)
883 struct nfp6000_pcie *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area));
884 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
886 if (!priv_area_put(area))
889 if (!priv->bar->iomem)
890 iounmap(priv->iomem);
892 nfp_bar_put(nfp, priv->bar);
898 static phys_addr_t nfp6000_area_phys(struct nfp_cpp_area *area)
900 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
905 static void __iomem *nfp6000_area_iomem(struct nfp_cpp_area *area)
907 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
912 static struct resource *nfp6000_area_resource(struct nfp_cpp_area *area)
914 /* Use the BAR resource as the resource for the CPP area.
915 * This enables us to share the BAR among multiple CPP areas
916 * without resource conflicts.
918 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
920 return priv->bar->resource;
923 static int nfp6000_area_read(struct nfp_cpp_area *area, void *kernel_vaddr,
924 unsigned long offset, unsigned int length)
926 u64 __maybe_unused *wrptr64 = kernel_vaddr;
927 const u64 __iomem __maybe_unused *rdptr64;
928 struct nfp6000_area_priv *priv;
929 u32 *wrptr32 = kernel_vaddr;
930 const u32 __iomem *rdptr32;
933 priv = nfp_cpp_area_priv(area);
934 rdptr64 = priv->iomem + offset;
935 rdptr32 = priv->iomem + offset;
937 if (offset + length > priv->size)
940 width = priv->width.read;
944 /* MU reads via a PCIe2CPP BAR support 32bit (and other) lengths */
945 if (priv->target == (NFP_CPP_TARGET_MU & NFP_CPP_TARGET_ID_MASK) &&
946 priv->action == NFP_CPP_ACTION_RW &&
947 (offset % sizeof(u64) == 4 || length % sizeof(u64) == 4))
948 width = TARGET_WIDTH_32;
950 /* Unaligned? Translate to an explicit access */
951 if ((priv->offset + offset) & (width - 1))
952 return nfp_cpp_explicit_read(nfp_cpp_area_cpp(area),
953 NFP_CPP_ID(priv->target,
956 priv->offset + offset,
957 kernel_vaddr, length, width);
959 if (WARN_ON(!priv->bar))
963 case TARGET_WIDTH_32:
964 if (offset % sizeof(u32) != 0 || length % sizeof(u32) != 0)
967 for (n = 0; n < length; n += sizeof(u32))
968 *wrptr32++ = __raw_readl(rdptr32++);
971 case TARGET_WIDTH_64:
972 if (offset % sizeof(u64) != 0 || length % sizeof(u64) != 0)
975 for (n = 0; n < length; n += sizeof(u64))
976 *wrptr64++ = __raw_readq(rdptr64++);
985 nfp6000_area_write(struct nfp_cpp_area *area,
986 const void *kernel_vaddr,
987 unsigned long offset, unsigned int length)
989 const u64 __maybe_unused *rdptr64 = kernel_vaddr;
990 u64 __iomem __maybe_unused *wrptr64;
991 const u32 *rdptr32 = kernel_vaddr;
992 struct nfp6000_area_priv *priv;
993 u32 __iomem *wrptr32;
996 priv = nfp_cpp_area_priv(area);
997 wrptr64 = priv->iomem + offset;
998 wrptr32 = priv->iomem + offset;
1000 if (offset + length > priv->size)
1003 width = priv->width.write;
1007 /* MU writes via a PCIe2CPP BAR support 32bit (and other) lengths */
1008 if (priv->target == (NFP_CPP_TARGET_ID_MASK & NFP_CPP_TARGET_MU) &&
1009 priv->action == NFP_CPP_ACTION_RW &&
1010 (offset % sizeof(u64) == 4 || length % sizeof(u64) == 4))
1011 width = TARGET_WIDTH_32;
1013 /* Unaligned? Translate to an explicit access */
1014 if ((priv->offset + offset) & (width - 1))
1015 return nfp_cpp_explicit_write(nfp_cpp_area_cpp(area),
1016 NFP_CPP_ID(priv->target,
1019 priv->offset + offset,
1020 kernel_vaddr, length, width);
1022 if (WARN_ON(!priv->bar))
1026 case TARGET_WIDTH_32:
1027 if (offset % sizeof(u32) != 0 || length % sizeof(u32) != 0)
1030 for (n = 0; n < length; n += sizeof(u32)) {
1031 __raw_writel(*rdptr32++, wrptr32++);
1036 case TARGET_WIDTH_64:
1037 if (offset % sizeof(u64) != 0 || length % sizeof(u64) != 0)
1040 for (n = 0; n < length; n += sizeof(u64)) {
1041 __raw_writeq(*rdptr64++, wrptr64++);
1051 struct nfp6000_explicit_priv {
1052 struct nfp6000_pcie *nfp;
1062 static int nfp6000_explicit_acquire(struct nfp_cpp_explicit *expl)
1064 struct nfp6000_pcie *nfp = nfp_cpp_priv(nfp_cpp_explicit_cpp(expl));
1065 struct nfp6000_explicit_priv *priv = nfp_cpp_explicit_priv(expl);
1068 mutex_lock(&nfp->expl.mutex);
1069 for (i = 0; i < ARRAY_SIZE(nfp->expl.group); i++) {
1070 if (!nfp->expl.group[i].bitsize)
1073 for (j = 0; j < ARRAY_SIZE(nfp->expl.group[i].free); j++) {
1076 if (!nfp->expl.group[i].free[j])
1080 priv->bar.group = i;
1082 priv->bitsize = nfp->expl.group[i].bitsize - 2;
1084 data_offset = (priv->bar.group << 9) +
1085 (priv->bar.area << 7);
1086 priv->data = nfp->expl.data + data_offset;
1087 priv->addr = nfp->expl.group[i].addr +
1088 (priv->bar.area << priv->bitsize);
1089 nfp->expl.group[i].free[j] = false;
1091 mutex_unlock(&nfp->expl.mutex);
1095 mutex_unlock(&nfp->expl.mutex);
1100 static void nfp6000_explicit_release(struct nfp_cpp_explicit *expl)
1102 struct nfp6000_explicit_priv *priv = nfp_cpp_explicit_priv(expl);
1103 struct nfp6000_pcie *nfp = priv->nfp;
1105 mutex_lock(&nfp->expl.mutex);
1106 nfp->expl.group[priv->bar.group].free[priv->bar.area] = true;
1107 mutex_unlock(&nfp->expl.mutex);
1110 static int nfp6000_explicit_put(struct nfp_cpp_explicit *expl,
1111 const void *buff, size_t len)
1113 struct nfp6000_explicit_priv *priv = nfp_cpp_explicit_priv(expl);
1114 const u32 *src = buff;
1117 for (i = 0; i < len; i += sizeof(u32))
1118 writel(*(src++), priv->data + i);
1124 nfp6000_explicit_do(struct nfp_cpp_explicit *expl,
1125 const struct nfp_cpp_explicit_command *cmd, u64 address)
1127 struct nfp6000_explicit_priv *priv = nfp_cpp_explicit_priv(expl);
1128 u8 signal_master, signal_ref, data_master;
1129 struct nfp6000_pcie *nfp = priv->nfp;
1135 sigmask |= 1 << cmd->siga;
1137 sigmask |= 1 << cmd->sigb;
1139 signal_master = cmd->signal_master;
1141 signal_master = nfp->expl.master_id;
1143 signal_ref = cmd->signal_ref;
1144 if (signal_master == nfp->expl.master_id)
1145 signal_ref = nfp->expl.signal_ref +
1146 ((priv->bar.group * 4 + priv->bar.area) << 1);
1148 data_master = cmd->data_master;
1150 data_master = nfp->expl.master_id;
1152 data_ref = cmd->data_ref;
1153 if (data_master == nfp->expl.master_id)
1155 (priv->bar.group << 9) + (priv->bar.area << 7);
1157 csr[0] = NFP_PCIE_BAR_EXPLICIT_BAR0_SignalType(sigmask) |
1158 NFP_PCIE_BAR_EXPLICIT_BAR0_Token(
1159 NFP_CPP_ID_TOKEN_of(cmd->cpp_id)) |
1160 NFP_PCIE_BAR_EXPLICIT_BAR0_Address(address >> 16);
1162 csr[1] = NFP_PCIE_BAR_EXPLICIT_BAR1_SignalRef(signal_ref) |
1163 NFP_PCIE_BAR_EXPLICIT_BAR1_DataMaster(data_master) |
1164 NFP_PCIE_BAR_EXPLICIT_BAR1_DataRef(data_ref);
1166 csr[2] = NFP_PCIE_BAR_EXPLICIT_BAR2_Target(
1167 NFP_CPP_ID_TARGET_of(cmd->cpp_id)) |
1168 NFP_PCIE_BAR_EXPLICIT_BAR2_Action(
1169 NFP_CPP_ID_ACTION_of(cmd->cpp_id)) |
1170 NFP_PCIE_BAR_EXPLICIT_BAR2_Length(cmd->len) |
1171 NFP_PCIE_BAR_EXPLICIT_BAR2_ByteMask(cmd->byte_mask) |
1172 NFP_PCIE_BAR_EXPLICIT_BAR2_SignalMaster(signal_master);
1174 if (nfp->iomem.csr) {
1175 writel(csr[0], nfp->iomem.csr +
1176 NFP_PCIE_BAR_EXPLICIT_BAR0(priv->bar.group,
1178 writel(csr[1], nfp->iomem.csr +
1179 NFP_PCIE_BAR_EXPLICIT_BAR1(priv->bar.group,
1181 writel(csr[2], nfp->iomem.csr +
1182 NFP_PCIE_BAR_EXPLICIT_BAR2(priv->bar.group,
1184 /* Readback to ensure BAR is flushed */
1185 readl(nfp->iomem.csr +
1186 NFP_PCIE_BAR_EXPLICIT_BAR0(priv->bar.group,
1188 readl(nfp->iomem.csr +
1189 NFP_PCIE_BAR_EXPLICIT_BAR1(priv->bar.group,
1191 readl(nfp->iomem.csr +
1192 NFP_PCIE_BAR_EXPLICIT_BAR2(priv->bar.group,
1195 pci_write_config_dword(nfp->pdev, 0x400 +
1196 NFP_PCIE_BAR_EXPLICIT_BAR0(
1197 priv->bar.group, priv->bar.area),
1200 pci_write_config_dword(nfp->pdev, 0x400 +
1201 NFP_PCIE_BAR_EXPLICIT_BAR1(
1202 priv->bar.group, priv->bar.area),
1205 pci_write_config_dword(nfp->pdev, 0x400 +
1206 NFP_PCIE_BAR_EXPLICIT_BAR2(
1207 priv->bar.group, priv->bar.area),
1211 /* Issue the 'kickoff' transaction */
1212 readb(priv->addr + (address & ((1 << priv->bitsize) - 1)));
1217 static int nfp6000_explicit_get(struct nfp_cpp_explicit *expl,
1218 void *buff, size_t len)
1220 struct nfp6000_explicit_priv *priv = nfp_cpp_explicit_priv(expl);
1224 for (i = 0; i < len; i += sizeof(u32))
1225 *(dst++) = readl(priv->data + i);
1230 static int nfp6000_init(struct nfp_cpp *cpp)
1232 nfp_cpp_area_cache_add(cpp, SZ_64K);
1233 nfp_cpp_area_cache_add(cpp, SZ_64K);
1234 nfp_cpp_area_cache_add(cpp, SZ_256K);
1239 static void nfp6000_free(struct nfp_cpp *cpp)
1241 struct nfp6000_pcie *nfp = nfp_cpp_priv(cpp);
1247 static int nfp6000_read_serial(struct device *dev, u8 *serial)
1249 struct pci_dev *pdev = to_pci_dev(dev);
1253 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
1255 dev_err(dev, "can't find PCIe Serial Number Capability\n");
1259 pci_read_config_dword(pdev, pos + 4, ®);
1260 put_unaligned_be16(reg >> 16, serial + 4);
1261 pci_read_config_dword(pdev, pos + 8, ®);
1262 put_unaligned_be32(reg, serial);
1267 static int nfp6000_get_interface(struct device *dev)
1269 struct pci_dev *pdev = to_pci_dev(dev);
1273 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
1275 dev_err(dev, "can't find PCIe Serial Number Capability\n");
1279 pci_read_config_dword(pdev, pos + 4, ®);
1281 return reg & 0xffff;
1284 static const struct nfp_cpp_operations nfp6000_pcie_ops = {
1285 .owner = THIS_MODULE,
1287 .init = nfp6000_init,
1288 .free = nfp6000_free,
1290 .read_serial = nfp6000_read_serial,
1291 .get_interface = nfp6000_get_interface,
1293 .area_priv_size = sizeof(struct nfp6000_area_priv),
1294 .area_init = nfp6000_area_init,
1295 .area_cleanup = nfp6000_area_cleanup,
1296 .area_acquire = nfp6000_area_acquire,
1297 .area_release = nfp6000_area_release,
1298 .area_phys = nfp6000_area_phys,
1299 .area_iomem = nfp6000_area_iomem,
1300 .area_resource = nfp6000_area_resource,
1301 .area_read = nfp6000_area_read,
1302 .area_write = nfp6000_area_write,
1304 .explicit_priv_size = sizeof(struct nfp6000_explicit_priv),
1305 .explicit_acquire = nfp6000_explicit_acquire,
1306 .explicit_release = nfp6000_explicit_release,
1307 .explicit_put = nfp6000_explicit_put,
1308 .explicit_do = nfp6000_explicit_do,
1309 .explicit_get = nfp6000_explicit_get,
1313 * nfp_cpp_from_nfp6000_pcie() - Build a NFP CPP bus from a NFP6000 PCI device
1314 * @pdev: NFP6000 PCI device
1316 * Return: NFP CPP handle
1318 struct nfp_cpp *nfp_cpp_from_nfp6000_pcie(struct pci_dev *pdev)
1320 struct nfp6000_pcie *nfp;
1324 /* Finished with card initialization. */
1325 dev_info(&pdev->dev,
1326 "Netronome Flow Processor NFP4000/NFP5000/NFP6000 PCIe Card Probe\n");
1327 pcie_print_link_status(pdev);
1329 nfp = kzalloc(sizeof(*nfp), GFP_KERNEL);
1335 nfp->dev = &pdev->dev;
1337 init_waitqueue_head(&nfp->bar_waiters);
1338 spin_lock_init(&nfp->bar_lock);
1340 interface = nfp6000_get_interface(&pdev->dev);
1342 if (NFP_CPP_INTERFACE_TYPE_of(interface) !=
1343 NFP_CPP_INTERFACE_TYPE_PCI) {
1345 "Interface type %d is not the expected %d\n",
1346 NFP_CPP_INTERFACE_TYPE_of(interface),
1347 NFP_CPP_INTERFACE_TYPE_PCI);
1352 if (NFP_CPP_INTERFACE_CHANNEL_of(interface) !=
1353 NFP_CPP_INTERFACE_CHANNEL_PEROPENER) {
1354 dev_err(&pdev->dev, "Interface channel %d is not the expected %d\n",
1355 NFP_CPP_INTERFACE_CHANNEL_of(interface),
1356 NFP_CPP_INTERFACE_CHANNEL_PEROPENER);
1361 err = enable_bars(nfp, interface);
1365 /* Probe for all the common NFP devices */
1366 return nfp_cpp_from_operations(&nfp6000_pcie_ops, &pdev->dev, nfp);
1371 dev_err(&pdev->dev, "NFP6000 PCI setup failed\n");
1372 return ERR_PTR(err);