1 // SPDX-License-Identifier: GPL-2.0+
3 #include "lan966x_main.h"
5 static int lan966x_fdma_channel_active(struct lan966x *lan966x)
7 return lan_rd(lan966x, FDMA_CH_ACTIVE);
10 static struct page *lan966x_fdma_rx_alloc_page(struct lan966x_rx *rx,
11 struct lan966x_db *db)
13 struct lan966x *lan966x = rx->lan966x;
17 page = dev_alloc_pages(rx->page_order);
21 dma_addr = dma_map_page(lan966x->dev, page, 0,
22 PAGE_SIZE << rx->page_order,
24 if (unlikely(dma_mapping_error(lan966x->dev, dma_addr)))
27 db->dataptr = dma_addr;
32 __free_pages(page, rx->page_order);
36 static void lan966x_fdma_rx_free_pages(struct lan966x_rx *rx)
38 struct lan966x *lan966x = rx->lan966x;
39 struct lan966x_rx_dcb *dcb;
40 struct lan966x_db *db;
43 for (i = 0; i < FDMA_DCB_MAX; ++i) {
46 for (j = 0; j < FDMA_RX_DCB_MAX_DBS; ++j) {
48 dma_unmap_single(lan966x->dev,
49 (dma_addr_t)db->dataptr,
50 PAGE_SIZE << rx->page_order,
52 __free_pages(rx->page[i][j], rx->page_order);
57 static void lan966x_fdma_rx_add_dcb(struct lan966x_rx *rx,
58 struct lan966x_rx_dcb *dcb,
61 struct lan966x_db *db;
64 for (i = 0; i < FDMA_RX_DCB_MAX_DBS; ++i) {
66 db->status = FDMA_DCB_STATUS_INTR;
69 dcb->nextptr = FDMA_DCB_INVALID_DATA;
70 dcb->info = FDMA_DCB_INFO_DATAL(PAGE_SIZE << rx->page_order);
72 rx->last_entry->nextptr = nextptr;
76 static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx)
78 struct lan966x *lan966x = rx->lan966x;
79 struct lan966x_rx_dcb *dcb;
80 struct lan966x_db *db;
85 /* calculate how many pages are needed to allocate the dcbs */
86 size = sizeof(struct lan966x_rx_dcb) * FDMA_DCB_MAX;
87 size = ALIGN(size, PAGE_SIZE);
89 rx->dcbs = dma_alloc_coherent(lan966x->dev, size, &rx->dma, GFP_KERNEL);
93 rx->last_entry = rx->dcbs;
97 /* Now for each dcb allocate the dbs */
98 for (i = 0; i < FDMA_DCB_MAX; ++i) {
102 /* For each db allocate a page and map it to the DB dataptr. */
103 for (j = 0; j < FDMA_RX_DCB_MAX_DBS; ++j) {
105 page = lan966x_fdma_rx_alloc_page(rx, db);
110 rx->page[i][j] = page;
113 lan966x_fdma_rx_add_dcb(rx, dcb, rx->dma + sizeof(*dcb) * i);
119 static void lan966x_fdma_rx_free(struct lan966x_rx *rx)
121 struct lan966x *lan966x = rx->lan966x;
124 /* Now it is possible to do the cleanup of dcb */
125 size = sizeof(struct lan966x_tx_dcb) * FDMA_DCB_MAX;
126 size = ALIGN(size, PAGE_SIZE);
127 dma_free_coherent(lan966x->dev, size, rx->dcbs, rx->dma);
130 static void lan966x_fdma_rx_start(struct lan966x_rx *rx)
132 struct lan966x *lan966x = rx->lan966x;
135 /* When activating a channel, first is required to write the first DCB
136 * address and then to activate it
138 lan_wr(lower_32_bits((u64)rx->dma), lan966x,
139 FDMA_DCB_LLP(rx->channel_id));
140 lan_wr(upper_32_bits((u64)rx->dma), lan966x,
141 FDMA_DCB_LLP1(rx->channel_id));
143 lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_RX_DCB_MAX_DBS) |
144 FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) |
145 FDMA_CH_CFG_CH_INJ_PORT_SET(0) |
146 FDMA_CH_CFG_CH_MEM_SET(1),
147 lan966x, FDMA_CH_CFG(rx->channel_id));
150 lan_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0),
151 FDMA_PORT_CTRL_XTR_STOP,
152 lan966x, FDMA_PORT_CTRL(0));
154 /* Enable interrupts */
155 mask = lan_rd(lan966x, FDMA_INTR_DB_ENA);
156 mask = FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(mask);
157 mask |= BIT(rx->channel_id);
158 lan_rmw(FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(mask),
159 FDMA_INTR_DB_ENA_INTR_DB_ENA,
160 lan966x, FDMA_INTR_DB_ENA);
162 /* Activate the channel */
163 lan_rmw(FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(BIT(rx->channel_id)),
164 FDMA_CH_ACTIVATE_CH_ACTIVATE,
165 lan966x, FDMA_CH_ACTIVATE);
168 static void lan966x_fdma_rx_disable(struct lan966x_rx *rx)
170 struct lan966x *lan966x = rx->lan966x;
173 /* Disable the channel */
174 lan_rmw(FDMA_CH_DISABLE_CH_DISABLE_SET(BIT(rx->channel_id)),
175 FDMA_CH_DISABLE_CH_DISABLE,
176 lan966x, FDMA_CH_DISABLE);
178 readx_poll_timeout_atomic(lan966x_fdma_channel_active, lan966x,
179 val, !(val & BIT(rx->channel_id)),
180 READL_SLEEP_US, READL_TIMEOUT_US);
182 lan_rmw(FDMA_CH_DB_DISCARD_DB_DISCARD_SET(BIT(rx->channel_id)),
183 FDMA_CH_DB_DISCARD_DB_DISCARD,
184 lan966x, FDMA_CH_DB_DISCARD);
187 static void lan966x_fdma_rx_reload(struct lan966x_rx *rx)
189 struct lan966x *lan966x = rx->lan966x;
191 lan_rmw(FDMA_CH_RELOAD_CH_RELOAD_SET(BIT(rx->channel_id)),
192 FDMA_CH_RELOAD_CH_RELOAD,
193 lan966x, FDMA_CH_RELOAD);
196 static void lan966x_fdma_tx_add_dcb(struct lan966x_tx *tx,
197 struct lan966x_tx_dcb *dcb)
199 dcb->nextptr = FDMA_DCB_INVALID_DATA;
203 static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx)
205 struct lan966x *lan966x = tx->lan966x;
206 struct lan966x_tx_dcb *dcb;
207 struct lan966x_db *db;
211 tx->dcbs_buf = kcalloc(FDMA_DCB_MAX, sizeof(struct lan966x_tx_dcb_buf),
216 /* calculate how many pages are needed to allocate the dcbs */
217 size = sizeof(struct lan966x_tx_dcb) * FDMA_DCB_MAX;
218 size = ALIGN(size, PAGE_SIZE);
219 tx->dcbs = dma_alloc_coherent(lan966x->dev, size, &tx->dma, GFP_KERNEL);
223 /* Now for each dcb allocate the db */
224 for (i = 0; i < FDMA_DCB_MAX; ++i) {
227 for (j = 0; j < FDMA_TX_DCB_MAX_DBS; ++j) {
233 lan966x_fdma_tx_add_dcb(tx, dcb);
243 static void lan966x_fdma_tx_free(struct lan966x_tx *tx)
245 struct lan966x *lan966x = tx->lan966x;
250 size = sizeof(struct lan966x_tx_dcb) * FDMA_DCB_MAX;
251 size = ALIGN(size, PAGE_SIZE);
252 dma_free_coherent(lan966x->dev, size, tx->dcbs, tx->dma);
255 static void lan966x_fdma_tx_activate(struct lan966x_tx *tx)
257 struct lan966x *lan966x = tx->lan966x;
260 /* When activating a channel, first is required to write the first DCB
261 * address and then to activate it
263 lan_wr(lower_32_bits((u64)tx->dma), lan966x,
264 FDMA_DCB_LLP(tx->channel_id));
265 lan_wr(upper_32_bits((u64)tx->dma), lan966x,
266 FDMA_DCB_LLP1(tx->channel_id));
268 lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_TX_DCB_MAX_DBS) |
269 FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) |
270 FDMA_CH_CFG_CH_INJ_PORT_SET(0) |
271 FDMA_CH_CFG_CH_MEM_SET(1),
272 lan966x, FDMA_CH_CFG(tx->channel_id));
275 lan_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0),
276 FDMA_PORT_CTRL_INJ_STOP,
277 lan966x, FDMA_PORT_CTRL(0));
279 /* Enable interrupts */
280 mask = lan_rd(lan966x, FDMA_INTR_DB_ENA);
281 mask = FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(mask);
282 mask |= BIT(tx->channel_id);
283 lan_rmw(FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(mask),
284 FDMA_INTR_DB_ENA_INTR_DB_ENA,
285 lan966x, FDMA_INTR_DB_ENA);
287 /* Activate the channel */
288 lan_rmw(FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(BIT(tx->channel_id)),
289 FDMA_CH_ACTIVATE_CH_ACTIVATE,
290 lan966x, FDMA_CH_ACTIVATE);
293 static void lan966x_fdma_tx_disable(struct lan966x_tx *tx)
295 struct lan966x *lan966x = tx->lan966x;
298 /* Disable the channel */
299 lan_rmw(FDMA_CH_DISABLE_CH_DISABLE_SET(BIT(tx->channel_id)),
300 FDMA_CH_DISABLE_CH_DISABLE,
301 lan966x, FDMA_CH_DISABLE);
303 readx_poll_timeout_atomic(lan966x_fdma_channel_active, lan966x,
304 val, !(val & BIT(tx->channel_id)),
305 READL_SLEEP_US, READL_TIMEOUT_US);
307 lan_rmw(FDMA_CH_DB_DISCARD_DB_DISCARD_SET(BIT(tx->channel_id)),
308 FDMA_CH_DB_DISCARD_DB_DISCARD,
309 lan966x, FDMA_CH_DB_DISCARD);
311 tx->activated = false;
312 tx->last_in_use = -1;
315 static void lan966x_fdma_tx_reload(struct lan966x_tx *tx)
317 struct lan966x *lan966x = tx->lan966x;
319 /* Write the registers to reload the channel */
320 lan_rmw(FDMA_CH_RELOAD_CH_RELOAD_SET(BIT(tx->channel_id)),
321 FDMA_CH_RELOAD_CH_RELOAD,
322 lan966x, FDMA_CH_RELOAD);
325 static void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x)
327 struct lan966x_port *port;
330 for (i = 0; i < lan966x->num_phys_ports; ++i) {
331 port = lan966x->ports[i];
335 if (netif_queue_stopped(port->dev))
336 netif_wake_queue(port->dev);
340 static void lan966x_fdma_stop_netdev(struct lan966x *lan966x)
342 struct lan966x_port *port;
345 for (i = 0; i < lan966x->num_phys_ports; ++i) {
346 port = lan966x->ports[i];
350 netif_stop_queue(port->dev);
354 static void lan966x_fdma_tx_clear_buf(struct lan966x *lan966x, int weight)
356 struct lan966x_tx *tx = &lan966x->tx;
357 struct lan966x_tx_dcb_buf *dcb_buf;
358 struct lan966x_db *db;
363 spin_lock_irqsave(&lan966x->tx_lock, flags);
364 for (i = 0; i < FDMA_DCB_MAX; ++i) {
365 dcb_buf = &tx->dcbs_buf[i];
370 db = &tx->dcbs[i].db[0];
371 if (!(db->status & FDMA_DCB_STATUS_DONE))
374 dcb_buf->dev->stats.tx_packets++;
375 dcb_buf->dev->stats.tx_bytes += dcb_buf->skb->len;
377 dcb_buf->used = false;
378 dma_unmap_single(lan966x->dev,
383 dev_kfree_skb_any(dcb_buf->skb);
389 lan966x_fdma_wakeup_netdev(lan966x);
391 spin_unlock_irqrestore(&lan966x->tx_lock, flags);
394 static bool lan966x_fdma_rx_more_frames(struct lan966x_rx *rx)
396 struct lan966x_db *db;
398 /* Check if there is any data */
399 db = &rx->dcbs[rx->dcb_index].db[rx->db_index];
400 if (unlikely(!(db->status & FDMA_DCB_STATUS_DONE)))
406 static struct sk_buff *lan966x_fdma_rx_get_frame(struct lan966x_rx *rx)
408 struct lan966x *lan966x = rx->lan966x;
409 u64 src_port, timestamp;
410 struct lan966x_db *db;
414 /* Get the received frame and unmap it */
415 db = &rx->dcbs[rx->dcb_index].db[rx->db_index];
416 page = rx->page[rx->dcb_index][rx->db_index];
418 dma_sync_single_for_cpu(lan966x->dev, (dma_addr_t)db->dataptr,
419 FDMA_DCB_STATUS_BLOCKL(db->status),
422 skb = build_skb(page_address(page), PAGE_SIZE << rx->page_order);
426 skb_put(skb, FDMA_DCB_STATUS_BLOCKL(db->status));
428 lan966x_ifh_get_src_port(skb->data, &src_port);
429 lan966x_ifh_get_timestamp(skb->data, ×tamp);
431 if (WARN_ON(src_port >= lan966x->num_phys_ports))
434 dma_unmap_single_attrs(lan966x->dev, (dma_addr_t)db->dataptr,
435 PAGE_SIZE << rx->page_order, DMA_FROM_DEVICE,
436 DMA_ATTR_SKIP_CPU_SYNC);
438 skb->dev = lan966x->ports[src_port]->dev;
439 skb_pull(skb, IFH_LEN * sizeof(u32));
441 if (likely(!(skb->dev->features & NETIF_F_RXFCS)))
442 skb_trim(skb, skb->len - ETH_FCS_LEN);
444 lan966x_ptp_rxtstamp(lan966x, skb, timestamp);
445 skb->protocol = eth_type_trans(skb, skb->dev);
447 if (lan966x->bridge_mask & BIT(src_port)) {
448 skb->offload_fwd_mark = 1;
450 skb_reset_network_header(skb);
451 if (!lan966x_hw_offload(lan966x, src_port, skb))
452 skb->offload_fwd_mark = 0;
455 skb->dev->stats.rx_bytes += skb->len;
456 skb->dev->stats.rx_packets++;
463 dma_unmap_single_attrs(lan966x->dev, (dma_addr_t)db->dataptr,
464 PAGE_SIZE << rx->page_order, DMA_FROM_DEVICE,
465 DMA_ATTR_SKIP_CPU_SYNC);
466 __free_pages(page, rx->page_order);
471 static int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight)
473 struct lan966x *lan966x = container_of(napi, struct lan966x, napi);
474 struct lan966x_rx *rx = &lan966x->rx;
475 int dcb_reload = rx->dcb_index;
476 struct lan966x_rx_dcb *old_dcb;
477 struct lan966x_db *db;
483 lan966x_fdma_tx_clear_buf(lan966x, weight);
485 /* Get all received skb */
486 while (counter < weight) {
487 if (!lan966x_fdma_rx_more_frames(rx))
490 skb = lan966x_fdma_rx_get_frame(rx);
492 rx->page[rx->dcb_index][rx->db_index] = NULL;
494 rx->dcb_index &= FDMA_DCB_MAX - 1;
499 napi_gro_receive(&lan966x->napi, skb);
503 /* Allocate new pages and map them */
504 while (dcb_reload != rx->dcb_index) {
505 db = &rx->dcbs[dcb_reload].db[rx->db_index];
506 page = lan966x_fdma_rx_alloc_page(rx, db);
509 rx->page[dcb_reload][rx->db_index] = page;
511 old_dcb = &rx->dcbs[dcb_reload];
513 dcb_reload &= FDMA_DCB_MAX - 1;
515 nextptr = rx->dma + ((unsigned long)old_dcb -
516 (unsigned long)rx->dcbs);
517 lan966x_fdma_rx_add_dcb(rx, old_dcb, nextptr);
518 lan966x_fdma_rx_reload(rx);
521 if (counter < weight && napi_complete_done(napi, counter))
522 lan_wr(0xff, lan966x, FDMA_INTR_DB_ENA);
527 irqreturn_t lan966x_fdma_irq_handler(int irq, void *args)
529 struct lan966x *lan966x = args;
530 u32 db, err, err_type;
532 db = lan_rd(lan966x, FDMA_INTR_DB);
533 err = lan_rd(lan966x, FDMA_INTR_ERR);
536 lan_wr(0, lan966x, FDMA_INTR_DB_ENA);
537 lan_wr(db, lan966x, FDMA_INTR_DB);
539 napi_schedule(&lan966x->napi);
543 err_type = lan_rd(lan966x, FDMA_ERRORS);
545 WARN(1, "Unexpected error: %d, error_type: %d\n", err, err_type);
547 lan_wr(err, lan966x, FDMA_INTR_ERR);
548 lan_wr(err_type, lan966x, FDMA_ERRORS);
554 static int lan966x_fdma_get_next_dcb(struct lan966x_tx *tx)
556 struct lan966x_tx_dcb_buf *dcb_buf;
559 for (i = 0; i < FDMA_DCB_MAX; ++i) {
560 dcb_buf = &tx->dcbs_buf[i];
561 if (!dcb_buf->used && i != tx->last_in_use)
568 int lan966x_fdma_xmit(struct sk_buff *skb, __be32 *ifh, struct net_device *dev)
570 struct lan966x_port *port = netdev_priv(dev);
571 struct lan966x *lan966x = port->lan966x;
572 struct lan966x_tx_dcb_buf *next_dcb_buf;
573 struct lan966x_tx_dcb *next_dcb, *dcb;
574 struct lan966x_tx *tx = &lan966x->tx;
575 struct lan966x_db *next_db;
583 next_to_use = lan966x_fdma_get_next_dcb(tx);
584 if (next_to_use < 0) {
585 netif_stop_queue(dev);
586 return NETDEV_TX_BUSY;
589 if (skb_put_padto(skb, ETH_ZLEN)) {
590 dev->stats.tx_dropped++;
595 needed_headroom = max_t(int, IFH_LEN * sizeof(u32) - skb_headroom(skb), 0);
596 needed_tailroom = max_t(int, ETH_FCS_LEN - skb_tailroom(skb), 0);
597 if (needed_headroom || needed_tailroom || skb_header_cloned(skb)) {
598 err = pskb_expand_head(skb, needed_headroom, needed_tailroom,
601 dev->stats.tx_dropped++;
607 skb_tx_timestamp(skb);
608 skb_push(skb, IFH_LEN * sizeof(u32));
609 memcpy(skb->data, ifh, IFH_LEN * sizeof(u32));
612 dma_addr = dma_map_single(lan966x->dev, skb->data, skb->len,
614 if (dma_mapping_error(lan966x->dev, dma_addr)) {
615 dev->stats.tx_dropped++;
621 next_dcb = &tx->dcbs[next_to_use];
622 next_dcb->nextptr = FDMA_DCB_INVALID_DATA;
624 next_db = &next_dcb->db[0];
625 next_db->dataptr = dma_addr;
626 next_db->status = FDMA_DCB_STATUS_SOF |
627 FDMA_DCB_STATUS_EOF |
628 FDMA_DCB_STATUS_INTR |
629 FDMA_DCB_STATUS_BLOCKO(0) |
630 FDMA_DCB_STATUS_BLOCKL(skb->len);
632 /* Fill up the buffer */
633 next_dcb_buf = &tx->dcbs_buf[next_to_use];
634 next_dcb_buf->skb = skb;
635 next_dcb_buf->dma_addr = dma_addr;
636 next_dcb_buf->used = true;
637 next_dcb_buf->ptp = false;
638 next_dcb_buf->dev = dev;
640 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
641 LAN966X_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP)
642 next_dcb_buf->ptp = true;
644 if (likely(lan966x->tx.activated)) {
645 /* Connect current dcb to the next db */
646 dcb = &tx->dcbs[tx->last_in_use];
647 dcb->nextptr = tx->dma + (next_to_use *
648 sizeof(struct lan966x_tx_dcb));
650 lan966x_fdma_tx_reload(tx);
652 /* Because it is first time, then just activate */
653 lan966x->tx.activated = true;
654 lan966x_fdma_tx_activate(tx);
657 /* Move to next dcb because this last in use */
658 tx->last_in_use = next_to_use;
663 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
664 LAN966X_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP)
665 lan966x_ptp_txtstamp_release(port, skb);
667 dev_kfree_skb_any(skb);
671 static int lan966x_fdma_get_max_mtu(struct lan966x *lan966x)
676 for (i = 0; i < lan966x->num_phys_ports; ++i) {
677 struct lan966x_port *port;
680 port = lan966x->ports[i];
684 mtu = lan_rd(lan966x, DEV_MAC_MAXLEN_CFG(port->chip_port));
692 static int lan966x_qsys_sw_status(struct lan966x *lan966x)
694 return lan_rd(lan966x, QSYS_SW_STATUS(CPU_PORT));
697 static int lan966x_fdma_reload(struct lan966x *lan966x, int new_mtu)
704 /* Store these for later to free them */
705 rx_dma = lan966x->rx.dma;
706 rx_dcbs = lan966x->rx.dcbs;
708 napi_synchronize(&lan966x->napi);
709 napi_disable(&lan966x->napi);
710 lan966x_fdma_stop_netdev(lan966x);
712 lan966x_fdma_rx_disable(&lan966x->rx);
713 lan966x_fdma_rx_free_pages(&lan966x->rx);
714 lan966x->rx.page_order = round_up(new_mtu, PAGE_SIZE) / PAGE_SIZE - 1;
715 err = lan966x_fdma_rx_alloc(&lan966x->rx);
718 lan966x_fdma_rx_start(&lan966x->rx);
720 size = sizeof(struct lan966x_rx_dcb) * FDMA_DCB_MAX;
721 size = ALIGN(size, PAGE_SIZE);
722 dma_free_coherent(lan966x->dev, size, rx_dcbs, rx_dma);
724 lan966x_fdma_wakeup_netdev(lan966x);
725 napi_enable(&lan966x->napi);
729 lan966x->rx.dma = rx_dma;
730 lan966x->rx.dcbs = rx_dcbs;
731 lan966x_fdma_rx_start(&lan966x->rx);
736 int lan966x_fdma_change_mtu(struct lan966x *lan966x)
742 max_mtu = lan966x_fdma_get_max_mtu(lan966x);
743 max_mtu += IFH_LEN * sizeof(u32);
744 max_mtu += SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
745 max_mtu += VLAN_HLEN * 2;
747 if (round_up(max_mtu, PAGE_SIZE) / PAGE_SIZE - 1 ==
748 lan966x->rx.page_order)
751 /* Disable the CPU port */
752 lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0),
753 QSYS_SW_PORT_MODE_PORT_ENA,
754 lan966x, QSYS_SW_PORT_MODE(CPU_PORT));
756 /* Flush the CPU queues */
757 readx_poll_timeout(lan966x_qsys_sw_status, lan966x,
758 val, !(QSYS_SW_STATUS_EQ_AVAIL_GET(val)),
759 READL_SLEEP_US, READL_TIMEOUT_US);
761 /* Add a sleep in case there are frames between the queues and the CPU
764 usleep_range(1000, 2000);
766 err = lan966x_fdma_reload(lan966x, max_mtu);
768 /* Enable back the CPU port */
769 lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(1),
770 QSYS_SW_PORT_MODE_PORT_ENA,
771 lan966x, QSYS_SW_PORT_MODE(CPU_PORT));
776 void lan966x_fdma_netdev_init(struct lan966x *lan966x, struct net_device *dev)
778 if (lan966x->fdma_ndev)
781 lan966x->fdma_ndev = dev;
782 netif_napi_add(dev, &lan966x->napi, lan966x_fdma_napi_poll);
783 napi_enable(&lan966x->napi);
786 void lan966x_fdma_netdev_deinit(struct lan966x *lan966x, struct net_device *dev)
788 if (lan966x->fdma_ndev == dev) {
789 netif_napi_del(&lan966x->napi);
790 lan966x->fdma_ndev = NULL;
794 int lan966x_fdma_init(struct lan966x *lan966x)
801 lan966x->rx.lan966x = lan966x;
802 lan966x->rx.channel_id = FDMA_XTR_CHANNEL;
803 lan966x->tx.lan966x = lan966x;
804 lan966x->tx.channel_id = FDMA_INJ_CHANNEL;
805 lan966x->tx.last_in_use = -1;
807 err = lan966x_fdma_rx_alloc(&lan966x->rx);
811 err = lan966x_fdma_tx_alloc(&lan966x->tx);
813 lan966x_fdma_rx_free(&lan966x->rx);
817 lan966x_fdma_rx_start(&lan966x->rx);
822 void lan966x_fdma_deinit(struct lan966x *lan966x)
827 lan966x_fdma_rx_disable(&lan966x->rx);
828 lan966x_fdma_tx_disable(&lan966x->tx);
830 napi_synchronize(&lan966x->napi);
831 napi_disable(&lan966x->napi);
833 lan966x_fdma_rx_free_pages(&lan966x->rx);
834 lan966x_fdma_rx_free(&lan966x->rx);
835 lan966x_fdma_tx_free(&lan966x->tx);