2 * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/slab.h>
43 #include <linux/device.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <net/switchdev.h>
47 #include <generated/utsrelease.h>
55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
56 static const char mlxsw_sx_driver_version[] = "1.0";
61 struct mlxsw_sx_port **ports;
62 struct mlxsw_core *core;
63 const struct mlxsw_bus_info *bus_info;
67 struct mlxsw_sx_port_pcpu_stats {
72 struct u64_stats_sync syncp;
76 struct mlxsw_sx_port {
77 struct mlxsw_core_port core_port; /* must be first */
78 struct net_device *dev;
79 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
80 struct mlxsw_sx *mlxsw_sx;
88 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
91 * Packet control type.
92 * 0 - Ethernet control (e.g. EMADs, LACP)
95 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
98 * Packet protocol type. Must be set to 1 (Ethernet).
100 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
103 * Egress TClass to be used on the egress device on the egress port.
104 * The MSB is specified in the 'ctclass3' field.
105 * Range is 0-15, where 15 is the highest priority.
107 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
110 * Switch partition ID.
112 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
115 * Destination local port for unicast packets.
116 * Destination multicast ID for multicast packets.
118 * Control packets are directed to a specific egress port, while data
119 * packets are transmitted through the CPU port (0) into the switch partition,
120 * where forwarding rules are applied.
122 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
125 * See field 'etclass'.
127 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
130 * RDQ for control packets sent to remote CPU.
131 * Must be set to 0x1F for EMADs, otherwise 0.
133 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
136 * Signature control for packets going to CPU. Must be set to 0.
138 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
141 * Stacking protocl signature. Must be set to 0xE0E0.
143 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
148 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
151 * EMAD bit. Must be set for EMADs.
153 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
157 * 6 - Control packets
159 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
162 const struct mlxsw_tx_info *tx_info)
164 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
165 bool is_emad = tx_info->is_emad;
167 memset(txhdr, 0, MLXSW_TXHDR_LEN);
169 /* We currently set default values for the egress tclass (QoS). */
170 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
171 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
172 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
173 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
174 MLXSW_TXHDR_ETCLASS_5);
175 mlxsw_tx_hdr_swid_set(txhdr, 0);
176 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
177 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
178 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
179 MLXSW_TXHDR_RDQ_OTHER);
180 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
181 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
182 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
183 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
184 MLXSW_TXHDR_NOT_EMAD);
185 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
188 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
191 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
192 char paos_pl[MLXSW_REG_PAOS_LEN];
194 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
195 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
196 MLXSW_PORT_ADMIN_STATUS_DOWN);
197 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
200 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
203 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
204 char paos_pl[MLXSW_REG_PAOS_LEN];
208 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
209 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
212 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
213 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
217 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
219 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
220 char pmtu_pl[MLXSW_REG_PMTU_LEN];
224 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
225 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
226 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
229 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
234 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
235 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
238 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
240 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
241 char pspa_pl[MLXSW_REG_PSPA_LEN];
243 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
244 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
248 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
250 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
251 char sspr_pl[MLXSW_REG_SSPR_LEN];
253 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
254 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
257 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
260 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
261 char pmlp_pl[MLXSW_REG_PMLP_LEN];
264 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
265 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
268 *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
272 static int mlxsw_sx_port_open(struct net_device *dev)
274 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
277 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
280 netif_start_queue(dev);
284 static int mlxsw_sx_port_stop(struct net_device *dev)
286 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
288 netif_stop_queue(dev);
289 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
292 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
293 struct net_device *dev)
295 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
296 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
297 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
298 const struct mlxsw_tx_info tx_info = {
299 .local_port = mlxsw_sx_port->local_port,
305 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
306 return NETDEV_TX_BUSY;
308 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
309 struct sk_buff *skb_orig = skb;
311 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
313 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
314 dev_kfree_skb_any(skb_orig);
318 mlxsw_sx_txhdr_construct(skb, &tx_info);
319 /* TX header is consumed by HW on the way so we shouldn't count its
320 * bytes as being sent.
322 len = skb->len - MLXSW_TXHDR_LEN;
323 /* Due to a race we might fail here because of a full queue. In that
324 * unlikely case we simply drop the packet.
326 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
329 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
330 u64_stats_update_begin(&pcpu_stats->syncp);
331 pcpu_stats->tx_packets++;
332 pcpu_stats->tx_bytes += len;
333 u64_stats_update_end(&pcpu_stats->syncp);
335 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
336 dev_kfree_skb_any(skb);
341 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
343 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
346 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
353 static struct rtnl_link_stats64 *
354 mlxsw_sx_port_get_stats64(struct net_device *dev,
355 struct rtnl_link_stats64 *stats)
357 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
358 struct mlxsw_sx_port_pcpu_stats *p;
359 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
364 for_each_possible_cpu(i) {
365 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
367 start = u64_stats_fetch_begin_irq(&p->syncp);
368 rx_packets = p->rx_packets;
369 rx_bytes = p->rx_bytes;
370 tx_packets = p->tx_packets;
371 tx_bytes = p->tx_bytes;
372 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
374 stats->rx_packets += rx_packets;
375 stats->rx_bytes += rx_bytes;
376 stats->tx_packets += tx_packets;
377 stats->tx_bytes += tx_bytes;
378 /* tx_dropped is u32, updated without syncp protection. */
379 tx_dropped += p->tx_dropped;
381 stats->tx_dropped = tx_dropped;
385 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
386 .ndo_open = mlxsw_sx_port_open,
387 .ndo_stop = mlxsw_sx_port_stop,
388 .ndo_start_xmit = mlxsw_sx_port_xmit,
389 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
390 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
393 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
394 struct ethtool_drvinfo *drvinfo)
396 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
397 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
399 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
400 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
401 sizeof(drvinfo->version));
402 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
404 mlxsw_sx->bus_info->fw_rev.major,
405 mlxsw_sx->bus_info->fw_rev.minor,
406 mlxsw_sx->bus_info->fw_rev.subminor);
407 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
408 sizeof(drvinfo->bus_info));
411 struct mlxsw_sx_port_hw_stats {
412 char str[ETH_GSTRING_LEN];
413 u64 (*getter)(char *payload);
416 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
418 .str = "a_frames_transmitted_ok",
419 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
422 .str = "a_frames_received_ok",
423 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
426 .str = "a_frame_check_sequence_errors",
427 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
430 .str = "a_alignment_errors",
431 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
434 .str = "a_octets_transmitted_ok",
435 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
438 .str = "a_octets_received_ok",
439 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
442 .str = "a_multicast_frames_xmitted_ok",
443 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
446 .str = "a_broadcast_frames_xmitted_ok",
447 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
450 .str = "a_multicast_frames_received_ok",
451 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
454 .str = "a_broadcast_frames_received_ok",
455 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
458 .str = "a_in_range_length_errors",
459 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
462 .str = "a_out_of_range_length_field",
463 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
466 .str = "a_frame_too_long_errors",
467 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
470 .str = "a_symbol_error_during_carrier",
471 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
474 .str = "a_mac_control_frames_transmitted",
475 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
478 .str = "a_mac_control_frames_received",
479 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
482 .str = "a_unsupported_opcodes_received",
483 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
486 .str = "a_pause_mac_ctrl_frames_received",
487 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
490 .str = "a_pause_mac_ctrl_frames_xmitted",
491 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
495 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
497 static void mlxsw_sx_port_get_strings(struct net_device *dev,
498 u32 stringset, u8 *data)
505 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
506 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
508 p += ETH_GSTRING_LEN;
514 static void mlxsw_sx_port_get_stats(struct net_device *dev,
515 struct ethtool_stats *stats, u64 *data)
517 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
518 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
519 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
523 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
524 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
525 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
526 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
527 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
530 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
534 return MLXSW_SX_PORT_HW_STATS_LEN;
540 struct mlxsw_sx_port_link_mode {
547 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
549 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
550 .supported = SUPPORTED_100baseT_Full,
551 .advertised = ADVERTISED_100baseT_Full,
555 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
559 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
560 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
561 .supported = SUPPORTED_1000baseKX_Full,
562 .advertised = ADVERTISED_1000baseKX_Full,
566 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
567 .supported = SUPPORTED_10000baseT_Full,
568 .advertised = ADVERTISED_10000baseT_Full,
572 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
573 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
574 .supported = SUPPORTED_10000baseKX4_Full,
575 .advertised = ADVERTISED_10000baseKX4_Full,
579 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
580 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
581 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
582 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
583 .supported = SUPPORTED_10000baseKR_Full,
584 .advertised = ADVERTISED_10000baseKR_Full,
588 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
589 .supported = SUPPORTED_20000baseKR2_Full,
590 .advertised = ADVERTISED_20000baseKR2_Full,
594 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
595 .supported = SUPPORTED_40000baseCR4_Full,
596 .advertised = ADVERTISED_40000baseCR4_Full,
600 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
601 .supported = SUPPORTED_40000baseKR4_Full,
602 .advertised = ADVERTISED_40000baseKR4_Full,
606 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
607 .supported = SUPPORTED_40000baseSR4_Full,
608 .advertised = ADVERTISED_40000baseSR4_Full,
612 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
613 .supported = SUPPORTED_40000baseLR4_Full,
614 .advertised = ADVERTISED_40000baseLR4_Full,
618 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
619 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
620 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
624 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
625 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
626 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
630 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
631 .supported = SUPPORTED_56000baseKR4_Full,
632 .advertised = ADVERTISED_56000baseKR4_Full,
636 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
637 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
639 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
644 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
646 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
648 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
649 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
650 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
651 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
652 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
653 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
654 return SUPPORTED_FIBRE;
656 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
657 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
658 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
659 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
660 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
661 return SUPPORTED_Backplane;
665 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
670 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
671 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
672 modes |= mlxsw_sx_port_link_mode[i].supported;
677 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
682 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
683 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
684 modes |= mlxsw_sx_port_link_mode[i].advertised;
689 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
690 struct ethtool_cmd *cmd)
692 u32 speed = SPEED_UNKNOWN;
693 u8 duplex = DUPLEX_UNKNOWN;
699 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
700 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
701 speed = mlxsw_sx_port_link_mode[i].speed;
702 duplex = DUPLEX_FULL;
707 ethtool_cmd_speed_set(cmd, speed);
708 cmd->duplex = duplex;
711 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
713 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
714 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
715 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
716 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
719 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
720 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
721 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
724 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
725 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
726 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
727 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
733 static int mlxsw_sx_port_get_settings(struct net_device *dev,
734 struct ethtool_cmd *cmd)
736 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
737 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
738 char ptys_pl[MLXSW_REG_PTYS_LEN];
744 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
745 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
747 netdev_err(dev, "Failed to get proto");
750 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap,
751 ð_proto_admin, ð_proto_oper);
753 cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
754 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
755 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
756 cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
757 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
758 eth_proto_oper, cmd);
760 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
761 cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
762 cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
764 cmd->transceiver = XCVR_INTERNAL;
768 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
773 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
774 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
775 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
780 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
785 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
786 if (speed == mlxsw_sx_port_link_mode[i].speed)
787 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
792 static int mlxsw_sx_port_set_settings(struct net_device *dev,
793 struct ethtool_cmd *cmd)
795 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
796 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
797 char ptys_pl[MLXSW_REG_PTYS_LEN];
805 speed = ethtool_cmd_speed(cmd);
807 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
808 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
809 mlxsw_sx_to_ptys_speed(speed);
811 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
812 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
814 netdev_err(dev, "Failed to get proto");
817 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, NULL);
819 eth_proto_new = eth_proto_new & eth_proto_cap;
820 if (!eth_proto_new) {
821 netdev_err(dev, "Not supported proto admin requested");
824 if (eth_proto_new == eth_proto_admin)
827 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
828 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
830 netdev_err(dev, "Failed to set proto admin");
834 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
836 netdev_err(dev, "Failed to get oper status");
842 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
844 netdev_err(dev, "Failed to set admin status");
848 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
850 netdev_err(dev, "Failed to set admin status");
857 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
858 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
859 .get_link = ethtool_op_get_link,
860 .get_strings = mlxsw_sx_port_get_strings,
861 .get_ethtool_stats = mlxsw_sx_port_get_stats,
862 .get_sset_count = mlxsw_sx_port_get_sset_count,
863 .get_settings = mlxsw_sx_port_get_settings,
864 .set_settings = mlxsw_sx_port_set_settings,
867 static int mlxsw_sx_port_attr_get(struct net_device *dev,
868 struct switchdev_attr *attr)
870 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
871 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
874 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
875 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
876 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
885 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
886 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
889 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
891 char spad_pl[MLXSW_REG_SPAD_LEN];
894 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
897 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
901 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
903 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
904 struct net_device *dev = mlxsw_sx_port->dev;
905 char ppad_pl[MLXSW_REG_PPAD_LEN];
908 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
909 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
912 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
913 /* The last byte value in base mac address is guaranteed
914 * to be such it does not overflow when adding local_port
917 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
921 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
922 u16 vid, enum mlxsw_reg_spms_state state)
924 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
928 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
931 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
932 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
933 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
938 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
941 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
942 char ptys_pl[MLXSW_REG_PTYS_LEN];
944 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
945 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
949 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
950 enum mlxsw_reg_spmlr_learn_mode mode)
952 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
953 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
955 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
956 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
959 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
961 struct mlxsw_sx_port *mlxsw_sx_port;
962 struct net_device *dev;
966 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
969 mlxsw_sx_port = netdev_priv(dev);
970 mlxsw_sx_port->dev = dev;
971 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
972 mlxsw_sx_port->local_port = local_port;
974 mlxsw_sx_port->pcpu_stats =
975 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
976 if (!mlxsw_sx_port->pcpu_stats) {
978 goto err_alloc_stats;
981 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
982 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
983 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
985 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
987 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
988 mlxsw_sx_port->local_port);
989 goto err_dev_addr_get;
992 netif_carrier_off(dev);
994 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
995 NETIF_F_VLAN_CHALLENGED;
998 dev->max_mtu = ETH_MAX_MTU;
1000 /* Each packet needs to have a Tx header (metadata) on top all other
1003 dev->needed_headroom = MLXSW_TXHDR_LEN;
1005 err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
1007 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
1008 mlxsw_sx_port->local_port);
1009 goto err_port_module_check;
1013 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1014 mlxsw_sx_port->local_port);
1015 goto port_not_usable;
1018 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1020 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1021 mlxsw_sx_port->local_port);
1022 goto err_port_system_port_mapping_set;
1025 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1027 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1028 mlxsw_sx_port->local_port);
1029 goto err_port_swid_set;
1032 err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1033 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1035 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1036 mlxsw_sx_port->local_port);
1037 goto err_port_speed_set;
1040 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1042 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1043 mlxsw_sx_port->local_port);
1044 goto err_port_mtu_set;
1047 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1049 goto err_port_admin_status_set;
1051 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1052 MLXSW_PORT_DEFAULT_VID,
1053 MLXSW_REG_SPMS_STATE_FORWARDING);
1055 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1056 mlxsw_sx_port->local_port);
1057 goto err_port_stp_state_set;
1060 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1061 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1063 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1064 mlxsw_sx_port->local_port);
1065 goto err_port_mac_learning_mode_set;
1068 err = register_netdev(dev);
1070 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1071 mlxsw_sx_port->local_port);
1072 goto err_register_netdev;
1075 err = mlxsw_core_port_init(mlxsw_sx->core, &mlxsw_sx_port->core_port,
1076 mlxsw_sx_port->local_port, dev, false, 0);
1078 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1079 mlxsw_sx_port->local_port);
1080 goto err_core_port_init;
1083 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1087 unregister_netdev(dev);
1088 err_register_netdev:
1089 err_port_mac_learning_mode_set:
1090 err_port_stp_state_set:
1091 err_port_admin_status_set:
1095 err_port_system_port_mapping_set:
1097 err_port_module_check:
1099 free_percpu(mlxsw_sx_port->pcpu_stats);
1105 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1107 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1111 mlxsw_core_port_fini(&mlxsw_sx_port->core_port);
1112 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1113 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1114 free_percpu(mlxsw_sx_port->pcpu_stats);
1115 free_netdev(mlxsw_sx_port->dev);
1118 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1122 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1123 mlxsw_sx_port_remove(mlxsw_sx, i);
1124 kfree(mlxsw_sx->ports);
1127 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1133 alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1134 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1135 if (!mlxsw_sx->ports)
1138 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1139 err = mlxsw_sx_port_create(mlxsw_sx, i);
1141 goto err_port_create;
1146 for (i--; i >= 1; i--)
1147 mlxsw_sx_port_remove(mlxsw_sx, i);
1148 kfree(mlxsw_sx->ports);
1152 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1153 char *pude_pl, void *priv)
1155 struct mlxsw_sx *mlxsw_sx = priv;
1156 struct mlxsw_sx_port *mlxsw_sx_port;
1157 enum mlxsw_reg_pude_oper_status status;
1160 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1161 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1162 if (!mlxsw_sx_port) {
1163 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1168 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1169 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1170 netdev_info(mlxsw_sx_port->dev, "link up\n");
1171 netif_carrier_on(mlxsw_sx_port->dev);
1173 netdev_info(mlxsw_sx_port->dev, "link down\n");
1174 netif_carrier_off(mlxsw_sx_port->dev);
1178 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1179 .func = mlxsw_sx_pude_event_func,
1180 .trap_id = MLXSW_TRAP_ID_PUDE,
1183 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1184 enum mlxsw_event_trap_id trap_id)
1186 struct mlxsw_event_listener *el;
1187 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1191 case MLXSW_TRAP_ID_PUDE:
1192 el = &mlxsw_sx_pude_event;
1195 err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1199 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
1200 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1202 goto err_event_trap_set;
1207 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1211 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1212 enum mlxsw_event_trap_id trap_id)
1214 struct mlxsw_event_listener *el;
1217 case MLXSW_TRAP_ID_PUDE:
1218 el = &mlxsw_sx_pude_event;
1221 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1224 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1227 struct mlxsw_sx *mlxsw_sx = priv;
1228 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1229 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1231 if (unlikely(!mlxsw_sx_port)) {
1232 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1237 skb->dev = mlxsw_sx_port->dev;
1239 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1240 u64_stats_update_begin(&pcpu_stats->syncp);
1241 pcpu_stats->rx_packets++;
1242 pcpu_stats->rx_bytes += skb->len;
1243 u64_stats_update_end(&pcpu_stats->syncp);
1245 skb->protocol = eth_type_trans(skb, skb->dev);
1246 netif_receive_skb(skb);
1249 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1251 .func = mlxsw_sx_rx_listener_func,
1252 .local_port = MLXSW_PORT_DONT_CARE,
1253 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1255 /* Traps for specific L2 packet types, not trapped as FDB MC */
1257 .func = mlxsw_sx_rx_listener_func,
1258 .local_port = MLXSW_PORT_DONT_CARE,
1259 .trap_id = MLXSW_TRAP_ID_STP,
1262 .func = mlxsw_sx_rx_listener_func,
1263 .local_port = MLXSW_PORT_DONT_CARE,
1264 .trap_id = MLXSW_TRAP_ID_LACP,
1267 .func = mlxsw_sx_rx_listener_func,
1268 .local_port = MLXSW_PORT_DONT_CARE,
1269 .trap_id = MLXSW_TRAP_ID_EAPOL,
1272 .func = mlxsw_sx_rx_listener_func,
1273 .local_port = MLXSW_PORT_DONT_CARE,
1274 .trap_id = MLXSW_TRAP_ID_LLDP,
1277 .func = mlxsw_sx_rx_listener_func,
1278 .local_port = MLXSW_PORT_DONT_CARE,
1279 .trap_id = MLXSW_TRAP_ID_MMRP,
1282 .func = mlxsw_sx_rx_listener_func,
1283 .local_port = MLXSW_PORT_DONT_CARE,
1284 .trap_id = MLXSW_TRAP_ID_MVRP,
1287 .func = mlxsw_sx_rx_listener_func,
1288 .local_port = MLXSW_PORT_DONT_CARE,
1289 .trap_id = MLXSW_TRAP_ID_RPVST,
1292 .func = mlxsw_sx_rx_listener_func,
1293 .local_port = MLXSW_PORT_DONT_CARE,
1294 .trap_id = MLXSW_TRAP_ID_DHCP,
1297 .func = mlxsw_sx_rx_listener_func,
1298 .local_port = MLXSW_PORT_DONT_CARE,
1299 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1302 .func = mlxsw_sx_rx_listener_func,
1303 .local_port = MLXSW_PORT_DONT_CARE,
1304 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1307 .func = mlxsw_sx_rx_listener_func,
1308 .local_port = MLXSW_PORT_DONT_CARE,
1309 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1312 .func = mlxsw_sx_rx_listener_func,
1313 .local_port = MLXSW_PORT_DONT_CARE,
1314 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1317 .func = mlxsw_sx_rx_listener_func,
1318 .local_port = MLXSW_PORT_DONT_CARE,
1319 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1323 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1325 char htgt_pl[MLXSW_REG_HTGT_LEN];
1326 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1330 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1331 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1335 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
1336 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1340 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1341 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1342 &mlxsw_sx_rx_listener[i],
1345 goto err_rx_listener_register;
1347 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1348 mlxsw_sx_rx_listener[i].trap_id);
1349 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1351 goto err_rx_trap_set;
1356 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1357 &mlxsw_sx_rx_listener[i],
1359 err_rx_listener_register:
1360 for (i--; i >= 0; i--) {
1361 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1362 mlxsw_sx_rx_listener[i].trap_id);
1363 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1365 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1366 &mlxsw_sx_rx_listener[i],
1372 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1374 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1377 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1378 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1379 mlxsw_sx_rx_listener[i].trap_id);
1380 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1382 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1383 &mlxsw_sx_rx_listener[i],
1388 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1390 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1391 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1395 /* Configure a flooding table, which includes only CPU port. */
1396 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1399 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1400 MLXSW_PORT_CPU_PORT, true);
1401 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1406 /* Flood different packet types using the flooding table. */
1407 mlxsw_reg_sfgc_pack(sfgc_pl,
1408 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1409 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1410 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1412 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1416 mlxsw_reg_sfgc_pack(sfgc_pl,
1417 MLXSW_REG_SFGC_TYPE_BROADCAST,
1418 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1419 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1421 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1425 mlxsw_reg_sfgc_pack(sfgc_pl,
1426 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1427 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1428 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1430 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1434 mlxsw_reg_sfgc_pack(sfgc_pl,
1435 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1436 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1437 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1439 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1443 mlxsw_reg_sfgc_pack(sfgc_pl,
1444 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1445 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1446 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1448 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1452 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1453 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1456 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1457 const struct mlxsw_bus_info *mlxsw_bus_info)
1459 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1462 mlxsw_sx->core = mlxsw_core;
1463 mlxsw_sx->bus_info = mlxsw_bus_info;
1465 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1467 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1471 err = mlxsw_sx_ports_create(mlxsw_sx);
1473 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1477 err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1479 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1480 goto err_event_register;
1483 err = mlxsw_sx_traps_init(mlxsw_sx);
1485 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1486 goto err_rx_listener_register;
1489 err = mlxsw_sx_flood_init(mlxsw_sx);
1491 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1492 goto err_flood_init;
1498 mlxsw_sx_traps_fini(mlxsw_sx);
1499 err_rx_listener_register:
1500 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1502 mlxsw_sx_ports_remove(mlxsw_sx);
1506 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1508 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1510 mlxsw_sx_traps_fini(mlxsw_sx);
1511 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1512 mlxsw_sx_ports_remove(mlxsw_sx);
1515 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1516 .used_max_vepa_channels = 1,
1517 .max_vepa_channels = 0,
1522 .used_max_system_port = 1,
1523 .max_system_port = 48000,
1524 .used_max_vlan_groups = 1,
1525 .max_vlan_groups = 127,
1526 .used_max_regions = 1,
1528 .used_flood_tables = 1,
1529 .max_flood_tables = 2,
1530 .max_vid_flood_tables = 1,
1531 .used_flood_mode = 1,
1533 .used_max_ib_mc = 1,
1540 .type = MLXSW_PORT_SWID_TYPE_ETH,
1543 .resource_query_enable = 0,
1546 static struct mlxsw_driver mlxsw_sx_driver = {
1547 .kind = MLXSW_DEVICE_KIND_SWITCHX2,
1548 .owner = THIS_MODULE,
1549 .priv_size = sizeof(struct mlxsw_sx),
1550 .init = mlxsw_sx_init,
1551 .fini = mlxsw_sx_fini,
1552 .txhdr_construct = mlxsw_sx_txhdr_construct,
1553 .txhdr_len = MLXSW_TXHDR_LEN,
1554 .profile = &mlxsw_sx_config_profile,
1557 static int __init mlxsw_sx_module_init(void)
1559 return mlxsw_core_driver_register(&mlxsw_sx_driver);
1562 static void __exit mlxsw_sx_module_exit(void)
1564 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1567 module_init(mlxsw_sx_module_init);
1568 module_exit(mlxsw_sx_module_exit);
1570 MODULE_LICENSE("Dual BSD/GPL");
1571 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1572 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1573 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);