2 * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015-2016 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/pci.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/slab.h>
44 #include <linux/device.h>
45 #include <linux/skbuff.h>
46 #include <linux/if_vlan.h>
47 #include <net/switchdev.h>
57 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
58 static const char mlxsw_sx_driver_version[] = "1.0";
63 struct mlxsw_sx_port **ports;
64 struct mlxsw_core *core;
65 const struct mlxsw_bus_info *bus_info;
69 struct mlxsw_sx_port_pcpu_stats {
74 struct u64_stats_sync syncp;
78 struct mlxsw_sx_port {
79 struct net_device *dev;
80 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
81 struct mlxsw_sx *mlxsw_sx;
92 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95 * Packet control type.
96 * 0 - Ethernet control (e.g. EMADs, LACP)
99 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102 * Packet protocol type. Must be set to 1 (Ethernet).
104 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107 * Egress TClass to be used on the egress device on the egress port.
108 * The MSB is specified in the 'ctclass3' field.
109 * Range is 0-15, where 15 is the highest priority.
111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
114 * Switch partition ID.
116 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
119 * Destination local port for unicast packets.
120 * Destination multicast ID for multicast packets.
122 * Control packets are directed to a specific egress port, while data
123 * packets are transmitted through the CPU port (0) into the switch partition,
124 * where forwarding rules are applied.
126 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
129 * See field 'etclass'.
131 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
134 * RDQ for control packets sent to remote CPU.
135 * Must be set to 0x1F for EMADs, otherwise 0.
137 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
140 * Signature control for packets going to CPU. Must be set to 0.
142 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
145 * Stacking protocl signature. Must be set to 0xE0E0.
147 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
152 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
155 * EMAD bit. Must be set for EMADs.
157 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
161 * 6 - Control packets
163 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
165 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
166 const struct mlxsw_tx_info *tx_info)
168 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
169 bool is_emad = tx_info->is_emad;
171 memset(txhdr, 0, MLXSW_TXHDR_LEN);
173 /* We currently set default values for the egress tclass (QoS). */
174 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
175 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
176 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
177 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
178 MLXSW_TXHDR_ETCLASS_5);
179 mlxsw_tx_hdr_swid_set(txhdr, 0);
180 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
181 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
182 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
183 MLXSW_TXHDR_RDQ_OTHER);
184 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
185 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
186 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
187 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
188 MLXSW_TXHDR_NOT_EMAD);
189 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
192 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
195 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
196 char paos_pl[MLXSW_REG_PAOS_LEN];
198 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
199 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
200 MLXSW_PORT_ADMIN_STATUS_DOWN);
201 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
204 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
207 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
208 char paos_pl[MLXSW_REG_PAOS_LEN];
212 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
213 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
216 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
217 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
221 static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
224 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
225 char pmtu_pl[MLXSW_REG_PMTU_LEN];
229 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
230 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
233 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
239 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
242 static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
245 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
246 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
249 static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
252 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
255 static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
258 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
259 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
262 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
263 mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
264 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
268 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
270 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
271 char pspa_pl[MLXSW_REG_PSPA_LEN];
273 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
274 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
278 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
280 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
281 char sspr_pl[MLXSW_REG_SSPR_LEN];
283 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
284 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
287 static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
288 u8 local_port, u8 *p_module,
291 char pmlp_pl[MLXSW_REG_PMLP_LEN];
294 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
295 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
298 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
299 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
303 static int mlxsw_sx_port_open(struct net_device *dev)
305 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
308 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
311 netif_start_queue(dev);
315 static int mlxsw_sx_port_stop(struct net_device *dev)
317 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
319 netif_stop_queue(dev);
320 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
323 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
324 struct net_device *dev)
326 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
327 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
328 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
329 const struct mlxsw_tx_info tx_info = {
330 .local_port = mlxsw_sx_port->local_port,
336 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
337 return NETDEV_TX_BUSY;
339 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
340 struct sk_buff *skb_orig = skb;
342 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
344 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
345 dev_kfree_skb_any(skb_orig);
349 mlxsw_sx_txhdr_construct(skb, &tx_info);
350 /* TX header is consumed by HW on the way so we shouldn't count its
351 * bytes as being sent.
353 len = skb->len - MLXSW_TXHDR_LEN;
354 /* Due to a race we might fail here because of a full queue. In that
355 * unlikely case we simply drop the packet.
357 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
360 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
361 u64_stats_update_begin(&pcpu_stats->syncp);
362 pcpu_stats->tx_packets++;
363 pcpu_stats->tx_bytes += len;
364 u64_stats_update_end(&pcpu_stats->syncp);
366 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
367 dev_kfree_skb_any(skb);
372 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
374 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
377 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
384 static struct rtnl_link_stats64 *
385 mlxsw_sx_port_get_stats64(struct net_device *dev,
386 struct rtnl_link_stats64 *stats)
388 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
389 struct mlxsw_sx_port_pcpu_stats *p;
390 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
395 for_each_possible_cpu(i) {
396 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
398 start = u64_stats_fetch_begin_irq(&p->syncp);
399 rx_packets = p->rx_packets;
400 rx_bytes = p->rx_bytes;
401 tx_packets = p->tx_packets;
402 tx_bytes = p->tx_bytes;
403 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
405 stats->rx_packets += rx_packets;
406 stats->rx_bytes += rx_bytes;
407 stats->tx_packets += tx_packets;
408 stats->tx_bytes += tx_bytes;
409 /* tx_dropped is u32, updated without syncp protection. */
410 tx_dropped += p->tx_dropped;
412 stats->tx_dropped = tx_dropped;
416 static int mlxsw_sx_port_get_phys_port_name(struct net_device *dev, char *name,
419 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
422 err = snprintf(name, len, "p%d", mlxsw_sx_port->mapping.module + 1);
429 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
430 .ndo_open = mlxsw_sx_port_open,
431 .ndo_stop = mlxsw_sx_port_stop,
432 .ndo_start_xmit = mlxsw_sx_port_xmit,
433 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
434 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
435 .ndo_get_phys_port_name = mlxsw_sx_port_get_phys_port_name,
438 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
439 struct ethtool_drvinfo *drvinfo)
441 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
442 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
444 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
445 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
446 sizeof(drvinfo->version));
447 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
449 mlxsw_sx->bus_info->fw_rev.major,
450 mlxsw_sx->bus_info->fw_rev.minor,
451 mlxsw_sx->bus_info->fw_rev.subminor);
452 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
453 sizeof(drvinfo->bus_info));
456 struct mlxsw_sx_port_hw_stats {
457 char str[ETH_GSTRING_LEN];
458 u64 (*getter)(const char *payload);
461 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
463 .str = "a_frames_transmitted_ok",
464 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
467 .str = "a_frames_received_ok",
468 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
471 .str = "a_frame_check_sequence_errors",
472 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
475 .str = "a_alignment_errors",
476 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
479 .str = "a_octets_transmitted_ok",
480 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
483 .str = "a_octets_received_ok",
484 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
487 .str = "a_multicast_frames_xmitted_ok",
488 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
491 .str = "a_broadcast_frames_xmitted_ok",
492 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
495 .str = "a_multicast_frames_received_ok",
496 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
499 .str = "a_broadcast_frames_received_ok",
500 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
503 .str = "a_in_range_length_errors",
504 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
507 .str = "a_out_of_range_length_field",
508 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
511 .str = "a_frame_too_long_errors",
512 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
515 .str = "a_symbol_error_during_carrier",
516 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
519 .str = "a_mac_control_frames_transmitted",
520 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
523 .str = "a_mac_control_frames_received",
524 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
527 .str = "a_unsupported_opcodes_received",
528 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
531 .str = "a_pause_mac_ctrl_frames_received",
532 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
535 .str = "a_pause_mac_ctrl_frames_xmitted",
536 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
540 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
542 static void mlxsw_sx_port_get_strings(struct net_device *dev,
543 u32 stringset, u8 *data)
550 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
551 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
553 p += ETH_GSTRING_LEN;
559 static void mlxsw_sx_port_get_stats(struct net_device *dev,
560 struct ethtool_stats *stats, u64 *data)
562 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
563 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
564 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
568 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
569 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
570 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
571 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
572 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
575 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
579 return MLXSW_SX_PORT_HW_STATS_LEN;
585 struct mlxsw_sx_port_link_mode {
592 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
594 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
595 .supported = SUPPORTED_100baseT_Full,
596 .advertised = ADVERTISED_100baseT_Full,
600 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
604 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
605 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
606 .supported = SUPPORTED_1000baseKX_Full,
607 .advertised = ADVERTISED_1000baseKX_Full,
611 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
612 .supported = SUPPORTED_10000baseT_Full,
613 .advertised = ADVERTISED_10000baseT_Full,
617 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
618 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
619 .supported = SUPPORTED_10000baseKX4_Full,
620 .advertised = ADVERTISED_10000baseKX4_Full,
624 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
625 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
626 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
627 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
628 .supported = SUPPORTED_10000baseKR_Full,
629 .advertised = ADVERTISED_10000baseKR_Full,
633 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
634 .supported = SUPPORTED_20000baseKR2_Full,
635 .advertised = ADVERTISED_20000baseKR2_Full,
639 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
640 .supported = SUPPORTED_40000baseCR4_Full,
641 .advertised = ADVERTISED_40000baseCR4_Full,
645 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
646 .supported = SUPPORTED_40000baseKR4_Full,
647 .advertised = ADVERTISED_40000baseKR4_Full,
651 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
652 .supported = SUPPORTED_40000baseSR4_Full,
653 .advertised = ADVERTISED_40000baseSR4_Full,
657 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
658 .supported = SUPPORTED_40000baseLR4_Full,
659 .advertised = ADVERTISED_40000baseLR4_Full,
663 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
664 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
665 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
669 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
670 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
671 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
675 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
676 .supported = SUPPORTED_56000baseKR4_Full,
677 .advertised = ADVERTISED_56000baseKR4_Full,
681 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
682 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
683 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
684 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
689 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
690 #define MLXSW_SX_PORT_BASE_SPEED 10000 /* Mb/s */
692 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
694 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
695 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
696 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
697 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
698 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
699 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
700 return SUPPORTED_FIBRE;
702 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
703 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
704 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
705 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
706 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
707 return SUPPORTED_Backplane;
711 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
716 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
717 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
718 modes |= mlxsw_sx_port_link_mode[i].supported;
723 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
728 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
729 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
730 modes |= mlxsw_sx_port_link_mode[i].advertised;
735 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
736 struct ethtool_cmd *cmd)
738 u32 speed = SPEED_UNKNOWN;
739 u8 duplex = DUPLEX_UNKNOWN;
745 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
746 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
747 speed = mlxsw_sx_port_link_mode[i].speed;
748 duplex = DUPLEX_FULL;
753 ethtool_cmd_speed_set(cmd, speed);
754 cmd->duplex = duplex;
757 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
759 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
760 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
761 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
762 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
765 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
766 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
767 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
770 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
771 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
772 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
773 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
779 static int mlxsw_sx_port_get_settings(struct net_device *dev,
780 struct ethtool_cmd *cmd)
782 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
783 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
784 char ptys_pl[MLXSW_REG_PTYS_LEN];
790 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
791 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
793 netdev_err(dev, "Failed to get proto");
796 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap,
797 ð_proto_admin, ð_proto_oper);
799 cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
800 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
801 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
802 cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
803 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
804 eth_proto_oper, cmd);
806 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
807 cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
808 cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
810 cmd->transceiver = XCVR_INTERNAL;
814 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
819 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
820 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
821 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
826 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
831 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
832 if (speed == mlxsw_sx_port_link_mode[i].speed)
833 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
838 static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
843 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
844 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
845 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
850 static int mlxsw_sx_port_set_settings(struct net_device *dev,
851 struct ethtool_cmd *cmd)
853 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
854 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
855 char ptys_pl[MLXSW_REG_PTYS_LEN];
863 speed = ethtool_cmd_speed(cmd);
865 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
866 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
867 mlxsw_sx_to_ptys_speed(speed);
869 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
870 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
872 netdev_err(dev, "Failed to get proto");
875 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
878 eth_proto_new = eth_proto_new & eth_proto_cap;
879 if (!eth_proto_new) {
880 netdev_err(dev, "Not supported proto admin requested");
883 if (eth_proto_new == eth_proto_admin)
886 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
888 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
890 netdev_err(dev, "Failed to set proto admin");
894 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
896 netdev_err(dev, "Failed to get oper status");
902 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
904 netdev_err(dev, "Failed to set admin status");
908 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
910 netdev_err(dev, "Failed to set admin status");
917 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
918 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
919 .get_link = ethtool_op_get_link,
920 .get_strings = mlxsw_sx_port_get_strings,
921 .get_ethtool_stats = mlxsw_sx_port_get_stats,
922 .get_sset_count = mlxsw_sx_port_get_sset_count,
923 .get_settings = mlxsw_sx_port_get_settings,
924 .set_settings = mlxsw_sx_port_set_settings,
927 static int mlxsw_sx_port_attr_get(struct net_device *dev,
928 struct switchdev_attr *attr)
930 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
931 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
934 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
935 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
936 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
945 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
946 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
949 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
951 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
954 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
957 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
961 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
963 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
964 struct net_device *dev = mlxsw_sx_port->dev;
965 char ppad_pl[MLXSW_REG_PPAD_LEN];
968 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
969 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
972 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
973 /* The last byte value in base mac address is guaranteed
974 * to be such it does not overflow when adding local_port
977 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
981 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
982 u16 vid, enum mlxsw_reg_spms_state state)
984 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
988 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
991 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
992 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
993 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
998 static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
999 u16 speed, u16 width)
1001 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
1002 char ptys_pl[MLXSW_REG_PTYS_LEN];
1004 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
1006 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
1010 mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
1012 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
1013 u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
1014 char ptys_pl[MLXSW_REG_PTYS_LEN];
1015 u32 eth_proto_admin;
1017 eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
1018 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
1020 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
1024 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
1025 enum mlxsw_reg_spmlr_learn_mode mode)
1027 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
1028 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
1030 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
1031 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
1034 static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1035 u8 module, u8 width)
1037 struct mlxsw_sx_port *mlxsw_sx_port;
1038 struct net_device *dev;
1041 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
1044 SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
1045 mlxsw_sx_port = netdev_priv(dev);
1046 mlxsw_sx_port->dev = dev;
1047 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1048 mlxsw_sx_port->local_port = local_port;
1049 mlxsw_sx_port->mapping.module = module;
1051 mlxsw_sx_port->pcpu_stats =
1052 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
1053 if (!mlxsw_sx_port->pcpu_stats) {
1055 goto err_alloc_stats;
1058 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
1059 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
1060 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
1062 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
1064 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
1065 mlxsw_sx_port->local_port);
1066 goto err_dev_addr_get;
1069 netif_carrier_off(dev);
1071 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1072 NETIF_F_VLAN_CHALLENGED;
1075 dev->max_mtu = ETH_MAX_MTU;
1077 /* Each packet needs to have a Tx header (metadata) on top all other
1080 dev->needed_headroom = MLXSW_TXHDR_LEN;
1082 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1084 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1085 mlxsw_sx_port->local_port);
1086 goto err_port_system_port_mapping_set;
1089 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1091 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1092 mlxsw_sx_port->local_port);
1093 goto err_port_swid_set;
1096 err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1098 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1099 mlxsw_sx_port->local_port);
1100 goto err_port_speed_set;
1103 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1105 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1106 mlxsw_sx_port->local_port);
1107 goto err_port_mtu_set;
1110 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1112 goto err_port_admin_status_set;
1114 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1115 MLXSW_PORT_DEFAULT_VID,
1116 MLXSW_REG_SPMS_STATE_FORWARDING);
1118 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1119 mlxsw_sx_port->local_port);
1120 goto err_port_stp_state_set;
1123 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1124 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1126 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1127 mlxsw_sx_port->local_port);
1128 goto err_port_mac_learning_mode_set;
1131 err = register_netdev(dev);
1133 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1134 mlxsw_sx_port->local_port);
1135 goto err_register_netdev;
1138 mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1139 mlxsw_sx_port, dev, false, 0);
1140 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1143 err_register_netdev:
1144 err_port_mac_learning_mode_set:
1145 err_port_stp_state_set:
1146 err_port_admin_status_set:
1149 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1151 err_port_system_port_mapping_set:
1153 free_percpu(mlxsw_sx_port->pcpu_stats);
1159 static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1160 u8 module, u8 width)
1164 err = mlxsw_core_port_init(mlxsw_sx->core, local_port);
1166 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1170 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1172 goto err_port_create;
1177 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1181 static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1183 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1185 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1186 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1187 mlxsw_sx->ports[local_port] = NULL;
1188 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1189 free_percpu(mlxsw_sx_port->pcpu_stats);
1190 free_netdev(mlxsw_sx_port->dev);
1193 static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1195 return mlxsw_sx->ports[local_port] != NULL;
1198 static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1199 u8 module, u8 width)
1201 struct mlxsw_sx_port *mlxsw_sx_port;
1204 mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1207 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1208 mlxsw_sx_port->local_port = local_port;
1209 mlxsw_sx_port->mapping.module = module;
1211 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1213 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1214 mlxsw_sx_port->local_port);
1215 goto err_port_system_port_mapping_set;
1218 /* Adding port to Infiniband swid (1) */
1219 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1221 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1222 mlxsw_sx_port->local_port);
1223 goto err_port_swid_set;
1226 /* Expose the IB port number as it's front panel name */
1227 err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1229 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1230 mlxsw_sx_port->local_port);
1231 goto err_port_ib_set;
1234 /* Supports all speeds from SDR to FDR (bitmask) and support bus width
1235 * of 1x, 2x and 4x (3 bits bitmask)
1237 err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1238 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1241 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1242 mlxsw_sx_port->local_port);
1243 goto err_port_speed_set;
1246 /* Change to the maximum MTU the device supports, the SMA will take
1247 * care of the active MTU
1249 err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1251 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1252 mlxsw_sx_port->local_port);
1253 goto err_port_mtu_set;
1256 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1258 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1259 mlxsw_sx_port->local_port);
1260 goto err_port_admin_set;
1263 mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1265 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1272 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1274 err_port_system_port_mapping_set:
1275 kfree(mlxsw_sx_port);
1279 static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1281 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1283 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1284 mlxsw_sx->ports[local_port] = NULL;
1285 mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1286 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1287 kfree(mlxsw_sx_port);
1290 static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1292 enum devlink_port_type port_type =
1293 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1295 if (port_type == DEVLINK_PORT_TYPE_ETH)
1296 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1297 else if (port_type == DEVLINK_PORT_TYPE_IB)
1298 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1301 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1303 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1304 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1307 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1311 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1312 if (mlxsw_sx_port_created(mlxsw_sx, i))
1313 mlxsw_sx_port_remove(mlxsw_sx, i);
1314 kfree(mlxsw_sx->ports);
1317 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1324 alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1325 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1326 if (!mlxsw_sx->ports)
1329 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1330 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1333 goto err_port_module_info_get;
1336 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1338 goto err_port_create;
1343 err_port_module_info_get:
1344 for (i--; i >= 1; i--)
1345 if (mlxsw_sx_port_created(mlxsw_sx, i))
1346 mlxsw_sx_port_remove(mlxsw_sx, i);
1347 kfree(mlxsw_sx->ports);
1351 static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1352 enum mlxsw_reg_pude_oper_status status)
1354 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1355 netdev_info(mlxsw_sx_port->dev, "link up\n");
1356 netif_carrier_on(mlxsw_sx_port->dev);
1358 netdev_info(mlxsw_sx_port->dev, "link down\n");
1359 netif_carrier_off(mlxsw_sx_port->dev);
1363 static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1364 enum mlxsw_reg_pude_oper_status status)
1366 if (status == MLXSW_PORT_OPER_STATUS_UP)
1367 pr_info("ib link for port %d - up\n",
1368 mlxsw_sx_port->mapping.module + 1);
1370 pr_info("ib link for port %d - down\n",
1371 mlxsw_sx_port->mapping.module + 1);
1374 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1375 char *pude_pl, void *priv)
1377 struct mlxsw_sx *mlxsw_sx = priv;
1378 struct mlxsw_sx_port *mlxsw_sx_port;
1379 enum mlxsw_reg_pude_oper_status status;
1380 enum devlink_port_type port_type;
1383 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1384 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1385 if (!mlxsw_sx_port) {
1386 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1391 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1392 port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1393 if (port_type == DEVLINK_PORT_TYPE_ETH)
1394 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1395 else if (port_type == DEVLINK_PORT_TYPE_IB)
1396 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1399 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1402 struct mlxsw_sx *mlxsw_sx = priv;
1403 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1404 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1406 if (unlikely(!mlxsw_sx_port)) {
1407 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1412 skb->dev = mlxsw_sx_port->dev;
1414 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1415 u64_stats_update_begin(&pcpu_stats->syncp);
1416 pcpu_stats->rx_packets++;
1417 pcpu_stats->rx_bytes += skb->len;
1418 u64_stats_update_end(&pcpu_stats->syncp);
1420 skb->protocol = eth_type_trans(skb, skb->dev);
1421 netif_receive_skb(skb);
1424 static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1425 enum devlink_port_type new_type)
1427 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1431 if (new_type == DEVLINK_PORT_TYPE_AUTO)
1434 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1435 err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1438 goto err_port_module_info_get;
1440 if (new_type == DEVLINK_PORT_TYPE_ETH)
1441 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1443 else if (new_type == DEVLINK_PORT_TYPE_IB)
1444 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1447 err_port_module_info_get:
1451 #define MLXSW_SX_RXL(_trap_id) \
1452 MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1453 false, SX2_RX, FORWARD)
1455 static const struct mlxsw_listener mlxsw_sx_listener[] = {
1456 MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1457 MLXSW_SX_RXL(FDB_MC),
1460 MLXSW_SX_RXL(EAPOL),
1464 MLXSW_SX_RXL(RPVST),
1466 MLXSW_SX_RXL(IGMP_QUERY),
1467 MLXSW_SX_RXL(IGMP_V1_REPORT),
1468 MLXSW_SX_RXL(IGMP_V2_REPORT),
1469 MLXSW_SX_RXL(IGMP_V2_LEAVE),
1470 MLXSW_SX_RXL(IGMP_V3_REPORT),
1473 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1475 char htgt_pl[MLXSW_REG_HTGT_LEN];
1479 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1480 MLXSW_REG_HTGT_INVALID_POLICER,
1481 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1482 MLXSW_REG_HTGT_DEFAULT_TC);
1483 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1484 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1486 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1490 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1491 MLXSW_REG_HTGT_INVALID_POLICER,
1492 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1493 MLXSW_REG_HTGT_DEFAULT_TC);
1494 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1495 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1497 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1501 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1502 err = mlxsw_core_trap_register(mlxsw_sx->core,
1503 &mlxsw_sx_listener[i],
1506 goto err_listener_register;
1511 err_listener_register:
1512 for (i--; i >= 0; i--) {
1513 mlxsw_core_trap_unregister(mlxsw_sx->core,
1514 &mlxsw_sx_listener[i],
1520 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1524 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1525 mlxsw_core_trap_unregister(mlxsw_sx->core,
1526 &mlxsw_sx_listener[i],
1531 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1533 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1534 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1538 /* Configure a flooding table, which includes only CPU port. */
1539 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1542 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1543 MLXSW_PORT_CPU_PORT, true);
1544 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1549 /* Flood different packet types using the flooding table. */
1550 mlxsw_reg_sfgc_pack(sfgc_pl,
1551 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1552 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1553 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1555 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1559 mlxsw_reg_sfgc_pack(sfgc_pl,
1560 MLXSW_REG_SFGC_TYPE_BROADCAST,
1561 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1562 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1564 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1568 mlxsw_reg_sfgc_pack(sfgc_pl,
1569 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1570 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1571 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1573 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1577 mlxsw_reg_sfgc_pack(sfgc_pl,
1578 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1579 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1580 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1582 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1586 mlxsw_reg_sfgc_pack(sfgc_pl,
1587 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1588 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1589 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1591 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1595 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1596 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1599 static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1601 char htgt_pl[MLXSW_REG_HTGT_LEN];
1603 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1604 MLXSW_REG_HTGT_INVALID_POLICER,
1605 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1606 MLXSW_REG_HTGT_DEFAULT_TC);
1607 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1608 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1609 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1610 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1613 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1614 const struct mlxsw_bus_info *mlxsw_bus_info)
1616 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1619 mlxsw_sx->core = mlxsw_core;
1620 mlxsw_sx->bus_info = mlxsw_bus_info;
1622 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1624 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1628 err = mlxsw_sx_ports_create(mlxsw_sx);
1630 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1634 err = mlxsw_sx_traps_init(mlxsw_sx);
1636 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1637 goto err_listener_register;
1640 err = mlxsw_sx_flood_init(mlxsw_sx);
1642 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1643 goto err_flood_init;
1649 mlxsw_sx_traps_fini(mlxsw_sx);
1650 err_listener_register:
1651 mlxsw_sx_ports_remove(mlxsw_sx);
1655 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1657 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1659 mlxsw_sx_traps_fini(mlxsw_sx);
1660 mlxsw_sx_ports_remove(mlxsw_sx);
1663 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1664 .used_max_vepa_channels = 1,
1665 .max_vepa_channels = 0,
1670 .used_max_system_port = 1,
1671 .max_system_port = 48000,
1672 .used_max_vlan_groups = 1,
1673 .max_vlan_groups = 127,
1674 .used_max_regions = 1,
1676 .used_flood_tables = 1,
1677 .max_flood_tables = 2,
1678 .max_vid_flood_tables = 1,
1679 .used_flood_mode = 1,
1681 .used_max_ib_mc = 1,
1688 .type = MLXSW_PORT_SWID_TYPE_ETH,
1692 .type = MLXSW_PORT_SWID_TYPE_IB,
1695 .resource_query_enable = 0,
1698 static struct mlxsw_driver mlxsw_sx_driver = {
1699 .kind = mlxsw_sx_driver_name,
1700 .priv_size = sizeof(struct mlxsw_sx),
1701 .init = mlxsw_sx_init,
1702 .fini = mlxsw_sx_fini,
1703 .basic_trap_groups_set = mlxsw_sx_basic_trap_groups_set,
1704 .txhdr_construct = mlxsw_sx_txhdr_construct,
1705 .txhdr_len = MLXSW_TXHDR_LEN,
1706 .profile = &mlxsw_sx_config_profile,
1707 .port_type_set = mlxsw_sx_port_type_set,
1710 static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1711 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1715 static struct pci_driver mlxsw_sx_pci_driver = {
1716 .name = mlxsw_sx_driver_name,
1717 .id_table = mlxsw_sx_pci_id_table,
1720 static int __init mlxsw_sx_module_init(void)
1724 err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1728 err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1730 goto err_pci_driver_register;
1734 err_pci_driver_register:
1735 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1739 static void __exit mlxsw_sx_module_exit(void)
1741 mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1742 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1745 module_init(mlxsw_sx_module_init);
1746 module_exit(mlxsw_sx_module_exit);
1748 MODULE_LICENSE("Dual BSD/GPL");
1749 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1750 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1751 MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);