drivers/net/ethernet/mellanox/mlxsw/spectrum.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/slab.h>
  12 #include <linux/device.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/bitops.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/dcbnl.h>
  22 #include <linux/inetdevice.h>
  23 #include <linux/netlink.h>
  24 #include <linux/jhash.h>
  25 #include <linux/log2.h>
  26 #include <net/switchdev.h>
  27 #include <net/pkt_cls.h>
  28 #include <net/netevent.h>
  29 #include <net/addrconf.h>
  30
  31 #include "spectrum.h"
  32 #include "pci.h"
  33 #include "core.h"
  34 #include "core_env.h"
  35 #include "reg.h"
  36 #include "port.h"
  37 #include "trap.h"
  38 #include "txheader.h"
  39 #include "spectrum_cnt.h"
  40 #include "spectrum_dpipe.h"
  41 #include "spectrum_acl_flex_actions.h"
  42 #include "spectrum_span.h"
  43 #include "spectrum_ptp.h"
  44 #include "spectrum_trap.h"
  45
  46 #define MLXSW_SP1_FWREV_MAJOR 13
  47 #define MLXSW_SP1_FWREV_MINOR 2008
  48 #define MLXSW_SP1_FWREV_SUBMINOR 1310
  49 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  50
  51 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  52         .major = MLXSW_SP1_FWREV_MAJOR,
  53         .minor = MLXSW_SP1_FWREV_MINOR,
  54         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  55         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  56 };
  57
  58 #define MLXSW_SP1_FW_FILENAME \
  59         "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
  60         "." __stringify(MLXSW_SP1_FWREV_MINOR) \
  61         "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
  62
  63 #define MLXSW_SP2_FWREV_MAJOR 29
  64 #define MLXSW_SP2_FWREV_MINOR 2008
  65 #define MLXSW_SP2_FWREV_SUBMINOR 1310
  66
  67 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
  68         .major = MLXSW_SP2_FWREV_MAJOR,
  69         .minor = MLXSW_SP2_FWREV_MINOR,
  70         .subminor = MLXSW_SP2_FWREV_SUBMINOR,
  71 };
  72
  73 #define MLXSW_SP2_FW_FILENAME \
  74         "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
  75         "." __stringify(MLXSW_SP2_FWREV_MINOR) \
  76         "." __stringify(MLXSW_SP2_FWREV_SUBMINOR) ".mfa2"
  77
  78 #define MLXSW_SP3_FWREV_MAJOR 30
  79 #define MLXSW_SP3_FWREV_MINOR 2008
  80 #define MLXSW_SP3_FWREV_SUBMINOR 1310
  81
  82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = {
  83         .major = MLXSW_SP3_FWREV_MAJOR,
  84         .minor = MLXSW_SP3_FWREV_MINOR,
  85         .subminor = MLXSW_SP3_FWREV_SUBMINOR,
  86 };
  87
  88 #define MLXSW_SP3_FW_FILENAME \
  89         "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \
  90         "." __stringify(MLXSW_SP3_FWREV_MINOR) \
  91         "." __stringify(MLXSW_SP3_FWREV_SUBMINOR) ".mfa2"
  92
  93 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  94 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  95 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
  96
  97 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
  98         0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
  99 };
 100 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
 101         0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
 102 };
 103
 104 /* tx_hdr_version
 105  * Tx header version.
 106  * Must be set to 1.
 107  */
 108 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
 109
 110 /* tx_hdr_ctl
 111  * Packet control type.
 112  * 0 - Ethernet control (e.g. EMADs, LACP)
 113  * 1 - Ethernet data
 114  */
 115 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
 116
 117 /* tx_hdr_proto
 118  * Packet protocol type. Must be set to 1 (Ethernet).
 119  */
 120 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
 121
 122 /* tx_hdr_rx_is_router
 123  * Packet is sent from the router. Valid for data packets only.
 124  */
 125 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
 126
 127 /* tx_hdr_fid_valid
 128  * Indicates if the 'fid' field is valid and should be used for
 129  * forwarding lookup. Valid for data packets only.
 130  */
 131 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
 132
 133 /* tx_hdr_swid
 134  * Switch partition ID. Must be set to 0.
 135  */
 136 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 137
 138 /* tx_hdr_control_tclass
 139  * Indicates if the packet should use the control TClass and not one
 140  * of the data TClasses.
 141  */
 142 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
 143
 144 /* tx_hdr_etclass
 145  * Egress TClass to be used on the egress device on the egress port.
 146  */
 147 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
 148
 149 /* tx_hdr_port_mid
 150  * Destination local port for unicast packets.
 151  * Destination multicast ID for multicast packets.
 152  *
 153  * Control packets are directed to a specific egress port, while data
 154  * packets are transmitted through the CPU port (0) into the switch partition,
 155  * where forwarding rules are applied.
 156  */
 157 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 158
 159 /* tx_hdr_fid
 160  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
 161  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
 162  * Valid for data packets only.
 163  */
 164 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
 165
 166 /* tx_hdr_type
 167  * 0 - Data packets
 168  * 6 - Control packets
 169  */
 170 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 171
 172 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
 173                               unsigned int counter_index, u64 *packets,
 174                               u64 *bytes)
 175 {
 176         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 177         int err;
 178
 179         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
 180                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 181         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 182         if (err)
 183                 return err;
 184         if (packets)
 185                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
 186         if (bytes)
 187                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
 188         return 0;
 189 }
 190
 191 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
 192                                        unsigned int counter_index)
 193 {
 194         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 195
 196         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
 197                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 198         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 199 }
 200
 201 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
 202                                 unsigned int *p_counter_index)
 203 {
 204         int err;
 205
 206         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 207                                      p_counter_index);
 208         if (err)
 209                 return err;
 210         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
 211         if (err)
 212                 goto err_counter_clear;
 213         return 0;
 214
 215 err_counter_clear:
 216         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 217                               *p_counter_index);
 218         return err;
 219 }
 220
 221 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
 222                                 unsigned int counter_index)
 223 {
 224          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 225                                counter_index);
 226 }
 227
 228 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
 229                                      const struct mlxsw_tx_info *tx_info)
 230 {
 231         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 232
 233         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 234
 235         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
 236         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 237         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 238         mlxsw_tx_hdr_swid_set(txhdr, 0);
 239         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
 240         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 241         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 242 }
 243
 244 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
 245 {
 246         switch (state) {
 247         case BR_STATE_FORWARDING:
 248                 return MLXSW_REG_SPMS_STATE_FORWARDING;
 249         case BR_STATE_LEARNING:
 250                 return MLXSW_REG_SPMS_STATE_LEARNING;
 251         case BR_STATE_LISTENING:
 252         case BR_STATE_DISABLED:
 253         case BR_STATE_BLOCKING:
 254                 return MLXSW_REG_SPMS_STATE_DISCARDING;
 255         default:
 256                 BUG();
 257         }
 258 }
 259
 260 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 261                               u8 state)
 262 {
 263         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
 264         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 265         char *spms_pl;
 266         int err;
 267
 268         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 269         if (!spms_pl)
 270                 return -ENOMEM;
 271         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
 272         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
 273
 274         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
 275         kfree(spms_pl);
 276         return err;
 277 }
 278
 279 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
 280 {
 281         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 282         int err;
 283
 284         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
 285         if (err)
 286                 return err;
 287         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
 288         return 0;
 289 }
 290
 291 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
 292                                    bool is_up)
 293 {
 294         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 295         char paos_pl[MLXSW_REG_PAOS_LEN];
 296
 297         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
 298                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 299                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 300         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
 301 }
 302
 303 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
 304                                       unsigned char *addr)
 305 {
 306         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 307         char ppad_pl[MLXSW_REG_PPAD_LEN];
 308
 309         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
 310         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
 311         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
 312 }
 313
 314 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
 315 {
 316         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 317         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
 318
 319         ether_addr_copy(addr, mlxsw_sp->base_mac);
 320         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
 321         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
 322 }
 323
 324 static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu)
 325 {
 326         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 327         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 328         int err;
 329
 330         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
 331         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 332         if (err)
 333                 return err;
 334
 335         *p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 336         return 0;
 337 }
 338
 339 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
 340 {
 341         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 342         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 343
 344         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 345         if (mtu > mlxsw_sp_port->max_mtu)
 346                 return -EINVAL;
 347
 348         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
 349         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 350 }
 351
 352 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
 353 {
 354         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 355         char pspa_pl[MLXSW_REG_PSPA_LEN];
 356
 357         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
 358         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
 359 }
 360
 361 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
 362 {
 363         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 364         char svpe_pl[MLXSW_REG_SVPE_LEN];
 365
 366         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
 367         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
 368 }
 369
 370 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 371                                    bool learn_enable)
 372 {
 373         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 374         char *spvmlr_pl;
 375         int err;
 376
 377         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
 378         if (!spvmlr_pl)
 379                 return -ENOMEM;
 380         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
 381                               learn_enable);
 382         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
 383         kfree(spvmlr_pl);
 384         return err;
 385 }
 386
 387 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
 388                                     u16 vid)
 389 {
 390         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 391         char spvid_pl[MLXSW_REG_SPVID_LEN];
 392
 393         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
 394         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
 395 }
 396
 397 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
 398                                             bool allow)
 399 {
 400         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 401         char spaft_pl[MLXSW_REG_SPAFT_LEN];
 402
 403         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
 404         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
 405 }
 406
 407 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 408 {
 409         int err;
 410
 411         if (!vid) {
 412                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
 413                 if (err)
 414                         return err;
 415         } else {
 416                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
 417                 if (err)
 418                         return err;
 419                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
 420                 if (err)
 421                         goto err_port_allow_untagged_set;
 422         }
 423
 424         mlxsw_sp_port->pvid = vid;
 425         return 0;
 426
 427 err_port_allow_untagged_set:
 428         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
 429         return err;
 430 }
 431
 432 static int
 433 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
 434 {
 435         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 436         char sspr_pl[MLXSW_REG_SSPR_LEN];
 437
 438         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
 439         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
 440 }
 441
 442 static int
 443 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 444                               struct mlxsw_sp_port_mapping *port_mapping)
 445 {
 446         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 447         bool separate_rxtx;
 448         u8 module;
 449         u8 width;
 450         int err;
 451         int i;
 452
 453         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 454         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 455         if (err)
 456                 return err;
 457         module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 458         width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 459         separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
 460
 461         if (width && !is_power_of_2(width)) {
 462                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
 463                         local_port);
 464                 return -EINVAL;
 465         }
 466
 467         for (i = 0; i < width; i++) {
 468                 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
 469                         dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
 470                                 local_port);
 471                         return -EINVAL;
 472                 }
 473                 if (separate_rxtx &&
 474                     mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
 475                     mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
 476                         dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
 477                                 local_port);
 478                         return -EINVAL;
 479                 }
 480                 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i) {
 481                         dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
 482                                 local_port);
 483                         return -EINVAL;
 484                 }
 485         }
 486
 487         port_mapping->module = module;
 488         port_mapping->width = width;
 489         port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
 490         return 0;
 491 }
 492
 493 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port)
 494 {
 495         struct mlxsw_sp_port_mapping *port_mapping = &mlxsw_sp_port->mapping;
 496         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 497         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 498         int i;
 499
 500         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 501         mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
 502         for (i = 0; i < port_mapping->width; i++) {
 503                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
 504                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
 505         }
 506
 507         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 508 }
 509
 510 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
 511 {
 512         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 513         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 514
 515         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 516         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
 517         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 518 }
 519
 520 static int mlxsw_sp_port_open(struct net_device *dev)
 521 {
 522         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 523         int err;
 524
 525         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
 526         if (err)
 527                 return err;
 528         netif_start_queue(dev);
 529         return 0;
 530 }
 531
 532 static int mlxsw_sp_port_stop(struct net_device *dev)
 533 {
 534         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 535
 536         netif_stop_queue(dev);
 537         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
 538 }
 539
 540 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
 541                                       struct net_device *dev)
 542 {
 543         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 544         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 545         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
 546         const struct mlxsw_tx_info tx_info = {
 547                 .local_port = mlxsw_sp_port->local_port,
 548                 .is_emad = false,
 549         };
 550         u64 len;
 551         int err;
 552
 553         if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
 554                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 555                 dev_kfree_skb_any(skb);
 556                 return NETDEV_TX_OK;
 557         }
 558
 559         memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
 560
 561         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
 562                 return NETDEV_TX_BUSY;
 563
 564         if (eth_skb_pad(skb)) {
 565                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 566                 return NETDEV_TX_OK;
 567         }
 568
 569         mlxsw_sp_txhdr_construct(skb, &tx_info);
 570         /* TX header is consumed by HW on the way so we shouldn't count its
 571          * bytes as being sent.
 572          */
 573         len = skb->len - MLXSW_TXHDR_LEN;
 574
 575         /* Due to a race we might fail here because of a full queue. In that
 576          * unlikely case we simply drop the packet.
 577          */
 578         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
 579
 580         if (!err) {
 581                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
 582                 u64_stats_update_begin(&pcpu_stats->syncp);
 583                 pcpu_stats->tx_packets++;
 584                 pcpu_stats->tx_bytes += len;
 585                 u64_stats_update_end(&pcpu_stats->syncp);
 586         } else {
 587                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 588                 dev_kfree_skb_any(skb);
 589         }
 590         return NETDEV_TX_OK;
 591 }
 592
 593 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
 594 {
 595 }
 596
 597 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
 598 {
 599         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 600         struct sockaddr *addr = p;
 601         int err;
 602
 603         if (!is_valid_ether_addr(addr->sa_data))
 604                 return -EADDRNOTAVAIL;
 605
 606         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
 607         if (err)
 608                 return err;
 609         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 610         return 0;
 611 }
 612
 613 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
 614 {
 615         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 616         struct mlxsw_sp_hdroom orig_hdroom;
 617         struct mlxsw_sp_hdroom hdroom;
 618         int err;
 619
 620         orig_hdroom = *mlxsw_sp_port->hdroom;
 621
 622         hdroom = orig_hdroom;
 623         hdroom.mtu = mtu;
 624         mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
 625
 626         err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
 627         if (err) {
 628                 netdev_err(dev, "Failed to configure port's headroom\n");
 629                 return err;
 630         }
 631
 632         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
 633         if (err)
 634                 goto err_port_mtu_set;
 635         dev->mtu = mtu;
 636         return 0;
 637
 638 err_port_mtu_set:
 639         mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
 640         return err;
 641 }
 642
 643 static int
 644 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
 645                              struct rtnl_link_stats64 *stats)
 646 {
 647         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 648         struct mlxsw_sp_port_pcpu_stats *p;
 649         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 650         u32 tx_dropped = 0;
 651         unsigned int start;
 652         int i;
 653
 654         for_each_possible_cpu(i) {
 655                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
 656                 do {
 657                         start = u64_stats_fetch_begin_irq(&p->syncp);
 658                         rx_packets      = p->rx_packets;
 659                         rx_bytes        = p->rx_bytes;
 660                         tx_packets      = p->tx_packets;
 661                         tx_bytes        = p->tx_bytes;
 662                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 663
 664                 stats->rx_packets       += rx_packets;
 665                 stats->rx_bytes         += rx_bytes;
 666                 stats->tx_packets       += tx_packets;
 667                 stats->tx_bytes         += tx_bytes;
 668                 /* tx_dropped is u32, updated without syncp protection. */
 669                 tx_dropped      += p->tx_dropped;
 670         }
 671         stats->tx_dropped       = tx_dropped;
 672         return 0;
 673 }
 674
 675 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
 676 {
 677         switch (attr_id) {
 678         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 679                 return true;
 680         }
 681
 682         return false;
 683 }
 684
 685 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
 686                                            void *sp)
 687 {
 688         switch (attr_id) {
 689         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 690                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
 691         }
 692
 693         return -EINVAL;
 694 }
 695
 696 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
 697                                 int prio, char *ppcnt_pl)
 698 {
 699         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 700         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 701
 702         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
 703         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
 704 }
 705
 706 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
 707                                       struct rtnl_link_stats64 *stats)
 708 {
 709         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 710         int err;
 711
 712         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
 713                                           0, ppcnt_pl);
 714         if (err)
 715                 goto out;
 716
 717         stats->tx_packets =
 718                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
 719         stats->rx_packets =
 720                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
 721         stats->tx_bytes =
 722                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
 723         stats->rx_bytes =
 724                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
 725         stats->multicast =
 726                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
 727
 728         stats->rx_crc_errors =
 729                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
 730         stats->rx_frame_errors =
 731                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
 732
 733         stats->rx_length_errors = (
 734                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
 735                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
 736                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
 737
 738         stats->rx_errors = (stats->rx_crc_errors +
 739                 stats->rx_frame_errors + stats->rx_length_errors);
 740
 741 out:
 742         return err;
 743 }
 744
 745 static void
 746 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
 747                             struct mlxsw_sp_port_xstats *xstats)
 748 {
 749         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 750         int err, i;
 751
 752         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
 753                                           ppcnt_pl);
 754         if (!err)
 755                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
 756
 757         for (i = 0; i < TC_MAX_QUEUE; i++) {
 758                 err = mlxsw_sp_port_get_stats_raw(dev,
 759                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
 760                                                   i, ppcnt_pl);
 761                 if (!err)
 762                         xstats->wred_drop[i] =
 763                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
 764
 765                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
 766                                                   i, ppcnt_pl);
 767                 if (err)
 768                         continue;
 769
 770                 xstats->backlog[i] =
 771                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
 772                 xstats->tail_drop[i] =
 773                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
 774         }
 775
 776         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 777                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
 778                                                   i, ppcnt_pl);
 779                 if (err)
 780                         continue;
 781
 782                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
 783                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
 784         }
 785 }
 786
 787 static void update_stats_cache(struct work_struct *work)
 788 {
 789         struct mlxsw_sp_port *mlxsw_sp_port =
 790                 container_of(work, struct mlxsw_sp_port,
 791                              periodic_hw_stats.update_dw.work);
 792
 793         if (!netif_carrier_ok(mlxsw_sp_port->dev))
 794                 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
 795                  * necessary when port goes down.
 796                  */
 797                 goto out;
 798
 799         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
 800                                    &mlxsw_sp_port->periodic_hw_stats.stats);
 801         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
 802                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
 803
 804 out:
 805         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
 806                                MLXSW_HW_STATS_UPDATE_TIME);
 807 }
 808
 809 /* Return the stats from a cache that is updated periodically,
 810  * as this function might get called in an atomic context.
 811  */
 812 static void
 813 mlxsw_sp_port_get_stats64(struct net_device *dev,
 814                           struct rtnl_link_stats64 *stats)
 815 {
 816         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 817
 818         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
 819 }
 820
 821 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
 822                                     u16 vid_begin, u16 vid_end,
 823                                     bool is_member, bool untagged)
 824 {
 825         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 826         char *spvm_pl;
 827         int err;
 828
 829         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
 830         if (!spvm_pl)
 831                 return -ENOMEM;
 832
 833         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
 834                             vid_end, is_member, untagged);
 835         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
 836         kfree(spvm_pl);
 837         return err;
 838 }
 839
 840 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
 841                            u16 vid_end, bool is_member, bool untagged)
 842 {
 843         u16 vid, vid_e;
 844         int err;
 845
 846         for (vid = vid_begin; vid <= vid_end;
 847              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
 848                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
 849                             vid_end);
 850
 851                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
 852                                                is_member, untagged);
 853                 if (err)
 854                         return err;
 855         }
 856
 857         return 0;
 858 }
 859
 860 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
 861                                      bool flush_default)
 862 {
 863         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
 864
 865         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
 866                                  &mlxsw_sp_port->vlans_list, list) {
 867                 if (!flush_default &&
 868                     mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
 869                         continue;
 870                 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
 871         }
 872 }
 873
 874 static void
 875 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
 876 {
 877         if (mlxsw_sp_port_vlan->bridge_port)
 878                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
 879         else if (mlxsw_sp_port_vlan->fid)
 880                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
 881 }
 882
 883 struct mlxsw_sp_port_vlan *
 884 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 885 {
 886         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
 887         bool untagged = vid == MLXSW_SP_DEFAULT_VID;
 888         int err;
 889
 890         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
 891         if (mlxsw_sp_port_vlan)
 892                 return ERR_PTR(-EEXIST);
 893
 894         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
 895         if (err)
 896                 return ERR_PTR(err);
 897
 898         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
 899         if (!mlxsw_sp_port_vlan) {
 900                 err = -ENOMEM;
 901                 goto err_port_vlan_alloc;
 902         }
 903
 904         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
 905         mlxsw_sp_port_vlan->vid = vid;
 906         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
 907
 908         return mlxsw_sp_port_vlan;
 909
 910 err_port_vlan_alloc:
 911         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
 912         return ERR_PTR(err);
 913 }
 914
 915 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
 916 {
 917         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
 918         u16 vid = mlxsw_sp_port_vlan->vid;
 919
 920         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
 921         list_del(&mlxsw_sp_port_vlan->list);
 922         kfree(mlxsw_sp_port_vlan);
 923         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
 924 }
 925
 926 static int mlxsw_sp_port_add_vid(struct net_device *dev,
 927                                  __be16 __always_unused proto, u16 vid)
 928 {
 929         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 930
 931         /* VLAN 0 is added to HW filter when device goes up, but it is
 932          * reserved in our case, so simply return.
 933          */
 934         if (!vid)
 935                 return 0;
 936
 937         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
 938 }
 939
 940 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
 941                                   __be16 __always_unused proto, u16 vid)
 942 {
 943         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 944         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
 945
 946         /* VLAN 0 is removed from HW filter when device goes down, but
 947          * it is reserved in our case, so simply return.
 948          */
 949         if (!vid)
 950                 return 0;
 951
 952         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
 953         if (!mlxsw_sp_port_vlan)
 954                 return 0;
 955         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
 956
 957         return 0;
 958 }
 959
 960 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
 961                                    struct flow_block_offload *f)
 962 {
 963         switch (f->binder_type) {
 964         case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS:
 965                 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true);
 966         case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS:
 967                 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false);
 968         case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP:
 969                 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f);
 970         default:
 971                 return -EOPNOTSUPP;
 972         }
 973 }
 974
 975 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
 976                              void *type_data)
 977 {
 978         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 979
 980         switch (type) {
 981         case TC_SETUP_BLOCK:
 982                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
 983         case TC_SETUP_QDISC_RED:
 984                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
 985         case TC_SETUP_QDISC_PRIO:
 986                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
 987         case TC_SETUP_QDISC_ETS:
 988                 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
 989         case TC_SETUP_QDISC_TBF:
 990                 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
 991         case TC_SETUP_QDISC_FIFO:
 992                 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
 993         default:
 994                 return -EOPNOTSUPP;
 995         }
 996 }
 997
 998 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
 999 {
1000         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001
1002         if (!enable) {
1003                 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) ||
1004                     mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) {
1005                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1006                         return -EINVAL;
1007                 }
1008                 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block);
1009                 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block);
1010         } else {
1011                 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block);
1012                 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block);
1013         }
1014         return 0;
1015 }
1016
1017 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1018 {
1019         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1020         char pplr_pl[MLXSW_REG_PPLR_LEN];
1021         int err;
1022
1023         if (netif_running(dev))
1024                 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1025
1026         mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1027         err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1028                               pplr_pl);
1029
1030         if (netif_running(dev))
1031                 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1032
1033         return err;
1034 }
1035
1036 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1037
1038 static int mlxsw_sp_handle_feature(struct net_device *dev,
1039                                    netdev_features_t wanted_features,
1040                                    netdev_features_t feature,
1041                                    mlxsw_sp_feature_handler feature_handler)
1042 {
1043         netdev_features_t changes = wanted_features ^ dev->features;
1044         bool enable = !!(wanted_features & feature);
1045         int err;
1046
1047         if (!(changes & feature))
1048                 return 0;
1049
1050         err = feature_handler(dev, enable);
1051         if (err) {
1052                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1053                            enable ? "Enable" : "Disable", &feature, err);
1054                 return err;
1055         }
1056
1057         if (enable)
1058                 dev->features |= feature;
1059         else
1060                 dev->features &= ~feature;
1061
1062         return 0;
1063 }
1064 static int mlxsw_sp_set_features(struct net_device *dev,
1065                                  netdev_features_t features)
1066 {
1067         netdev_features_t oper_features = dev->features;
1068         int err = 0;
1069
1070         err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1071                                        mlxsw_sp_feature_hw_tc);
1072         err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1073                                        mlxsw_sp_feature_loopback);
1074
1075         if (err) {
1076                 dev->features = oper_features;
1077                 return -EINVAL;
1078         }
1079
1080         return 0;
1081 }
1082
1083 static struct devlink_port *
1084 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1085 {
1086         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1088
1089         return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1090                                                 mlxsw_sp_port->local_port);
1091 }
1092
1093 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1094                                       struct ifreq *ifr)
1095 {
1096         struct hwtstamp_config config;
1097         int err;
1098
1099         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1100                 return -EFAULT;
1101
1102         err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1103                                                              &config);
1104         if (err)
1105                 return err;
1106
1107         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1108                 return -EFAULT;
1109
1110         return 0;
1111 }
1112
1113 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1114                                       struct ifreq *ifr)
1115 {
1116         struct hwtstamp_config config;
1117         int err;
1118
1119         err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1120                                                              &config);
1121         if (err)
1122                 return err;
1123
1124         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1125                 return -EFAULT;
1126
1127         return 0;
1128 }
1129
1130 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1131 {
1132         struct hwtstamp_config config = {0};
1133
1134         mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1135 }
1136
1137 static int
1138 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1139 {
1140         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1141
1142         switch (cmd) {
1143         case SIOCSHWTSTAMP:
1144                 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1145         case SIOCGHWTSTAMP:
1146                 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1147         default:
1148                 return -EOPNOTSUPP;
1149         }
1150 }
1151
1152 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1153         .ndo_open               = mlxsw_sp_port_open,
1154         .ndo_stop               = mlxsw_sp_port_stop,
1155         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1156         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1157         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1158         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1159         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1160         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1161         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1162         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1163         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1164         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1165         .ndo_set_features       = mlxsw_sp_set_features,
1166         .ndo_get_devlink_port   = mlxsw_sp_port_get_devlink_port,
1167         .ndo_do_ioctl           = mlxsw_sp_port_ioctl,
1168 };
1169
1170 static int
1171 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
1172 {
1173         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1174         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
1175         const struct mlxsw_sp_port_type_speed_ops *ops;
1176         char ptys_pl[MLXSW_REG_PTYS_LEN];
1177         int err;
1178
1179         ops = mlxsw_sp->port_type_speed_ops;
1180
1181         /* Set advertised speeds to supported speeds. */
1182         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1183                                0, false);
1184         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1185         if (err)
1186                 return err;
1187
1188         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap,
1189                                  &eth_proto_admin, &eth_proto_oper);
1190         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1191                                eth_proto_cap, mlxsw_sp_port->link.autoneg);
1192         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1193 }
1194
1195 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
1196 {
1197         const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
1198         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1199         char ptys_pl[MLXSW_REG_PTYS_LEN];
1200         u32 eth_proto_oper;
1201         int err;
1202
1203         port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
1204         port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
1205                                                mlxsw_sp_port->local_port, 0,
1206                                                false);
1207         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1208         if (err)
1209                 return err;
1210         port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
1211                                                  &eth_proto_oper);
1212         *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
1213         return 0;
1214 }
1215
1216 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1217                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1218                           bool dwrr, u8 dwrr_weight)
1219 {
1220         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1221         char qeec_pl[MLXSW_REG_QEEC_LEN];
1222
1223         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1224                             next_index);
1225         mlxsw_reg_qeec_de_set(qeec_pl, true);
1226         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1227         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1228         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1229 }
1230
1231 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1232                                   enum mlxsw_reg_qeec_hr hr, u8 index,
1233                                   u8 next_index, u32 maxrate, u8 burst_size)
1234 {
1235         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1236         char qeec_pl[MLXSW_REG_QEEC_LEN];
1237
1238         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1239                             next_index);
1240         mlxsw_reg_qeec_mase_set(qeec_pl, true);
1241         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1242         mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
1243         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1244 }
1245
1246 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
1247                                     enum mlxsw_reg_qeec_hr hr, u8 index,
1248                                     u8 next_index, u32 minrate)
1249 {
1250         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1251         char qeec_pl[MLXSW_REG_QEEC_LEN];
1252
1253         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1254                             next_index);
1255         mlxsw_reg_qeec_mise_set(qeec_pl, true);
1256         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
1257
1258         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1259 }
1260
1261 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1262                               u8 switch_prio, u8 tclass)
1263 {
1264         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1265         char qtct_pl[MLXSW_REG_QTCT_LEN];
1266
1267         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1268                             tclass);
1269         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1270 }
1271
1272 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1273 {
1274         int err, i;
1275
1276         /* Setup the elements hierarcy, so that each TC is linked to
1277          * one subgroup, which are all member in the same group.
1278          */
1279         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1280                                     MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
1281         if (err)
1282                 return err;
1283         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1284                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1285                                             MLXSW_REG_QEEC_HR_SUBGROUP, i,
1286                                             0, false, 0);
1287                 if (err)
1288                         return err;
1289         }
1290         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1291                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1292                                             MLXSW_REG_QEEC_HR_TC, i, i,
1293                                             false, 0);
1294                 if (err)
1295                         return err;
1296
1297                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1298                                             MLXSW_REG_QEEC_HR_TC,
1299                                             i + 8, i,
1300                                             true, 100);
1301                 if (err)
1302                         return err;
1303         }
1304
1305         /* Make sure the max shaper is disabled in all hierarchies that support
1306          * it. Note that this disables ptps (PTP shaper), but that is intended
1307          * for the initial configuration.
1308          */
1309         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1310                                             MLXSW_REG_QEEC_HR_PORT, 0, 0,
1311                                             MLXSW_REG_QEEC_MAS_DIS, 0);
1312         if (err)
1313                 return err;
1314         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1315                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1316                                                     MLXSW_REG_QEEC_HR_SUBGROUP,
1317                                                     i, 0,
1318                                                     MLXSW_REG_QEEC_MAS_DIS, 0);
1319                 if (err)
1320                         return err;
1321         }
1322         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1323                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1324                                                     MLXSW_REG_QEEC_HR_TC,
1325                                                     i, i,
1326                                                     MLXSW_REG_QEEC_MAS_DIS, 0);
1327                 if (err)
1328                         return err;
1329
1330                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1331                                                     MLXSW_REG_QEEC_HR_TC,
1332                                                     i + 8, i,
1333                                                     MLXSW_REG_QEEC_MAS_DIS, 0);
1334                 if (err)
1335                         return err;
1336         }
1337
1338         /* Configure the min shaper for multicast TCs. */
1339         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1340                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
1341                                                MLXSW_REG_QEEC_HR_TC,
1342                                                i + 8, i,
1343                                                MLXSW_REG_QEEC_MIS_MIN);
1344                 if (err)
1345                         return err;
1346         }
1347
1348         /* Map all priorities to traffic class 0. */
1349         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1350                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1351                 if (err)
1352                         return err;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
1359                                         bool enable)
1360 {
1361         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1362         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
1363
1364         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
1365         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
1366 }
1367
1368 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1369                                 u8 split_base_local_port,
1370                                 struct mlxsw_sp_port_mapping *port_mapping)
1371 {
1372         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1373         bool split = !!split_base_local_port;
1374         struct mlxsw_sp_port *mlxsw_sp_port;
1375         u32 lanes = port_mapping->width;
1376         struct net_device *dev;
1377         bool splittable;
1378         int err;
1379
1380         splittable = lanes > 1 && !split;
1381         err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
1382                                    port_mapping->module + 1, split,
1383                                    port_mapping->lane / lanes,
1384                                    splittable, lanes,
1385                                    mlxsw_sp->base_mac,
1386                                    sizeof(mlxsw_sp->base_mac));
1387         if (err) {
1388                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1389                         local_port);
1390                 return err;
1391         }
1392
1393         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1394         if (!dev) {
1395                 err = -ENOMEM;
1396                 goto err_alloc_etherdev;
1397         }
1398         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
1399         dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
1400         mlxsw_sp_port = netdev_priv(dev);
1401         mlxsw_sp_port->dev = dev;
1402         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1403         mlxsw_sp_port->local_port = local_port;
1404         mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
1405         mlxsw_sp_port->split = split;
1406         mlxsw_sp_port->split_base_local_port = split_base_local_port;
1407         mlxsw_sp_port->mapping = *port_mapping;
1408         mlxsw_sp_port->link.autoneg = 1;
1409         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
1410
1411         mlxsw_sp_port->pcpu_stats =
1412                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1413         if (!mlxsw_sp_port->pcpu_stats) {
1414                 err = -ENOMEM;
1415                 goto err_alloc_stats;
1416         }
1417
1418         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1419                           &update_stats_cache);
1420
1421         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1422         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1423
1424         err = mlxsw_sp_port_module_map(mlxsw_sp_port);
1425         if (err) {
1426                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
1427                         mlxsw_sp_port->local_port);
1428                 goto err_port_module_map;
1429         }
1430
1431         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1432         if (err) {
1433                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1434                         mlxsw_sp_port->local_port);
1435                 goto err_port_swid_set;
1436         }
1437
1438         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1439         if (err) {
1440                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1441                         mlxsw_sp_port->local_port);
1442                 goto err_dev_addr_init;
1443         }
1444
1445         netif_carrier_off(dev);
1446
1447         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1448                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
1449         dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
1450
1451         dev->min_mtu = 0;
1452         dev->max_mtu = ETH_MAX_MTU;
1453
1454         /* Each packet needs to have a Tx header (metadata) on top all other
1455          * headers.
1456          */
1457         dev->needed_headroom = MLXSW_TXHDR_LEN;
1458
1459         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1460         if (err) {
1461                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1462                         mlxsw_sp_port->local_port);
1463                 goto err_port_system_port_mapping_set;
1464         }
1465
1466         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
1467         if (err) {
1468                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1469                         mlxsw_sp_port->local_port);
1470                 goto err_port_speed_by_width_set;
1471         }
1472
1473         err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
1474                                                             &mlxsw_sp_port->max_speed);
1475         if (err) {
1476                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
1477                         mlxsw_sp_port->local_port);
1478                 goto err_max_speed_get;
1479         }
1480
1481         err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu);
1482         if (err) {
1483                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n",
1484                         mlxsw_sp_port->local_port);
1485                 goto err_port_max_mtu_get;
1486         }
1487
1488         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1489         if (err) {
1490                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1491                         mlxsw_sp_port->local_port);
1492                 goto err_port_mtu_set;
1493         }
1494
1495         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1496         if (err)
1497                 goto err_port_admin_status_set;
1498
1499         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1500         if (err) {
1501                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1502                         mlxsw_sp_port->local_port);
1503                 goto err_port_buffers_init;
1504         }
1505
1506         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1507         if (err) {
1508                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1509                         mlxsw_sp_port->local_port);
1510                 goto err_port_ets_init;
1511         }
1512
1513         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
1514         if (err) {
1515                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
1516                         mlxsw_sp_port->local_port);
1517                 goto err_port_tc_mc_mode;
1518         }
1519
1520         /* ETS and buffers must be initialized before DCB. */
1521         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1522         if (err) {
1523                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1524                         mlxsw_sp_port->local_port);
1525                 goto err_port_dcb_init;
1526         }
1527
1528         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
1529         if (err) {
1530                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
1531                         mlxsw_sp_port->local_port);
1532                 goto err_port_fids_init;
1533         }
1534
1535         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
1536         if (err) {
1537                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
1538                         mlxsw_sp_port->local_port);
1539                 goto err_port_qdiscs_init;
1540         }
1541
1542         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
1543                                      false);
1544         if (err) {
1545                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
1546                         mlxsw_sp_port->local_port);
1547                 goto err_port_vlan_clear;
1548         }
1549
1550         err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
1551         if (err) {
1552                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
1553                         mlxsw_sp_port->local_port);
1554                 goto err_port_nve_init;
1555         }
1556
1557         err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
1558         if (err) {
1559                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
1560                         mlxsw_sp_port->local_port);
1561                 goto err_port_pvid_set;
1562         }
1563
1564         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
1565                                                        MLXSW_SP_DEFAULT_VID);
1566         if (IS_ERR(mlxsw_sp_port_vlan)) {
1567                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
1568                         mlxsw_sp_port->local_port);
1569                 err = PTR_ERR(mlxsw_sp_port_vlan);
1570                 goto err_port_vlan_create;
1571         }
1572         mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
1573
1574         INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
1575                           mlxsw_sp->ptp_ops->shaper_work);
1576
1577         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1578         err = register_netdev(dev);
1579         if (err) {
1580                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1581                         mlxsw_sp_port->local_port);
1582                 goto err_register_netdev;
1583         }
1584
1585         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
1586                                 mlxsw_sp_port, dev);
1587         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
1588         return 0;
1589
1590 err_register_netdev:
1591         mlxsw_sp->ports[local_port] = NULL;
1592         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1593 err_port_vlan_create:
1594 err_port_pvid_set:
1595         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1596 err_port_nve_init:
1597 err_port_vlan_clear:
1598         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1599 err_port_qdiscs_init:
1600         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1601 err_port_fids_init:
1602         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1603 err_port_dcb_init:
1604         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1605 err_port_tc_mc_mode:
1606 err_port_ets_init:
1607         mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1608 err_port_buffers_init:
1609 err_port_admin_status_set:
1610 err_port_mtu_set:
1611 err_port_max_mtu_get:
1612 err_max_speed_get:
1613 err_port_speed_by_width_set:
1614 err_port_system_port_mapping_set:
1615 err_dev_addr_init:
1616         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1617 err_port_swid_set:
1618         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
1619 err_port_module_map:
1620         free_percpu(mlxsw_sp_port->pcpu_stats);
1621 err_alloc_stats:
1622         free_netdev(dev);
1623 err_alloc_etherdev:
1624         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1625         return err;
1626 }
1627
1628 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1629 {
1630         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1631
1632         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
1633         cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
1634         mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
1635         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
1636         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
1637         mlxsw_sp->ports[local_port] = NULL;
1638         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
1639         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1640         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1641         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1642         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1643         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1644         mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1645         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1646         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
1647         free_percpu(mlxsw_sp_port->pcpu_stats);
1648         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
1649         free_netdev(mlxsw_sp_port->dev);
1650         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1651 }
1652
1653 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
1654 {
1655         struct mlxsw_sp_port *mlxsw_sp_port;
1656         int err;
1657
1658         mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
1659         if (!mlxsw_sp_port)
1660                 return -ENOMEM;
1661
1662         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1663         mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
1664
1665         err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
1666                                        mlxsw_sp_port,
1667                                        mlxsw_sp->base_mac,
1668                                        sizeof(mlxsw_sp->base_mac));
1669         if (err) {
1670                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
1671                 goto err_core_cpu_port_init;
1672         }
1673
1674         mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
1675         return 0;
1676
1677 err_core_cpu_port_init:
1678         kfree(mlxsw_sp_port);
1679         return err;
1680 }
1681
1682 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
1683 {
1684         struct mlxsw_sp_port *mlxsw_sp_port =
1685                                 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
1686
1687         mlxsw_core_cpu_port_fini(mlxsw_sp->core);
1688         mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
1689         kfree(mlxsw_sp_port);
1690 }
1691
1692 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1693 {
1694         return mlxsw_sp->ports[local_port] != NULL;
1695 }
1696
1697 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1698 {
1699         int i;
1700
1701         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
1702                 if (mlxsw_sp_port_created(mlxsw_sp, i))
1703                         mlxsw_sp_port_remove(mlxsw_sp, i);
1704         mlxsw_sp_cpu_port_remove(mlxsw_sp);
1705         kfree(mlxsw_sp->ports);
1706         mlxsw_sp->ports = NULL;
1707 }
1708
1709 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1710 {
1711         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
1712         struct mlxsw_sp_port_mapping *port_mapping;
1713         size_t alloc_size;
1714         int i;
1715         int err;
1716
1717         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
1718         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1719         if (!mlxsw_sp->ports)
1720                 return -ENOMEM;
1721
1722         err = mlxsw_sp_cpu_port_create(mlxsw_sp);
1723         if (err)
1724                 goto err_cpu_port_create;
1725
1726         for (i = 1; i < max_ports; i++) {
1727                 port_mapping = mlxsw_sp->port_mapping[i];
1728                 if (!port_mapping)
1729                         continue;
1730                 err = mlxsw_sp_port_create(mlxsw_sp, i, 0, port_mapping);
1731                 if (err)
1732                         goto err_port_create;
1733         }
1734         return 0;
1735
1736 err_port_create:
1737         for (i--; i >= 1; i--)
1738                 if (mlxsw_sp_port_created(mlxsw_sp, i))
1739                         mlxsw_sp_port_remove(mlxsw_sp, i);
1740         mlxsw_sp_cpu_port_remove(mlxsw_sp);
1741 err_cpu_port_create:
1742         kfree(mlxsw_sp->ports);
1743         mlxsw_sp->ports = NULL;
1744         return err;
1745 }
1746
1747 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
1748 {
1749         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
1750         struct mlxsw_sp_port_mapping port_mapping;
1751         int i;
1752         int err;
1753
1754         mlxsw_sp->port_mapping = kcalloc(max_ports,
1755                                          sizeof(struct mlxsw_sp_port_mapping *),
1756                                          GFP_KERNEL);
1757         if (!mlxsw_sp->port_mapping)
1758                 return -ENOMEM;
1759
1760         for (i = 1; i < max_ports; i++) {
1761                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &port_mapping);
1762                 if (err)
1763                         goto err_port_module_info_get;
1764                 if (!port_mapping.width)
1765                         continue;
1766
1767                 mlxsw_sp->port_mapping[i] = kmemdup(&port_mapping,
1768                                                     sizeof(port_mapping),
1769                                                     GFP_KERNEL);
1770                 if (!mlxsw_sp->port_mapping[i]) {
1771                         err = -ENOMEM;
1772                         goto err_port_module_info_dup;
1773                 }
1774         }
1775         return 0;
1776
1777 err_port_module_info_get:
1778 err_port_module_info_dup:
1779         for (i--; i >= 1; i--)
1780                 kfree(mlxsw_sp->port_mapping[i]);
1781         kfree(mlxsw_sp->port_mapping);
1782         return err;
1783 }
1784
1785 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
1786 {
1787         int i;
1788
1789         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
1790                 kfree(mlxsw_sp->port_mapping[i]);
1791         kfree(mlxsw_sp->port_mapping);
1792 }
1793
1794 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port, unsigned int max_width)
1795 {
1796         u8 offset = (local_port - 1) % max_width;
1797
1798         return local_port - offset;
1799 }
1800
1801 static int
1802 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1803                            struct mlxsw_sp_port_mapping *port_mapping,
1804                            unsigned int count, u8 offset)
1805 {
1806         struct mlxsw_sp_port_mapping split_port_mapping;
1807         int err, i;
1808
1809         split_port_mapping = *port_mapping;
1810         split_port_mapping.width /= count;
1811         for (i = 0; i < count; i++) {
1812                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
1813                                            base_port, &split_port_mapping);
1814                 if (err)
1815                         goto err_port_create;
1816                 split_port_mapping.lane += split_port_mapping.width;
1817         }
1818
1819         return 0;
1820
1821 err_port_create:
1822         for (i--; i >= 0; i--)
1823                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
1824                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
1825         return err;
1826 }
1827
1828 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1829                                          u8 base_port,
1830                                          unsigned int count, u8 offset)
1831 {
1832         struct mlxsw_sp_port_mapping *port_mapping;
1833         int i;
1834
1835         /* Go over original unsplit ports in the gap and recreate them. */
1836         for (i = 0; i < count * offset; i++) {
1837                 port_mapping = mlxsw_sp->port_mapping[base_port + i];
1838                 if (!port_mapping)
1839                         continue;
1840                 mlxsw_sp_port_create(mlxsw_sp, base_port + i, 0, port_mapping);
1841         }
1842 }
1843
1844 static int mlxsw_sp_local_ports_offset(struct mlxsw_core *mlxsw_core,
1845                                        unsigned int count,
1846                                        unsigned int max_width)
1847 {
1848         enum mlxsw_res_id local_ports_in_x_res_id;
1849         int split_width = max_width / count;
1850
1851         if (split_width == 1)
1852                 local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_1X;
1853         else if (split_width == 2)
1854                 local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_2X;
1855         else if (split_width == 4)
1856                 local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_4X;
1857         else
1858                 return -EINVAL;
1859
1860         if (!mlxsw_core_res_valid(mlxsw_core, local_ports_in_x_res_id))
1861                 return -EINVAL;
1862         return mlxsw_core_res_get(mlxsw_core, local_ports_in_x_res_id);
1863 }
1864
1865 static struct mlxsw_sp_port *
1866 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1867 {
1868         if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
1869                 return mlxsw_sp->ports[local_port];
1870         return NULL;
1871 }
1872
1873 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1874                                unsigned int count,
1875                                struct netlink_ext_ack *extack)
1876 {
1877         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
1878         struct mlxsw_sp_port_mapping port_mapping;
1879         struct mlxsw_sp_port *mlxsw_sp_port;
1880         int max_width;
1881         u8 base_port;
1882         int offset;
1883         int i;
1884         int err;
1885
1886         mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
1887         if (!mlxsw_sp_port) {
1888                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1889                         local_port);
1890                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
1891                 return -EINVAL;
1892         }
1893
1894         max_width = mlxsw_core_module_max_width(mlxsw_core,
1895                                                 mlxsw_sp_port->mapping.module);
1896         if (max_width < 0) {
1897                 netdev_err(mlxsw_sp_port->dev, "Cannot get max width of port module\n");
1898                 NL_SET_ERR_MSG_MOD(extack, "Cannot get max width of port module");
1899                 return max_width;
1900         }
1901
1902         /* Split port with non-max cannot be split. */
1903         if (mlxsw_sp_port->mapping.width != max_width) {
1904                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split\n");
1905                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split");
1906                 return -EINVAL;
1907         }
1908
1909         offset = mlxsw_sp_local_ports_offset(mlxsw_core, count, max_width);
1910         if (offset < 0) {
1911                 netdev_err(mlxsw_sp_port->dev, "Cannot obtain local port offset\n");
1912                 NL_SET_ERR_MSG_MOD(extack, "Cannot obtain local port offset");
1913                 return -EINVAL;
1914         }
1915
1916         /* Only in case max split is being done, the local port and
1917          * base port may differ.
1918          */
1919         base_port = count == max_width ?
1920                     mlxsw_sp_cluster_base_port_get(local_port, max_width) :
1921                     local_port;
1922
1923         for (i = 0; i < count * offset; i++) {
1924                 /* Expect base port to exist and also the one in the middle in
1925                  * case of maximal split count.
1926                  */
1927                 if (i == 0 || (count == max_width && i == count / 2))
1928                         continue;
1929
1930                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) {
1931                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1932                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
1933                         return -EINVAL;
1934                 }
1935         }
1936
1937         port_mapping = mlxsw_sp_port->mapping;
1938
1939         for (i = 0; i < count; i++)
1940                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
1941                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
1942
1943         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, &port_mapping,
1944                                          count, offset);
1945         if (err) {
1946                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
1947                 goto err_port_split_create;
1948         }
1949
1950         return 0;
1951
1952 err_port_split_create:
1953         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count, offset);
1954         return err;
1955 }
1956
1957 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
1958                                  struct netlink_ext_ack *extack)
1959 {
1960         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
1961         struct mlxsw_sp_port *mlxsw_sp_port;
1962         unsigned int count;
1963         int max_width;
1964         u8 base_port;
1965         int offset;
1966         int i;
1967
1968         mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
1969         if (!mlxsw_sp_port) {
1970                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1971                         local_port);
1972                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
1973                 return -EINVAL;
1974         }
1975
1976         if (!mlxsw_sp_port->split) {
1977                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
1978                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
1979                 return -EINVAL;
1980         }
1981
1982         max_width = mlxsw_core_module_max_width(mlxsw_core,
1983                                                 mlxsw_sp_port->mapping.module);
1984         if (max_width < 0) {
1985                 netdev_err(mlxsw_sp_port->dev, "Cannot get max width of port module\n");
1986                 NL_SET_ERR_MSG_MOD(extack, "Cannot get max width of port module");
1987                 return max_width;
1988         }
1989
1990         count = max_width / mlxsw_sp_port->mapping.width;
1991
1992         offset = mlxsw_sp_local_ports_offset(mlxsw_core, count, max_width);
1993         if (WARN_ON(offset < 0)) {
1994                 netdev_err(mlxsw_sp_port->dev, "Cannot obtain local port offset\n");
1995                 NL_SET_ERR_MSG_MOD(extack, "Cannot obtain local port offset");
1996                 return -EINVAL;
1997         }
1998
1999         base_port = mlxsw_sp_port->split_base_local_port;
2000
2001         for (i = 0; i < count; i++)
2002                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
2003                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
2004
2005         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count, offset);
2006
2007         return 0;
2008 }
2009
2010 static void
2011 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
2012 {
2013         int i;
2014
2015         for (i = 0; i < TC_MAX_QUEUE; i++)
2016                 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
2017 }
2018
2019 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2020                                      char *pude_pl, void *priv)
2021 {
2022         struct mlxsw_sp *mlxsw_sp = priv;
2023         struct mlxsw_sp_port *mlxsw_sp_port;
2024         enum mlxsw_reg_pude_oper_status status;
2025         u8 local_port;
2026
2027         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2028         mlxsw_sp_port = mlxsw_sp->ports[local_port];
2029         if (!mlxsw_sp_port)
2030                 return;
2031
2032         status = mlxsw_reg_pude_oper_status_get(pude_pl);
2033         if (status == MLXSW_PORT_OPER_STATUS_UP) {
2034                 netdev_info(mlxsw_sp_port->dev, "link up\n");
2035                 netif_carrier_on(mlxsw_sp_port->dev);
2036                 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
2037         } else {
2038                 netdev_info(mlxsw_sp_port->dev, "link down\n");
2039                 netif_carrier_off(mlxsw_sp_port->dev);
2040                 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
2041         }
2042 }
2043
2044 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
2045                                           char *mtpptr_pl, bool ingress)
2046 {
2047         u8 local_port;
2048         u8 num_rec;
2049         int i;
2050
2051         local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
2052         num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
2053         for (i = 0; i < num_rec; i++) {
2054                 u8 domain_number;
2055                 u8 message_type;
2056                 u16 sequence_id;
2057                 u64 timestamp;
2058
2059                 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
2060                                         &domain_number, &sequence_id,
2061                                         &timestamp);
2062                 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
2063                                             message_type, domain_number,
2064                                             sequence_id, timestamp);
2065         }
2066 }
2067
2068 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
2069                                               char *mtpptr_pl, void *priv)
2070 {
2071         struct mlxsw_sp *mlxsw_sp = priv;
2072
2073         mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
2074 }
2075
2076 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
2077                                               char *mtpptr_pl, void *priv)
2078 {
2079         struct mlxsw_sp *mlxsw_sp = priv;
2080
2081         mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
2082 }
2083
2084 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2085                                        u8 local_port, void *priv)
2086 {
2087         struct mlxsw_sp *mlxsw_sp = priv;
2088         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2089         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2090
2091         if (unlikely(!mlxsw_sp_port)) {
2092                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2093                                      local_port);
2094                 return;
2095         }
2096
2097         skb->dev = mlxsw_sp_port->dev;
2098
2099         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2100         u64_stats_update_begin(&pcpu_stats->syncp);
2101         pcpu_stats->rx_packets++;
2102         pcpu_stats->rx_bytes += skb->len;
2103         u64_stats_update_end(&pcpu_stats->syncp);
2104
2105         skb->protocol = eth_type_trans(skb, skb->dev);
2106         netif_receive_skb(skb);
2107 }
2108
2109 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2110                                            void *priv)
2111 {
2112         skb->offload_fwd_mark = 1;
2113         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2114 }
2115
2116 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
2117                                               u8 local_port, void *priv)
2118 {
2119         skb->offload_l3_fwd_mark = 1;
2120         skb->offload_fwd_mark = 1;
2121         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2122 }
2123
2124 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
2125                           u8 local_port)
2126 {
2127         mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
2128 }
2129
2130 void mlxsw_sp_sample_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
2131                              u8 local_port)
2132 {
2133         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2134         struct mlxsw_sp_port_sample *sample;
2135         u32 size;
2136
2137         if (unlikely(!mlxsw_sp_port)) {
2138                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
2139                                      local_port);
2140                 goto out;
2141         }
2142
2143         rcu_read_lock();
2144         sample = rcu_dereference(mlxsw_sp_port->sample);
2145         if (!sample)
2146                 goto out_unlock;
2147         size = sample->truncate ? sample->trunc_size : skb->len;
2148         psample_sample_packet(sample->psample_group, skb, size,
2149                               mlxsw_sp_port->dev->ifindex, 0, sample->rate);
2150 out_unlock:
2151         rcu_read_unlock();
2152 out:
2153         consume_skb(skb);
2154 }
2155
2156 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
2157         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2158                   _is_ctrl, SP_##_trap_group, DISCARD)
2159
2160 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
2161         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
2162                 _is_ctrl, SP_##_trap_group, DISCARD)
2163
2164 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
2165         MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
2166                 _is_ctrl, SP_##_trap_group, DISCARD)
2167
2168 #define MLXSW_SP_EVENTL(_func, _trap_id)                \
2169         MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
2170
2171 static const struct mlxsw_listener mlxsw_sp_listener[] = {
2172         /* Events */
2173         MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
2174         /* L2 traps */
2175         MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),
2176         /* L3 traps */
2177         MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
2178                           false),
2179         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
2180         MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
2181                           false),
2182         MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
2183                              ROUTER_EXP, false),
2184         MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
2185                              ROUTER_EXP, false),
2186         MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
2187                              ROUTER_EXP, false),
2188         MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
2189                              ROUTER_EXP, false),
2190         /* Multicast Router Traps */
2191         MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
2192         MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
2193         /* NVE traps */
2194         MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false),
2195 };
2196
2197 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
2198         /* Events */
2199         MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
2200         MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
2201 };
2202
2203 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2204 {
2205         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2206         char qpcr_pl[MLXSW_REG_QPCR_LEN];
2207         enum mlxsw_reg_qpcr_ir_units ir_units;
2208         int max_cpu_policers;
2209         bool is_bytes;
2210         u8 burst_size;
2211         u32 rate;
2212         int i, err;
2213
2214         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2215                 return -EIO;
2216
2217         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2218
2219         ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2220         for (i = 0; i < max_cpu_policers; i++) {
2221                 is_bytes = false;
2222                 switch (i) {
2223                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2224                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2225                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2226                         rate = 1024;
2227                         burst_size = 7;
2228                         break;
2229                 default:
2230                         continue;
2231                 }
2232
2233                 __set_bit(i, mlxsw_sp->trap->policers_usage);
2234                 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2235                                     burst_size);
2236                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2237                 if (err)
2238                         return err;
2239         }
2240
2241         return 0;
2242 }
2243
2244 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
2245 {
2246         char htgt_pl[MLXSW_REG_HTGT_LEN];
2247         enum mlxsw_reg_htgt_trap_group i;
2248         int max_cpu_policers;
2249         int max_trap_groups;
2250         u8 priority, tc;
2251         u16 policer_id;
2252         int err;
2253
2254         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2255                 return -EIO;
2256
2257         max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2258         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2259
2260         for (i = 0; i < max_trap_groups; i++) {
2261                 policer_id = i;
2262                 switch (i) {
2263                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2264                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2265                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2266                         priority = 1;
2267                         tc = 1;
2268                         break;
2269                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
2270                         priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2271                         tc = MLXSW_REG_HTGT_DEFAULT_TC;
2272                         policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
2273                         break;
2274                 default:
2275                         continue;
2276                 }
2277
2278                 if (max_cpu_policers <= policer_id &&
2279                     policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
2280                         return -EIO;
2281
2282                 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
2283                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2284                 if (err)
2285                         return err;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
2292                                    const struct mlxsw_listener listeners[],
2293                                    size_t listeners_count)
2294 {
2295         int i;
2296         int err;
2297
2298         for (i = 0; i < listeners_count; i++) {
2299                 err = mlxsw_core_trap_register(mlxsw_sp->core,
2300                                                &listeners[i],
2301                                                mlxsw_sp);
2302                 if (err)
2303                         goto err_listener_register;
2304
2305         }
2306         return 0;
2307
2308 err_listener_register:
2309         for (i--; i >= 0; i--) {
2310                 mlxsw_core_trap_unregister(mlxsw_sp->core,
2311                                            &listeners[i],
2312                                            mlxsw_sp);
2313         }
2314         return err;
2315 }
2316
2317 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
2318                                       const struct mlxsw_listener listeners[],
2319                                       size_t listeners_count)
2320 {
2321         int i;
2322
2323         for (i = 0; i < listeners_count; i++) {
2324                 mlxsw_core_trap_unregister(mlxsw_sp->core,
2325                                            &listeners[i],
2326                                            mlxsw_sp);
2327         }
2328 }
2329
2330 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2331 {
2332         struct mlxsw_sp_trap *trap;
2333         u64 max_policers;
2334         int err;
2335
2336         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
2337                 return -EIO;
2338         max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
2339         trap = kzalloc(struct_size(trap, policers_usage,
2340                                    BITS_TO_LONGS(max_policers)), GFP_KERNEL);
2341         if (!trap)
2342                 return -ENOMEM;
2343         trap->max_policers = max_policers;
2344         mlxsw_sp->trap = trap;
2345
2346         err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2347         if (err)
2348                 goto err_cpu_policers_set;
2349
2350         err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2351         if (err)
2352                 goto err_trap_groups_set;
2353
2354         err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
2355                                       ARRAY_SIZE(mlxsw_sp_listener));
2356         if (err)
2357                 goto err_traps_register;
2358
2359         err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
2360                                       mlxsw_sp->listeners_count);
2361         if (err)
2362                 goto err_extra_traps_init;
2363
2364         return 0;
2365
2366 err_extra_traps_init:
2367         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
2368                                   ARRAY_SIZE(mlxsw_sp_listener));
2369 err_traps_register:
2370 err_trap_groups_set:
2371 err_cpu_policers_set:
2372         kfree(trap);
2373         return err;
2374 }
2375
2376 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2377 {
2378         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
2379                                   mlxsw_sp->listeners_count);
2380         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
2381                                   ARRAY_SIZE(mlxsw_sp_listener));
2382         kfree(mlxsw_sp->trap);
2383 }
2384
2385 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
2386
2387 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2388 {
2389         char slcr_pl[MLXSW_REG_SLCR_LEN];
2390         u32 seed;
2391         int err;
2392
2393         seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
2394                      MLXSW_SP_LAG_SEED_INIT);
2395         mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2396                                      MLXSW_REG_SLCR_LAG_HASH_DMAC |
2397                                      MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2398                                      MLXSW_REG_SLCR_LAG_HASH_VLANID |
2399                                      MLXSW_REG_SLCR_LAG_HASH_SIP |
2400                                      MLXSW_REG_SLCR_LAG_HASH_DIP |
2401                                      MLXSW_REG_SLCR_LAG_HASH_SPORT |
2402                                      MLXSW_REG_SLCR_LAG_HASH_DPORT |
2403                                      MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
2404         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2405         if (err)
2406                 return err;
2407
2408         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
2409             !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
2410                 return -EIO;
2411
2412         mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
2413                                  sizeof(struct mlxsw_sp_upper),
2414                                  GFP_KERNEL);
2415         if (!mlxsw_sp->lags)
2416                 return -ENOMEM;
2417
2418         return 0;
2419 }
2420
2421 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2422 {
2423         kfree(mlxsw_sp->lags);
2424 }
2425
2426 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
2427 {
2428         char htgt_pl[MLXSW_REG_HTGT_LEN];
2429         int err;
2430
2431         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
2432                             MLXSW_REG_HTGT_INVALID_POLICER,
2433                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
2434                             MLXSW_REG_HTGT_DEFAULT_TC);
2435         err =  mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2436         if (err)
2437                 return err;
2438
2439         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MFDE,
2440                             MLXSW_REG_HTGT_INVALID_POLICER,
2441                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
2442                             MLXSW_REG_HTGT_DEFAULT_TC);
2443         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2444 }
2445
2446 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
2447         .clock_init     = mlxsw_sp1_ptp_clock_init,
2448         .clock_fini     = mlxsw_sp1_ptp_clock_fini,
2449         .init           = mlxsw_sp1_ptp_init,
2450         .fini           = mlxsw_sp1_ptp_fini,
2451         .receive        = mlxsw_sp1_ptp_receive,
2452         .transmitted    = mlxsw_sp1_ptp_transmitted,
2453         .hwtstamp_get   = mlxsw_sp1_ptp_hwtstamp_get,
2454         .hwtstamp_set   = mlxsw_sp1_ptp_hwtstamp_set,
2455         .shaper_work    = mlxsw_sp1_ptp_shaper_work,
2456         .get_ts_info    = mlxsw_sp1_ptp_get_ts_info,
2457         .get_stats_count = mlxsw_sp1_get_stats_count,
2458         .get_stats_strings = mlxsw_sp1_get_stats_strings,
2459         .get_stats      = mlxsw_sp1_get_stats,
2460 };
2461
2462 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
2463         .clock_init     = mlxsw_sp2_ptp_clock_init,
2464         .clock_fini     = mlxsw_sp2_ptp_clock_fini,
2465         .init           = mlxsw_sp2_ptp_init,
2466         .fini           = mlxsw_sp2_ptp_fini,
2467         .receive        = mlxsw_sp2_ptp_receive,
2468         .transmitted    = mlxsw_sp2_ptp_transmitted,
2469         .hwtstamp_get   = mlxsw_sp2_ptp_hwtstamp_get,
2470         .hwtstamp_set   = mlxsw_sp2_ptp_hwtstamp_set,
2471         .shaper_work    = mlxsw_sp2_ptp_shaper_work,
2472         .get_ts_info    = mlxsw_sp2_ptp_get_ts_info,
2473         .get_stats_count = mlxsw_sp2_get_stats_count,
2474         .get_stats_strings = mlxsw_sp2_get_stats_strings,
2475         .get_stats      = mlxsw_sp2_get_stats,
2476 };
2477
2478 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
2479                                     unsigned long event, void *ptr);
2480
2481 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
2482                          const struct mlxsw_bus_info *mlxsw_bus_info,
2483                          struct netlink_ext_ack *extack)
2484 {
2485         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2486         int err;
2487
2488         mlxsw_sp->core = mlxsw_core;
2489         mlxsw_sp->bus_info = mlxsw_bus_info;
2490
2491         mlxsw_core_emad_string_tlv_enable(mlxsw_core);
2492
2493         err = mlxsw_sp_base_mac_get(mlxsw_sp);
2494         if (err) {
2495                 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2496                 return err;
2497         }
2498
2499         err = mlxsw_sp_kvdl_init(mlxsw_sp);
2500         if (err) {
2501                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
2502                 return err;
2503         }
2504
2505         err = mlxsw_sp_fids_init(mlxsw_sp);
2506         if (err) {
2507                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
2508                 goto err_fids_init;
2509         }
2510
2511         err = mlxsw_sp_policers_init(mlxsw_sp);
2512         if (err) {
2513                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
2514                 goto err_policers_init;
2515         }
2516
2517         err = mlxsw_sp_traps_init(mlxsw_sp);
2518         if (err) {
2519                 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
2520                 goto err_traps_init;
2521         }
2522
2523         err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
2524         if (err) {
2525                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
2526                 goto err_devlink_traps_init;
2527         }
2528
2529         err = mlxsw_sp_buffers_init(mlxsw_sp);
2530         if (err) {
2531                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2532                 goto err_buffers_init;
2533         }
2534
2535         err = mlxsw_sp_lag_init(mlxsw_sp);
2536         if (err) {
2537                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2538                 goto err_lag_init;
2539         }
2540
2541         /* Initialize SPAN before router and switchdev, so that those components
2542          * can call mlxsw_sp_span_respin().
2543          */
2544         err = mlxsw_sp_span_init(mlxsw_sp);
2545         if (err) {
2546                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
2547                 goto err_span_init;
2548         }
2549
2550         err = mlxsw_sp_switchdev_init(mlxsw_sp);
2551         if (err) {
2552                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2553                 goto err_switchdev_init;
2554         }
2555
2556         err = mlxsw_sp_counter_pool_init(mlxsw_sp);
2557         if (err) {
2558                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
2559                 goto err_counter_pool_init;
2560         }
2561
2562         err = mlxsw_sp_afa_init(mlxsw_sp);
2563         if (err) {
2564                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
2565                 goto err_afa_init;
2566         }
2567
2568         err = mlxsw_sp_nve_init(mlxsw_sp);
2569         if (err) {
2570                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
2571                 goto err_nve_init;
2572         }
2573
2574         err = mlxsw_sp_acl_init(mlxsw_sp);
2575         if (err) {
2576                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
2577                 goto err_acl_init;
2578         }
2579
2580         err = mlxsw_sp_router_init(mlxsw_sp, extack);
2581         if (err) {
2582                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
2583                 goto err_router_init;
2584         }
2585
2586         if (mlxsw_sp->bus_info->read_frc_capable) {
2587                 /* NULL is a valid return value from clock_init */
2588                 mlxsw_sp->clock =
2589                         mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
2590                                                       mlxsw_sp->bus_info->dev);
2591                 if (IS_ERR(mlxsw_sp->clock)) {
2592                         err = PTR_ERR(mlxsw_sp->clock);
2593                         dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
2594                         goto err_ptp_clock_init;
2595                 }
2596         }
2597
2598         if (mlxsw_sp->clock) {
2599                 /* NULL is a valid return value from ptp_ops->init */
2600                 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
2601                 if (IS_ERR(mlxsw_sp->ptp_state)) {
2602                         err = PTR_ERR(mlxsw_sp->ptp_state);
2603                         dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
2604                         goto err_ptp_init;
2605                 }
2606         }
2607
2608         /* Initialize netdevice notifier after router and SPAN is initialized,
2609          * so that the event handler can use router structures and call SPAN
2610          * respin.
2611          */
2612         mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
2613         err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
2614                                               &mlxsw_sp->netdevice_nb);
2615         if (err) {
2616                 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
2617                 goto err_netdev_notifier;
2618         }
2619
2620         err = mlxsw_sp_dpipe_init(mlxsw_sp);
2621         if (err) {
2622                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
2623                 goto err_dpipe_init;
2624         }
2625
2626         err = mlxsw_sp_port_module_info_init(mlxsw_sp);
2627         if (err) {
2628                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
2629                 goto err_port_module_info_init;
2630         }
2631
2632         err = mlxsw_sp_ports_create(mlxsw_sp);
2633         if (err) {
2634                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2635                 goto err_ports_create;
2636         }
2637
2638         return 0;
2639
2640 err_ports_create:
2641         mlxsw_sp_port_module_info_fini(mlxsw_sp);
2642 err_port_module_info_init:
2643         mlxsw_sp_dpipe_fini(mlxsw_sp);
2644 err_dpipe_init:
2645         unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
2646                                           &mlxsw_sp->netdevice_nb);
2647 err_netdev_notifier:
2648         if (mlxsw_sp->clock)
2649                 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
2650 err_ptp_init:
2651         if (mlxsw_sp->clock)
2652                 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
2653 err_ptp_clock_init:
2654         mlxsw_sp_router_fini(mlxsw_sp);
2655 err_router_init:
2656         mlxsw_sp_acl_fini(mlxsw_sp);
2657 err_acl_init:
2658         mlxsw_sp_nve_fini(mlxsw_sp);
2659 err_nve_init:
2660         mlxsw_sp_afa_fini(mlxsw_sp);
2661 err_afa_init:
2662         mlxsw_sp_counter_pool_fini(mlxsw_sp);
2663 err_counter_pool_init:
2664         mlxsw_sp_switchdev_fini(mlxsw_sp);
2665 err_switchdev_init:
2666         mlxsw_sp_span_fini(mlxsw_sp);
2667 err_span_init:
2668         mlxsw_sp_lag_fini(mlxsw_sp);
2669 err_lag_init:
2670         mlxsw_sp_buffers_fini(mlxsw_sp);
2671 err_buffers_init:
2672         mlxsw_sp_devlink_traps_fini(mlxsw_sp);
2673 err_devlink_traps_init:
2674         mlxsw_sp_traps_fini(mlxsw_sp);
2675 err_traps_init:
2676         mlxsw_sp_policers_fini(mlxsw_sp);
2677 err_policers_init:
2678         mlxsw_sp_fids_fini(mlxsw_sp);
2679 err_fids_init:
2680         mlxsw_sp_kvdl_fini(mlxsw_sp);
2681         return err;
2682 }
2683
2684 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
2685                           const struct mlxsw_bus_info *mlxsw_bus_info,
2686                           struct netlink_ext_ack *extack)
2687 {
2688         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2689
2690         mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
2691         mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
2692         mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
2693         mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
2694         mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
2695         mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
2696         mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
2697         mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
2698         mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
2699         mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
2700         mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
2701         mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
2702         mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
2703         mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
2704         mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
2705         mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
2706         mlxsw_sp->listeners = mlxsw_sp1_listener;
2707         mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
2708         mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
2709
2710         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
2711 }
2712
2713 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
2714                           const struct mlxsw_bus_info *mlxsw_bus_info,
2715                           struct netlink_ext_ack *extack)
2716 {
2717         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2718
2719         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
2720         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
2721         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
2722         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
2723         mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
2724         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
2725         mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
2726         mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
2727         mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
2728         mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
2729         mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
2730         mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
2731         mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
2732         mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
2733         mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
2734         mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
2735         mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
2736
2737         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
2738 }
2739
2740 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
2741                           const struct mlxsw_bus_info *mlxsw_bus_info,
2742                           struct netlink_ext_ack *extack)
2743 {
2744         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2745
2746         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
2747         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
2748         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
2749         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
2750         mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
2751         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
2752         mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
2753         mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
2754         mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
2755         mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
2756         mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
2757         mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
2758         mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
2759         mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
2760         mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
2761         mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
2762         mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
2763
2764         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
2765 }
2766
2767 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
2768 {
2769         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2770
2771         mlxsw_sp_ports_remove(mlxsw_sp);
2772         mlxsw_sp_port_module_info_fini(mlxsw_sp);
2773         mlxsw_sp_dpipe_fini(mlxsw_sp);
2774         unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
2775                                           &mlxsw_sp->netdevice_nb);
2776         if (mlxsw_sp->clock) {
2777                 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
2778                 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
2779         }
2780         mlxsw_sp_router_fini(mlxsw_sp);
2781         mlxsw_sp_acl_fini(mlxsw_sp);
2782         mlxsw_sp_nve_fini(mlxsw_sp);
2783         mlxsw_sp_afa_fini(mlxsw_sp);
2784         mlxsw_sp_counter_pool_fini(mlxsw_sp);
2785         mlxsw_sp_switchdev_fini(mlxsw_sp);
2786         mlxsw_sp_span_fini(mlxsw_sp);
2787         mlxsw_sp_lag_fini(mlxsw_sp);
2788         mlxsw_sp_buffers_fini(mlxsw_sp);
2789         mlxsw_sp_devlink_traps_fini(mlxsw_sp);
2790         mlxsw_sp_traps_fini(mlxsw_sp);
2791         mlxsw_sp_policers_fini(mlxsw_sp);
2792         mlxsw_sp_fids_fini(mlxsw_sp);
2793         mlxsw_sp_kvdl_fini(mlxsw_sp);
2794 }
2795
2796 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
2797  * 802.1Q FIDs
2798  */
2799 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE   (MLXSW_SP_FID_8021D_MAX + \
2800                                          VLAN_VID_MASK - 1)
2801
2802 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
2803         .used_max_mid                   = 1,
2804         .max_mid                        = MLXSW_SP_MID_MAX,
2805         .used_flood_tables              = 1,
2806         .used_flood_mode                = 1,
2807         .flood_mode                     = 3,
2808         .max_fid_flood_tables           = 3,
2809         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
2810         .used_max_ib_mc                 = 1,
2811         .max_ib_mc                      = 0,
2812         .used_max_pkey                  = 1,
2813         .max_pkey                       = 0,
2814         .used_kvd_sizes                 = 1,
2815         .kvd_hash_single_parts          = 59,
2816         .kvd_hash_double_parts          = 41,
2817         .kvd_linear_size                = MLXSW_SP_KVD_LINEAR_SIZE,
2818         .swid_config                    = {
2819                 {
2820                         .used_type      = 1,
2821                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
2822                 }
2823         },
2824 };
2825
2826 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
2827         .used_max_mid                   = 1,
2828         .max_mid                        = MLXSW_SP_MID_MAX,
2829         .used_flood_tables              = 1,
2830         .used_flood_mode                = 1,
2831         .flood_mode                     = 3,
2832         .max_fid_flood_tables           = 3,
2833         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
2834         .used_max_ib_mc                 = 1,
2835         .max_ib_mc                      = 0,
2836         .used_max_pkey                  = 1,
2837         .max_pkey                       = 0,
2838         .swid_config                    = {
2839                 {
2840                         .used_type      = 1,
2841                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
2842                 }
2843         },
2844 };
2845
2846 static void
2847 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
2848                                       struct devlink_resource_size_params *kvd_size_params,
2849                                       struct devlink_resource_size_params *linear_size_params,
2850                                       struct devlink_resource_size_params *hash_double_size_params,
2851                                       struct devlink_resource_size_params *hash_single_size_params)
2852 {
2853         u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
2854                                                  KVD_SINGLE_MIN_SIZE);
2855         u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
2856                                                  KVD_DOUBLE_MIN_SIZE);
2857         u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
2858         u32 linear_size_min = 0;
2859
2860         devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
2861                                           MLXSW_SP_KVD_GRANULARITY,
2862                                           DEVLINK_RESOURCE_UNIT_ENTRY);
2863         devlink_resource_size_params_init(linear_size_params, linear_size_min,
2864                                           kvd_size - single_size_min -
2865                                           double_size_min,
2866                                           MLXSW_SP_KVD_GRANULARITY,
2867                                           DEVLINK_RESOURCE_UNIT_ENTRY);
2868         devlink_resource_size_params_init(hash_double_size_params,
2869                                           double_size_min,
2870                                           kvd_size - single_size_min -
2871                                           linear_size_min,
2872                                           MLXSW_SP_KVD_GRANULARITY,
2873                                           DEVLINK_RESOURCE_UNIT_ENTRY);
2874         devlink_resource_size_params_init(hash_single_size_params,
2875                                           single_size_min,
2876                                           kvd_size - double_size_min -
2877                                           linear_size_min,
2878                                           MLXSW_SP_KVD_GRANULARITY,
2879                                           DEVLINK_RESOURCE_UNIT_ENTRY);
2880 }
2881
2882 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
2883 {
2884         struct devlink *devlink = priv_to_devlink(mlxsw_core);
2885         struct devlink_resource_size_params hash_single_size_params;
2886         struct devlink_resource_size_params hash_double_size_params;
2887         struct devlink_resource_size_params linear_size_params;
2888         struct devlink_resource_size_params kvd_size_params;
2889         u32 kvd_size, single_size, double_size, linear_size;
2890         const struct mlxsw_config_profile *profile;
2891         int err;
2892
2893         profile = &mlxsw_sp1_config_profile;
2894         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
2895                 return -EIO;
2896
2897         mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
2898                                               &linear_size_params,
2899                                               &hash_double_size_params,
2900                                               &hash_single_size_params);
2901
2902         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
2903         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
2904                                         kvd_size, MLXSW_SP_RESOURCE_KVD,
2905                                         DEVLINK_RESOURCE_ID_PARENT_TOP,
2906                                         &kvd_size_params);
2907         if (err)
2908                 return err;
2909
2910         linear_size = profile->kvd_linear_size;
2911         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
2912                                         linear_size,
2913                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
2914                                         MLXSW_SP_RESOURCE_KVD,
2915                                         &linear_size_params);
2916         if (err)
2917                 return err;
2918
2919         err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
2920         if  (err)
2921                 return err;
2922
2923         double_size = kvd_size - linear_size;
2924         double_size *= profile->kvd_hash_double_parts;
2925         double_size /= profile->kvd_hash_double_parts +
2926                        profile->kvd_hash_single_parts;
2927         double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
2928         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
2929                                         double_size,
2930                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
2931                                         MLXSW_SP_RESOURCE_KVD,
2932                                         &hash_double_size_params);
2933         if (err)
2934                 return err;
2935
2936         single_size = kvd_size - double_size - linear_size;
2937         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
2938                                         single_size,
2939                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
2940                                         MLXSW_SP_RESOURCE_KVD,
2941                                         &hash_single_size_params);
2942         if (err)
2943                 return err;
2944
2945         return 0;
2946 }
2947
2948 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
2949 {
2950         struct devlink *devlink = priv_to_devlink(mlxsw_core);
2951         struct devlink_resource_size_params kvd_size_params;
2952         u32 kvd_size;
2953
2954         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
2955                 return -EIO;
2956
2957         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
2958         devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
2959                                           MLXSW_SP_KVD_GRANULARITY,
2960                                           DEVLINK_RESOURCE_UNIT_ENTRY);
2961
2962         return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
2963                                          kvd_size, MLXSW_SP_RESOURCE_KVD,
2964                                          DEVLINK_RESOURCE_ID_PARENT_TOP,
2965                                          &kvd_size_params);
2966 }
2967
2968 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
2969 {
2970         struct devlink *devlink = priv_to_devlink(mlxsw_core);
2971         struct devlink_resource_size_params span_size_params;
2972         u32 max_span;
2973
2974         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
2975                 return -EIO;
2976
2977         max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
2978         devlink_resource_size_params_init(&span_size_params, max_span, max_span,
2979                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
2980
2981         return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
2982                                          max_span, MLXSW_SP_RESOURCE_SPAN,
2983                                          DEVLINK_RESOURCE_ID_PARENT_TOP,
2984                                          &span_size_params);
2985 }
2986
2987 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
2988 {
2989         int err;
2990
2991         err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
2992         if (err)
2993                 return err;
2994
2995         err = mlxsw_sp_resources_span_register(mlxsw_core);
2996         if (err)
2997                 goto err_resources_span_register;
2998
2999         err = mlxsw_sp_counter_resources_register(mlxsw_core);
3000         if (err)
3001                 goto err_resources_counter_register;
3002
3003         err = mlxsw_sp_policer_resources_register(mlxsw_core);
3004         if (err)
3005                 goto err_resources_counter_register;
3006
3007         return 0;
3008
3009 err_resources_counter_register:
3010 err_resources_span_register:
3011         devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL);
3012         return err;
3013 }
3014
3015 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
3016 {
3017         int err;
3018
3019         err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
3020         if (err)
3021                 return err;
3022
3023         err = mlxsw_sp_resources_span_register(mlxsw_core);
3024         if (err)
3025                 goto err_resources_span_register;
3026
3027         err = mlxsw_sp_counter_resources_register(mlxsw_core);
3028         if (err)
3029                 goto err_resources_counter_register;
3030
3031         err = mlxsw_sp_policer_resources_register(mlxsw_core);
3032         if (err)
3033                 goto err_resources_counter_register;
3034
3035         return 0;
3036
3037 err_resources_counter_register:
3038 err_resources_span_register:
3039         devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL);
3040         return err;
3041 }
3042
3043 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3044                                   const struct mlxsw_config_profile *profile,
3045                                   u64 *p_single_size, u64 *p_double_size,
3046                                   u64 *p_linear_size)
3047 {
3048         struct devlink *devlink = priv_to_devlink(mlxsw_core);
3049         u32 double_size;
3050         int err;
3051
3052         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3053             !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
3054                 return -EIO;
3055
3056         /* The hash part is what left of the kvd without the
3057          * linear part. It is split to the single size and
3058          * double size by the parts ratio from the profile.
3059          * Both sizes must be a multiplications of the
3060          * granularity from the profile. In case the user
3061          * provided the sizes they are obtained via devlink.
3062          */
3063         err = devlink_resource_size_get(devlink,
3064                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
3065                                         p_linear_size);
3066         if (err)
3067                 *p_linear_size = profile->kvd_linear_size;
3068
3069         err = devlink_resource_size_get(devlink,
3070                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3071                                         p_double_size);
3072         if (err) {
3073                 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3074                               *p_linear_size;
3075                 double_size *= profile->kvd_hash_double_parts;
3076                 double_size /= profile->kvd_hash_double_parts +
3077                                profile->kvd_hash_single_parts;
3078                 *p_double_size = rounddown(double_size,
3079                                            MLXSW_SP_KVD_GRANULARITY);
3080         }
3081
3082         err = devlink_resource_size_get(devlink,
3083                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3084                                         p_single_size);
3085         if (err)
3086                 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3087                                  *p_double_size - *p_linear_size;
3088
3089         /* Check results are legal. */
3090         if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3091             *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3092             MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3093                 return -EIO;
3094
3095         return 0;
3096 }
3097
3098 static int
3099 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
3100                                              struct devlink_param_gset_ctx *ctx)
3101 {
3102         struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3103         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3104
3105         ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
3106         return 0;
3107 }
3108
3109 static int
3110 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
3111                                              struct devlink_param_gset_ctx *ctx)
3112 {
3113         struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3114         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3115
3116         return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
3117 }
3118
3119 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
3120         DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
3121                              "acl_region_rehash_interval",
3122                              DEVLINK_PARAM_TYPE_U32,
3123                              BIT(DEVLINK_PARAM_CMODE_RUNTIME),
3124                              mlxsw_sp_params_acl_region_rehash_intrvl_get,
3125                              mlxsw_sp_params_acl_region_rehash_intrvl_set,
3126                              NULL),
3127 };
3128
3129 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
3130 {
3131         struct devlink *devlink = priv_to_devlink(mlxsw_core);
3132         union devlink_param_value value;
3133         int err;
3134
3135         err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
3136                                       ARRAY_SIZE(mlxsw_sp2_devlink_params));
3137         if (err)
3138                 return err;
3139
3140         value.vu32 = 0;
3141         devlink_param_driverinit_value_set(devlink,
3142                                            MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
3143                                            value);
3144         return 0;
3145 }
3146
3147 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
3148 {
3149         devlink_params_unregister(priv_to_devlink(mlxsw_core),
3150                                   mlxsw_sp2_devlink_params,
3151                                   ARRAY_SIZE(mlxsw_sp2_devlink_params));
3152 }
3153
3154 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
3155                                      struct sk_buff *skb, u8 local_port)
3156 {
3157         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3158
3159         skb_pull(skb, MLXSW_TXHDR_LEN);
3160         mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
3161 }
3162
3163 static struct mlxsw_driver mlxsw_sp1_driver = {
3164         .kind                           = mlxsw_sp1_driver_name,
3165         .priv_size                      = sizeof(struct mlxsw_sp),
3166         .fw_req_rev                     = &mlxsw_sp1_fw_rev,
3167         .fw_filename                    = MLXSW_SP1_FW_FILENAME,
3168         .init                           = mlxsw_sp1_init,
3169         .fini                           = mlxsw_sp_fini,
3170         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
3171         .port_split                     = mlxsw_sp_port_split,
3172         .port_unsplit                   = mlxsw_sp_port_unsplit,
3173         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
3174         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
3175         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
3176         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
3177         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
3178         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
3179         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
3180         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
3181         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
3182         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
3183         .trap_init                      = mlxsw_sp_trap_init,
3184         .trap_fini                      = mlxsw_sp_trap_fini,
3185         .trap_action_set                = mlxsw_sp_trap_action_set,
3186         .trap_group_init                = mlxsw_sp_trap_group_init,
3187         .trap_group_set                 = mlxsw_sp_trap_group_set,
3188         .trap_policer_init              = mlxsw_sp_trap_policer_init,
3189         .trap_policer_fini              = mlxsw_sp_trap_policer_fini,
3190         .trap_policer_set               = mlxsw_sp_trap_policer_set,
3191         .trap_policer_counter_get       = mlxsw_sp_trap_policer_counter_get,
3192         .txhdr_construct                = mlxsw_sp_txhdr_construct,
3193         .resources_register             = mlxsw_sp1_resources_register,
3194         .kvd_sizes_get                  = mlxsw_sp_kvd_sizes_get,
3195         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
3196         .txhdr_len                      = MLXSW_TXHDR_LEN,
3197         .profile                        = &mlxsw_sp1_config_profile,
3198         .res_query_enabled              = true,
3199         .fw_fatal_enabled               = true,
3200 };
3201
3202 static struct mlxsw_driver mlxsw_sp2_driver = {
3203         .kind                           = mlxsw_sp2_driver_name,
3204         .priv_size                      = sizeof(struct mlxsw_sp),
3205         .fw_req_rev                     = &mlxsw_sp2_fw_rev,
3206         .fw_filename                    = MLXSW_SP2_FW_FILENAME,
3207         .init                           = mlxsw_sp2_init,
3208         .fini                           = mlxsw_sp_fini,
3209         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
3210         .port_split                     = mlxsw_sp_port_split,
3211         .port_unsplit                   = mlxsw_sp_port_unsplit,
3212         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
3213         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
3214         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
3215         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
3216         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
3217         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
3218         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
3219         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
3220         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
3221         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
3222         .trap_init                      = mlxsw_sp_trap_init,
3223         .trap_fini                      = mlxsw_sp_trap_fini,
3224         .trap_action_set                = mlxsw_sp_trap_action_set,
3225         .trap_group_init                = mlxsw_sp_trap_group_init,
3226         .trap_group_set                 = mlxsw_sp_trap_group_set,
3227         .trap_policer_init              = mlxsw_sp_trap_policer_init,
3228         .trap_policer_fini              = mlxsw_sp_trap_policer_fini,
3229         .trap_policer_set               = mlxsw_sp_trap_policer_set,
3230         .trap_policer_counter_get       = mlxsw_sp_trap_policer_counter_get,
3231         .txhdr_construct                = mlxsw_sp_txhdr_construct,
3232         .resources_register             = mlxsw_sp2_resources_register,
3233         .params_register                = mlxsw_sp2_params_register,
3234         .params_unregister              = mlxsw_sp2_params_unregister,
3235         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
3236         .txhdr_len                      = MLXSW_TXHDR_LEN,
3237         .profile                        = &mlxsw_sp2_config_profile,
3238         .res_query_enabled              = true,
3239         .fw_fatal_enabled               = true,
3240 };
3241
3242 static struct mlxsw_driver mlxsw_sp3_driver = {
3243         .kind                           = mlxsw_sp3_driver_name,
3244         .priv_size                      = sizeof(struct mlxsw_sp),
3245         .fw_req_rev                     = &mlxsw_sp3_fw_rev,
3246         .fw_filename                    = MLXSW_SP3_FW_FILENAME,
3247         .init                           = mlxsw_sp3_init,
3248         .fini                           = mlxsw_sp_fini,
3249         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
3250         .port_split                     = mlxsw_sp_port_split,
3251         .port_unsplit                   = mlxsw_sp_port_unsplit,
3252         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
3253         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
3254         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
3255         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
3256         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
3257         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
3258         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
3259         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
3260         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
3261         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
3262         .trap_init                      = mlxsw_sp_trap_init,
3263         .trap_fini                      = mlxsw_sp_trap_fini,
3264         .trap_action_set                = mlxsw_sp_trap_action_set,
3265         .trap_group_init                = mlxsw_sp_trap_group_init,
3266         .trap_group_set                 = mlxsw_sp_trap_group_set,
3267         .trap_policer_init              = mlxsw_sp_trap_policer_init,
3268         .trap_policer_fini              = mlxsw_sp_trap_policer_fini,
3269         .trap_policer_set               = mlxsw_sp_trap_policer_set,
3270         .trap_policer_counter_get       = mlxsw_sp_trap_policer_counter_get,
3271         .txhdr_construct                = mlxsw_sp_txhdr_construct,
3272         .resources_register             = mlxsw_sp2_resources_register,
3273         .params_register                = mlxsw_sp2_params_register,
3274         .params_unregister              = mlxsw_sp2_params_unregister,
3275         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
3276         .txhdr_len                      = MLXSW_TXHDR_LEN,
3277         .profile                        = &mlxsw_sp2_config_profile,
3278         .res_query_enabled              = true,
3279         .fw_fatal_enabled               = true,
3280 };
3281
3282 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3283 {
3284         return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3285 }
3286
3287 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
3288 {
3289         struct mlxsw_sp_port **p_mlxsw_sp_port = data;
3290         int ret = 0;
3291
3292         if (mlxsw_sp_port_dev_check(lower_dev)) {
3293                 *p_mlxsw_sp_port = netdev_priv(lower_dev);
3294                 ret = 1;
3295         }
3296
3297         return ret;
3298 }
3299
3300 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3301 {
3302         struct mlxsw_sp_port *mlxsw_sp_port;
3303
3304         if (mlxsw_sp_port_dev_check(dev))
3305                 return netdev_priv(dev);
3306
3307         mlxsw_sp_port = NULL;
3308         netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
3309
3310         return mlxsw_sp_port;
3311 }
3312
3313 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3314 {
3315         struct mlxsw_sp_port *mlxsw_sp_port;
3316
3317         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3318         return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3319 }
3320
3321 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3322 {
3323         struct mlxsw_sp_port *mlxsw_sp_port;
3324
3325         if (mlxsw_sp_port_dev_check(dev))
3326                 return netdev_priv(dev);
3327
3328         mlxsw_sp_port = NULL;
3329         netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3330                                       &mlxsw_sp_port);
3331
3332         return mlxsw_sp_port;
3333 }
3334
3335 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3336 {
3337         struct mlxsw_sp_port *mlxsw_sp_port;
3338
3339         rcu_read_lock();
3340         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3341         if (mlxsw_sp_port)
3342                 dev_hold(mlxsw_sp_port->dev);
3343         rcu_read_unlock();
3344         return mlxsw_sp_port;
3345 }
3346
3347 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3348 {
3349         dev_put(mlxsw_sp_port->dev);
3350 }
3351
3352 static void
3353 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
3354                                  struct net_device *lag_dev)
3355 {
3356         struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
3357         struct net_device *upper_dev;
3358         struct list_head *iter;
3359
3360         if (netif_is_bridge_port(lag_dev))
3361                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
3362
3363         netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
3364                 if (!netif_is_bridge_port(upper_dev))
3365                         continue;
3366                 br_dev = netdev_master_upper_dev_get(upper_dev);
3367                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
3368         }
3369 }
3370
3371 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3372 {
3373         char sldr_pl[MLXSW_REG_SLDR_LEN];
3374
3375         mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3376         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3377 }
3378
3379 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3380 {
3381         char sldr_pl[MLXSW_REG_SLDR_LEN];
3382
3383         mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3384         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3385 }
3386
3387 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3388                                      u16 lag_id, u8 port_index)
3389 {
3390         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3391         char slcor_pl[MLXSW_REG_SLCOR_LEN];
3392
3393         mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3394                                       lag_id, port_index);
3395         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3396 }
3397
3398 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3399                                         u16 lag_id)
3400 {
3401         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3402         char slcor_pl[MLXSW_REG_SLCOR_LEN];
3403
3404         mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3405                                          lag_id);
3406         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3407 }
3408
3409 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3410                                         u16 lag_id)
3411 {
3412         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3413         char slcor_pl[MLXSW_REG_SLCOR_LEN];
3414
3415         mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3416                                         lag_id);
3417         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3418 }
3419
3420 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3421                                          u16 lag_id)
3422 {
3423         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3424         char slcor_pl[MLXSW_REG_SLCOR_LEN];
3425
3426         mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3427                                          lag_id);
3428         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3429 }
3430
3431 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3432                                   struct net_device *lag_dev,
3433                                   u16 *p_lag_id)
3434 {
3435         struct mlxsw_sp_upper *lag;
3436         int free_lag_id = -1;
3437         u64 max_lag;
3438         int i;
3439
3440         max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3441         for (i = 0; i < max_lag; i++) {
3442                 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3443                 if (lag->ref_count) {
3444                         if (lag->dev == lag_dev) {
3445                                 *p_lag_id = i;
3446                                 return 0;
3447                         }
3448                 } else if (free_lag_id < 0) {
3449                         free_lag_id = i;
3450                 }
3451         }
3452         if (free_lag_id < 0)
3453                 return -EBUSY;
3454         *p_lag_id = free_lag_id;
3455         return 0;
3456 }
3457
3458 static bool
3459 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3460                           struct net_device *lag_dev,
3461                           struct netdev_lag_upper_info *lag_upper_info,
3462                           struct netlink_ext_ack *extack)
3463 {
3464         u16 lag_id;
3465
3466         if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
3467                 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
3468                 return false;
3469         }
3470         if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
3471                 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
3472                 return false;
3473         }
3474         return true;
3475 }
3476
3477 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3478                                        u16 lag_id, u8 *p_port_index)
3479 {
3480         u64 max_lag_members;
3481         int i;
3482
3483         max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3484                                              MAX_LAG_MEMBERS);
3485         for (i = 0; i < max_lag_members; i++) {
3486                 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3487                         *p_port_index = i;
3488                         return 0;
3489                 }
3490         }
3491         return -EBUSY;
3492 }
3493
3494 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3495                                   struct net_device *lag_dev)
3496 {
3497         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3498         struct mlxsw_sp_upper *lag;
3499         u16 lag_id;
3500         u8 port_index;
3501         int err;
3502
3503         err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3504         if (err)
3505                 return err;
3506         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3507         if (!lag->ref_count) {
3508                 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3509                 if (err)
3510                         return err;
3511                 lag->dev = lag_dev;
3512         }
3513
3514         err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3515         if (err)
3516                 return err;
3517         err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3518         if (err)
3519                 goto err_col_port_add;
3520
3521         mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3522                                    mlxsw_sp_port->local_port);
3523         mlxsw_sp_port->lag_id = lag_id;
3524         mlxsw_sp_port->lagged = 1;
3525         lag->ref_count++;
3526
3527         /* Port is no longer usable as a router interface */
3528         if (mlxsw_sp_port->default_vlan->fid)
3529                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
3530
3531         return 0;
3532
3533 err_col_port_add:
3534         if (!lag->ref_count)
3535                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
3536         return err;
3537 }
3538
3539 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3540                                     struct net_device *lag_dev)
3541 {
3542         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3543         u16 lag_id = mlxsw_sp_port->lag_id;
3544         struct mlxsw_sp_upper *lag;
3545
3546         if (!mlxsw_sp_port->lagged)
3547                 return;
3548         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3549         WARN_ON(lag->ref_count == 0);
3550
3551         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
3552
3553         /* Any VLANs configured on the port are no longer valid */
3554         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
3555         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
3556         /* Make the LAG and its directly linked uppers leave bridges they
3557          * are memeber in
3558          */
3559         mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
3560
3561         if (lag->ref_count == 1)
3562                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
3563
3564         mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3565                                      mlxsw_sp_port->local_port);
3566         mlxsw_sp_port->lagged = 0;
3567         lag->ref_count--;
3568
3569         /* Make sure untagged frames are allowed to ingress */
3570         mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3571 }
3572
3573 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3574                                       u16 lag_id)
3575 {
3576         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3577         char sldr_pl[MLXSW_REG_SLDR_LEN];
3578
3579         mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
3580                                          mlxsw_sp_port->local_port);
3581         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3582 }
3583
3584 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3585                                          u16 lag_id)
3586 {
3587         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3588         char sldr_pl[MLXSW_REG_SLDR_LEN];
3589
3590         mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
3591                                             mlxsw_sp_port->local_port);
3592         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3593 }
3594
3595 static int
3596 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
3597 {
3598         int err;
3599
3600         err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
3601                                            mlxsw_sp_port->lag_id);
3602         if (err)
3603                 return err;
3604
3605         err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
3606         if (err)
3607                 goto err_dist_port_add;
3608
3609         return 0;
3610
3611 err_dist_port_add:
3612         mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
3613         return err;
3614 }
3615
3616 static int
3617 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
3618 {
3619         int err;
3620
3621         err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
3622                                             mlxsw_sp_port->lag_id);
3623         if (err)
3624                 return err;
3625
3626         err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
3627                                             mlxsw_sp_port->lag_id);
3628         if (err)
3629                 goto err_col_port_disable;
3630
3631         return 0;
3632
3633 err_col_port_disable:
3634         mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
3635         return err;
3636 }
3637
3638 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
3639                                      struct netdev_lag_lower_state_info *info)
3640 {
3641         if (info->tx_enabled)
3642                 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
3643         else
3644                 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
3645 }
3646
3647 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
3648                                  bool enable)
3649 {
3650         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3651         enum mlxsw_reg_spms_state spms_state;
3652         char *spms_pl;
3653         u16 vid;
3654         int err;
3655
3656         spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
3657                               MLXSW_REG_SPMS_STATE_DISCARDING;
3658
3659         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
3660         if (!spms_pl)
3661                 return -ENOMEM;
3662         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
3663
3664         for (vid = 0; vid < VLAN_N_VID; vid++)
3665                 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
3666
3667         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
3668         kfree(spms_pl);
3669         return err;
3670 }
3671
3672 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
3673 {
3674         u16 vid = 1;
3675         int err;
3676
3677         err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
3678         if (err)
3679                 return err;
3680         err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
3681         if (err)
3682                 goto err_port_stp_set;
3683         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
3684                                      true, false);
3685         if (err)
3686                 goto err_port_vlan_set;
3687
3688         for (; vid <= VLAN_N_VID - 1; vid++) {
3689                 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
3690                                                      vid, false);
3691                 if (err)
3692                         goto err_vid_learning_set;
3693         }
3694
3695         return 0;
3696
3697 err_vid_learning_set:
3698         for (vid--; vid >= 1; vid--)
3699                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
3700 err_port_vlan_set:
3701         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
3702 err_port_stp_set:
3703         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
3704         return err;
3705 }
3706
3707 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3708 {
3709         u16 vid;
3710
3711         for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
3712                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
3713                                                vid, true);
3714
3715         mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
3716                                false, false);
3717         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
3718         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
3719 }
3720
3721 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
3722 {
3723         unsigned int num_vxlans = 0;
3724         struct net_device *dev;
3725         struct list_head *iter;
3726
3727         netdev_for_each_lower_dev(br_dev, dev, iter) {
3728                 if (netif_is_vxlan(dev))
3729                         num_vxlans++;
3730         }
3731
3732         return num_vxlans > 1;
3733 }
3734
3735 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
3736 {
3737         DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
3738         struct net_device *dev;
3739         struct list_head *iter;
3740
3741         netdev_for_each_lower_dev(br_dev, dev, iter) {
3742                 u16 pvid;
3743                 int err;
3744
3745                 if (!netif_is_vxlan(dev))
3746                         continue;
3747
3748                 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
3749                 if (err || !pvid)
3750                         continue;
3751
3752                 if (test_and_set_bit(pvid, vlans))
3753                         return false;
3754         }
3755
3756         return true;
3757 }
3758
3759 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
3760                                            struct netlink_ext_ack *extack)
3761 {
3762         if (br_multicast_enabled(br_dev)) {
3763                 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
3764                 return false;
3765         }
3766
3767         if (!br_vlan_enabled(br_dev) &&
3768             mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
3769                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
3770                 return false;
3771         }
3772
3773         if (br_vlan_enabled(br_dev) &&
3774             !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
3775                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
3776                 return false;
3777         }
3778
3779         return true;
3780 }
3781
3782 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
3783                                                struct net_device *dev,
3784                                                unsigned long event, void *ptr)
3785 {
3786         struct netdev_notifier_changeupper_info *info;
3787         struct mlxsw_sp_port *mlxsw_sp_port;
3788         struct netlink_ext_ack *extack;
3789         struct net_device *upper_dev;
3790         struct mlxsw_sp *mlxsw_sp;
3791         int err = 0;
3792
3793         mlxsw_sp_port = netdev_priv(dev);
3794         mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3795         info = ptr;
3796         extack = netdev_notifier_info_to_extack(&info->info);
3797
3798         switch (event) {
3799         case NETDEV_PRECHANGEUPPER:
3800                 upper_dev = info->upper_dev;
3801                 if (!is_vlan_dev(upper_dev) &&
3802                     !netif_is_lag_master(upper_dev) &&
3803                     !netif_is_bridge_master(upper_dev) &&
3804                     !netif_is_ovs_master(upper_dev) &&
3805                     !netif_is_macvlan(upper_dev)) {
3806                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
3807                         return -EINVAL;
3808                 }
3809                 if (!info->linking)
3810                         break;
3811                 if (netif_is_bridge_master(upper_dev) &&
3812                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
3813                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
3814                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
3815                         return -EOPNOTSUPP;
3816                 if (netdev_has_any_upper_dev(upper_dev) &&
3817                     (!netif_is_bridge_master(upper_dev) ||
3818                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
3819                                                           upper_dev))) {
3820                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
3821                         return -EINVAL;
3822                 }
3823                 if (netif_is_lag_master(upper_dev) &&
3824                     !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3825                                                info->upper_info, extack))
3826                         return -EINVAL;
3827                 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
3828                         NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
3829                         return -EINVAL;
3830                 }
3831                 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3832                     !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
3833                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
3834                         return -EINVAL;
3835                 }
3836                 if (netif_is_macvlan(upper_dev) &&
3837                     !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) {
3838                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
3839                         return -EOPNOTSUPP;
3840                 }
3841                 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
3842                         NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
3843                         return -EINVAL;
3844                 }
3845                 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
3846                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
3847                         return -EINVAL;
3848                 }
3849                 break;
3850         case NETDEV_CHANGEUPPER:
3851                 upper_dev = info->upper_dev;
3852                 if (netif_is_bridge_master(upper_dev)) {
3853                         if (info->linking)
3854                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3855                                                                 lower_dev,
3856                                                                 upper_dev,
3857                                                                 extack);
3858                         else
3859                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
3860                                                            lower_dev,
3861                                                            upper_dev);
3862                 } else if (netif_is_lag_master(upper_dev)) {
3863                         if (info->linking) {
3864                                 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3865                                                              upper_dev);
3866                         } else {
3867                                 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
3868                                 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3869                                                         upper_dev);
3870                         }
3871                 } else if (netif_is_ovs_master(upper_dev)) {
3872                         if (info->linking)
3873                                 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
3874                         else
3875                                 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
3876                 } else if (netif_is_macvlan(upper_dev)) {
3877                         if (!info->linking)
3878                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
3879                 } else if (is_vlan_dev(upper_dev)) {
3880                         struct net_device *br_dev;
3881
3882                         if (!netif_is_bridge_port(upper_dev))
3883                                 break;
3884                         if (info->linking)
3885                                 break;
3886                         br_dev = netdev_master_upper_dev_get(upper_dev);
3887                         mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
3888                                                    br_dev);
3889                 }
3890                 break;
3891         }
3892
3893         return err;
3894 }
3895
3896 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3897                                                unsigned long event, void *ptr)
3898 {
3899         struct netdev_notifier_changelowerstate_info *info;
3900         struct mlxsw_sp_port *mlxsw_sp_port;
3901         int err;
3902
3903         mlxsw_sp_port = netdev_priv(dev);
3904         info = ptr;
3905
3906         switch (event) {
3907         case NETDEV_CHANGELOWERSTATE:
3908                 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3909                         err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3910                                                         info->lower_state_info);
3911                         if (err)
3912                                 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3913                 }
3914                 break;
3915         }
3916
3917         return 0;
3918 }
3919
3920 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
3921                                          struct net_device *port_dev,
3922                                          unsigned long event, void *ptr)
3923 {
3924         switch (event) {
3925         case NETDEV_PRECHANGEUPPER:
3926         case NETDEV_CHANGEUPPER:
3927                 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
3928                                                            event, ptr);
3929         case NETDEV_CHANGELOWERSTATE:
3930                 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
3931                                                            ptr);
3932         }
3933
3934         return 0;
3935 }
3936
3937 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3938                                         unsigned long event, void *ptr)
3939 {
3940         struct net_device *dev;
3941         struct list_head *iter;
3942         int ret;
3943
3944         netdev_for_each_lower_dev(lag_dev, dev, iter) {
3945                 if (mlxsw_sp_port_dev_check(dev)) {
3946                         ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
3947                                                             ptr);
3948                         if (ret)
3949                                 return ret;
3950                 }
3951         }
3952
3953         return 0;
3954 }
3955
3956 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
3957                                               struct net_device *dev,
3958                                               unsigned long event, void *ptr,
3959                                               u16 vid)
3960 {
3961         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3962         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3963         struct netdev_notifier_changeupper_info *info = ptr;
3964         struct netlink_ext_ack *extack;
3965         struct net_device *upper_dev;
3966         int err = 0;
3967
3968         extack = netdev_notifier_info_to_extack(&info->info);
3969
3970         switch (event) {
3971         case NETDEV_PRECHANGEUPPER:
3972                 upper_dev = info->upper_dev;
3973                 if (!netif_is_bridge_master(upper_dev) &&
3974                     !netif_is_macvlan(upper_dev)) {
3975                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
3976                         return -EINVAL;
3977                 }
3978                 if (!info->linking)
3979                         break;
3980                 if (netif_is_bridge_master(upper_dev) &&
3981                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
3982                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
3983                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
3984                         return -EOPNOTSUPP;
3985                 if (netdev_has_any_upper_dev(upper_dev) &&
3986                     (!netif_is_bridge_master(upper_dev) ||
3987                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
3988                                                           upper_dev))) {
3989                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
3990                         return -EINVAL;
3991                 }
3992                 if (netif_is_macvlan(upper_dev) &&
3993                     !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
3994                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
3995                         return -EOPNOTSUPP;
3996                 }
3997                 break;
3998         case NETDEV_CHANGEUPPER:
3999                 upper_dev = info->upper_dev;
4000                 if (netif_is_bridge_master(upper_dev)) {
4001                         if (info->linking)
4002                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4003                                                                 vlan_dev,
4004                                                                 upper_dev,
4005                                                                 extack);
4006                         else
4007                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4008                                                            vlan_dev,
4009                                                            upper_dev);
4010                 } else if (netif_is_macvlan(upper_dev)) {
4011                         if (!info->linking)
4012                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4013                 } else {
4014                         err = -EINVAL;
4015                         WARN_ON(1);
4016                 }
4017                 break;
4018         }
4019
4020         return err;
4021 }
4022
4023 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4024                                                   struct net_device *lag_dev,
4025                                                   unsigned long event,
4026                                                   void *ptr, u16 vid)
4027 {
4028         struct net_device *dev;
4029         struct list_head *iter;
4030         int ret;
4031
4032         netdev_for_each_lower_dev(lag_dev, dev, iter) {
4033                 if (mlxsw_sp_port_dev_check(dev)) {
4034                         ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4035                                                                  event, ptr,
4036                                                                  vid);
4037                         if (ret)
4038                                 return ret;
4039                 }
4040         }
4041
4042         return 0;
4043 }
4044
4045 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
4046                                                 struct net_device *br_dev,
4047                                                 unsigned long event, void *ptr,
4048                                                 u16 vid)
4049 {
4050         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
4051         struct netdev_notifier_changeupper_info *info = ptr;
4052         struct netlink_ext_ack *extack;
4053         struct net_device *upper_dev;
4054
4055         if (!mlxsw_sp)
4056                 return 0;
4057
4058         extack = netdev_notifier_info_to_extack(&info->info);
4059
4060         switch (event) {
4061         case NETDEV_PRECHANGEUPPER:
4062                 upper_dev = info->upper_dev;
4063                 if (!netif_is_macvlan(upper_dev)) {
4064                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4065                         return -EOPNOTSUPP;
4066                 }
4067                 if (!info->linking)
4068                         break;
4069                 if (netif_is_macvlan(upper_dev) &&
4070                     !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
4071                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4072                         return -EOPNOTSUPP;
4073                 }
4074                 break;
4075         case NETDEV_CHANGEUPPER:
4076                 upper_dev = info->upper_dev;
4077                 if (info->linking)
4078                         break;
4079                 if (netif_is_macvlan(upper_dev))
4080                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4081                 break;
4082         }
4083
4084         return 0;
4085 }
4086
4087 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4088                                          unsigned long event, void *ptr)
4089 {
4090         struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4091         u16 vid = vlan_dev_vlan_id(vlan_dev);
4092
4093         if (mlxsw_sp_port_dev_check(real_dev))
4094                 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4095                                                           event, ptr, vid);
4096         else if (netif_is_lag_master(real_dev))
4097                 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4098                                                               real_dev, event,
4099                                                               ptr, vid);
4100         else if (netif_is_bridge_master(real_dev))
4101                 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
4102                                                             event, ptr, vid);
4103
4104         return 0;
4105 }
4106
4107 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4108                                            unsigned long event, void *ptr)
4109 {
4110         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4111         struct netdev_notifier_changeupper_info *info = ptr;
4112         struct netlink_ext_ack *extack;
4113         struct net_device *upper_dev;
4114
4115         if (!mlxsw_sp)
4116                 return 0;
4117
4118         extack = netdev_notifier_info_to_extack(&info->info);
4119
4120         switch (event) {
4121         case NETDEV_PRECHANGEUPPER:
4122                 upper_dev = info->upper_dev;
4123                 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
4124                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4125                         return -EOPNOTSUPP;
4126                 }
4127                 if (!info->linking)
4128                         break;
4129                 if (netif_is_macvlan(upper_dev) &&
4130                     !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) {
4131                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4132                         return -EOPNOTSUPP;
4133                 }
4134                 break;
4135         case NETDEV_CHANGEUPPER:
4136                 upper_dev = info->upper_dev;
4137                 if (info->linking)
4138                         break;
4139                 if (is_vlan_dev(upper_dev))
4140                         mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
4141                 if (netif_is_macvlan(upper_dev))
4142                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4143                 break;
4144         }
4145
4146         return 0;
4147 }
4148
4149 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
4150                                             unsigned long event, void *ptr)
4151 {
4152         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
4153         struct netdev_notifier_changeupper_info *info = ptr;
4154         struct netlink_ext_ack *extack;
4155
4156         if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
4157                 return 0;
4158
4159         extack = netdev_notifier_info_to_extack(&info->info);
4160
4161         /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
4162         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4163
4164         return -EOPNOTSUPP;
4165 }
4166
4167 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4168 {
4169         struct netdev_notifier_changeupper_info *info = ptr;
4170
4171         if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4172                 return false;
4173         return netif_is_l3_master(info->upper_dev);
4174 }
4175
4176 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
4177                                           struct net_device *dev,
4178                                           unsigned long event, void *ptr)
4179 {
4180         struct netdev_notifier_changeupper_info *cu_info;
4181         struct netdev_notifier_info *info = ptr;
4182         struct netlink_ext_ack *extack;
4183         struct net_device *upper_dev;
4184
4185         extack = netdev_notifier_info_to_extack(info);
4186
4187         switch (event) {
4188         case NETDEV_CHANGEUPPER:
4189                 cu_info = container_of(info,
4190                                        struct netdev_notifier_changeupper_info,
4191                                        info);
4192                 upper_dev = cu_info->upper_dev;
4193                 if (!netif_is_bridge_master(upper_dev))
4194                         return 0;
4195                 if (!mlxsw_sp_lower_get(upper_dev))
4196                         return 0;
4197                 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4198                         return -EOPNOTSUPP;
4199                 if (cu_info->linking) {
4200                         if (!netif_running(dev))
4201                                 return 0;
4202                         /* When the bridge is VLAN-aware, the VNI of the VxLAN
4203                          * device needs to be mapped to a VLAN, but at this
4204                          * point no VLANs are configured on the VxLAN device
4205                          */
4206                         if (br_vlan_enabled(upper_dev))
4207                                 return 0;
4208                         return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
4209                                                           dev, 0, extack);
4210                 } else {
4211                         /* VLANs were already flushed, which triggered the
4212                          * necessary cleanup
4213                          */
4214                         if (br_vlan_enabled(upper_dev))
4215                                 return 0;
4216                         mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
4217                 }
4218                 break;
4219         case NETDEV_PRE_UP:
4220                 upper_dev = netdev_master_upper_dev_get(dev);
4221                 if (!upper_dev)
4222                         return 0;
4223                 if (!netif_is_bridge_master(upper_dev))
4224                         return 0;
4225                 if (!mlxsw_sp_lower_get(upper_dev))
4226                         return 0;
4227                 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
4228                                                   extack);
4229         case NETDEV_DOWN:
4230                 upper_dev = netdev_master_upper_dev_get(dev);
4231                 if (!upper_dev)
4232                         return 0;
4233                 if (!netif_is_bridge_master(upper_dev))
4234                         return 0;
4235                 if (!mlxsw_sp_lower_get(upper_dev))
4236                         return 0;
4237                 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
4238                 break;
4239         }
4240
4241         return 0;
4242 }
4243
4244 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
4245                                     unsigned long event, void *ptr)
4246 {
4247         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4248         struct mlxsw_sp_span_entry *span_entry;
4249         struct mlxsw_sp *mlxsw_sp;
4250         int err = 0;
4251
4252         mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
4253         if (event == NETDEV_UNREGISTER) {
4254                 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4255                 if (span_entry)
4256                         mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4257         }
4258         mlxsw_sp_span_respin(mlxsw_sp);
4259
4260         if (netif_is_vxlan(dev))
4261                 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
4262         if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4263                 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4264                                                        event, ptr);
4265         else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4266                 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4267                                                        event, ptr);
4268         else if (event == NETDEV_PRE_CHANGEADDR ||
4269                  event == NETDEV_CHANGEADDR ||
4270                  event == NETDEV_CHANGEMTU)
4271                 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
4272         else if (mlxsw_sp_is_vrf_event(event, ptr))
4273                 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
4274         else if (mlxsw_sp_port_dev_check(dev))
4275                 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
4276         else if (netif_is_lag_master(dev))
4277                 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4278         else if (is_vlan_dev(dev))
4279                 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
4280         else if (netif_is_bridge_master(dev))
4281                 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
4282         else if (netif_is_macvlan(dev))
4283                 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
4284
4285         return notifier_from_errno(err);
4286 }
4287
4288 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4289         .notifier_call = mlxsw_sp_inetaddr_valid_event,
4290 };
4291
4292 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4293         .notifier_call = mlxsw_sp_inet6addr_valid_event,
4294 };
4295
4296 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
4297         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4298         {0, },
4299 };
4300
4301 static struct pci_driver mlxsw_sp1_pci_driver = {
4302         .name = mlxsw_sp1_driver_name,
4303         .id_table = mlxsw_sp1_pci_id_table,
4304 };
4305
4306 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
4307         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
4308         {0, },
4309 };
4310
4311 static struct pci_driver mlxsw_sp2_pci_driver = {
4312         .name = mlxsw_sp2_driver_name,
4313         .id_table = mlxsw_sp2_pci_id_table,
4314 };
4315
4316 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
4317         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
4318         {0, },
4319 };
4320
4321 static struct pci_driver mlxsw_sp3_pci_driver = {
4322         .name = mlxsw_sp3_driver_name,
4323         .id_table = mlxsw_sp3_pci_id_table,
4324 };
4325
4326 static int __init mlxsw_sp_module_init(void)
4327 {
4328         int err;
4329
4330         register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4331         register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4332
4333         err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
4334         if (err)
4335                 goto err_sp1_core_driver_register;
4336
4337         err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
4338         if (err)
4339                 goto err_sp2_core_driver_register;
4340
4341         err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
4342         if (err)
4343                 goto err_sp3_core_driver_register;
4344
4345         err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
4346         if (err)
4347                 goto err_sp1_pci_driver_register;
4348
4349         err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
4350         if (err)
4351                 goto err_sp2_pci_driver_register;
4352
4353         err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
4354         if (err)
4355                 goto err_sp3_pci_driver_register;
4356
4357         return 0;
4358
4359 err_sp3_pci_driver_register:
4360         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
4361 err_sp2_pci_driver_register:
4362         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
4363 err_sp1_pci_driver_register:
4364         mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
4365 err_sp3_core_driver_register:
4366         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
4367 err_sp2_core_driver_register:
4368         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
4369 err_sp1_core_driver_register:
4370         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4371         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4372         return err;
4373 }
4374
4375 static void __exit mlxsw_sp_module_exit(void)
4376 {
4377         mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
4378         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
4379         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
4380         mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
4381         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
4382         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
4383         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4384         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4385 }
4386
4387 module_init(mlxsw_sp_module_init);
4388 module_exit(mlxsw_sp_module_exit);
4389
4390 MODULE_LICENSE("Dual BSD/GPL");
4391 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4392 MODULE_DESCRIPTION("Mellanox Spectrum driver");
4393 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
4394 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
4395 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
4396 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
4397 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);
4398 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME);