2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the names of the copyright holders nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * Alternatively, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") version 2 as published by the Free
23 * Software Foundation.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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35 * POSSIBILITY OF SUCH DAMAGE.
41 #include <linux/string.h>
42 #include <linux/bitops.h>
43 #include <linux/if_vlan.h>
48 struct mlxsw_reg_info {
53 #define MLXSW_REG(type) (&mlxsw_reg_##type)
54 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
55 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
57 /* SGCR - Switch General Configuration Register
58 * --------------------------------------------
59 * This register is used for configuration of the switch capabilities.
61 #define MLXSW_REG_SGCR_ID 0x2000
62 #define MLXSW_REG_SGCR_LEN 0x10
64 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
65 .id = MLXSW_REG_SGCR_ID,
66 .len = MLXSW_REG_SGCR_LEN,
70 * Link Local Broadcast (Default=0)
71 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
72 * packets and ignore the IGMP snooping entries.
75 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
77 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
79 MLXSW_REG_ZERO(sgcr, payload);
80 mlxsw_reg_sgcr_llb_set(payload, !!llb);
83 /* SPAD - Switch Physical Address Register
84 * ---------------------------------------
85 * The SPAD register configures the switch physical MAC address.
87 #define MLXSW_REG_SPAD_ID 0x2002
88 #define MLXSW_REG_SPAD_LEN 0x10
90 static const struct mlxsw_reg_info mlxsw_reg_spad = {
91 .id = MLXSW_REG_SPAD_ID,
92 .len = MLXSW_REG_SPAD_LEN,
96 * Base MAC address for the switch partitions.
97 * Per switch partition MAC address is equal to:
101 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
103 /* SMID - Switch Multicast ID
104 * --------------------------
105 * The MID record maps from a MID (Multicast ID), which is a unique identifier
106 * of the multicast group within the stacking domain, into a list of local
107 * ports into which the packet is replicated.
109 #define MLXSW_REG_SMID_ID 0x2007
110 #define MLXSW_REG_SMID_LEN 0x240
112 static const struct mlxsw_reg_info mlxsw_reg_smid = {
113 .id = MLXSW_REG_SMID_ID,
114 .len = MLXSW_REG_SMID_LEN,
118 * Switch partition ID.
121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
124 * Multicast identifier - global identifier that represents the multicast group
125 * across all devices.
128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
131 * Local port memebership (1 bit per port).
134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
136 /* reg_smid_port_mask
137 * Local port mask (1 bit per port).
140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
145 MLXSW_REG_ZERO(smid, payload);
146 mlxsw_reg_smid_swid_set(payload, 0);
147 mlxsw_reg_smid_mid_set(payload, mid);
148 mlxsw_reg_smid_port_set(payload, port, set);
149 mlxsw_reg_smid_port_mask_set(payload, port, 1);
152 /* SSPR - Switch System Port Record Register
153 * -----------------------------------------
154 * Configures the system port to local port mapping.
156 #define MLXSW_REG_SSPR_ID 0x2008
157 #define MLXSW_REG_SSPR_LEN 0x8
159 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
160 .id = MLXSW_REG_SSPR_ID,
161 .len = MLXSW_REG_SSPR_LEN,
165 * Master - if set, then the record describes the master system port.
166 * This is needed in case a local port is mapped into several system ports
167 * (for multipathing). That number will be reported as the source system
168 * port when packets are forwarded to the CPU. Only one master port is allowed
171 * Note: Must be set for Spectrum.
174 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
176 /* reg_sspr_local_port
181 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
184 * Virtual port within the physical port.
185 * Should be set to 0 when virtual ports are not enabled on the port.
189 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
191 /* reg_sspr_system_port
192 * Unique identifier within the stacking domain that represents all the ports
193 * that are available in the system (external ports).
195 * Currently, only single-ASIC configurations are supported, so we default to
196 * 1:1 mapping between system ports and local ports.
199 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
201 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
203 MLXSW_REG_ZERO(sspr, payload);
204 mlxsw_reg_sspr_m_set(payload, 1);
205 mlxsw_reg_sspr_local_port_set(payload, local_port);
206 mlxsw_reg_sspr_sub_port_set(payload, 0);
207 mlxsw_reg_sspr_system_port_set(payload, local_port);
210 /* SFDAT - Switch Filtering Database Aging Time
211 * --------------------------------------------
212 * Controls the Switch aging time. Aging time is able to be set per Switch
215 #define MLXSW_REG_SFDAT_ID 0x2009
216 #define MLXSW_REG_SFDAT_LEN 0x8
218 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
219 .id = MLXSW_REG_SFDAT_ID,
220 .len = MLXSW_REG_SFDAT_LEN,
224 * Switch partition ID.
227 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
229 /* reg_sfdat_age_time
230 * Aging time in seconds
232 * Max - 1,000,000 seconds
233 * Default is 300 seconds.
236 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
238 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
240 MLXSW_REG_ZERO(sfdat, payload);
241 mlxsw_reg_sfdat_swid_set(payload, 0);
242 mlxsw_reg_sfdat_age_time_set(payload, age_time);
245 /* SFD - Switch Filtering Database
246 * -------------------------------
247 * The following register defines the access to the filtering database.
248 * The register supports querying, adding, removing and modifying the database.
249 * The access is optimized for bulk updates in which case more than one
250 * FDB record is present in the same command.
252 #define MLXSW_REG_SFD_ID 0x200A
253 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
254 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
255 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
256 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
257 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
259 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
260 .id = MLXSW_REG_SFD_ID,
261 .len = MLXSW_REG_SFD_LEN,
265 * Switch partition ID for queries. Reserved on Write.
268 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
270 enum mlxsw_reg_sfd_op {
271 /* Dump entire FDB a (process according to record_locator) */
272 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
273 /* Query records by {MAC, VID/FID} value */
274 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
275 /* Query and clear activity. Query records by {MAC, VID/FID} value */
276 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
277 /* Test. Response indicates if each of the records could be
280 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
281 /* Add/modify. Aged-out records cannot be added. This command removes
282 * the learning notification of the {MAC, VID/FID}. Response includes
283 * the entries that were added to the FDB.
285 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
286 /* Remove record by {MAC, VID/FID}. This command also removes
287 * the learning notification and aged-out notifications
288 * of the {MAC, VID/FID}. The response provides current (pre-removal)
289 * entries as non-aged-out.
291 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
292 /* Remove learned notification by {MAC, VID/FID}. The response provides
293 * the removed learning notification.
295 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
302 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
304 /* reg_sfd_record_locator
305 * Used for querying the FDB. Use record_locator=0 to initiate the
306 * query. When a record is returned, a new record_locator is
307 * returned to be used in the subsequent query.
308 * Reserved for database update.
311 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
314 * Request: Number of records to read/add/modify/remove
315 * Response: Number of records read/added/replaced/removed
316 * See above description for more details.
320 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
322 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
325 MLXSW_REG_ZERO(sfd, payload);
326 mlxsw_reg_sfd_op_set(payload, op);
327 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
331 * Switch partition ID.
334 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
335 MLXSW_REG_SFD_REC_LEN, 0x00, false);
337 enum mlxsw_reg_sfd_rec_type {
338 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
339 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
340 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
347 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
348 MLXSW_REG_SFD_REC_LEN, 0x00, false);
350 enum mlxsw_reg_sfd_rec_policy {
351 /* Replacement disabled, aging disabled. */
352 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
353 /* (mlag remote): Replacement enabled, aging disabled,
354 * learning notification enabled on this port.
356 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
357 /* (ingress device): Replacement enabled, aging enabled. */
358 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
361 /* reg_sfd_rec_policy
365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
366 MLXSW_REG_SFD_REC_LEN, 0x00, false);
369 * Activity. Set for new static entries. Set for static entries if a frame SMAC
370 * lookup hits on the entry.
371 * To clear the a bit, use "query and clear activity" op.
374 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
375 MLXSW_REG_SFD_REC_LEN, 0x00, false);
381 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
382 MLXSW_REG_SFD_REC_LEN, 0x02);
384 enum mlxsw_reg_sfd_rec_action {
386 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
387 /* forward and trap, trap_id is FDB_TRAP */
388 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
389 /* trap and do not forward, trap_id is FDB_TRAP */
390 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
391 /* forward to IP router */
392 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
393 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
396 /* reg_sfd_rec_action
397 * Action to apply on the packet.
398 * Note: Dynamic entries can only be configured with NOP action.
401 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
402 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
404 /* reg_sfd_uc_sub_port
405 * VEPA channel on local port.
406 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
407 * VEPA is not enabled.
410 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
411 MLXSW_REG_SFD_REC_LEN, 0x08, false);
413 /* reg_sfd_uc_fid_vid
414 * Filtering ID or VLAN ID
415 * For SwitchX and SwitchX-2:
416 * - Dynamic entries (policy 2,3) use FID
417 * - Static entries (policy 0) use VID
418 * - When independent learning is configured, VID=FID
419 * For Spectrum: use FID for both Dynamic and Static entries.
420 * VID should not be used.
423 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
424 MLXSW_REG_SFD_REC_LEN, 0x08, false);
426 /* reg_sfd_uc_system_port
427 * Unique port identifier for the final destination of the packet.
430 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
431 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
433 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
434 enum mlxsw_reg_sfd_rec_type rec_type,
436 enum mlxsw_reg_sfd_rec_action action)
438 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
440 if (rec_index >= num_rec)
441 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
442 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
443 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
444 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
445 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
448 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
449 enum mlxsw_reg_sfd_rec_policy policy,
450 const char *mac, u16 fid_vid,
451 enum mlxsw_reg_sfd_rec_action action,
454 mlxsw_reg_sfd_rec_pack(payload, rec_index,
455 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
457 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
458 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
459 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
462 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
463 char *mac, u16 *p_fid_vid,
466 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
467 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
468 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
471 /* reg_sfd_uc_lag_sub_port
473 * Must be 0 if multichannel VEPA is not enabled.
476 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
477 MLXSW_REG_SFD_REC_LEN, 0x08, false);
479 /* reg_sfd_uc_lag_fid_vid
480 * Filtering ID or VLAN ID
481 * For SwitchX and SwitchX-2:
482 * - Dynamic entries (policy 2,3) use FID
483 * - Static entries (policy 0) use VID
484 * - When independent learning is configured, VID=FID
485 * For Spectrum: use FID for both Dynamic and Static entries.
486 * VID should not be used.
489 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
490 MLXSW_REG_SFD_REC_LEN, 0x08, false);
492 /* reg_sfd_uc_lag_lag_vid
493 * Indicates VID in case of vFIDs. Reserved for FIDs.
496 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
497 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
499 /* reg_sfd_uc_lag_lag_id
500 * LAG Identifier - pointer into the LAG descriptor table.
503 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
504 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
507 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
508 enum mlxsw_reg_sfd_rec_policy policy,
509 const char *mac, u16 fid_vid,
510 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
513 mlxsw_reg_sfd_rec_pack(payload, rec_index,
514 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
516 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
517 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
518 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
519 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
520 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
523 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
524 char *mac, u16 *p_vid,
527 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
528 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
529 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
534 * Multicast port group index - index into the port group table.
535 * Value 0x1FFF indicates the pgi should point to the MID entry.
536 * For Spectrum this value must be set to 0x1FFF
539 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
540 MLXSW_REG_SFD_REC_LEN, 0x08, false);
542 /* reg_sfd_mc_fid_vid
544 * Filtering ID or VLAN ID
547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
548 MLXSW_REG_SFD_REC_LEN, 0x08, false);
552 * Multicast identifier - global identifier that represents the multicast
553 * group across all devices.
556 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
557 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
560 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
561 const char *mac, u16 fid_vid,
562 enum mlxsw_reg_sfd_rec_action action, u16 mid)
564 mlxsw_reg_sfd_rec_pack(payload, rec_index,
565 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
566 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
567 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
568 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
571 /* SFN - Switch FDB Notification Register
572 * -------------------------------------------
573 * The switch provides notifications on newly learned FDB entries and
574 * aged out entries. The notifications can be polled by software.
576 #define MLXSW_REG_SFN_ID 0x200B
577 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
578 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
579 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
580 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
581 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
583 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
584 .id = MLXSW_REG_SFN_ID,
585 .len = MLXSW_REG_SFN_LEN,
589 * Switch partition ID.
592 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
595 * Request: Number of learned notifications and aged-out notification
597 * Response: Number of notification records returned (must be smaller
598 * than or equal to the value requested)
602 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
604 static inline void mlxsw_reg_sfn_pack(char *payload)
606 MLXSW_REG_ZERO(sfn, payload);
607 mlxsw_reg_sfn_swid_set(payload, 0);
608 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
612 * Switch partition ID.
615 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
616 MLXSW_REG_SFN_REC_LEN, 0x00, false);
618 enum mlxsw_reg_sfn_rec_type {
619 /* MAC addresses learned on a regular port. */
620 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
621 /* MAC addresses learned on a LAG port. */
622 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
623 /* Aged-out MAC address on a regular port. */
624 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
625 /* Aged-out MAC address on a LAG port. */
626 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
630 * Notification record type.
633 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
634 MLXSW_REG_SFN_REC_LEN, 0x00, false);
640 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
641 MLXSW_REG_SFN_REC_LEN, 0x02);
643 /* reg_sfn_mac_sub_port
644 * VEPA channel on the local port.
645 * 0 if multichannel VEPA is not enabled.
648 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
649 MLXSW_REG_SFN_REC_LEN, 0x08, false);
652 * Filtering identifier.
655 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
656 MLXSW_REG_SFN_REC_LEN, 0x08, false);
658 /* reg_sfn_mac_system_port
659 * Unique port identifier for the final destination of the packet.
662 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
663 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
665 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
666 char *mac, u16 *p_vid,
669 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
670 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
671 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
674 /* reg_sfn_mac_lag_lag_id
675 * LAG ID (pointer into the LAG descriptor table).
678 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
679 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
681 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
682 char *mac, u16 *p_vid,
685 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
686 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
687 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
690 /* SPMS - Switch Port MSTP/RSTP State Register
691 * -------------------------------------------
692 * Configures the spanning tree state of a physical port.
694 #define MLXSW_REG_SPMS_ID 0x200D
695 #define MLXSW_REG_SPMS_LEN 0x404
697 static const struct mlxsw_reg_info mlxsw_reg_spms = {
698 .id = MLXSW_REG_SPMS_ID,
699 .len = MLXSW_REG_SPMS_LEN,
702 /* reg_spms_local_port
706 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
708 enum mlxsw_reg_spms_state {
709 MLXSW_REG_SPMS_STATE_NO_CHANGE,
710 MLXSW_REG_SPMS_STATE_DISCARDING,
711 MLXSW_REG_SPMS_STATE_LEARNING,
712 MLXSW_REG_SPMS_STATE_FORWARDING,
716 * Spanning tree state of each VLAN ID (VID) of the local port.
717 * 0 - Do not change spanning tree state (used only when writing).
718 * 1 - Discarding. No learning or forwarding to/from this port (default).
719 * 2 - Learning. Port is learning, but not forwarding.
720 * 3 - Forwarding. Port is learning and forwarding.
723 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
725 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
727 MLXSW_REG_ZERO(spms, payload);
728 mlxsw_reg_spms_local_port_set(payload, local_port);
731 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
732 enum mlxsw_reg_spms_state state)
734 mlxsw_reg_spms_state_set(payload, vid, state);
737 /* SPVID - Switch Port VID
738 * -----------------------
739 * The switch port VID configures the default VID for a port.
741 #define MLXSW_REG_SPVID_ID 0x200E
742 #define MLXSW_REG_SPVID_LEN 0x08
744 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
745 .id = MLXSW_REG_SPVID_ID,
746 .len = MLXSW_REG_SPVID_LEN,
749 /* reg_spvid_local_port
753 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
755 /* reg_spvid_sub_port
756 * Virtual port within the physical port.
757 * Should be set to 0 when virtual ports are not enabled on the port.
760 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
766 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
768 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
770 MLXSW_REG_ZERO(spvid, payload);
771 mlxsw_reg_spvid_local_port_set(payload, local_port);
772 mlxsw_reg_spvid_pvid_set(payload, pvid);
775 /* SPVM - Switch Port VLAN Membership
776 * ----------------------------------
777 * The Switch Port VLAN Membership register configures the VLAN membership
778 * of a port in a VLAN denoted by VID. VLAN membership is managed per
779 * virtual port. The register can be used to add and remove VID(s) from a port.
781 #define MLXSW_REG_SPVM_ID 0x200F
782 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
783 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
784 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
785 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
786 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
788 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
789 .id = MLXSW_REG_SPVM_ID,
790 .len = MLXSW_REG_SPVM_LEN,
794 * Priority tagged. If this bit is set, packets forwarded to the port with
795 * untagged VLAN membership (u bit is set) will be tagged with priority tag
799 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
802 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
803 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
806 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
808 /* reg_spvm_local_port
812 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
815 * Virtual port within the physical port.
816 * Should be set to 0 when virtual ports are not enabled on the port.
819 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
822 * Number of records to update. Each record contains: i, e, u, vid.
825 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
828 * Ingress membership in VLAN ID.
831 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
832 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
833 MLXSW_REG_SPVM_REC_LEN, 0, false);
836 * Egress membership in VLAN ID.
839 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
840 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
841 MLXSW_REG_SPVM_REC_LEN, 0, false);
844 * Untagged - port is an untagged member - egress transmission uses untagged
848 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
849 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
850 MLXSW_REG_SPVM_REC_LEN, 0, false);
853 * Egress membership in VLAN ID.
856 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
857 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
858 MLXSW_REG_SPVM_REC_LEN, 0, false);
860 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
861 u16 vid_begin, u16 vid_end,
862 bool is_member, bool untagged)
864 int size = vid_end - vid_begin + 1;
867 MLXSW_REG_ZERO(spvm, payload);
868 mlxsw_reg_spvm_local_port_set(payload, local_port);
869 mlxsw_reg_spvm_num_rec_set(payload, size);
871 for (i = 0; i < size; i++) {
872 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
873 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
874 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
875 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
879 /* SPAFT - Switch Port Acceptable Frame Types
880 * ------------------------------------------
881 * The Switch Port Acceptable Frame Types register configures the frame
882 * admittance of the port.
884 #define MLXSW_REG_SPAFT_ID 0x2010
885 #define MLXSW_REG_SPAFT_LEN 0x08
887 static const struct mlxsw_reg_info mlxsw_reg_spaft = {
888 .id = MLXSW_REG_SPAFT_ID,
889 .len = MLXSW_REG_SPAFT_LEN,
892 /* reg_spaft_local_port
896 * Note: CPU port is not supported (all tag types are allowed).
898 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
900 /* reg_spaft_sub_port
901 * Virtual port within the physical port.
902 * Should be set to 0 when virtual ports are not enabled on the port.
905 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
907 /* reg_spaft_allow_untagged
908 * When set, untagged frames on the ingress are allowed (default).
911 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
913 /* reg_spaft_allow_prio_tagged
914 * When set, priority tagged frames on the ingress are allowed (default).
917 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
919 /* reg_spaft_allow_tagged
920 * When set, tagged frames on the ingress are allowed (default).
923 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
925 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
928 MLXSW_REG_ZERO(spaft, payload);
929 mlxsw_reg_spaft_local_port_set(payload, local_port);
930 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
931 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
932 mlxsw_reg_spaft_allow_tagged_set(payload, true);
935 /* SFGC - Switch Flooding Group Configuration
936 * ------------------------------------------
937 * The following register controls the association of flooding tables and MIDs
938 * to packet types used for flooding.
940 #define MLXSW_REG_SFGC_ID 0x2011
941 #define MLXSW_REG_SFGC_LEN 0x10
943 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
944 .id = MLXSW_REG_SFGC_ID,
945 .len = MLXSW_REG_SFGC_LEN,
948 enum mlxsw_reg_sfgc_type {
949 MLXSW_REG_SFGC_TYPE_BROADCAST,
950 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
951 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
952 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
953 MLXSW_REG_SFGC_TYPE_RESERVED,
954 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
955 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
956 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
957 MLXSW_REG_SFGC_TYPE_MAX,
961 * The traffic type to reach the flooding table.
964 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
966 enum mlxsw_reg_sfgc_bridge_type {
967 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
968 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
971 /* reg_sfgc_bridge_type
974 * Note: SwitchX-2 only supports 802.1Q mode.
976 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
978 enum mlxsw_flood_table_type {
979 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
980 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
981 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
982 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
983 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
986 /* reg_sfgc_table_type
987 * See mlxsw_flood_table_type
990 * Note: FID offset and FID types are not supported in SwitchX-2.
992 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
994 /* reg_sfgc_flood_table
995 * Flooding table index to associate with the specific type on the specific
999 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1002 * The multicast ID for the swid. Not supported for Spectrum
1005 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1007 /* reg_sfgc_counter_set_type
1008 * Counter Set Type for flow counters.
1011 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1013 /* reg_sfgc_counter_index
1014 * Counter Index for flow counters.
1017 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1020 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1021 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1022 enum mlxsw_flood_table_type table_type,
1023 unsigned int flood_table)
1025 MLXSW_REG_ZERO(sfgc, payload);
1026 mlxsw_reg_sfgc_type_set(payload, type);
1027 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1028 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1029 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1030 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1033 /* SFTR - Switch Flooding Table Register
1034 * -------------------------------------
1035 * The switch flooding table is used for flooding packet replication. The table
1036 * defines a bit mask of ports for packet replication.
1038 #define MLXSW_REG_SFTR_ID 0x2012
1039 #define MLXSW_REG_SFTR_LEN 0x420
1041 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1042 .id = MLXSW_REG_SFTR_ID,
1043 .len = MLXSW_REG_SFTR_LEN,
1047 * Switch partition ID with which to associate the port.
1050 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1052 /* reg_sftr_flood_table
1053 * Flooding table index to associate with the specific type on the specific
1057 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1060 * Index. Used as an index into the Flooding Table in case the table is
1061 * configured to use VID / FID or FID Offset.
1064 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1066 /* reg_sftr_table_type
1067 * See mlxsw_flood_table_type
1070 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1073 * Range of entries to update
1076 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1079 * Local port membership (1 bit per port).
1082 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1084 /* reg_sftr_cpu_port_mask
1085 * CPU port mask (1 bit per port).
1088 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1090 static inline void mlxsw_reg_sftr_pack(char *payload,
1091 unsigned int flood_table,
1093 enum mlxsw_flood_table_type table_type,
1094 unsigned int range, u8 port, bool set)
1096 MLXSW_REG_ZERO(sftr, payload);
1097 mlxsw_reg_sftr_swid_set(payload, 0);
1098 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1099 mlxsw_reg_sftr_index_set(payload, index);
1100 mlxsw_reg_sftr_table_type_set(payload, table_type);
1101 mlxsw_reg_sftr_range_set(payload, range);
1102 mlxsw_reg_sftr_port_set(payload, port, set);
1103 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1106 /* SFDF - Switch Filtering DB Flush
1107 * --------------------------------
1108 * The switch filtering DB flush register is used to flush the FDB.
1109 * Note that FDB notifications are flushed as well.
1111 #define MLXSW_REG_SFDF_ID 0x2013
1112 #define MLXSW_REG_SFDF_LEN 0x14
1114 static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1115 .id = MLXSW_REG_SFDF_ID,
1116 .len = MLXSW_REG_SFDF_LEN,
1120 * Switch partition ID.
1123 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1125 enum mlxsw_reg_sfdf_flush_type {
1126 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1127 MLXSW_REG_SFDF_FLUSH_PER_FID,
1128 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1129 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1130 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1131 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1134 /* reg_sfdf_flush_type
1136 * 0 - All SWID dynamic entries are flushed.
1137 * 1 - All FID dynamic entries are flushed.
1138 * 2 - All dynamic entries pointing to port are flushed.
1139 * 3 - All FID dynamic entries pointing to port are flushed.
1140 * 4 - All dynamic entries pointing to LAG are flushed.
1141 * 5 - All FID dynamic entries pointing to LAG are flushed.
1144 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1146 /* reg_sfdf_flush_static
1148 * 0 - Flush only dynamic entries.
1149 * 1 - Flush both dynamic and static entries.
1152 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1154 static inline void mlxsw_reg_sfdf_pack(char *payload,
1155 enum mlxsw_reg_sfdf_flush_type type)
1157 MLXSW_REG_ZERO(sfdf, payload);
1158 mlxsw_reg_sfdf_flush_type_set(payload, type);
1159 mlxsw_reg_sfdf_flush_static_set(payload, true);
1166 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1168 /* reg_sfdf_system_port
1172 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1174 /* reg_sfdf_port_fid_system_port
1175 * Port to flush, pointed to by FID.
1178 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1184 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1186 /* reg_sfdf_lag_fid_lag_id
1187 * LAG ID to flush, pointed to by FID.
1190 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1192 /* SLDR - Switch LAG Descriptor Register
1193 * -----------------------------------------
1194 * The switch LAG descriptor register is populated by LAG descriptors.
1195 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1198 #define MLXSW_REG_SLDR_ID 0x2014
1199 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1201 static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1202 .id = MLXSW_REG_SLDR_ID,
1203 .len = MLXSW_REG_SLDR_LEN,
1206 enum mlxsw_reg_sldr_op {
1207 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1208 MLXSW_REG_SLDR_OP_LAG_CREATE,
1209 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1210 /* Ports that appear in the list have the Distributor enabled */
1211 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1212 /* Removes ports from the disributor list */
1213 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1220 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1223 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1226 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1228 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1230 MLXSW_REG_ZERO(sldr, payload);
1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1235 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1237 MLXSW_REG_ZERO(sldr, payload);
1238 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1239 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1242 /* reg_sldr_num_ports
1243 * The number of member ports of the LAG.
1244 * Reserved for Create / Destroy operations
1245 * For Add / Remove operations - indicates the number of ports in the list.
1248 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1250 /* reg_sldr_system_port
1254 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1256 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1259 MLXSW_REG_ZERO(sldr, payload);
1260 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1261 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1262 mlxsw_reg_sldr_num_ports_set(payload, 1);
1263 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1266 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1269 MLXSW_REG_ZERO(sldr, payload);
1270 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1271 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1272 mlxsw_reg_sldr_num_ports_set(payload, 1);
1273 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1276 /* SLCR - Switch LAG Configuration 2 Register
1277 * -------------------------------------------
1278 * The Switch LAG Configuration register is used for configuring the
1279 * LAG properties of the switch.
1281 #define MLXSW_REG_SLCR_ID 0x2015
1282 #define MLXSW_REG_SLCR_LEN 0x10
1284 static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1285 .id = MLXSW_REG_SLCR_ID,
1286 .len = MLXSW_REG_SLCR_LEN,
1289 enum mlxsw_reg_slcr_pp {
1290 /* Global Configuration (for all ports) */
1291 MLXSW_REG_SLCR_PP_GLOBAL,
1292 /* Per port configuration, based on local_port field */
1293 MLXSW_REG_SLCR_PP_PER_PORT,
1297 * Per Port Configuration
1298 * Note: Reading at Global mode results in reading port 1 configuration.
1301 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1303 /* reg_slcr_local_port
1305 * Supported from CPU port
1306 * Not supported from router port
1307 * Reserved when pp = Global Configuration
1310 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1312 enum mlxsw_reg_slcr_type {
1313 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1314 MLXSW_REG_SLCR_TYPE_XOR,
1315 MLXSW_REG_SLCR_TYPE_RANDOM,
1322 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1325 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1326 /* SMAC - for IPv4 and IPv6 packets */
1327 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1328 /* SMAC - for non-IP packets */
1329 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1330 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1331 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1332 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1333 /* DMAC - for IPv4 and IPv6 packets */
1334 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1335 /* DMAC - for non-IP packets */
1336 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1337 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1338 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1339 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1340 /* Ethertype - for IPv4 and IPv6 packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1342 /* Ethertype - for non-IP packets */
1343 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1344 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1345 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1346 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1347 /* VLAN ID - for IPv4 and IPv6 packets */
1348 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1349 /* VLAN ID - for non-IP packets */
1350 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1351 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1352 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1353 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1354 /* Source IP address (can be IPv4 or IPv6) */
1355 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1356 /* Destination IP address (can be IPv4 or IPv6) */
1357 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1358 /* TCP/UDP source port */
1359 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1360 /* TCP/UDP destination port*/
1361 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1362 /* IPv4 Protocol/IPv6 Next Header */
1363 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1364 /* IPv6 Flow label */
1365 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1366 /* SID - FCoE source ID */
1367 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1368 /* DID - FCoE destination ID */
1369 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1370 /* OXID - FCoE originator exchange ID */
1371 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1372 /* Destination QP number - for RoCE packets */
1373 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1375 /* reg_slcr_lag_hash
1376 * LAG hashing configuration. This is a bitmask, in which each set
1377 * bit includes the corresponding item in the LAG hash calculation.
1378 * The default lag_hash contains SMAC, DMAC, VLANID and
1379 * Ethertype (for all packet types).
1382 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1384 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1386 MLXSW_REG_ZERO(slcr, payload);
1387 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1388 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1389 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1392 /* SLCOR - Switch LAG Collector Register
1393 * -------------------------------------
1394 * The Switch LAG Collector register controls the Local Port membership
1395 * in a LAG and enablement of the collector.
1397 #define MLXSW_REG_SLCOR_ID 0x2016
1398 #define MLXSW_REG_SLCOR_LEN 0x10
1400 static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1401 .id = MLXSW_REG_SLCOR_ID,
1402 .len = MLXSW_REG_SLCOR_LEN,
1405 enum mlxsw_reg_slcor_col {
1406 /* Port is added with collector disabled */
1407 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1408 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1409 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1410 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1414 * Collector configuration
1417 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1419 /* reg_slcor_local_port
1421 * Not supported for CPU port
1424 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1427 * LAG Identifier. Index into the LAG descriptor table.
1430 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1432 /* reg_slcor_port_index
1433 * Port index in the LAG list. Only valid on Add Port to LAG col.
1434 * Valid range is from 0 to cap_max_lag_members-1
1437 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1439 static inline void mlxsw_reg_slcor_pack(char *payload,
1440 u8 local_port, u16 lag_id,
1441 enum mlxsw_reg_slcor_col col)
1443 MLXSW_REG_ZERO(slcor, payload);
1444 mlxsw_reg_slcor_col_set(payload, col);
1445 mlxsw_reg_slcor_local_port_set(payload, local_port);
1446 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1449 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1450 u8 local_port, u16 lag_id,
1453 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1454 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1455 mlxsw_reg_slcor_port_index_set(payload, port_index);
1458 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1459 u8 local_port, u16 lag_id)
1461 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1462 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1465 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1472 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1479 /* SPMLR - Switch Port MAC Learning Register
1480 * -----------------------------------------
1481 * Controls the Switch MAC learning policy per port.
1483 #define MLXSW_REG_SPMLR_ID 0x2018
1484 #define MLXSW_REG_SPMLR_LEN 0x8
1486 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1487 .id = MLXSW_REG_SPMLR_ID,
1488 .len = MLXSW_REG_SPMLR_LEN,
1491 /* reg_spmlr_local_port
1492 * Local port number.
1495 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1497 /* reg_spmlr_sub_port
1498 * Virtual port within the physical port.
1499 * Should be set to 0 when virtual ports are not enabled on the port.
1502 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1504 enum mlxsw_reg_spmlr_learn_mode {
1505 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1506 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1507 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1510 /* reg_spmlr_learn_mode
1511 * Learning mode on the port.
1512 * 0 - Learning disabled.
1513 * 2 - Learning enabled.
1514 * 3 - Security mode.
1516 * In security mode the switch does not learn MACs on the port, but uses the
1517 * SMAC to see if it exists on another ingress port. If so, the packet is
1518 * classified as a bad packet and is discarded unless the software registers
1519 * to receive port security error packets usign HPKT.
1521 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1523 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1524 enum mlxsw_reg_spmlr_learn_mode mode)
1526 MLXSW_REG_ZERO(spmlr, payload);
1527 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1528 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1529 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1532 /* SVFA - Switch VID to FID Allocation Register
1533 * --------------------------------------------
1534 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1535 * virtualized ports.
1537 #define MLXSW_REG_SVFA_ID 0x201C
1538 #define MLXSW_REG_SVFA_LEN 0x10
1540 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1541 .id = MLXSW_REG_SVFA_ID,
1542 .len = MLXSW_REG_SVFA_LEN,
1546 * Switch partition ID.
1549 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1551 /* reg_svfa_local_port
1552 * Local port number.
1555 * Note: Reserved for 802.1Q FIDs.
1557 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1559 enum mlxsw_reg_svfa_mt {
1560 MLXSW_REG_SVFA_MT_VID_TO_FID,
1561 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1564 /* reg_svfa_mapping_table
1567 * 1 - {Port, VID} to FID
1570 * Note: Reserved for SwitchX-2.
1572 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1579 * Note: Reserved for SwitchX-2.
1581 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1587 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1593 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1595 /* reg_svfa_counter_set_type
1596 * Counter set type for flow counters.
1599 * Note: Reserved for SwitchX-2.
1601 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1603 /* reg_svfa_counter_index
1604 * Counter index for flow counters.
1607 * Note: Reserved for SwitchX-2.
1609 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1611 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1612 enum mlxsw_reg_svfa_mt mt, bool valid,
1615 MLXSW_REG_ZERO(svfa, payload);
1616 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1617 mlxsw_reg_svfa_swid_set(payload, 0);
1618 mlxsw_reg_svfa_local_port_set(payload, local_port);
1619 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1620 mlxsw_reg_svfa_v_set(payload, valid);
1621 mlxsw_reg_svfa_fid_set(payload, fid);
1622 mlxsw_reg_svfa_vid_set(payload, vid);
1625 /* SVPE - Switch Virtual-Port Enabling Register
1626 * --------------------------------------------
1627 * Enables port virtualization.
1629 #define MLXSW_REG_SVPE_ID 0x201E
1630 #define MLXSW_REG_SVPE_LEN 0x4
1632 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1633 .id = MLXSW_REG_SVPE_ID,
1634 .len = MLXSW_REG_SVPE_LEN,
1637 /* reg_svpe_local_port
1641 * Note: CPU port is not supported (uses VLAN mode only).
1643 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1646 * Virtual port enable.
1647 * 0 - Disable, VLAN mode (VID to FID).
1648 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1651 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1653 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1656 MLXSW_REG_ZERO(svpe, payload);
1657 mlxsw_reg_svpe_local_port_set(payload, local_port);
1658 mlxsw_reg_svpe_vp_en_set(payload, enable);
1661 /* SFMR - Switch FID Management Register
1662 * -------------------------------------
1663 * Creates and configures FIDs.
1665 #define MLXSW_REG_SFMR_ID 0x201F
1666 #define MLXSW_REG_SFMR_LEN 0x18
1668 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1669 .id = MLXSW_REG_SFMR_ID,
1670 .len = MLXSW_REG_SFMR_LEN,
1673 enum mlxsw_reg_sfmr_op {
1674 MLXSW_REG_SFMR_OP_CREATE_FID,
1675 MLXSW_REG_SFMR_OP_DESTROY_FID,
1680 * 0 - Create or edit FID.
1684 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1690 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1692 /* reg_sfmr_fid_offset
1694 * Used to point into the flooding table selected by SFGC register if
1695 * the table is of type FID-Offset. Otherwise, this field is reserved.
1698 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1701 * Valid Tunnel Flood Pointer.
1702 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1705 * Note: Reserved for 802.1Q FIDs.
1707 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1709 /* reg_sfmr_nve_tunnel_flood_ptr
1710 * Underlay Flooding and BC Pointer.
1711 * Used as a pointer to the first entry of the group based link lists of
1712 * flooding or BC entries (for NVE tunnels).
1715 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1719 * If not set, then vni is reserved.
1722 * Note: Reserved for 802.1Q FIDs.
1724 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1727 * Virtual Network Identifier.
1730 * Note: A given VNI can only be assigned to one FID.
1732 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1734 static inline void mlxsw_reg_sfmr_pack(char *payload,
1735 enum mlxsw_reg_sfmr_op op, u16 fid,
1738 MLXSW_REG_ZERO(sfmr, payload);
1739 mlxsw_reg_sfmr_op_set(payload, op);
1740 mlxsw_reg_sfmr_fid_set(payload, fid);
1741 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1742 mlxsw_reg_sfmr_vtfp_set(payload, false);
1743 mlxsw_reg_sfmr_vv_set(payload, false);
1746 /* SPVMLR - Switch Port VLAN MAC Learning Register
1747 * -----------------------------------------------
1748 * Controls the switch MAC learning policy per {Port, VID}.
1750 #define MLXSW_REG_SPVMLR_ID 0x2020
1751 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1752 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1753 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1754 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1755 MLXSW_REG_SPVMLR_REC_LEN * \
1756 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1758 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1759 .id = MLXSW_REG_SPVMLR_ID,
1760 .len = MLXSW_REG_SPVMLR_LEN,
1763 /* reg_spvmlr_local_port
1764 * Local ingress port.
1767 * Note: CPU port is not supported.
1769 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1771 /* reg_spvmlr_num_rec
1772 * Number of records to update.
1775 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1777 /* reg_spvmlr_rec_learn_enable
1778 * 0 - Disable learning for {Port, VID}.
1779 * 1 - Enable learning for {Port, VID}.
1782 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1783 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1785 /* reg_spvmlr_rec_vid
1786 * VLAN ID to be added/removed from port or for querying.
1789 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1790 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1792 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1793 u16 vid_begin, u16 vid_end,
1796 int num_rec = vid_end - vid_begin + 1;
1799 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1801 MLXSW_REG_ZERO(spvmlr, payload);
1802 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1803 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1805 for (i = 0; i < num_rec; i++) {
1806 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1807 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1811 /* QTCT - QoS Switch Traffic Class Table
1812 * -------------------------------------
1813 * Configures the mapping between the packet switch priority and the
1814 * traffic class on the transmit port.
1816 #define MLXSW_REG_QTCT_ID 0x400A
1817 #define MLXSW_REG_QTCT_LEN 0x08
1819 static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1820 .id = MLXSW_REG_QTCT_ID,
1821 .len = MLXSW_REG_QTCT_LEN,
1824 /* reg_qtct_local_port
1825 * Local port number.
1828 * Note: CPU port is not supported.
1830 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1832 /* reg_qtct_sub_port
1833 * Virtual port within the physical port.
1834 * Should be set to 0 when virtual ports are not enabled on the port.
1837 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1839 /* reg_qtct_switch_prio
1843 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1848 * switch_prio 0 : tclass 1
1849 * switch_prio 1 : tclass 0
1850 * switch_prio i : tclass i, for i > 1
1853 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1855 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1856 u8 switch_prio, u8 tclass)
1858 MLXSW_REG_ZERO(qtct, payload);
1859 mlxsw_reg_qtct_local_port_set(payload, local_port);
1860 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1861 mlxsw_reg_qtct_tclass_set(payload, tclass);
1864 /* QEEC - QoS ETS Element Configuration Register
1865 * ---------------------------------------------
1866 * Configures the ETS elements.
1868 #define MLXSW_REG_QEEC_ID 0x400D
1869 #define MLXSW_REG_QEEC_LEN 0x1C
1871 static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1872 .id = MLXSW_REG_QEEC_ID,
1873 .len = MLXSW_REG_QEEC_LEN,
1876 /* reg_qeec_local_port
1877 * Local port number.
1880 * Note: CPU port is supported.
1882 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1884 enum mlxsw_reg_qeec_hr {
1885 MLXSW_REG_QEEC_HIERARCY_PORT,
1886 MLXSW_REG_QEEC_HIERARCY_GROUP,
1887 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1888 MLXSW_REG_QEEC_HIERARCY_TC,
1891 /* reg_qeec_element_hierarchy
1898 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1900 /* reg_qeec_element_index
1901 * The index of the element in the hierarchy.
1904 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1906 /* reg_qeec_next_element_index
1907 * The index of the next (lower) element in the hierarchy.
1910 * Note: Reserved for element_hierarchy 0.
1912 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1915 MLXSW_REG_QEEC_BYTES_MODE,
1916 MLXSW_REG_QEEC_PACKETS_MODE,
1920 * Packets or bytes mode.
1925 * Note: Used for max shaper configuration. For Spectrum, packets mode
1926 * is supported only for traffic classes of CPU port.
1928 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1931 * Max shaper configuration enable. Enables configuration of the max
1932 * shaper on this ETS element.
1937 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1939 /* A large max rate will disable the max shaper. */
1940 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
1942 /* reg_qeec_max_shaper_rate
1943 * Max shaper information rate.
1944 * For CPU port, can only be configured for port hierarchy.
1945 * When in bytes mode, value is specified in units of 1000bps.
1948 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1951 * DWRR configuration enable. Enables configuration of the dwrr and
1957 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1960 * Transmission selection algorithm to use on the link going down from
1962 * 0 - Strict priority
1966 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1968 /* reg_qeec_dwrr_weight
1969 * DWRR weight on the link going down from the ETS element. The
1970 * percentage of bandwidth guaranteed to an ETS element within
1971 * its hierarchy. The sum of all weights across all ETS elements
1972 * within one hierarchy should be equal to 100. Reserved when
1973 * transmission selection algorithm is strict priority.
1976 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1978 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1979 enum mlxsw_reg_qeec_hr hr, u8 index,
1982 MLXSW_REG_ZERO(qeec, payload);
1983 mlxsw_reg_qeec_local_port_set(payload, local_port);
1984 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1985 mlxsw_reg_qeec_element_index_set(payload, index);
1986 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1989 /* PMLP - Ports Module to Local Port Register
1990 * ------------------------------------------
1991 * Configures the assignment of modules to local ports.
1993 #define MLXSW_REG_PMLP_ID 0x5002
1994 #define MLXSW_REG_PMLP_LEN 0x40
1996 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1997 .id = MLXSW_REG_PMLP_ID,
1998 .len = MLXSW_REG_PMLP_LEN,
2002 * 0 - Tx value is used for both Tx and Rx.
2003 * 1 - Rx value is taken from a separte field.
2006 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2008 /* reg_pmlp_local_port
2009 * Local port number.
2012 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2015 * 0 - Unmap local port.
2016 * 1 - Lane 0 is used.
2017 * 2 - Lanes 0 and 1 are used.
2018 * 4 - Lanes 0, 1, 2 and 3 are used.
2021 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2027 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2030 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2033 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2036 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2040 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2042 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2044 MLXSW_REG_ZERO(pmlp, payload);
2045 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2048 /* PMTU - Port MTU Register
2049 * ------------------------
2050 * Configures and reports the port MTU.
2052 #define MLXSW_REG_PMTU_ID 0x5003
2053 #define MLXSW_REG_PMTU_LEN 0x10
2055 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2056 .id = MLXSW_REG_PMTU_ID,
2057 .len = MLXSW_REG_PMTU_LEN,
2060 /* reg_pmtu_local_port
2061 * Local port number.
2064 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2068 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2069 * reported, otherwise the minimum between the max_mtu of the different
2070 * types is reported.
2073 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2075 /* reg_pmtu_admin_mtu
2076 * MTU value to set port to. Must be smaller or equal to max_mtu.
2077 * Note: If port type is Infiniband, then port must be disabled, when its
2081 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2083 /* reg_pmtu_oper_mtu
2084 * The actual MTU configured on the port. Packets exceeding this size
2086 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2087 * oper_mtu might be smaller than admin_mtu.
2090 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2092 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2095 MLXSW_REG_ZERO(pmtu, payload);
2096 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2097 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2098 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2099 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2102 /* PTYS - Port Type and Speed Register
2103 * -----------------------------------
2104 * Configures and reports the port speed type.
2106 * Note: When set while the link is up, the changes will not take effect
2107 * until the port transitions from down to up state.
2109 #define MLXSW_REG_PTYS_ID 0x5004
2110 #define MLXSW_REG_PTYS_LEN 0x40
2112 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2113 .id = MLXSW_REG_PTYS_ID,
2114 .len = MLXSW_REG_PTYS_LEN,
2117 /* reg_ptys_local_port
2118 * Local port number.
2121 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2123 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2125 /* reg_ptys_proto_mask
2126 * Protocol mask. Indicates which protocol is used.
2128 * 1 - Fibre Channel.
2132 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2134 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2135 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2136 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2137 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2138 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2139 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2140 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2141 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2142 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2144 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2145 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2146 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2147 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2148 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2149 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2150 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2151 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2152 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2153 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2154 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2155 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2156 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2157 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2158 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2159 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2160 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2162 /* reg_ptys_eth_proto_cap
2163 * Ethernet port supported speeds and protocols.
2166 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2168 /* reg_ptys_eth_proto_admin
2169 * Speed and protocol to set port to.
2172 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2174 /* reg_ptys_eth_proto_oper
2175 * The current speed and protocol configured for the port.
2178 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2180 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2183 MLXSW_REG_ZERO(ptys, payload);
2184 mlxsw_reg_ptys_local_port_set(payload, local_port);
2185 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2186 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2189 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2190 u32 *p_eth_proto_adm,
2191 u32 *p_eth_proto_oper)
2193 if (p_eth_proto_cap)
2194 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2195 if (p_eth_proto_adm)
2196 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2197 if (p_eth_proto_oper)
2198 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2201 /* PPAD - Port Physical Address Register
2202 * -------------------------------------
2203 * The PPAD register configures the per port physical MAC address.
2205 #define MLXSW_REG_PPAD_ID 0x5005
2206 #define MLXSW_REG_PPAD_LEN 0x10
2208 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2209 .id = MLXSW_REG_PPAD_ID,
2210 .len = MLXSW_REG_PPAD_LEN,
2213 /* reg_ppad_single_base_mac
2214 * 0: base_mac, local port should be 0 and mac[7:0] is
2215 * reserved. HW will set incremental
2216 * 1: single_mac - mac of the local_port
2219 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2221 /* reg_ppad_local_port
2222 * port number, if single_base_mac = 0 then local_port is reserved
2225 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2228 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2229 * If single_base_mac = 1 - the per port MAC address
2232 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2234 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2237 MLXSW_REG_ZERO(ppad, payload);
2238 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2239 mlxsw_reg_ppad_local_port_set(payload, local_port);
2242 /* PAOS - Ports Administrative and Operational Status Register
2243 * -----------------------------------------------------------
2244 * Configures and retrieves per port administrative and operational status.
2246 #define MLXSW_REG_PAOS_ID 0x5006
2247 #define MLXSW_REG_PAOS_LEN 0x10
2249 static const struct mlxsw_reg_info mlxsw_reg_paos = {
2250 .id = MLXSW_REG_PAOS_ID,
2251 .len = MLXSW_REG_PAOS_LEN,
2255 * Switch partition ID with which to associate the port.
2256 * Note: while external ports uses unique local port numbers (and thus swid is
2257 * redundant), router ports use the same local port number where swid is the
2258 * only indication for the relevant port.
2261 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2263 /* reg_paos_local_port
2264 * Local port number.
2267 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2269 /* reg_paos_admin_status
2270 * Port administrative state (the desired state of the port):
2273 * 3 - Up once. This means that in case of link failure, the port won't go
2274 * into polling mode, but will wait to be re-enabled by software.
2275 * 4 - Disabled by system. Can only be set by hardware.
2278 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2280 /* reg_paos_oper_status
2281 * Port operational state (the current state):
2284 * 3 - Down by port failure. This means that the device will not let the
2285 * port up again until explicitly specified by software.
2288 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2291 * Admin state update enabled.
2294 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2297 * Event update enable. If this bit is set, event generation will be
2298 * updated based on the e field.
2301 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2304 * Event generation on operational state change:
2305 * 0 - Do not generate event.
2306 * 1 - Generate Event.
2307 * 2 - Generate Single Event.
2310 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2312 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2313 enum mlxsw_port_admin_status status)
2315 MLXSW_REG_ZERO(paos, payload);
2316 mlxsw_reg_paos_swid_set(payload, 0);
2317 mlxsw_reg_paos_local_port_set(payload, local_port);
2318 mlxsw_reg_paos_admin_status_set(payload, status);
2319 mlxsw_reg_paos_oper_status_set(payload, 0);
2320 mlxsw_reg_paos_ase_set(payload, 1);
2321 mlxsw_reg_paos_ee_set(payload, 1);
2322 mlxsw_reg_paos_e_set(payload, 1);
2325 /* PFCC - Ports Flow Control Configuration Register
2326 * ------------------------------------------------
2327 * Configures and retrieves the per port flow control configuration.
2329 #define MLXSW_REG_PFCC_ID 0x5007
2330 #define MLXSW_REG_PFCC_LEN 0x20
2332 static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2333 .id = MLXSW_REG_PFCC_ID,
2334 .len = MLXSW_REG_PFCC_LEN,
2337 /* reg_pfcc_local_port
2338 * Local port number.
2341 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2344 * Port number access type. Determines the way local_port is interpreted:
2345 * 0 - Local port number.
2346 * 1 - IB / label port number.
2349 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2352 * Send to higher layers capabilities:
2353 * 0 - No capability of sending Pause and PFC frames to higher layers.
2354 * 1 - Device has capability of sending Pause and PFC frames to higher
2358 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2361 * Send to higher layers operation:
2362 * 0 - Pause and PFC frames are handled by the port (default).
2363 * 1 - Pause and PFC frames are handled by the port and also sent to
2364 * higher layers. Only valid if shl_cap = 1.
2367 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2370 * Pause policy auto negotiation.
2371 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2372 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2373 * based on the auto-negotiation resolution.
2376 * Note: The auto-negotiation advertisement is set according to pptx and
2377 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2379 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2381 /* reg_pfcc_prio_mask_tx
2382 * Bit per priority indicating if Tx flow control policy should be
2383 * updated based on bit pfctx.
2386 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2388 /* reg_pfcc_prio_mask_rx
2389 * Bit per priority indicating if Rx flow control policy should be
2390 * updated based on bit pfcrx.
2393 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2396 * Admin Pause policy on Tx.
2397 * 0 - Never generate Pause frames (default).
2398 * 1 - Generate Pause frames according to Rx buffer threshold.
2401 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2404 * Active (operational) Pause policy on Tx.
2405 * 0 - Never generate Pause frames.
2406 * 1 - Generate Pause frames according to Rx buffer threshold.
2409 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2412 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2413 * 0 - Never generate priority Pause frames on the specified priority
2415 * 1 - Generate priority Pause frames according to Rx buffer threshold on
2416 * the specified priority.
2419 * Note: pfctx and pptx must be mutually exclusive.
2421 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2424 * Admin Pause policy on Rx.
2425 * 0 - Ignore received Pause frames (default).
2426 * 1 - Respect received Pause frames.
2429 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2432 * Active (operational) Pause policy on Rx.
2433 * 0 - Ignore received Pause frames.
2434 * 1 - Respect received Pause frames.
2437 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2440 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2441 * 0 - Ignore incoming priority Pause frames on the specified priority
2443 * 1 - Respect incoming priority Pause frames on the specified priority.
2446 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2448 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2450 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2452 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2453 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2454 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2455 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2458 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2460 MLXSW_REG_ZERO(pfcc, payload);
2461 mlxsw_reg_pfcc_local_port_set(payload, local_port);
2464 /* PPCNT - Ports Performance Counters Register
2465 * -------------------------------------------
2466 * The PPCNT register retrieves per port performance counters.
2468 #define MLXSW_REG_PPCNT_ID 0x5008
2469 #define MLXSW_REG_PPCNT_LEN 0x100
2471 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2472 .id = MLXSW_REG_PPCNT_ID,
2473 .len = MLXSW_REG_PPCNT_LEN,
2477 * For HCA: must be always 0.
2478 * Switch partition ID to associate port with.
2479 * Switch partitions are numbered from 0 to 7 inclusively.
2480 * Switch partition 254 indicates stacking ports.
2481 * Switch partition 255 indicates all switch partitions.
2482 * Only valid on Set() operation with local_port=255.
2485 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2487 /* reg_ppcnt_local_port
2488 * Local port number.
2489 * 255 indicates all ports on the device, and is only allowed
2490 * for Set() operation.
2493 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2496 * Port number access type:
2497 * 0 - Local port number
2498 * 1 - IB port number
2501 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2503 enum mlxsw_reg_ppcnt_grp {
2504 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2505 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2506 MLXSW_REG_PPCNT_TC_CNT = 0x11,
2510 * Performance counter group.
2511 * Group 63 indicates all groups. Only valid on Set() operation with
2513 * 0x0: IEEE 802.3 Counters
2514 * 0x1: RFC 2863 Counters
2515 * 0x2: RFC 2819 Counters
2516 * 0x3: RFC 3635 Counters
2517 * 0x5: Ethernet Extended Counters
2518 * 0x8: Link Level Retransmission Counters
2519 * 0x10: Per Priority Counters
2520 * 0x11: Per Traffic Class Counters
2521 * 0x12: Physical Layer Counters
2524 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2527 * Clear counters. Setting the clr bit will reset the counter value
2528 * for all counters in the counter group. This bit can be set
2529 * for both Set() and Get() operation.
2532 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2534 /* reg_ppcnt_prio_tc
2535 * Priority for counter set that support per priority, valid values: 0-7.
2536 * Traffic class for counter set that support per traffic class,
2537 * valid values: 0- cap_max_tclass-1 .
2538 * For HCA: cap_max_tclass is always 8.
2539 * Otherwise must be 0.
2542 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2544 /* Ethernet IEEE 802.3 Counter Group */
2546 /* reg_ppcnt_a_frames_transmitted_ok
2549 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2550 0x08 + 0x00, 0, 64);
2552 /* reg_ppcnt_a_frames_received_ok
2555 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2556 0x08 + 0x08, 0, 64);
2558 /* reg_ppcnt_a_frame_check_sequence_errors
2561 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2562 0x08 + 0x10, 0, 64);
2564 /* reg_ppcnt_a_alignment_errors
2567 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2568 0x08 + 0x18, 0, 64);
2570 /* reg_ppcnt_a_octets_transmitted_ok
2573 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2574 0x08 + 0x20, 0, 64);
2576 /* reg_ppcnt_a_octets_received_ok
2579 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2580 0x08 + 0x28, 0, 64);
2582 /* reg_ppcnt_a_multicast_frames_xmitted_ok
2585 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2586 0x08 + 0x30, 0, 64);
2588 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
2591 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2592 0x08 + 0x38, 0, 64);
2594 /* reg_ppcnt_a_multicast_frames_received_ok
2597 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2598 0x08 + 0x40, 0, 64);
2600 /* reg_ppcnt_a_broadcast_frames_received_ok
2603 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2604 0x08 + 0x48, 0, 64);
2606 /* reg_ppcnt_a_in_range_length_errors
2609 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2610 0x08 + 0x50, 0, 64);
2612 /* reg_ppcnt_a_out_of_range_length_field
2615 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2616 0x08 + 0x58, 0, 64);
2618 /* reg_ppcnt_a_frame_too_long_errors
2621 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2622 0x08 + 0x60, 0, 64);
2624 /* reg_ppcnt_a_symbol_error_during_carrier
2627 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2628 0x08 + 0x68, 0, 64);
2630 /* reg_ppcnt_a_mac_control_frames_transmitted
2633 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2634 0x08 + 0x70, 0, 64);
2636 /* reg_ppcnt_a_mac_control_frames_received
2639 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2640 0x08 + 0x78, 0, 64);
2642 /* reg_ppcnt_a_unsupported_opcodes_received
2645 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2646 0x08 + 0x80, 0, 64);
2648 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
2651 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2652 0x08 + 0x88, 0, 64);
2654 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2657 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2658 0x08 + 0x90, 0, 64);
2660 /* Ethernet Per Priority Group Counters */
2662 /* reg_ppcnt_rx_octets
2665 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2667 /* reg_ppcnt_rx_frames
2670 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2672 /* reg_ppcnt_tx_octets
2675 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2677 /* reg_ppcnt_tx_frames
2680 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2682 /* reg_ppcnt_rx_pause
2685 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2687 /* reg_ppcnt_rx_pause_duration
2690 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2692 /* reg_ppcnt_tx_pause
2695 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2697 /* reg_ppcnt_tx_pause_duration
2700 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2702 /* reg_ppcnt_rx_pause_transition
2705 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2707 /* Ethernet Per Traffic Group Counters */
2709 /* reg_ppcnt_tc_transmit_queue
2710 * Contains the transmit queue depth in cells of traffic class
2711 * selected by prio_tc and the port selected by local_port.
2712 * The field cannot be cleared.
2715 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64);
2717 /* reg_ppcnt_tc_no_buffer_discard_uc
2718 * The number of unicast packets dropped due to lack of shared
2722 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64);
2724 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2725 enum mlxsw_reg_ppcnt_grp grp,
2728 MLXSW_REG_ZERO(ppcnt, payload);
2729 mlxsw_reg_ppcnt_swid_set(payload, 0);
2730 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2731 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2732 mlxsw_reg_ppcnt_grp_set(payload, grp);
2733 mlxsw_reg_ppcnt_clr_set(payload, 0);
2734 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2737 /* PPTB - Port Prio To Buffer Register
2738 * -----------------------------------
2739 * Configures the switch priority to buffer table.
2741 #define MLXSW_REG_PPTB_ID 0x500B
2742 #define MLXSW_REG_PPTB_LEN 0x10
2744 static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2745 .id = MLXSW_REG_PPTB_ID,
2746 .len = MLXSW_REG_PPTB_LEN,
2750 MLXSW_REG_PPTB_MM_UM,
2751 MLXSW_REG_PPTB_MM_UNICAST,
2752 MLXSW_REG_PPTB_MM_MULTICAST,
2757 * 0 - Map both unicast and multicast packets to the same buffer.
2758 * 1 - Map only unicast packets.
2759 * 2 - Map only multicast packets.
2762 * Note: SwitchX-2 only supports the first option.
2764 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2766 /* reg_pptb_local_port
2767 * Local port number.
2770 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2773 * Enables the update of the untagged_buf field.
2776 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2779 * Enables the update of the prio_to_buff field.
2780 * Bit <i> is a flag for updating the mapping for switch priority <i>.
2783 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2785 /* reg_pptb_prio_to_buff
2786 * Mapping of switch priority <i> to one of the allocated receive port
2790 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2793 * Enables the update of the prio_to_buff field.
2794 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2797 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2799 /* reg_pptb_untagged_buff
2800 * Mapping of untagged frames to one of the allocated receive port buffers.
2803 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2804 * Spectrum, as it maps untagged packets based on the default switch priority.
2806 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2808 /* reg_pptb_prio_to_buff_msb
2809 * Mapping of switch priority <i+8> to one of the allocated receive port
2813 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
2815 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2817 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2819 MLXSW_REG_ZERO(pptb, payload);
2820 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2821 mlxsw_reg_pptb_local_port_set(payload, local_port);
2822 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2823 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2826 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
2829 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
2830 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
2833 /* PBMC - Port Buffer Management Control Register
2834 * ----------------------------------------------
2835 * The PBMC register configures and retrieves the port packet buffer
2836 * allocation for different Prios, and the Pause threshold management.
2838 #define MLXSW_REG_PBMC_ID 0x500C
2839 #define MLXSW_REG_PBMC_LEN 0x6C
2841 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2842 .id = MLXSW_REG_PBMC_ID,
2843 .len = MLXSW_REG_PBMC_LEN,
2846 /* reg_pbmc_local_port
2847 * Local port number.
2850 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2852 /* reg_pbmc_xoff_timer_value
2853 * When device generates a pause frame, it uses this value as the pause
2854 * timer (time for the peer port to pause in quota-512 bit time).
2857 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2859 /* reg_pbmc_xoff_refresh
2860 * The time before a new pause frame should be sent to refresh the pause RW
2861 * state. Using the same units as xoff_timer_value above (in quota-512 bit
2865 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2867 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2869 /* reg_pbmc_buf_lossy
2870 * The field indicates if the buffer is lossy.
2875 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2877 /* reg_pbmc_buf_epsb
2878 * Eligible for Port Shared buffer.
2879 * If epsb is set, packets assigned to buffer are allowed to insert the port
2881 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2884 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2886 /* reg_pbmc_buf_size
2887 * The part of the packet buffer array is allocated for the specific buffer.
2888 * Units are represented in cells.
2891 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2893 /* reg_pbmc_buf_xoff_threshold
2894 * Once the amount of data in the buffer goes above this value, device
2895 * starts sending PFC frames for all priorities associated with the
2896 * buffer. Units are represented in cells. Reserved in case of lossy
2900 * Note: In Spectrum, reserved for buffer[9].
2902 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2905 /* reg_pbmc_buf_xon_threshold
2906 * When the amount of data in the buffer goes below this value, device
2907 * stops sending PFC frames for the priorities associated with the
2908 * buffer. Units are represented in cells. Reserved in case of lossy
2912 * Note: In Spectrum, reserved for buffer[9].
2914 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2917 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2918 u16 xoff_timer_value, u16 xoff_refresh)
2920 MLXSW_REG_ZERO(pbmc, payload);
2921 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2922 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2923 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2926 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2930 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2931 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2932 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2935 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2936 int buf_index, u16 size,
2939 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2940 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2941 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2942 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2943 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2946 /* PSPA - Port Switch Partition Allocation
2947 * ---------------------------------------
2948 * Controls the association of a port with a switch partition and enables
2949 * configuring ports as stacking ports.
2951 #define MLXSW_REG_PSPA_ID 0x500D
2952 #define MLXSW_REG_PSPA_LEN 0x8
2954 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2955 .id = MLXSW_REG_PSPA_ID,
2956 .len = MLXSW_REG_PSPA_LEN,
2960 * Switch partition ID.
2963 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2965 /* reg_pspa_local_port
2966 * Local port number.
2969 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2971 /* reg_pspa_sub_port
2972 * Virtual port within the local port. Set to 0 when virtual ports are
2973 * disabled on the local port.
2976 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2978 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2980 MLXSW_REG_ZERO(pspa, payload);
2981 mlxsw_reg_pspa_swid_set(payload, swid);
2982 mlxsw_reg_pspa_local_port_set(payload, local_port);
2983 mlxsw_reg_pspa_sub_port_set(payload, 0);
2986 /* HTGT - Host Trap Group Table
2987 * ----------------------------
2988 * Configures the properties for forwarding to CPU.
2990 #define MLXSW_REG_HTGT_ID 0x7002
2991 #define MLXSW_REG_HTGT_LEN 0x100
2993 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2994 .id = MLXSW_REG_HTGT_ID,
2995 .len = MLXSW_REG_HTGT_LEN,
2999 * Switch partition ID.
3002 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3004 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
3010 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3012 enum mlxsw_reg_htgt_trap_group {
3013 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3014 MLXSW_REG_HTGT_TRAP_GROUP_RX,
3015 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3018 /* reg_htgt_trap_group
3019 * Trap group number. User defined number specifying which trap groups
3020 * should be forwarded to the CPU. The mapping between trap IDs and trap
3021 * groups is configured using HPKT register.
3024 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3027 MLXSW_REG_HTGT_POLICER_DISABLE,
3028 MLXSW_REG_HTGT_POLICER_ENABLE,
3032 * Enable policer ID specified using 'pid' field.
3035 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3038 * Policer ID for the trap group.
3041 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3043 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3045 /* reg_htgt_mirror_action
3046 * Mirror action to use.
3048 * 1 - Trap to CPU and mirror to a mirroring agent.
3049 * 2 - Mirror to a mirroring agent and do not trap to CPU.
3052 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3054 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3056 /* reg_htgt_mirroring_agent
3060 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3062 /* reg_htgt_priority
3063 * Trap group priority.
3064 * In case a packet matches multiple classification rules, the packet will
3065 * only be trapped once, based on the trap ID associated with the group (via
3066 * register HPKT) with the highest priority.
3067 * Supported values are 0-7, with 7 represnting the highest priority.
3070 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3071 * by the 'trap_group' field.
3073 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3075 /* reg_htgt_local_path_cpu_tclass
3076 * CPU ingress traffic class for the trap group.
3079 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3081 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
3082 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
3083 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
3085 /* reg_htgt_local_path_rdq
3086 * Receive descriptor queue (RDQ) to use for the trap group.
3089 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3091 static inline void mlxsw_reg_htgt_pack(char *payload,
3092 enum mlxsw_reg_htgt_trap_group group)
3096 MLXSW_REG_ZERO(htgt, payload);
3098 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3099 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3100 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3102 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3104 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3106 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3108 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3111 mlxsw_reg_htgt_swid_set(payload, swid);
3112 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3113 mlxsw_reg_htgt_trap_group_set(payload, group);
3114 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3115 mlxsw_reg_htgt_pid_set(payload, 0);
3116 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3117 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3118 mlxsw_reg_htgt_priority_set(payload, 0);
3119 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3120 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3123 /* HPKT - Host Packet Trap
3124 * -----------------------
3125 * Configures trap IDs inside trap groups.
3127 #define MLXSW_REG_HPKT_ID 0x7003
3128 #define MLXSW_REG_HPKT_LEN 0x10
3130 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3131 .id = MLXSW_REG_HPKT_ID,
3132 .len = MLXSW_REG_HPKT_LEN,
3136 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3137 MLXSW_REG_HPKT_ACK_REQUIRED,
3141 * Require acknowledgements from the host for events.
3142 * If set, then the device will wait for the event it sent to be acknowledged
3143 * by the host. This option is only relevant for event trap IDs.
3146 * Note: Currently not supported by firmware.
3148 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3150 enum mlxsw_reg_hpkt_action {
3151 MLXSW_REG_HPKT_ACTION_FORWARD,
3152 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3153 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3154 MLXSW_REG_HPKT_ACTION_DISCARD,
3155 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3156 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3160 * Action to perform on packet when trapped.
3161 * 0 - No action. Forward to CPU based on switching rules.
3162 * 1 - Trap to CPU (CPU receives sole copy).
3163 * 2 - Mirror to CPU (CPU receives a replica of the packet).
3165 * 4 - Soft discard (allow other traps to act on the packet).
3166 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3169 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3170 * addressed to the CPU.
3172 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3174 /* reg_hpkt_trap_group
3175 * Trap group to associate the trap with.
3178 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3184 * Note: A trap ID can only be associated with a single trap group. The device
3185 * will associate the trap ID with the last trap group configured.
3187 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3190 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3191 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3192 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3196 * Configure dedicated buffer resources for control packets.
3197 * 0 - Keep factory defaults.
3198 * 1 - Do not use control buffer for this trap ID.
3199 * 2 - Use control buffer for this trap ID.
3202 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3204 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3206 enum mlxsw_reg_htgt_trap_group trap_group;
3208 MLXSW_REG_ZERO(hpkt, payload);
3209 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3210 mlxsw_reg_hpkt_action_set(payload, action);
3212 case MLXSW_TRAP_ID_ETHEMAD:
3213 case MLXSW_TRAP_ID_PUDE:
3214 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3217 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3220 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3221 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3222 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3225 /* RGCR - Router General Configuration Register
3226 * --------------------------------------------
3227 * The register is used for setting up the router configuration.
3229 #define MLXSW_REG_RGCR_ID 0x8001
3230 #define MLXSW_REG_RGCR_LEN 0x28
3232 static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3233 .id = MLXSW_REG_RGCR_ID,
3234 .len = MLXSW_REG_RGCR_LEN,
3238 * IPv4 router enable.
3241 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3244 * IPv6 router enable.
3247 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3249 /* reg_rgcr_max_router_interfaces
3250 * Defines the maximum number of active router interfaces for all virtual
3254 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3257 * Update switch priority and packet color.
3258 * 0 - Preserve the value of Switch Priority and packet color.
3259 * 1 - Recalculate the value of Switch Priority and packet color.
3262 * Note: Not supported by SwitchX and SwitchX-2.
3264 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3267 * Indicates how to handle the pcp_rewrite_en value:
3268 * 0 - Preserve the value of pcp_rewrite_en.
3269 * 2 - Disable PCP rewrite.
3270 * 3 - Enable PCP rewrite.
3273 * Note: Not supported by SwitchX and SwitchX-2.
3275 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3277 /* reg_rgcr_activity_dis
3279 * 0 - Activity will be set when an entry is hit (default).
3280 * 1 - Activity will not be set when an entry is hit.
3282 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3284 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3286 * Bits 2:7 are reserved.
3289 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3291 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3293 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3295 MLXSW_REG_ZERO(rgcr, payload);
3296 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3299 /* RITR - Router Interface Table Register
3300 * --------------------------------------
3301 * The register is used to configure the router interface table.
3303 #define MLXSW_REG_RITR_ID 0x8002
3304 #define MLXSW_REG_RITR_LEN 0x40
3306 static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3307 .id = MLXSW_REG_RITR_ID,
3308 .len = MLXSW_REG_RITR_LEN,
3312 * Enables routing on the router interface.
3315 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3318 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3322 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3325 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3329 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3331 enum mlxsw_reg_ritr_if_type {
3332 MLXSW_REG_RITR_VLAN_IF,
3333 MLXSW_REG_RITR_FID_IF,
3334 MLXSW_REG_RITR_SP_IF,
3338 * Router interface type.
3339 * 0 - VLAN interface.
3340 * 1 - FID interface.
3341 * 2 - Sub-port interface.
3344 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3347 MLXSW_REG_RITR_RIF_CREATE,
3348 MLXSW_REG_RITR_RIF_DEL,
3353 * 0 - Create or edit RIF.
3355 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3356 * is not supported. An interface must be deleted and re-created in order
3357 * to update properties.
3360 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3363 * Router interface index. A pointer to the Router Interface Table.
3366 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3369 * IPv4 Forwarding Enable.
3370 * Enables routing of IPv4 traffic on the router interface. When disabled,
3371 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3372 * Not supported in SwitchX-2.
3375 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3378 * IPv6 Forwarding Enable.
3379 * Enables routing of IPv6 traffic on the router interface. When disabled,
3380 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3381 * Not supported in SwitchX-2.
3384 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3387 * Loop-back filter enable for unicast packets.
3388 * If the flag is set then loop-back filter for unicast packets is
3389 * implemented on the RIF. Multicast packets are always subject to
3390 * loop-back filtering.
3393 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
3395 /* reg_ritr_virtual_router
3396 * Virtual router ID associated with the router interface.
3399 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3402 * Router interface MTU.
3405 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3408 * Switch partition ID.
3411 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3414 * Router interface MAC address.
3415 * In Spectrum, all MAC addresses must have the same 38 MSBits.
3418 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3420 /* VLAN Interface */
3422 /* reg_ritr_vlan_if_vid
3426 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3430 /* reg_ritr_fid_if_fid
3431 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3432 * the vFID range are supported.
3435 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3437 static inline void mlxsw_reg_ritr_fid_set(char *payload,
3438 enum mlxsw_reg_ritr_if_type rif_type,
3441 if (rif_type == MLXSW_REG_RITR_FID_IF)
3442 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3444 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3447 /* Sub-port Interface */
3449 /* reg_ritr_sp_if_lag
3450 * LAG indication. When this bit is set the system_port field holds the
3454 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3456 /* reg_ritr_sp_system_port
3457 * Port unique indentifier. When lag bit is set, this field holds the
3458 * lag_id in bits 0:9.
3461 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3463 /* reg_ritr_sp_if_vid
3467 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3469 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3471 MLXSW_REG_ZERO(ritr, payload);
3472 mlxsw_reg_ritr_rif_set(payload, rif);
3475 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3476 u16 system_port, u16 vid)
3478 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3479 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3480 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3483 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3484 enum mlxsw_reg_ritr_if_type type,
3485 u16 rif, u16 mtu, const char *mac)
3487 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3489 MLXSW_REG_ZERO(ritr, payload);
3490 mlxsw_reg_ritr_enable_set(payload, enable);
3491 mlxsw_reg_ritr_ipv4_set(payload, 1);
3492 mlxsw_reg_ritr_type_set(payload, type);
3493 mlxsw_reg_ritr_op_set(payload, op);
3494 mlxsw_reg_ritr_rif_set(payload, rif);
3495 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3496 mlxsw_reg_ritr_lb_en_set(payload, 1);
3497 mlxsw_reg_ritr_mtu_set(payload, mtu);
3498 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3501 /* RATR - Router Adjacency Table Register
3502 * --------------------------------------
3503 * The RATR register is used to configure the Router Adjacency (next-hop)
3506 #define MLXSW_REG_RATR_ID 0x8008
3507 #define MLXSW_REG_RATR_LEN 0x2C
3509 static const struct mlxsw_reg_info mlxsw_reg_ratr = {
3510 .id = MLXSW_REG_RATR_ID,
3511 .len = MLXSW_REG_RATR_LEN,
3514 enum mlxsw_reg_ratr_op {
3516 MLXSW_REG_RATR_OP_QUERY_READ = 0,
3517 /* Read and clear activity */
3518 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
3519 /* Write Adjacency entry */
3520 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
3521 /* Write Adjacency entry only if the activity is cleared.
3522 * The write may not succeed if the activity is set. There is not
3523 * direct feedback if the write has succeeded or not, however
3524 * the get will reveal the actual entry (SW can compare the get
3525 * response to the set command).
3527 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
3531 * Note that Write operation may also be used for updating
3532 * counter_set_type and counter_index. In this case all other
3533 * fields must not be updated.
3536 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
3539 * Valid bit. Indicates if the adjacency entry is valid.
3540 * Note: the device may need some time before reusing an invalidated
3541 * entry. During this time the entry can not be reused. It is
3542 * recommended to use another entry before reusing an invalidated
3543 * entry (e.g. software can put it at the end of the list for
3544 * reusing). Trying to access an invalidated entry not yet cleared
3545 * by the device results with failure indicating "Try Again" status.
3546 * When valid is '0' then egress_router_interface,trap_action,
3547 * adjacency_parameters and counters are reserved
3550 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
3553 * Activity. Set for new entries. Set if a packet lookup has hit on
3554 * the specific entry. To clear the a bit, use "clear activity".
3557 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
3559 /* reg_ratr_adjacency_index_low
3560 * Bits 15:0 of index into the adjacency table.
3561 * For SwitchX and SwitchX-2, the adjacency table is linear and
3562 * used for adjacency entries only.
3563 * For Spectrum, the index is to the KVD linear.
3566 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
3568 /* reg_ratr_egress_router_interface
3569 * Range is 0 .. cap_max_router_interfaces - 1
3572 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
3574 enum mlxsw_reg_ratr_trap_action {
3575 MLXSW_REG_RATR_TRAP_ACTION_NOP,
3576 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
3577 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
3578 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
3579 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
3582 /* reg_ratr_trap_action
3583 * see mlxsw_reg_ratr_trap_action
3586 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
3588 enum mlxsw_reg_ratr_trap_id {
3589 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
3590 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
3593 /* reg_ratr_adjacency_index_high
3594 * Bits 23:16 of the adjacency_index.
3597 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
3600 * Trap ID to be reported to CPU.
3601 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
3602 * For trap_action of NOP, MIRROR and DISCARD_ERROR
3605 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
3607 /* reg_ratr_eth_destination_mac
3608 * MAC address of the destination next-hop.
3611 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
3614 mlxsw_reg_ratr_pack(char *payload,
3615 enum mlxsw_reg_ratr_op op, bool valid,
3616 u32 adjacency_index, u16 egress_rif)
3618 MLXSW_REG_ZERO(ratr, payload);
3619 mlxsw_reg_ratr_op_set(payload, op);
3620 mlxsw_reg_ratr_v_set(payload, valid);
3621 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
3622 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
3623 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
3626 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
3627 const char *dest_mac)
3629 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
3632 /* RALTA - Router Algorithmic LPM Tree Allocation Register
3633 * -------------------------------------------------------
3634 * RALTA is used to allocate the LPM trees of the SHSPM method.
3636 #define MLXSW_REG_RALTA_ID 0x8010
3637 #define MLXSW_REG_RALTA_LEN 0x04
3639 static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3640 .id = MLXSW_REG_RALTA_ID,
3641 .len = MLXSW_REG_RALTA_LEN,
3645 * opcode (valid for Write, must be 0 on Read)
3646 * 0 - allocate a tree
3647 * 1 - deallocate a tree
3650 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3652 enum mlxsw_reg_ralxx_protocol {
3653 MLXSW_REG_RALXX_PROTOCOL_IPV4,
3654 MLXSW_REG_RALXX_PROTOCOL_IPV6,
3657 /* reg_ralta_protocol
3659 * Deallocation opcode: Reserved.
3662 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3664 /* reg_ralta_tree_id
3665 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
3666 * the tree identifier (managed by software).
3667 * Note that tree_id 0 is allocated for a default-route tree.
3670 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3672 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3673 enum mlxsw_reg_ralxx_protocol protocol,
3676 MLXSW_REG_ZERO(ralta, payload);
3677 mlxsw_reg_ralta_op_set(payload, !alloc);
3678 mlxsw_reg_ralta_protocol_set(payload, protocol);
3679 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3682 /* RALST - Router Algorithmic LPM Structure Tree Register
3683 * ------------------------------------------------------
3684 * RALST is used to set and query the structure of an LPM tree.
3685 * The structure of the tree must be sorted as a sorted binary tree, while
3686 * each node is a bin that is tagged as the length of the prefixes the lookup
3687 * will refer to. Therefore, bin X refers to a set of entries with prefixes
3688 * of X bits to match with the destination address. The bin 0 indicates
3689 * the default action, when there is no match of any prefix.
3691 #define MLXSW_REG_RALST_ID 0x8011
3692 #define MLXSW_REG_RALST_LEN 0x104
3694 static const struct mlxsw_reg_info mlxsw_reg_ralst = {
3695 .id = MLXSW_REG_RALST_ID,
3696 .len = MLXSW_REG_RALST_LEN,
3699 /* reg_ralst_root_bin
3700 * The bin number of the root bin.
3701 * 0<root_bin=<(length of IP address)
3702 * For a default-route tree configure 0xff
3705 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
3707 /* reg_ralst_tree_id
3708 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3711 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
3713 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
3714 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
3715 #define MLXSW_REG_RALST_BIN_COUNT 128
3717 /* reg_ralst_left_child_bin
3718 * Holding the children of the bin according to the stored tree's structure.
3719 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3720 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3723 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
3725 /* reg_ralst_right_child_bin
3726 * Holding the children of the bin according to the stored tree's structure.
3727 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3728 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3731 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
3734 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
3736 MLXSW_REG_ZERO(ralst, payload);
3738 /* Initialize all bins to have no left or right child */
3739 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
3740 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
3742 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
3743 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
3746 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
3750 int bin_index = bin_number - 1;
3752 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
3753 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
3757 /* RALTB - Router Algorithmic LPM Tree Binding Register
3758 * ----------------------------------------------------
3759 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
3761 #define MLXSW_REG_RALTB_ID 0x8012
3762 #define MLXSW_REG_RALTB_LEN 0x04
3764 static const struct mlxsw_reg_info mlxsw_reg_raltb = {
3765 .id = MLXSW_REG_RALTB_ID,
3766 .len = MLXSW_REG_RALTB_LEN,
3769 /* reg_raltb_virtual_router
3771 * Range is 0..cap_max_virtual_routers-1
3774 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
3776 /* reg_raltb_protocol
3780 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
3782 /* reg_raltb_tree_id
3783 * Tree to be used for the {virtual_router, protocol}
3784 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3785 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
3788 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
3790 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
3791 enum mlxsw_reg_ralxx_protocol protocol,
3794 MLXSW_REG_ZERO(raltb, payload);
3795 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
3796 mlxsw_reg_raltb_protocol_set(payload, protocol);
3797 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
3800 /* RALUE - Router Algorithmic LPM Unicast Entry Register
3801 * -----------------------------------------------------
3802 * RALUE is used to configure and query LPM entries that serve
3803 * the Unicast protocols.
3805 #define MLXSW_REG_RALUE_ID 0x8013
3806 #define MLXSW_REG_RALUE_LEN 0x38
3808 static const struct mlxsw_reg_info mlxsw_reg_ralue = {
3809 .id = MLXSW_REG_RALUE_ID,
3810 .len = MLXSW_REG_RALUE_LEN,
3813 /* reg_ralue_protocol
3817 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
3819 enum mlxsw_reg_ralue_op {
3820 /* Read operation. If entry doesn't exist, the operation fails. */
3821 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
3822 /* Clear on read operation. Used to read entry and
3823 * clear Activity bit.
3825 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
3826 /* Write operation. Used to write a new entry to the table. All RW
3827 * fields are written for new entry. Activity bit is set
3830 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
3831 /* Update operation. Used to update an existing route entry and
3832 * only update the RW fields that are detailed in the field
3833 * op_u_mask. If entry doesn't exist, the operation fails.
3835 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
3836 /* Clear activity. The Activity bit (the field a) is cleared
3839 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
3840 /* Delete operation. Used to delete an existing entry. If entry
3841 * doesn't exist, the operation fails.
3843 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
3850 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
3853 * Activity. Set for new entries. Set if a packet lookup has hit on the
3854 * specific entry, only if the entry is a route. To clear the a bit, use
3855 * "clear activity" op.
3856 * Enabled by activity_dis in RGCR
3859 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
3861 /* reg_ralue_virtual_router
3863 * Range is 0..cap_max_virtual_routers-1
3866 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
3868 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
3869 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
3870 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
3872 /* reg_ralue_op_u_mask
3873 * opcode update mask.
3874 * On read operation, this field is reserved.
3875 * This field is valid for update opcode, otherwise - reserved.
3876 * This field is a bitmask of the fields that should be updated.
3879 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
3881 /* reg_ralue_prefix_len
3882 * Number of bits in the prefix of the LPM route.
3883 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
3884 * two entries in the physical HW table.
3887 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
3890 * The prefix of the route or of the marker that the object of the LPM
3891 * is compared with. The most significant bits of the dip are the prefix.
3892 * The list significant bits must be '0' if the prefix_len is smaller
3893 * than 128 for IPv6 or smaller than 32 for IPv4.
3894 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
3897 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
3899 enum mlxsw_reg_ralue_entry_type {
3900 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
3901 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
3902 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
3905 /* reg_ralue_entry_type
3907 * Note - for Marker entries, the action_type and action fields are reserved.
3910 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
3912 /* reg_ralue_bmp_len
3913 * The best match prefix length in the case that there is no match for
3915 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
3916 * Note for any update operation with entry_type modification this
3917 * field must be set.
3920 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
3922 enum mlxsw_reg_ralue_action_type {
3923 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
3924 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
3925 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
3928 /* reg_ralue_action_type
3930 * Indicates how the IP address is connected.
3931 * It can be connected to a local subnet through local_erif or can be
3932 * on a remote subnet connected through a next-hop router,
3933 * or transmitted to the CPU.
3934 * Reserved when entry_type = MARKER_ENTRY
3937 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
3939 enum mlxsw_reg_ralue_trap_action {
3940 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
3941 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
3942 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
3943 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
3944 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
3947 /* reg_ralue_trap_action
3949 * For IP2ME action, only NOP and MIRROR are possible.
3952 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
3954 /* reg_ralue_trap_id
3955 * Trap ID to be reported to CPU.
3956 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
3957 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
3960 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
3962 /* reg_ralue_adjacency_index
3963 * Points to the first entry of the group-based ECMP.
3964 * Only relevant in case of REMOTE action.
3967 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
3969 /* reg_ralue_ecmp_size
3970 * Amount of sequential entries starting
3971 * from the adjacency_index (the number of ECMPs).
3972 * The valid range is 1-64, 512, 1024, 2048 and 4096.
3973 * Reserved when trap_action is TRAP or DISCARD_ERROR.
3974 * Only relevant in case of REMOTE action.
3977 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
3979 /* reg_ralue_local_erif
3980 * Egress Router Interface.
3981 * Only relevant in case of LOCAL action.
3984 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
3987 * Valid bit for the tunnel_ptr field.
3988 * If valid = 0 then trap to CPU as IP2ME trap ID.
3989 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
3990 * decapsulation then tunnel decapsulation is done.
3991 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
3992 * decapsulation then trap as IP2ME trap ID.
3993 * Only relevant in case of IP2ME action.
3996 MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
3998 /* reg_ralue_tunnel_ptr
3999 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
4000 * For Spectrum, pointer to KVD Linear.
4001 * Only relevant in case of IP2ME action.
4004 MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
4006 static inline void mlxsw_reg_ralue_pack(char *payload,
4007 enum mlxsw_reg_ralxx_protocol protocol,
4008 enum mlxsw_reg_ralue_op op,
4009 u16 virtual_router, u8 prefix_len)
4011 MLXSW_REG_ZERO(ralue, payload);
4012 mlxsw_reg_ralue_protocol_set(payload, protocol);
4013 mlxsw_reg_ralue_op_set(payload, op);
4014 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
4015 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
4016 mlxsw_reg_ralue_entry_type_set(payload,
4017 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
4018 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
4021 static inline void mlxsw_reg_ralue_pack4(char *payload,
4022 enum mlxsw_reg_ralxx_protocol protocol,
4023 enum mlxsw_reg_ralue_op op,
4024 u16 virtual_router, u8 prefix_len,
4027 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
4028 mlxsw_reg_ralue_dip4_set(payload, dip);
4032 mlxsw_reg_ralue_act_remote_pack(char *payload,
4033 enum mlxsw_reg_ralue_trap_action trap_action,
4034 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
4036 mlxsw_reg_ralue_action_type_set(payload,
4037 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
4038 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4039 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4040 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
4041 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
4045 mlxsw_reg_ralue_act_local_pack(char *payload,
4046 enum mlxsw_reg_ralue_trap_action trap_action,
4047 u16 trap_id, u16 local_erif)
4049 mlxsw_reg_ralue_action_type_set(payload,
4050 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
4051 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4052 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4053 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
4057 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
4059 mlxsw_reg_ralue_action_type_set(payload,
4060 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
4063 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
4064 * ----------------------------------------------------------
4065 * The RAUHT register is used to configure and query the Unicast Host table in
4066 * devices that implement the Algorithmic LPM.
4068 #define MLXSW_REG_RAUHT_ID 0x8014
4069 #define MLXSW_REG_RAUHT_LEN 0x74
4071 static const struct mlxsw_reg_info mlxsw_reg_rauht = {
4072 .id = MLXSW_REG_RAUHT_ID,
4073 .len = MLXSW_REG_RAUHT_LEN,
4076 enum mlxsw_reg_rauht_type {
4077 MLXSW_REG_RAUHT_TYPE_IPV4,
4078 MLXSW_REG_RAUHT_TYPE_IPV6,
4084 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
4086 enum mlxsw_reg_rauht_op {
4087 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
4088 /* Read operation */
4089 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
4090 /* Clear on read operation. Used to read entry and clear
4093 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
4094 /* Add. Used to write a new entry to the table. All R/W fields are
4095 * relevant for new entry. Activity bit is set for new entries.
4097 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
4098 /* Update action. Used to update an existing route entry and
4099 * only update the following fields:
4100 * trap_action, trap_id, mac, counter_set_type, counter_index
4102 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
4103 /* Clear activity. A bit is cleared for the entry. */
4104 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
4106 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
4107 /* Delete all host entries on a RIF. In this command, dip
4108 * field is reserved.
4115 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
4118 * Activity. Set for new entries. Set if a packet lookup has hit on
4119 * the specific entry.
4120 * To clear the a bit, use "clear activity" op.
4121 * Enabled by activity_dis in RGCR
4124 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
4130 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
4133 * Destination address.
4136 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
4138 enum mlxsw_reg_rauht_trap_action {
4139 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
4140 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
4141 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
4142 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
4143 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
4146 /* reg_rauht_trap_action
4149 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
4151 enum mlxsw_reg_rauht_trap_id {
4152 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
4153 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
4156 /* reg_rauht_trap_id
4157 * Trap ID to be reported to CPU.
4158 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
4159 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
4160 * trap_id is reserved.
4163 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
4165 /* reg_rauht_counter_set_type
4166 * Counter set type for flow counters
4169 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
4171 /* reg_rauht_counter_index
4172 * Counter index for flow counters
4175 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
4181 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
4183 static inline void mlxsw_reg_rauht_pack(char *payload,
4184 enum mlxsw_reg_rauht_op op, u16 rif,
4187 MLXSW_REG_ZERO(rauht, payload);
4188 mlxsw_reg_rauht_op_set(payload, op);
4189 mlxsw_reg_rauht_rif_set(payload, rif);
4190 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
4193 static inline void mlxsw_reg_rauht_pack4(char *payload,
4194 enum mlxsw_reg_rauht_op op, u16 rif,
4195 const char *mac, u32 dip)
4197 mlxsw_reg_rauht_pack(payload, op, rif, mac);
4198 mlxsw_reg_rauht_dip4_set(payload, dip);
4201 /* RALEU - Router Algorithmic LPM ECMP Update Register
4202 * ---------------------------------------------------
4203 * The register enables updating the ECMP section in the action for multiple
4204 * LPM Unicast entries in a single operation. The update is executed to
4205 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
4207 #define MLXSW_REG_RALEU_ID 0x8015
4208 #define MLXSW_REG_RALEU_LEN 0x28
4210 static const struct mlxsw_reg_info mlxsw_reg_raleu = {
4211 .id = MLXSW_REG_RALEU_ID,
4212 .len = MLXSW_REG_RALEU_LEN,
4215 /* reg_raleu_protocol
4219 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
4221 /* reg_raleu_virtual_router
4223 * Range is 0..cap_max_virtual_routers-1
4226 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
4228 /* reg_raleu_adjacency_index
4229 * Adjacency Index used for matching on the existing entries.
4232 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
4234 /* reg_raleu_ecmp_size
4235 * ECMP Size used for matching on the existing entries.
4238 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
4240 /* reg_raleu_new_adjacency_index
4241 * New Adjacency Index.
4244 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
4246 /* reg_raleu_new_ecmp_size
4250 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
4252 static inline void mlxsw_reg_raleu_pack(char *payload,
4253 enum mlxsw_reg_ralxx_protocol protocol,
4255 u32 adjacency_index, u16 ecmp_size,
4256 u32 new_adjacency_index,
4259 MLXSW_REG_ZERO(raleu, payload);
4260 mlxsw_reg_raleu_protocol_set(payload, protocol);
4261 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
4262 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
4263 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
4264 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
4265 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
4268 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
4269 * ----------------------------------------------------------------
4270 * The RAUHTD register allows dumping entries from the Router Unicast Host
4271 * Table. For a given session an entry is dumped no more than one time. The
4272 * first RAUHTD access after reset is a new session. A session ends when the
4273 * num_rec response is smaller than num_rec request or for IPv4 when the
4274 * num_entries is smaller than 4. The clear activity affect the current session
4275 * or the last session if a new session has not started.
4277 #define MLXSW_REG_RAUHTD_ID 0x8018
4278 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
4279 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
4280 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
4281 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
4282 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
4283 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
4285 static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
4286 .id = MLXSW_REG_RAUHTD_ID,
4287 .len = MLXSW_REG_RAUHTD_LEN,
4290 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
4291 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
4293 /* reg_rauhtd_filter_fields
4294 * if a bit is '0' then the relevant field is ignored and dump is done
4295 * regardless of the field value
4296 * Bit0 - filter by activity: entry_a
4297 * Bit3 - filter by entry rip: entry_rif
4300 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
4302 enum mlxsw_reg_rauhtd_op {
4303 MLXSW_REG_RAUHTD_OP_DUMP,
4304 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
4310 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
4312 /* reg_rauhtd_num_rec
4313 * At request: number of records requested
4314 * At response: number of records dumped
4315 * For IPv4, each record has 4 entries at request and up to 4 entries
4317 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
4320 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
4322 /* reg_rauhtd_entry_a
4323 * Dump only if activity has value of entry_a
4324 * Reserved if filter_fields bit0 is '0'
4327 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
4329 enum mlxsw_reg_rauhtd_type {
4330 MLXSW_REG_RAUHTD_TYPE_IPV4,
4331 MLXSW_REG_RAUHTD_TYPE_IPV6,
4335 * Dump only if record type is:
4340 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
4342 /* reg_rauhtd_entry_rif
4343 * Dump only if RIF has value of entry_rif
4344 * Reserved if filter_fields bit3 is '0'
4347 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
4349 static inline void mlxsw_reg_rauhtd_pack(char *payload,
4350 enum mlxsw_reg_rauhtd_type type)
4352 MLXSW_REG_ZERO(rauhtd, payload);
4353 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
4354 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
4355 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
4356 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
4357 mlxsw_reg_rauhtd_type_set(payload, type);
4360 /* reg_rauhtd_ipv4_rec_num_entries
4361 * Number of valid entries in this record:
4363 * 1 - 2 valid entries
4364 * 2 - 3 valid entries
4365 * 3 - 4 valid entries
4368 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
4369 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
4370 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4372 /* reg_rauhtd_rec_type
4378 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
4379 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4381 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
4383 /* reg_rauhtd_ipv4_ent_a
4384 * Activity. Set for new entries. Set if a packet lookup has hit on the
4388 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
4389 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4391 /* reg_rauhtd_ipv4_ent_rif
4395 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4396 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4398 /* reg_rauhtd_ipv4_ent_dip
4399 * Destination IPv4 address.
4402 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4403 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
4405 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
4406 int ent_index, u16 *p_rif,
4409 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
4410 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
4413 /* MFCR - Management Fan Control Register
4414 * --------------------------------------
4415 * This register controls the settings of the Fan Speed PWM mechanism.
4417 #define MLXSW_REG_MFCR_ID 0x9001
4418 #define MLXSW_REG_MFCR_LEN 0x08
4420 static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
4421 .id = MLXSW_REG_MFCR_ID,
4422 .len = MLXSW_REG_MFCR_LEN,
4425 enum mlxsw_reg_mfcr_pwm_frequency {
4426 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
4427 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
4428 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
4429 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
4430 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
4431 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
4432 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
4433 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
4436 /* reg_mfcr_pwm_frequency
4437 * Controls the frequency of the PWM signal.
4440 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
4442 #define MLXSW_MFCR_TACHOS_MAX 10
4444 /* reg_mfcr_tacho_active
4445 * Indicates which of the tachometer is active (bit per tachometer).
4448 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
4450 #define MLXSW_MFCR_PWMS_MAX 5
4452 /* reg_mfcr_pwm_active
4453 * Indicates which of the PWM control is active (bit per PWM).
4456 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
4459 mlxsw_reg_mfcr_pack(char *payload,
4460 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
4462 MLXSW_REG_ZERO(mfcr, payload);
4463 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
4467 mlxsw_reg_mfcr_unpack(char *payload,
4468 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
4469 u16 *p_tacho_active, u8 *p_pwm_active)
4471 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
4472 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
4473 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
4476 /* MFSC - Management Fan Speed Control Register
4477 * --------------------------------------------
4478 * This register controls the settings of the Fan Speed PWM mechanism.
4480 #define MLXSW_REG_MFSC_ID 0x9002
4481 #define MLXSW_REG_MFSC_LEN 0x08
4483 static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
4484 .id = MLXSW_REG_MFSC_ID,
4485 .len = MLXSW_REG_MFSC_LEN,
4489 * Fan pwm to control / monitor.
4492 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
4494 /* reg_mfsc_pwm_duty_cycle
4495 * Controls the duty cycle of the PWM. Value range from 0..255 to
4496 * represent duty cycle of 0%...100%.
4499 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
4501 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
4504 MLXSW_REG_ZERO(mfsc, payload);
4505 mlxsw_reg_mfsc_pwm_set(payload, pwm);
4506 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
4509 /* MFSM - Management Fan Speed Measurement
4510 * ---------------------------------------
4511 * This register controls the settings of the Tacho measurements and
4512 * enables reading the Tachometer measurements.
4514 #define MLXSW_REG_MFSM_ID 0x9003
4515 #define MLXSW_REG_MFSM_LEN 0x08
4517 static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
4518 .id = MLXSW_REG_MFSM_ID,
4519 .len = MLXSW_REG_MFSM_LEN,
4523 * Fan tachometer index.
4526 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
4529 * Fan speed (round per minute).
4532 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
4534 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
4536 MLXSW_REG_ZERO(mfsm, payload);
4537 mlxsw_reg_mfsm_tacho_set(payload, tacho);
4540 /* MTCAP - Management Temperature Capabilities
4541 * -------------------------------------------
4542 * This register exposes the capabilities of the device and
4543 * system temperature sensing.
4545 #define MLXSW_REG_MTCAP_ID 0x9009
4546 #define MLXSW_REG_MTCAP_LEN 0x08
4548 static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
4549 .id = MLXSW_REG_MTCAP_ID,
4550 .len = MLXSW_REG_MTCAP_LEN,
4553 /* reg_mtcap_sensor_count
4554 * Number of sensors supported by the device.
4555 * This includes the QSFP module sensors (if exists in the QSFP module).
4558 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
4560 /* MTMP - Management Temperature
4561 * -----------------------------
4562 * This register controls the settings of the temperature measurements
4563 * and enables reading the temperature measurements. Note that temperature
4564 * is in 0.125 degrees Celsius.
4566 #define MLXSW_REG_MTMP_ID 0x900A
4567 #define MLXSW_REG_MTMP_LEN 0x20
4569 static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
4570 .id = MLXSW_REG_MTMP_ID,
4571 .len = MLXSW_REG_MTMP_LEN,
4574 /* reg_mtmp_sensor_index
4575 * Sensors index to access.
4576 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
4577 * (module 0 is mapped to sensor_index 64).
4580 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
4582 /* Convert to milli degrees Celsius */
4583 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
4585 /* reg_mtmp_temperature
4586 * Temperature reading from the sensor. Reading is in 0.125 Celsius
4590 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
4593 * Max Temperature Enable - enables measuring the max temperature on a sensor.
4596 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
4599 * Max Temperature Reset - clears the value of the max temperature register.
4602 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
4604 /* reg_mtmp_max_temperature
4605 * The highest measured temperature from the sensor.
4606 * When the bit mte is cleared, the field max_temperature is reserved.
4609 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
4611 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
4613 /* reg_mtmp_sensor_name
4617 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
4619 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
4620 bool max_temp_enable,
4621 bool max_temp_reset)
4623 MLXSW_REG_ZERO(mtmp, payload);
4624 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
4625 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
4626 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
4629 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
4630 unsigned int *p_max_temp,
4636 temp = mlxsw_reg_mtmp_temperature_get(payload);
4637 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4640 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
4641 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4644 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
4647 /* MPAT - Monitoring Port Analyzer Table
4648 * -------------------------------------
4649 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
4650 * For an enabled analyzer, all fields except e (enable) cannot be modified.
4652 #define MLXSW_REG_MPAT_ID 0x901A
4653 #define MLXSW_REG_MPAT_LEN 0x78
4655 static const struct mlxsw_reg_info mlxsw_reg_mpat = {
4656 .id = MLXSW_REG_MPAT_ID,
4657 .len = MLXSW_REG_MPAT_LEN,
4664 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
4666 /* reg_mpat_system_port
4667 * A unique port identifier for the final destination of the packet.
4670 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
4673 * Enable. Indicating the Port Analyzer is enabled.
4676 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
4679 * Quality Of Service Mode.
4680 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
4681 * PCP, DEI, DSCP or VL) are configured.
4682 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
4683 * same as in the original packet that has triggered the mirroring. For
4684 * SPAN also the pcp,dei are maintained.
4687 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
4690 * Best effort mode. Indicates mirroring traffic should not cause packet
4691 * drop or back pressure, but will discard the mirrored packets. Mirrored
4692 * packets will be forwarded on a best effort manner.
4693 * 0: Do not discard mirrored packets
4694 * 1: Discard mirrored packets if causing congestion
4697 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
4699 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
4700 u16 system_port, bool e)
4702 MLXSW_REG_ZERO(mpat, payload);
4703 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
4704 mlxsw_reg_mpat_system_port_set(payload, system_port);
4705 mlxsw_reg_mpat_e_set(payload, e);
4706 mlxsw_reg_mpat_qos_set(payload, 1);
4707 mlxsw_reg_mpat_be_set(payload, 1);
4710 /* MPAR - Monitoring Port Analyzer Register
4711 * ----------------------------------------
4712 * MPAR register is used to query and configure the port analyzer port mirroring
4715 #define MLXSW_REG_MPAR_ID 0x901B
4716 #define MLXSW_REG_MPAR_LEN 0x08
4718 static const struct mlxsw_reg_info mlxsw_reg_mpar = {
4719 .id = MLXSW_REG_MPAR_ID,
4720 .len = MLXSW_REG_MPAR_LEN,
4723 /* reg_mpar_local_port
4724 * The local port to mirror the packets from.
4727 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
4729 enum mlxsw_reg_mpar_i_e {
4730 MLXSW_REG_MPAR_TYPE_EGRESS,
4731 MLXSW_REG_MPAR_TYPE_INGRESS,
4738 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
4742 * By default, port mirroring is disabled for all ports.
4745 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
4751 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
4753 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
4754 enum mlxsw_reg_mpar_i_e i_e,
4755 bool enable, u8 pa_id)
4757 MLXSW_REG_ZERO(mpar, payload);
4758 mlxsw_reg_mpar_local_port_set(payload, local_port);
4759 mlxsw_reg_mpar_enable_set(payload, enable);
4760 mlxsw_reg_mpar_i_e_set(payload, i_e);
4761 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
4764 /* MLCR - Management LED Control Register
4765 * --------------------------------------
4766 * Controls the system LEDs.
4768 #define MLXSW_REG_MLCR_ID 0x902B
4769 #define MLXSW_REG_MLCR_LEN 0x0C
4771 static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
4772 .id = MLXSW_REG_MLCR_ID,
4773 .len = MLXSW_REG_MLCR_LEN,
4776 /* reg_mlcr_local_port
4777 * Local port number.
4780 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
4782 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
4784 /* reg_mlcr_beacon_duration
4785 * Duration of the beacon to be active, in seconds.
4786 * 0x0 - Will turn off the beacon.
4787 * 0xFFFF - Will turn on the beacon until explicitly turned off.
4790 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
4792 /* reg_mlcr_beacon_remain
4793 * Remaining duration of the beacon, in seconds.
4794 * 0xFFFF indicates an infinite amount of time.
4797 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
4799 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
4802 MLXSW_REG_ZERO(mlcr, payload);
4803 mlxsw_reg_mlcr_local_port_set(payload, local_port);
4804 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
4805 MLXSW_REG_MLCR_DURATION_MAX : 0);
4808 /* SBPR - Shared Buffer Pools Register
4809 * -----------------------------------
4810 * The SBPR configures and retrieves the shared buffer pools and configuration.
4812 #define MLXSW_REG_SBPR_ID 0xB001
4813 #define MLXSW_REG_SBPR_LEN 0x14
4815 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
4816 .id = MLXSW_REG_SBPR_ID,
4817 .len = MLXSW_REG_SBPR_LEN,
4820 /* shared direstion enum for SBPR, SBCM, SBPM */
4821 enum mlxsw_reg_sbxx_dir {
4822 MLXSW_REG_SBXX_DIR_INGRESS,
4823 MLXSW_REG_SBXX_DIR_EGRESS,
4830 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
4836 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
4839 * Pool size in buffer cells.
4842 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
4844 enum mlxsw_reg_sbpr_mode {
4845 MLXSW_REG_SBPR_MODE_STATIC,
4846 MLXSW_REG_SBPR_MODE_DYNAMIC,
4850 * Pool quota calculation mode.
4853 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
4855 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
4856 enum mlxsw_reg_sbxx_dir dir,
4857 enum mlxsw_reg_sbpr_mode mode, u32 size)
4859 MLXSW_REG_ZERO(sbpr, payload);
4860 mlxsw_reg_sbpr_pool_set(payload, pool);
4861 mlxsw_reg_sbpr_dir_set(payload, dir);
4862 mlxsw_reg_sbpr_mode_set(payload, mode);
4863 mlxsw_reg_sbpr_size_set(payload, size);
4866 /* SBCM - Shared Buffer Class Management Register
4867 * ----------------------------------------------
4868 * The SBCM register configures and retrieves the shared buffer allocation
4869 * and configuration according to Port-PG, including the binding to pool
4870 * and definition of the associated quota.
4872 #define MLXSW_REG_SBCM_ID 0xB002
4873 #define MLXSW_REG_SBCM_LEN 0x28
4875 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
4876 .id = MLXSW_REG_SBCM_ID,
4877 .len = MLXSW_REG_SBCM_LEN,
4880 /* reg_sbcm_local_port
4881 * Local port number.
4882 * For Ingress: excludes CPU port and Router port
4883 * For Egress: excludes IP Router
4886 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
4889 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
4890 * For PG buffer: range is 0..cap_max_pg_buffers - 1
4891 * For traffic class: range is 0..cap_max_tclass - 1
4892 * Note that when traffic class is in MC aware mode then the traffic
4893 * classes which are MC aware cannot be configured.
4896 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
4902 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
4904 /* reg_sbcm_min_buff
4905 * Minimum buffer size for the limiter, in cells.
4908 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
4910 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
4911 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
4912 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
4914 /* reg_sbcm_max_buff
4915 * When the pool associated to the port-pg/tclass is configured to
4916 * static, Maximum buffer size for the limiter configured in cells.
4917 * When the pool associated to the port-pg/tclass is configured to
4918 * dynamic, the max_buff holds the "alpha" parameter, supporting
4919 * the following values:
4921 * i: (1/128)*2^(i-1), for i=1..14
4925 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
4928 * Association of the port-priority to a pool.
4931 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
4933 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
4934 enum mlxsw_reg_sbxx_dir dir,
4935 u32 min_buff, u32 max_buff, u8 pool)
4937 MLXSW_REG_ZERO(sbcm, payload);
4938 mlxsw_reg_sbcm_local_port_set(payload, local_port);
4939 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
4940 mlxsw_reg_sbcm_dir_set(payload, dir);
4941 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
4942 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
4943 mlxsw_reg_sbcm_pool_set(payload, pool);
4946 /* SBPM - Shared Buffer Port Management Register
4947 * ---------------------------------------------
4948 * The SBPM register configures and retrieves the shared buffer allocation
4949 * and configuration according to Port-Pool, including the definition
4950 * of the associated quota.
4952 #define MLXSW_REG_SBPM_ID 0xB003
4953 #define MLXSW_REG_SBPM_LEN 0x28
4955 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
4956 .id = MLXSW_REG_SBPM_ID,
4957 .len = MLXSW_REG_SBPM_LEN,
4960 /* reg_sbpm_local_port
4961 * Local port number.
4962 * For Ingress: excludes CPU port and Router port
4963 * For Egress: excludes IP Router
4966 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
4969 * The pool associated to quota counting on the local_port.
4972 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
4978 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
4980 /* reg_sbpm_buff_occupancy
4981 * Current buffer occupancy in cells.
4984 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
4987 * Clear Max Buffer Occupancy
4988 * When this bit is set, max_buff_occupancy field is cleared (and a
4989 * new max value is tracked from the time the clear was performed).
4992 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
4994 /* reg_sbpm_max_buff_occupancy
4995 * Maximum value of buffer occupancy in cells monitored. Cleared by
4996 * writing to the clr field.
4999 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
5001 /* reg_sbpm_min_buff
5002 * Minimum buffer size for the limiter, in cells.
5005 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
5007 /* reg_sbpm_max_buff
5008 * When the pool associated to the port-pg/tclass is configured to
5009 * static, Maximum buffer size for the limiter configured in cells.
5010 * When the pool associated to the port-pg/tclass is configured to
5011 * dynamic, the max_buff holds the "alpha" parameter, supporting
5012 * the following values:
5014 * i: (1/128)*2^(i-1), for i=1..14
5018 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
5020 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
5021 enum mlxsw_reg_sbxx_dir dir, bool clr,
5022 u32 min_buff, u32 max_buff)
5024 MLXSW_REG_ZERO(sbpm, payload);
5025 mlxsw_reg_sbpm_local_port_set(payload, local_port);
5026 mlxsw_reg_sbpm_pool_set(payload, pool);
5027 mlxsw_reg_sbpm_dir_set(payload, dir);
5028 mlxsw_reg_sbpm_clr_set(payload, clr);
5029 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
5030 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
5033 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
5034 u32 *p_max_buff_occupancy)
5036 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
5037 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
5040 /* SBMM - Shared Buffer Multicast Management Register
5041 * --------------------------------------------------
5042 * The SBMM register configures and retrieves the shared buffer allocation
5043 * and configuration for MC packets according to Switch-Priority, including
5044 * the binding to pool and definition of the associated quota.
5046 #define MLXSW_REG_SBMM_ID 0xB004
5047 #define MLXSW_REG_SBMM_LEN 0x28
5049 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
5050 .id = MLXSW_REG_SBMM_ID,
5051 .len = MLXSW_REG_SBMM_LEN,
5058 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
5060 /* reg_sbmm_min_buff
5061 * Minimum buffer size for the limiter, in cells.
5064 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
5066 /* reg_sbmm_max_buff
5067 * When the pool associated to the port-pg/tclass is configured to
5068 * static, Maximum buffer size for the limiter configured in cells.
5069 * When the pool associated to the port-pg/tclass is configured to
5070 * dynamic, the max_buff holds the "alpha" parameter, supporting
5071 * the following values:
5073 * i: (1/128)*2^(i-1), for i=1..14
5077 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
5080 * Association of the port-priority to a pool.
5083 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
5085 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
5086 u32 max_buff, u8 pool)
5088 MLXSW_REG_ZERO(sbmm, payload);
5089 mlxsw_reg_sbmm_prio_set(payload, prio);
5090 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
5091 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
5092 mlxsw_reg_sbmm_pool_set(payload, pool);
5095 /* SBSR - Shared Buffer Status Register
5096 * ------------------------------------
5097 * The SBSR register retrieves the shared buffer occupancy according to
5098 * Port-Pool. Note that this register enables reading a large amount of data.
5099 * It is the user's responsibility to limit the amount of data to ensure the
5100 * response can match the maximum transfer unit. In case the response exceeds
5101 * the maximum transport unit, it will be truncated with no special notice.
5103 #define MLXSW_REG_SBSR_ID 0xB005
5104 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
5105 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
5106 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
5107 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
5108 MLXSW_REG_SBSR_REC_LEN * \
5109 MLXSW_REG_SBSR_REC_MAX_COUNT)
5111 static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
5112 .id = MLXSW_REG_SBSR_ID,
5113 .len = MLXSW_REG_SBSR_LEN,
5117 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
5118 * field is cleared (and a new max value is tracked from the time the clear
5122 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
5124 /* reg_sbsr_ingress_port_mask
5125 * Bit vector for all ingress network ports.
5126 * Indicates which of the ports (for which the relevant bit is set)
5127 * are affected by the set operation. Configuration of any other port
5131 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
5133 /* reg_sbsr_pg_buff_mask
5134 * Bit vector for all switch priority groups.
5135 * Indicates which of the priorities (for which the relevant bit is set)
5136 * are affected by the set operation. Configuration of any other priority
5138 * Range is 0..cap_max_pg_buffers - 1
5141 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
5143 /* reg_sbsr_egress_port_mask
5144 * Bit vector for all egress network ports.
5145 * Indicates which of the ports (for which the relevant bit is set)
5146 * are affected by the set operation. Configuration of any other port
5150 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
5152 /* reg_sbsr_tclass_mask
5153 * Bit vector for all traffic classes.
5154 * Indicates which of the traffic classes (for which the relevant bit is
5155 * set) are affected by the set operation. Configuration of any other
5156 * traffic class does not change.
5157 * Range is 0..cap_max_tclass - 1
5160 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
5162 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
5164 MLXSW_REG_ZERO(sbsr, payload);
5165 mlxsw_reg_sbsr_clr_set(payload, clr);
5168 /* reg_sbsr_rec_buff_occupancy
5169 * Current buffer occupancy in cells.
5172 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5173 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
5175 /* reg_sbsr_rec_max_buff_occupancy
5176 * Maximum value of buffer occupancy in cells monitored. Cleared by
5177 * writing to the clr field.
5180 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5181 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
5183 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
5184 u32 *p_buff_occupancy,
5185 u32 *p_max_buff_occupancy)
5188 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
5189 *p_max_buff_occupancy =
5190 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
5193 /* SBIB - Shared Buffer Internal Buffer Register
5194 * ---------------------------------------------
5195 * The SBIB register configures per port buffers for internal use. The internal
5196 * buffers consume memory on the port buffers (note that the port buffers are
5197 * used also by PBMC).
5199 * For Spectrum this is used for egress mirroring.
5201 #define MLXSW_REG_SBIB_ID 0xB006
5202 #define MLXSW_REG_SBIB_LEN 0x10
5204 static const struct mlxsw_reg_info mlxsw_reg_sbib = {
5205 .id = MLXSW_REG_SBIB_ID,
5206 .len = MLXSW_REG_SBIB_LEN,
5209 /* reg_sbib_local_port
5211 * Not supported for CPU port and router port
5214 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
5216 /* reg_sbib_buff_size
5217 * Units represented in cells
5218 * Allowed range is 0 to (cap_max_headroom_size - 1)
5222 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
5224 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
5227 MLXSW_REG_ZERO(sbib, payload);
5228 mlxsw_reg_sbib_local_port_set(payload, local_port);
5229 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
5232 static inline const char *mlxsw_reg_id_str(u16 reg_id)
5235 case MLXSW_REG_SGCR_ID:
5237 case MLXSW_REG_SPAD_ID:
5239 case MLXSW_REG_SMID_ID:
5241 case MLXSW_REG_SSPR_ID:
5243 case MLXSW_REG_SFDAT_ID:
5245 case MLXSW_REG_SFD_ID:
5247 case MLXSW_REG_SFN_ID:
5249 case MLXSW_REG_SPMS_ID:
5251 case MLXSW_REG_SPVID_ID:
5253 case MLXSW_REG_SPVM_ID:
5255 case MLXSW_REG_SPAFT_ID:
5257 case MLXSW_REG_SFGC_ID:
5259 case MLXSW_REG_SFTR_ID:
5261 case MLXSW_REG_SFDF_ID:
5263 case MLXSW_REG_SLDR_ID:
5265 case MLXSW_REG_SLCR_ID:
5267 case MLXSW_REG_SLCOR_ID:
5269 case MLXSW_REG_SPMLR_ID:
5271 case MLXSW_REG_SVFA_ID:
5273 case MLXSW_REG_SVPE_ID:
5275 case MLXSW_REG_SFMR_ID:
5277 case MLXSW_REG_SPVMLR_ID:
5279 case MLXSW_REG_QTCT_ID:
5281 case MLXSW_REG_QEEC_ID:
5283 case MLXSW_REG_PMLP_ID:
5285 case MLXSW_REG_PMTU_ID:
5287 case MLXSW_REG_PTYS_ID:
5289 case MLXSW_REG_PPAD_ID:
5291 case MLXSW_REG_PAOS_ID:
5293 case MLXSW_REG_PFCC_ID:
5295 case MLXSW_REG_PPCNT_ID:
5297 case MLXSW_REG_PPTB_ID:
5299 case MLXSW_REG_PBMC_ID:
5301 case MLXSW_REG_PSPA_ID:
5303 case MLXSW_REG_HTGT_ID:
5305 case MLXSW_REG_HPKT_ID:
5307 case MLXSW_REG_RGCR_ID:
5309 case MLXSW_REG_RITR_ID:
5311 case MLXSW_REG_RATR_ID:
5313 case MLXSW_REG_RALTA_ID:
5315 case MLXSW_REG_RALST_ID:
5317 case MLXSW_REG_RALTB_ID:
5319 case MLXSW_REG_RALUE_ID:
5321 case MLXSW_REG_RAUHT_ID:
5323 case MLXSW_REG_RALEU_ID:
5325 case MLXSW_REG_RAUHTD_ID:
5327 case MLXSW_REG_MFCR_ID:
5329 case MLXSW_REG_MFSC_ID:
5331 case MLXSW_REG_MFSM_ID:
5333 case MLXSW_REG_MTCAP_ID:
5335 case MLXSW_REG_MPAT_ID:
5337 case MLXSW_REG_MPAR_ID:
5339 case MLXSW_REG_MTMP_ID:
5341 case MLXSW_REG_MLCR_ID:
5343 case MLXSW_REG_SBPR_ID:
5345 case MLXSW_REG_SBCM_ID:
5347 case MLXSW_REG_SBPM_ID:
5349 case MLXSW_REG_SBMM_ID:
5351 case MLXSW_REG_SBSR_ID:
5353 case MLXSW_REG_SBIB_ID:
5360 /* PUDE - Port Up / Down Event
5361 * ---------------------------
5362 * Reports the operational state change of a port.
5364 #define MLXSW_REG_PUDE_LEN 0x10
5367 * Switch partition ID with which to associate the port.
5370 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
5372 /* reg_pude_local_port
5373 * Local port number.
5376 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
5378 /* reg_pude_admin_status
5379 * Port administrative state (the desired state).
5382 * 3 - Up once. This means that in case of link failure, the port won't go
5383 * into polling mode, but will wait to be re-enabled by software.
5384 * 4 - Disabled by system. Can only be set by hardware.
5387 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
5389 /* reg_pude_oper_status
5390 * Port operatioanl state.
5393 * 3 - Down by port failure. This means that the device will not let the
5394 * port up again until explicitly specified by software.
5397 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);