drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
   2
   3 /* Gigabit Ethernet driver for Mellanox BlueField SoC
   4  *
   5  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/device.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/etherdevice.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/phy.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/skbuff.h>
  18
  19 #include "mlxbf_gige.h"
  20 #include "mlxbf_gige_regs.h"
  21
  22 /* Allocate SKB whose payload pointer aligns with the Bluefield
  23  * hardware DMA limitation, i.e. DMA operation can't cross
  24  * a 4KB boundary.  A maximum packet size of 2KB is assumed in the
  25  * alignment formula.  The alignment logic overallocates an SKB,
  26  * and then adjusts the headroom so that the SKB data pointer is
  27  * naturally aligned to a 2KB boundary.
  28  */
  29 struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
  30                                      unsigned int map_len,
  31                                      dma_addr_t *buf_dma,
  32                                      enum dma_data_direction dir)
  33 {
  34         struct sk_buff *skb;
  35         u64 addr, offset;
  36
  37         /* Overallocate the SKB so that any headroom adjustment (to
  38          * provide 2KB natural alignment) does not exceed payload area
  39          */
  40         skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2);
  41         if (!skb)
  42                 return NULL;
  43
  44         /* Adjust the headroom so that skb->data is naturally aligned to
  45          * a 2KB boundary, which is the maximum packet size supported.
  46          */
  47         addr = (long)skb->data;
  48         offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) &
  49                 ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1);
  50         offset -= addr;
  51         if (offset)
  52                 skb_reserve(skb, offset);
  53
  54         /* Return streaming DMA mapping to caller */
  55         *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir);
  56         if (dma_mapping_error(priv->dev, *buf_dma)) {
  57                 dev_kfree_skb(skb);
  58                 *buf_dma = (dma_addr_t)0;
  59                 return NULL;
  60         }
  61
  62         return skb;
  63 }
  64
  65 static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv)
  66 {
  67         u8 mac[ETH_ALEN];
  68         u64 local_mac;
  69
  70         eth_zero_addr(mac);
  71         mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
  72                                      &local_mac);
  73         u64_to_ether_addr(local_mac, mac);
  74
  75         if (is_valid_ether_addr(mac)) {
  76                 eth_hw_addr_set(priv->netdev, mac);
  77         } else {
  78                 /* Provide a random MAC if for some reason the device has
  79                  * not been configured with a valid MAC address already.
  80                  */
  81                 eth_hw_addr_random(priv->netdev);
  82         }
  83
  84         local_mac = ether_addr_to_u64(priv->netdev->dev_addr);
  85         mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
  86                                      local_mac);
  87 }
  88
  89 static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv)
  90 {
  91         struct mlxbf_gige_stats *p;
  92
  93         /* Cache stats that will be cleared by clean port operation */
  94         p = &priv->stats;
  95         p->rx_din_dropped_pkts += readq(priv->base +
  96                                         MLXBF_GIGE_RX_DIN_DROP_COUNTER);
  97         p->rx_filter_passed_pkts += readq(priv->base +
  98                                           MLXBF_GIGE_RX_PASS_COUNTER_ALL);
  99         p->rx_filter_discard_pkts += readq(priv->base +
 100                                            MLXBF_GIGE_RX_DISC_COUNTER_ALL);
 101 }
 102
 103 static int mlxbf_gige_clean_port(struct mlxbf_gige *priv)
 104 {
 105         u64 control;
 106         u64 temp;
 107         int err;
 108
 109         /* Set the CLEAN_PORT_EN bit to trigger SW reset */
 110         control = readq(priv->base + MLXBF_GIGE_CONTROL);
 111         control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
 112         writeq(control, priv->base + MLXBF_GIGE_CONTROL);
 113
 114         /* Ensure completion of "clean port" write before polling status */
 115         mb();
 116
 117         err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp,
 118                                         (temp & MLXBF_GIGE_STATUS_READY),
 119                                         100, 100000);
 120
 121         /* Clear the CLEAN_PORT_EN bit at end of this loop */
 122         control = readq(priv->base + MLXBF_GIGE_CONTROL);
 123         control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
 124         writeq(control, priv->base + MLXBF_GIGE_CONTROL);
 125
 126         return err;
 127 }
 128
 129 static int mlxbf_gige_open(struct net_device *netdev)
 130 {
 131         struct mlxbf_gige *priv = netdev_priv(netdev);
 132         struct phy_device *phydev = netdev->phydev;
 133         u64 control;
 134         u64 int_en;
 135         int err;
 136
 137         /* Perform general init of GigE block */
 138         control = readq(priv->base + MLXBF_GIGE_CONTROL);
 139         control |= MLXBF_GIGE_CONTROL_PORT_EN;
 140         writeq(control, priv->base + MLXBF_GIGE_CONTROL);
 141
 142         err = mlxbf_gige_request_irqs(priv);
 143         if (err)
 144                 return err;
 145         mlxbf_gige_cache_stats(priv);
 146         err = mlxbf_gige_clean_port(priv);
 147         if (err)
 148                 goto free_irqs;
 149
 150         /* Clear driver's valid_polarity to match hardware,
 151          * since the above call to clean_port() resets the
 152          * receive polarity used by hardware.
 153          */
 154         priv->valid_polarity = 0;
 155
 156         phy_start(phydev);
 157
 158         err = mlxbf_gige_tx_init(priv);
 159         if (err)
 160                 goto free_irqs;
 161         err = mlxbf_gige_rx_init(priv);
 162         if (err)
 163                 goto tx_deinit;
 164
 165         netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll);
 166         napi_enable(&priv->napi);
 167         netif_start_queue(netdev);
 168
 169         /* Set bits in INT_EN that we care about */
 170         int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR |
 171                  MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS |
 172                  MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE |
 173                  MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE |
 174                  MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR |
 175                  MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR |
 176                  MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET;
 177
 178         /* Ensure completion of all initialization before enabling interrupts */
 179         mb();
 180
 181         writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);
 182
 183         return 0;
 184
 185 tx_deinit:
 186         mlxbf_gige_tx_deinit(priv);
 187
 188 free_irqs:
 189         mlxbf_gige_free_irqs(priv);
 190         return err;
 191 }
 192
 193 static int mlxbf_gige_stop(struct net_device *netdev)
 194 {
 195         struct mlxbf_gige *priv = netdev_priv(netdev);
 196
 197         writeq(0, priv->base + MLXBF_GIGE_INT_EN);
 198         netif_stop_queue(netdev);
 199         napi_disable(&priv->napi);
 200         netif_napi_del(&priv->napi);
 201         mlxbf_gige_free_irqs(priv);
 202
 203         phy_stop(netdev->phydev);
 204
 205         mlxbf_gige_rx_deinit(priv);
 206         mlxbf_gige_tx_deinit(priv);
 207         mlxbf_gige_cache_stats(priv);
 208         mlxbf_gige_clean_port(priv);
 209
 210         return 0;
 211 }
 212
 213 static int mlxbf_gige_eth_ioctl(struct net_device *netdev,
 214                                 struct ifreq *ifr, int cmd)
 215 {
 216         if (!(netif_running(netdev)))
 217                 return -EINVAL;
 218
 219         return phy_mii_ioctl(netdev->phydev, ifr, cmd);
 220 }
 221
 222 static void mlxbf_gige_set_rx_mode(struct net_device *netdev)
 223 {
 224         struct mlxbf_gige *priv = netdev_priv(netdev);
 225         bool new_promisc_enabled;
 226
 227         new_promisc_enabled = netdev->flags & IFF_PROMISC;
 228
 229         /* Only write to the hardware registers if the new setting
 230          * of promiscuous mode is different from the current one.
 231          */
 232         if (new_promisc_enabled != priv->promisc_enabled) {
 233                 priv->promisc_enabled = new_promisc_enabled;
 234
 235                 if (new_promisc_enabled)
 236                         mlxbf_gige_enable_promisc(priv);
 237                 else
 238                         mlxbf_gige_disable_promisc(priv);
 239         }
 240 }
 241
 242 static void mlxbf_gige_get_stats64(struct net_device *netdev,
 243                                    struct rtnl_link_stats64 *stats)
 244 {
 245         struct mlxbf_gige *priv = netdev_priv(netdev);
 246
 247         netdev_stats_to_stats64(stats, &netdev->stats);
 248
 249         stats->rx_length_errors = priv->stats.rx_truncate_errors;
 250         stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts +
 251                                 readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER);
 252         stats->rx_crc_errors = priv->stats.rx_mac_errors;
 253         stats->rx_errors = stats->rx_length_errors +
 254                            stats->rx_fifo_errors +
 255                            stats->rx_crc_errors;
 256
 257         stats->tx_fifo_errors = priv->stats.tx_fifo_full;
 258         stats->tx_errors = stats->tx_fifo_errors;
 259 }
 260
 261 static const struct net_device_ops mlxbf_gige_netdev_ops = {
 262         .ndo_open               = mlxbf_gige_open,
 263         .ndo_stop               = mlxbf_gige_stop,
 264         .ndo_start_xmit         = mlxbf_gige_start_xmit,
 265         .ndo_set_mac_address    = eth_mac_addr,
 266         .ndo_validate_addr      = eth_validate_addr,
 267         .ndo_eth_ioctl          = mlxbf_gige_eth_ioctl,
 268         .ndo_set_rx_mode        = mlxbf_gige_set_rx_mode,
 269         .ndo_get_stats64        = mlxbf_gige_get_stats64,
 270 };
 271
 272 static void mlxbf_gige_bf2_adjust_link(struct net_device *netdev)
 273 {
 274         struct phy_device *phydev = netdev->phydev;
 275
 276         phy_print_status(phydev);
 277 }
 278
 279 static void mlxbf_gige_bf3_adjust_link(struct net_device *netdev)
 280 {
 281         struct mlxbf_gige *priv = netdev_priv(netdev);
 282         struct phy_device *phydev = netdev->phydev;
 283         u8 sgmii_mode;
 284         u16 ipg_size;
 285         u32 val;
 286
 287         if (phydev->link && phydev->speed != priv->prev_speed) {
 288                 switch (phydev->speed) {
 289                 case 1000:
 290                         ipg_size = MLXBF_GIGE_1G_IPG_SIZE;
 291                         sgmii_mode = MLXBF_GIGE_1G_SGMII_MODE;
 292                         break;
 293                 case 100:
 294                         ipg_size = MLXBF_GIGE_100M_IPG_SIZE;
 295                         sgmii_mode = MLXBF_GIGE_100M_SGMII_MODE;
 296                         break;
 297                 case 10:
 298                         ipg_size = MLXBF_GIGE_10M_IPG_SIZE;
 299                         sgmii_mode = MLXBF_GIGE_10M_SGMII_MODE;
 300                         break;
 301                 default:
 302                         return;
 303                 }
 304
 305                 val = readl(priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
 306                 val &= ~(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK | MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK);
 307                 val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK, ipg_size);
 308                 val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK, sgmii_mode);
 309                 writel(val, priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
 310
 311                 val = readl(priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
 312                 val &= ~MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK;
 313                 val |= FIELD_PREP(MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK, sgmii_mode);
 314                 writel(val, priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
 315
 316                 priv->prev_speed = phydev->speed;
 317         }
 318
 319         phy_print_status(phydev);
 320 }
 321
 322 static void mlxbf_gige_bf2_set_phy_link_mode(struct phy_device *phydev)
 323 {
 324         /* MAC only supports 1000T full duplex mode */
 325         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
 326         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
 327         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
 328         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
 329         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
 330
 331         /* Only symmetric pause with flow control enabled is supported so no
 332          * need to negotiate pause.
 333          */
 334         linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
 335         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
 336 }
 337
 338 static void mlxbf_gige_bf3_set_phy_link_mode(struct phy_device *phydev)
 339 {
 340         /* MAC only supports full duplex mode */
 341         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
 342         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
 343         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
 344
 345         /* Only symmetric pause with flow control enabled is supported so no
 346          * need to negotiate pause.
 347          */
 348         linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
 349         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
 350 }
 351
 352 static struct mlxbf_gige_link_cfg mlxbf_gige_link_cfgs[] = {
 353         [MLXBF_GIGE_VERSION_BF2] = {
 354                 .set_phy_link_mode = mlxbf_gige_bf2_set_phy_link_mode,
 355                 .adjust_link = mlxbf_gige_bf2_adjust_link,
 356                 .phy_mode = PHY_INTERFACE_MODE_GMII
 357         },
 358         [MLXBF_GIGE_VERSION_BF3] = {
 359                 .set_phy_link_mode = mlxbf_gige_bf3_set_phy_link_mode,
 360                 .adjust_link = mlxbf_gige_bf3_adjust_link,
 361                 .phy_mode = PHY_INTERFACE_MODE_SGMII
 362         }
 363 };
 364
 365 static int mlxbf_gige_probe(struct platform_device *pdev)
 366 {
 367         struct phy_device *phydev;
 368         struct net_device *netdev;
 369         struct mlxbf_gige *priv;
 370         void __iomem *llu_base;
 371         void __iomem *plu_base;
 372         void __iomem *base;
 373         int addr, phy_irq;
 374         int err;
 375
 376         base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);
 377         if (IS_ERR(base))
 378                 return PTR_ERR(base);
 379
 380         llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU);
 381         if (IS_ERR(llu_base))
 382                 return PTR_ERR(llu_base);
 383
 384         plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU);
 385         if (IS_ERR(plu_base))
 386                 return PTR_ERR(plu_base);
 387
 388         netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv));
 389         if (!netdev)
 390                 return -ENOMEM;
 391
 392         SET_NETDEV_DEV(netdev, &pdev->dev);
 393         netdev->netdev_ops = &mlxbf_gige_netdev_ops;
 394         netdev->ethtool_ops = &mlxbf_gige_ethtool_ops;
 395         priv = netdev_priv(netdev);
 396         priv->netdev = netdev;
 397
 398         platform_set_drvdata(pdev, priv);
 399         priv->dev = &pdev->dev;
 400         priv->pdev = pdev;
 401
 402         spin_lock_init(&priv->lock);
 403
 404         priv->hw_version = readq(base + MLXBF_GIGE_VERSION);
 405
 406         /* Attach MDIO device */
 407         err = mlxbf_gige_mdio_probe(pdev, priv);
 408         if (err)
 409                 return err;
 410
 411         priv->base = base;
 412         priv->llu_base = llu_base;
 413         priv->plu_base = plu_base;
 414
 415         priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ;
 416         priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ;
 417
 418         /* Write initial MAC address to hardware */
 419         mlxbf_gige_initial_mac(priv);
 420
 421         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 422         if (err) {
 423                 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
 424                 goto out;
 425         }
 426
 427         priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX);
 428         priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX);
 429         priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX);
 430
 431         phy_irq = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(&pdev->dev), "phy-gpios", 0);
 432         if (phy_irq < 0) {
 433                 dev_err(&pdev->dev, "Error getting PHY irq. Use polling instead");
 434                 phy_irq = PHY_POLL;
 435         }
 436
 437         phydev = phy_find_first(priv->mdiobus);
 438         if (!phydev) {
 439                 err = -ENODEV;
 440                 goto out;
 441         }
 442
 443         addr = phydev->mdio.addr;
 444         priv->mdiobus->irq[addr] = phy_irq;
 445         phydev->irq = phy_irq;
 446
 447         err = phy_connect_direct(netdev, phydev,
 448                                  mlxbf_gige_link_cfgs[priv->hw_version].adjust_link,
 449                                  mlxbf_gige_link_cfgs[priv->hw_version].phy_mode);
 450         if (err) {
 451                 dev_err(&pdev->dev, "Could not attach to PHY\n");
 452                 goto out;
 453         }
 454
 455         mlxbf_gige_link_cfgs[priv->hw_version].set_phy_link_mode(phydev);
 456
 457         /* Display information about attached PHY device */
 458         phy_attached_info(phydev);
 459
 460         err = register_netdev(netdev);
 461         if (err) {
 462                 dev_err(&pdev->dev, "Failed to register netdev\n");
 463                 phy_disconnect(phydev);
 464                 goto out;
 465         }
 466
 467         return 0;
 468
 469 out:
 470         mlxbf_gige_mdio_remove(priv);
 471         return err;
 472 }
 473
 474 static void mlxbf_gige_remove(struct platform_device *pdev)
 475 {
 476         struct mlxbf_gige *priv = platform_get_drvdata(pdev);
 477
 478         unregister_netdev(priv->netdev);
 479         phy_disconnect(priv->netdev->phydev);
 480         mlxbf_gige_mdio_remove(priv);
 481         platform_set_drvdata(pdev, NULL);
 482 }
 483
 484 static void mlxbf_gige_shutdown(struct platform_device *pdev)
 485 {
 486         struct mlxbf_gige *priv = platform_get_drvdata(pdev);
 487
 488         writeq(0, priv->base + MLXBF_GIGE_INT_EN);
 489         mlxbf_gige_clean_port(priv);
 490 }
 491
 492 static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = {
 493         { "MLNXBF17", 0 },
 494         {},
 495 };
 496 MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match);
 497
 498 static struct platform_driver mlxbf_gige_driver = {
 499         .probe = mlxbf_gige_probe,
 500         .remove_new = mlxbf_gige_remove,
 501         .shutdown = mlxbf_gige_shutdown,
 502         .driver = {
 503                 .name = KBUILD_MODNAME,
 504                 .acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match),
 505         },
 506 };
 507
 508 module_platform_driver(mlxbf_gige_driver);
 509
 510 MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver");
 511 MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>");
 512 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
 513 MODULE_LICENSE("Dual BSD/GPL");