drivers/net/ethernet/mellanox/mlx5/core/qp.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33
  34 #include <linux/gfp.h>
  35 #include <linux/export.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include <linux/mlx5/qp.h>
  38 #include <linux/mlx5/driver.h>
  39
  40 #include "mlx5_core.h"
  41
  42 static struct mlx5_core_rsc_common *mlx5_get_rsc(struct mlx5_core_dev *dev,
  43                                                  u32 rsn)
  44 {
  45         struct mlx5_qp_table *table = &dev->priv.qp_table;
  46         struct mlx5_core_rsc_common *common;
  47
  48         spin_lock(&table->lock);
  49
  50         common = radix_tree_lookup(&table->tree, rsn);
  51         if (common)
  52                 atomic_inc(&common->refcount);
  53
  54         spin_unlock(&table->lock);
  55
  56         if (!common) {
  57                 mlx5_core_warn(dev, "Async event for bogus resource 0x%x\n",
  58                                rsn);
  59                 return NULL;
  60         }
  61         return common;
  62 }
  63
  64 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
  65 {
  66         if (atomic_dec_and_test(&common->refcount))
  67                 complete(&common->free);
  68 }
  69
  70 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
  71 {
  72         struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, rsn);
  73         struct mlx5_core_qp *qp;
  74
  75         if (!common)
  76                 return;
  77
  78         switch (common->res) {
  79         case MLX5_RES_QP:
  80                 qp = (struct mlx5_core_qp *)common;
  81                 qp->event(qp, event_type);
  82                 break;
  83
  84         default:
  85                 mlx5_core_warn(dev, "invalid resource type for 0x%x\n", rsn);
  86         }
  87
  88         mlx5_core_put_rsc(common);
  89 }
  90
  91 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
  92                         struct mlx5_core_qp *qp,
  93                         struct mlx5_create_qp_mbox_in *in,
  94                         int inlen)
  95 {
  96         struct mlx5_qp_table *table = &dev->priv.qp_table;
  97         struct mlx5_create_qp_mbox_out out;
  98         struct mlx5_destroy_qp_mbox_in din;
  99         struct mlx5_destroy_qp_mbox_out dout;
 100         int err;
 101
 102         memset(&out, 0, sizeof(out));
 103         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_QP);
 104
 105         err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
 106         if (err) {
 107                 mlx5_core_warn(dev, "ret %d\n", err);
 108                 return err;
 109         }
 110
 111         if (out.hdr.status) {
 112                 mlx5_core_warn(dev, "current num of QPs 0x%x\n",
 113                                atomic_read(&dev->num_qps));
 114                 return mlx5_cmd_status_to_err(&out.hdr);
 115         }
 116
 117         qp->qpn = be32_to_cpu(out.qpn) & 0xffffff;
 118         mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn);
 119
 120         qp->common.res = MLX5_RES_QP;
 121         spin_lock_irq(&table->lock);
 122         err = radix_tree_insert(&table->tree, qp->qpn, qp);
 123         spin_unlock_irq(&table->lock);
 124         if (err) {
 125                 mlx5_core_warn(dev, "err %d\n", err);
 126                 goto err_cmd;
 127         }
 128
 129         err = mlx5_debug_qp_add(dev, qp);
 130         if (err)
 131                 mlx5_core_dbg(dev, "failed adding QP 0x%x to debug file system\n",
 132                               qp->qpn);
 133
 134         qp->pid = current->pid;
 135         atomic_set(&qp->common.refcount, 1);
 136         atomic_inc(&dev->num_qps);
 137         init_completion(&qp->common.free);
 138
 139         return 0;
 140
 141 err_cmd:
 142         memset(&din, 0, sizeof(din));
 143         memset(&dout, 0, sizeof(dout));
 144         din.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
 145         din.qpn = cpu_to_be32(qp->qpn);
 146         mlx5_cmd_exec(dev, &din, sizeof(din), &out, sizeof(dout));
 147
 148         return err;
 149 }
 150 EXPORT_SYMBOL_GPL(mlx5_core_create_qp);
 151
 152 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
 153                          struct mlx5_core_qp *qp)
 154 {
 155         struct mlx5_destroy_qp_mbox_in in;
 156         struct mlx5_destroy_qp_mbox_out out;
 157         struct mlx5_qp_table *table = &dev->priv.qp_table;
 158         unsigned long flags;
 159         int err;
 160
 161         mlx5_debug_qp_remove(dev, qp);
 162
 163         spin_lock_irqsave(&table->lock, flags);
 164         radix_tree_delete(&table->tree, qp->qpn);
 165         spin_unlock_irqrestore(&table->lock, flags);
 166
 167         mlx5_core_put_rsc((struct mlx5_core_rsc_common *)qp);
 168         wait_for_completion(&qp->common.free);
 169
 170         memset(&in, 0, sizeof(in));
 171         memset(&out, 0, sizeof(out));
 172         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
 173         in.qpn = cpu_to_be32(qp->qpn);
 174         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 175         if (err)
 176                 return err;
 177
 178         if (out.hdr.status)
 179                 return mlx5_cmd_status_to_err(&out.hdr);
 180
 181         atomic_dec(&dev->num_qps);
 182         return 0;
 183 }
 184 EXPORT_SYMBOL_GPL(mlx5_core_destroy_qp);
 185
 186 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
 187                         enum mlx5_qp_state new_state,
 188                         struct mlx5_modify_qp_mbox_in *in, int sqd_event,
 189                         struct mlx5_core_qp *qp)
 190 {
 191         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
 192                 [MLX5_QP_STATE_RST] = {
 193                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 194                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 195                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
 196                 },
 197                 [MLX5_QP_STATE_INIT]  = {
 198                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 199                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 200                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
 201                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
 202                 },
 203                 [MLX5_QP_STATE_RTR]   = {
 204                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 205                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 206                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
 207                 },
 208                 [MLX5_QP_STATE_RTS]   = {
 209                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 210                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 211                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
 212                 },
 213                 [MLX5_QP_STATE_SQD] = {
 214                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 215                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 216                 },
 217                 [MLX5_QP_STATE_SQER] = {
 218                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 219                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 220                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
 221                 },
 222                 [MLX5_QP_STATE_ERR] = {
 223                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
 224                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
 225                 }
 226         };
 227
 228         struct mlx5_modify_qp_mbox_out out;
 229         int err = 0;
 230         u16 op;
 231
 232         if (cur_state >= MLX5_QP_NUM_STATE || new_state >= MLX5_QP_NUM_STATE ||
 233             !optab[cur_state][new_state])
 234                 return -EINVAL;
 235
 236         memset(&out, 0, sizeof(out));
 237         op = optab[cur_state][new_state];
 238         in->hdr.opcode = cpu_to_be16(op);
 239         in->qpn = cpu_to_be32(qp->qpn);
 240         err = mlx5_cmd_exec(dev, in, sizeof(*in), &out, sizeof(out));
 241         if (err)
 242                 return err;
 243
 244         return mlx5_cmd_status_to_err(&out.hdr);
 245 }
 246 EXPORT_SYMBOL_GPL(mlx5_core_qp_modify);
 247
 248 void mlx5_init_qp_table(struct mlx5_core_dev *dev)
 249 {
 250         struct mlx5_qp_table *table = &dev->priv.qp_table;
 251
 252         spin_lock_init(&table->lock);
 253         INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
 254         mlx5_qp_debugfs_init(dev);
 255 }
 256
 257 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
 258 {
 259         mlx5_qp_debugfs_cleanup(dev);
 260 }
 261
 262 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
 263                        struct mlx5_query_qp_mbox_out *out, int outlen)
 264 {
 265         struct mlx5_query_qp_mbox_in in;
 266         int err;
 267
 268         memset(&in, 0, sizeof(in));
 269         memset(out, 0, outlen);
 270         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_QP);
 271         in.qpn = cpu_to_be32(qp->qpn);
 272         err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
 273         if (err)
 274                 return err;
 275
 276         if (out->hdr.status)
 277                 return mlx5_cmd_status_to_err(&out->hdr);
 278
 279         return err;
 280 }
 281 EXPORT_SYMBOL_GPL(mlx5_core_qp_query);
 282
 283 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn)
 284 {
 285         struct mlx5_alloc_xrcd_mbox_in in;
 286         struct mlx5_alloc_xrcd_mbox_out out;
 287         int err;
 288
 289         memset(&in, 0, sizeof(in));
 290         memset(&out, 0, sizeof(out));
 291         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_XRCD);
 292         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 293         if (err)
 294                 return err;
 295
 296         if (out.hdr.status)
 297                 err = mlx5_cmd_status_to_err(&out.hdr);
 298         else
 299                 *xrcdn = be32_to_cpu(out.xrcdn);
 300
 301         return err;
 302 }
 303 EXPORT_SYMBOL_GPL(mlx5_core_xrcd_alloc);
 304
 305 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn)
 306 {
 307         struct mlx5_dealloc_xrcd_mbox_in in;
 308         struct mlx5_dealloc_xrcd_mbox_out out;
 309         int err;
 310
 311         memset(&in, 0, sizeof(in));
 312         memset(&out, 0, sizeof(out));
 313         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_XRCD);
 314         in.xrcdn = cpu_to_be32(xrcdn);
 315         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 316         if (err)
 317                 return err;
 318
 319         if (out.hdr.status)
 320                 err = mlx5_cmd_status_to_err(&out.hdr);
 321
 322         return err;
 323 }
 324 EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc);