2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/mlx5/port.h>
34 #include "mlx5_core.h"
36 /* calling with verbose false will not print error to log */
37 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
38 void *data_out, int size_out, u16 reg_id, int arg,
39 int write, bool verbose)
41 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
42 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
48 in = kvzalloc(inlen, GFP_KERNEL);
49 out = kvzalloc(outlen, GFP_KERNEL);
53 data = MLX5_ADDR_OF(access_register_in, in, register_data);
54 memcpy(data, data_in, size_in);
56 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
57 MLX5_SET(access_register_in, in, op_mod, !write);
58 MLX5_SET(access_register_in, in, argument, arg);
59 MLX5_SET(access_register_in, in, register_id, reg_id);
61 err = mlx5_cmd_do(dev, in, inlen, out, outlen);
63 err = mlx5_cmd_check(dev, err, in, out);
67 data = MLX5_ADDR_OF(access_register_out, out, register_data);
68 memcpy(data_out, data, size_out);
75 EXPORT_SYMBOL_GPL(mlx5_access_reg);
77 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
78 int size_in, void *data_out, int size_out,
79 u16 reg_id, int arg, int write)
81 return mlx5_access_reg(dev, data_in, size_in, data_out, size_out,
82 reg_id, arg, write, true);
84 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
86 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
90 int sz = MLX5_ST_SZ_BYTES(pcam_reg);
92 MLX5_SET(pcam_reg, in, feature_group, feature_group);
93 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
95 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
98 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
102 int sz = MLX5_ST_SZ_BYTES(mcam_reg);
104 MLX5_SET(mcam_reg, in, feature_group, feature_group);
105 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
107 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
110 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
111 u8 feature_group, u8 access_reg_group)
113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
114 int sz = MLX5_ST_SZ_BYTES(qcam_reg);
116 MLX5_SET(qcam_reg, in, feature_group, feature_group);
117 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
119 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
122 struct mlx5_reg_pcap {
132 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
134 struct mlx5_reg_pcap in;
135 struct mlx5_reg_pcap out;
137 memset(&in, 0, sizeof(in));
138 in.caps_127_96 = cpu_to_be32(caps);
139 in.port_num = port_num;
141 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
142 sizeof(out), MLX5_REG_PCAP, 0, 1);
144 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
146 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
147 int ptys_size, int proto_mask, u8 local_port)
149 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
151 MLX5_SET(ptys_reg, in, local_port, local_port);
152 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
153 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
154 ptys_size, MLX5_REG_PTYS, 0, 0);
156 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
158 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
160 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
161 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
163 MLX5_SET(mlcr_reg, in, local_port, 1);
164 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
165 return mlx5_core_access_reg(dev, in, sizeof(in), out,
166 sizeof(out), MLX5_REG_MLCR, 0, 1);
169 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
170 u16 *proto_oper, u8 local_port)
172 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
175 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
180 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
181 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
185 EXPORT_SYMBOL(mlx5_query_ib_port_oper);
187 /* This function should be used after setting a port register only */
188 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
190 enum mlx5_port_status ps;
192 mlx5_query_port_admin_status(dev, &ps);
193 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
194 if (ps == MLX5_PORT_UP)
195 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
197 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
199 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
200 enum mlx5_port_status status)
202 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
203 u32 out[MLX5_ST_SZ_DW(paos_reg)];
205 MLX5_SET(paos_reg, in, local_port, 1);
206 MLX5_SET(paos_reg, in, admin_status, status);
207 MLX5_SET(paos_reg, in, ase, 1);
208 return mlx5_core_access_reg(dev, in, sizeof(in), out,
209 sizeof(out), MLX5_REG_PAOS, 0, 1);
211 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
213 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
214 enum mlx5_port_status *status)
216 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
217 u32 out[MLX5_ST_SZ_DW(paos_reg)];
220 MLX5_SET(paos_reg, in, local_port, 1);
221 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
222 sizeof(out), MLX5_REG_PAOS, 0, 0);
225 *status = MLX5_GET(paos_reg, out, admin_status);
228 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
230 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
231 u16 *max_mtu, u16 *oper_mtu, u8 port)
233 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
234 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
236 MLX5_SET(pmtu_reg, in, local_port, port);
237 mlx5_core_access_reg(dev, in, sizeof(in), out,
238 sizeof(out), MLX5_REG_PMTU, 0, 0);
241 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
243 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
245 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
248 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
250 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
251 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
253 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
254 MLX5_SET(pmtu_reg, in, local_port, port);
255 return mlx5_core_access_reg(dev, in, sizeof(in), out,
256 sizeof(out), MLX5_REG_PMTU, 0, 1);
258 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
260 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
263 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
265 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
267 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
270 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
272 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
274 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
276 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
277 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
280 MLX5_SET(pmlp_reg, in, local_port, 1);
281 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
282 MLX5_REG_PMLP, 0, 0);
286 *module_num = MLX5_GET(lane_2_module_mapping,
287 MLX5_ADDR_OF(pmlp_reg, out, lane0_module_mapping),
293 static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num,
296 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
297 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
301 MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW);
302 MLX5_SET(mcia_reg, in, module, module_num);
303 MLX5_SET(mcia_reg, in, device_address, 0);
304 MLX5_SET(mcia_reg, in, page_number, 0);
305 MLX5_SET(mcia_reg, in, size, 1);
306 MLX5_SET(mcia_reg, in, l, 0);
308 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
309 sizeof(out), MLX5_REG_MCIA, 0, 0);
313 status = MLX5_GET(mcia_reg, out, status);
315 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
319 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
326 static int mlx5_qsfp_eeprom_page(u16 offset)
328 if (offset < MLX5_EEPROM_PAGE_LENGTH)
329 /* Addresses between 0-255 - page 00 */
332 /* Addresses between 256 - 639 belongs to pages 01, 02 and 03
333 * For example, offset = 400 belongs to page 02:
334 * 1 + ((400 - 256)/128) = 2
336 return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) /
337 MLX5_EEPROM_HIGH_PAGE_LENGTH);
340 static int mlx5_qsfp_eeprom_high_page_offset(int page_num)
342 if (!page_num) /* Page 0 always start from low page */
346 return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH;
349 static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
351 *i2c_addr = MLX5_I2C_ADDR_LOW;
352 *page_num = mlx5_qsfp_eeprom_page(*offset);
353 *offset -= mlx5_qsfp_eeprom_high_page_offset(*page_num);
356 static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
358 *i2c_addr = MLX5_I2C_ADDR_LOW;
361 if (*offset < MLX5_EEPROM_PAGE_LENGTH)
364 *i2c_addr = MLX5_I2C_ADDR_HIGH;
365 *offset -= MLX5_EEPROM_PAGE_LENGTH;
368 static int mlx5_mcia_max_bytes(struct mlx5_core_dev *dev)
370 /* mcia supports either 12 dwords or 32 dwords */
371 return (MLX5_CAP_MCAM_FEATURE(dev, mcia_32dwords) ? 32 : 12) * sizeof(u32);
374 static int mlx5_query_mcia(struct mlx5_core_dev *dev,
375 struct mlx5_module_eeprom_query_params *params, u8 *data)
377 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
378 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
383 size = min_t(int, params->size, mlx5_mcia_max_bytes(dev));
385 MLX5_SET(mcia_reg, in, l, 0);
386 MLX5_SET(mcia_reg, in, size, size);
387 MLX5_SET(mcia_reg, in, module, params->module_number);
388 MLX5_SET(mcia_reg, in, device_address, params->offset);
389 MLX5_SET(mcia_reg, in, page_number, params->page);
390 MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address);
392 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
393 sizeof(out), MLX5_REG_MCIA, 0, 0);
397 status = MLX5_GET(mcia_reg, out, status);
399 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
404 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
405 memcpy(data, ptr, size);
410 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
411 u16 offset, u16 size, u8 *data)
413 struct mlx5_module_eeprom_query_params query = {0};
417 err = mlx5_query_module_num(dev, &query.module_number);
421 err = mlx5_query_module_id(dev, query.module_number, &module_id);
426 case MLX5_MODULE_ID_SFP:
427 mlx5_sfp_eeprom_params_set(&query.i2c_address, &query.page, &offset);
429 case MLX5_MODULE_ID_QSFP:
430 case MLX5_MODULE_ID_QSFP_PLUS:
431 case MLX5_MODULE_ID_QSFP28:
432 mlx5_qsfp_eeprom_params_set(&query.i2c_address, &query.page, &offset);
435 mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id);
439 if (offset + size > MLX5_EEPROM_PAGE_LENGTH)
440 /* Cross pages read, read until offset 256 in low page */
441 size = MLX5_EEPROM_PAGE_LENGTH - offset;
444 query.offset = offset;
446 return mlx5_query_mcia(dev, &query, data);
448 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
450 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
451 struct mlx5_module_eeprom_query_params *params,
456 err = mlx5_query_module_num(dev, ¶ms->module_number);
460 if (params->i2c_address != MLX5_I2C_ADDR_HIGH &&
461 params->i2c_address != MLX5_I2C_ADDR_LOW) {
462 mlx5_core_err(dev, "I2C address not recognized: 0x%x\n", params->i2c_address);
466 return mlx5_query_mcia(dev, params, data);
468 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom_by_page);
470 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
471 int pvlc_size, u8 local_port)
473 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
475 MLX5_SET(pvlc_reg, in, local_port, local_port);
476 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
477 pvlc_size, MLX5_REG_PVLC, 0, 0);
480 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
481 u8 *vl_hw_cap, u8 local_port)
483 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
486 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
490 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
494 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
496 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
499 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
501 MLX5_SET(pfcc_reg, in, local_port, 1);
503 return mlx5_core_access_reg(dev, in, sizeof(in), out,
504 out_size, MLX5_REG_PFCC, 0, 0);
507 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
509 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
510 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
512 MLX5_SET(pfcc_reg, in, local_port, 1);
513 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
514 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
516 return mlx5_core_access_reg(dev, in, sizeof(in), out,
517 sizeof(out), MLX5_REG_PFCC, 0, 1);
519 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
521 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
522 u32 *rx_pause, u32 *tx_pause)
524 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
527 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
532 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
535 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
539 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
541 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
542 u16 stall_critical_watermark,
543 u16 stall_minor_watermark)
545 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
546 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
548 MLX5_SET(pfcc_reg, in, local_port, 1);
549 MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
550 MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
551 MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
552 MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
553 MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
554 MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
555 stall_critical_watermark);
556 MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
558 return mlx5_core_access_reg(dev, in, sizeof(in), out,
559 sizeof(out), MLX5_REG_PFCC, 0, 1);
562 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
563 u16 *stall_critical_watermark,
564 u16 *stall_minor_watermark)
566 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
569 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
573 if (stall_critical_watermark)
574 *stall_critical_watermark = MLX5_GET(pfcc_reg, out,
575 device_stall_critical_watermark);
577 if (stall_minor_watermark)
578 *stall_minor_watermark = MLX5_GET(pfcc_reg, out,
579 device_stall_minor_watermark);
584 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
586 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
587 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
589 MLX5_SET(pfcc_reg, in, local_port, 1);
590 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
591 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
592 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
593 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
595 return mlx5_core_access_reg(dev, in, sizeof(in), out,
596 sizeof(out), MLX5_REG_PFCC, 0, 1);
598 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
600 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
602 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
605 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
610 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
613 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
617 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
619 int mlx5_max_tc(struct mlx5_core_dev *mdev)
621 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
626 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
628 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
630 MLX5_SET(dcbx_param, in, port_number, 1);
632 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
633 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
636 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
638 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
640 MLX5_SET(dcbx_param, in, port_number, 1);
642 return mlx5_core_access_reg(mdev, in, sizeof(out), out,
643 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
646 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
648 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
649 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
653 for (i = 0; i < 8; i++) {
654 if (prio_tc[i] > mlx5_max_tc(mdev))
657 MLX5_SET(qtct_reg, in, prio, i);
658 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
660 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
661 sizeof(out), MLX5_REG_QTCT, 0, 1);
668 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
670 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
673 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
674 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
677 memset(in, 0, sizeof(in));
678 memset(out, 0, sizeof(out));
680 MLX5_SET(qtct_reg, in, port_number, 1);
681 MLX5_SET(qtct_reg, in, prio, prio);
683 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
684 sizeof(out), MLX5_REG_QTCT, 0, 0);
686 *tc = MLX5_GET(qtct_reg, out, tclass);
690 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
692 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
695 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
697 if (!MLX5_CAP_GEN(mdev, ets))
700 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
701 MLX5_REG_QETCR, 0, 1);
704 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
707 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
709 if (!MLX5_CAP_GEN(mdev, ets))
712 memset(in, 0, sizeof(in));
713 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
714 MLX5_REG_QETCR, 0, 0);
717 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
719 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
722 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
723 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
724 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
727 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
729 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
731 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
734 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
738 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
742 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
743 tc_configuration[tc]);
745 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
750 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
752 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
754 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
757 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
758 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
759 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
762 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
764 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
766 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
769 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
773 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
777 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
778 tc_configuration[tc]);
780 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
785 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
787 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
791 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
795 MLX5_SET(qetc_reg, in, port_number, 1);
797 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
798 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
800 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
801 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
803 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
807 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
809 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
811 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
815 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
820 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
824 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
825 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
827 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
829 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
835 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
837 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
839 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {};
841 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
842 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
843 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
844 return mlx5_cmd_exec_in(mdev, set_wol_rol, in);
846 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
848 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
850 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {};
851 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {};
854 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
855 err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out);
857 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
861 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
863 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
865 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
867 MLX5_SET(pcmr_reg, in, local_port, 1);
868 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
869 outlen, MLX5_REG_PCMR, 0, 0);
872 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
874 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
876 return mlx5_core_access_reg(mdev, in, inlen, out,
877 sizeof(out), MLX5_REG_PCMR, 0, 1);
880 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
882 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
885 err = mlx5_query_ports_check(mdev, in, sizeof(in));
888 MLX5_SET(pcmr_reg, in, local_port, 1);
889 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
890 return mlx5_set_ports_check(mdev, in, sizeof(in));
893 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
896 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
897 /* Default values for FW which do not support MLX5_REG_PCMR */
901 if (!MLX5_CAP_GEN(mdev, ports_check))
904 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
907 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
908 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
911 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
913 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
915 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
916 mtpps_size, MLX5_REG_MTPPS, 0, 0);
919 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
921 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
923 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
924 sizeof(out), MLX5_REG_MTPPS, 0, 1);
927 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
929 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
930 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
933 MLX5_SET(mtppse_reg, in, pin, pin);
935 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
936 sizeof(out), MLX5_REG_MTPPSE, 0, 0);
940 *arm = MLX5_GET(mtppse_reg, in, event_arm);
941 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
946 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
948 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
949 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
951 MLX5_SET(mtppse_reg, in, pin, pin);
952 MLX5_SET(mtppse_reg, in, event_arm, arm);
953 MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
955 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
956 sizeof(out), MLX5_REG_MTPPSE, 0, 1);
959 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
961 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
962 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
965 MLX5_SET(qpts_reg, in, local_port, 1);
966 MLX5_SET(qpts_reg, in, trust_state, trust_state);
968 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
969 sizeof(out), MLX5_REG_QPTS, 0, 1);
973 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
975 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
976 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
979 MLX5_SET(qpts_reg, in, local_port, 1);
981 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
982 sizeof(out), MLX5_REG_QPTS, 0, 0);
984 *trust_state = MLX5_GET(qpts_reg, out, trust_state);
989 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
991 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
997 in = kzalloc(sz, GFP_KERNEL);
998 out = kzalloc(sz, GFP_KERNEL);
1004 MLX5_SET(qpdpm_reg, in, local_port, 1);
1005 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1009 memcpy(in, out, sz);
1010 MLX5_SET(qpdpm_reg, in, local_port, 1);
1012 /* Update the corresponding dscp entry */
1013 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
1014 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
1015 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
1016 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1024 /* dscp2prio[i]: priority that dscp i mapped to */
1025 #define MLX5E_SUPPORTED_DSCP 64
1026 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
1028 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1035 in = kzalloc(sz, GFP_KERNEL);
1036 out = kzalloc(sz, GFP_KERNEL);
1042 MLX5_SET(qpdpm_reg, in, local_port, 1);
1043 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1047 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
1048 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
1049 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);