2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
40 int size_in, void *data_out, int size_out,
41 u16 reg_num, int arg, int write)
43 struct mlx5_access_reg_mbox_in *in = NULL;
44 struct mlx5_access_reg_mbox_out *out = NULL;
47 in = mlx5_vzalloc(sizeof(*in) + size_in);
51 out = mlx5_vzalloc(sizeof(*out) + size_out);
55 memcpy(in->data, data_in, size_in);
56 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
57 in->hdr.opmod = cpu_to_be16(!write);
58 in->arg = cpu_to_be32(arg);
59 in->register_id = cpu_to_be16(reg_num);
60 err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
61 sizeof(*out) + size_out);
66 err = mlx5_cmd_status_to_err(&out->hdr);
69 memcpy(data_out, out->data, size_out);
77 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
80 struct mlx5_reg_pcap {
90 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
92 struct mlx5_reg_pcap in;
93 struct mlx5_reg_pcap out;
95 memset(&in, 0, sizeof(in));
96 in.caps_127_96 = cpu_to_be32(caps);
97 in.port_num = port_num;
99 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
100 sizeof(out), MLX5_REG_PCAP, 0, 1);
102 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
104 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
105 int ptys_size, int proto_mask, u8 local_port)
107 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
109 memset(in, 0, sizeof(in));
110 MLX5_SET(ptys_reg, in, local_port, local_port);
111 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
113 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
114 ptys_size, MLX5_REG_PTYS, 0, 0);
116 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
118 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
120 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
121 u32 in[MLX5_ST_SZ_DW(mlcr_reg)];
123 memset(in, 0, sizeof(in));
124 MLX5_SET(mlcr_reg, in, local_port, 1);
125 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
127 return mlx5_core_access_reg(dev, in, sizeof(in), out,
128 sizeof(out), MLX5_REG_MLCR, 0, 1);
131 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
132 u32 *proto_cap, int proto_mask)
134 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
137 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
141 if (proto_mask == MLX5_PTYS_EN)
142 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
144 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
148 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
150 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
151 u32 *proto_admin, int proto_mask)
153 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
156 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
160 if (proto_mask == MLX5_PTYS_EN)
161 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
163 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
167 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
169 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
170 u8 *link_width_oper, u8 local_port)
172 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
175 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
179 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
183 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
185 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
186 u8 *proto_oper, int proto_mask,
189 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
192 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
196 if (proto_mask == MLX5_PTYS_EN)
197 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
199 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
203 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
205 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
208 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
209 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
211 memset(in, 0, sizeof(in));
213 MLX5_SET(ptys_reg, in, local_port, 1);
214 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
215 if (proto_mask == MLX5_PTYS_EN)
216 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
218 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
220 return mlx5_core_access_reg(dev, in, sizeof(in), out,
221 sizeof(out), MLX5_REG_PTYS, 0, 1);
223 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
225 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
226 enum mlx5_port_status status)
228 u32 in[MLX5_ST_SZ_DW(paos_reg)];
229 u32 out[MLX5_ST_SZ_DW(paos_reg)];
231 memset(in, 0, sizeof(in));
233 MLX5_SET(paos_reg, in, local_port, 1);
234 MLX5_SET(paos_reg, in, admin_status, status);
235 MLX5_SET(paos_reg, in, ase, 1);
237 return mlx5_core_access_reg(dev, in, sizeof(in), out,
238 sizeof(out), MLX5_REG_PAOS, 0, 1);
240 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
242 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
243 enum mlx5_port_status *status)
245 u32 in[MLX5_ST_SZ_DW(paos_reg)];
246 u32 out[MLX5_ST_SZ_DW(paos_reg)];
249 memset(in, 0, sizeof(in));
251 MLX5_SET(paos_reg, in, local_port, 1);
253 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
254 sizeof(out), MLX5_REG_PAOS, 0, 0);
258 *status = MLX5_GET(paos_reg, out, admin_status);
261 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
263 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu,
264 int *max_mtu, int *oper_mtu, u8 port)
266 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
267 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
269 memset(in, 0, sizeof(in));
271 MLX5_SET(pmtu_reg, in, local_port, port);
273 mlx5_core_access_reg(dev, in, sizeof(in), out,
274 sizeof(out), MLX5_REG_PMTU, 0, 0);
277 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
279 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
281 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
284 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
286 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
287 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
289 memset(in, 0, sizeof(in));
291 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
292 MLX5_SET(pmtu_reg, in, local_port, port);
294 return mlx5_core_access_reg(dev, in, sizeof(in), out,
295 sizeof(out), MLX5_REG_PMTU, 0, 1);
297 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
299 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu,
302 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
304 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
306 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
309 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
311 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
313 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
314 int pvlc_size, u8 local_port)
316 u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
318 memset(in, 0, sizeof(in));
319 MLX5_SET(pvlc_reg, in, local_port, local_port);
321 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
322 pvlc_size, MLX5_REG_PVLC, 0, 0);
325 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
326 u8 *vl_hw_cap, u8 local_port)
328 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
331 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
335 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
339 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
341 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
342 u8 port_num, void *out, size_t sz)
347 in = mlx5_vzalloc(sz);
353 MLX5_SET(ppcnt_reg, in, local_port, port_num);
355 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
356 err = mlx5_core_access_reg(dev, in, sz, out,
357 sz, MLX5_REG_PPCNT, 0, 0);
362 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
364 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
366 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
367 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
369 memset(in, 0, sizeof(in));
370 MLX5_SET(pfcc_reg, in, local_port, 1);
371 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
372 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
374 return mlx5_core_access_reg(dev, in, sizeof(in), out,
375 sizeof(out), MLX5_REG_PFCC, 0, 1);
377 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
379 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
380 u32 *rx_pause, u32 *tx_pause)
382 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
383 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
386 memset(in, 0, sizeof(in));
387 MLX5_SET(pfcc_reg, in, local_port, 1);
389 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
390 sizeof(out), MLX5_REG_PFCC, 0, 0);
395 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
398 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
402 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
404 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
406 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
407 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
409 memset(in, 0, sizeof(in));
410 MLX5_SET(pfcc_reg, in, local_port, 1);
411 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
412 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
413 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
414 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
416 return mlx5_core_access_reg(dev, in, sizeof(in), out,
417 sizeof(out), MLX5_REG_PFCC, 0, 1);
419 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
421 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
423 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
424 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
427 memset(in, 0, sizeof(in));
428 MLX5_SET(pfcc_reg, in, local_port, 1);
430 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
431 sizeof(out), MLX5_REG_PFCC, 0, 0);
436 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
439 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
443 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
445 int mlx5_max_tc(struct mlx5_core_dev *mdev)
447 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
452 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
454 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
455 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
459 memset(in, 0, sizeof(in));
460 for (i = 0; i < 8; i++) {
461 if (prio_tc[i] > mlx5_max_tc(mdev))
464 MLX5_SET(qtct_reg, in, prio, i);
465 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
467 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
468 sizeof(out), MLX5_REG_QTCT, 0, 1);
475 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
477 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
480 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
482 if (!MLX5_CAP_GEN(mdev, ets))
485 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
486 MLX5_REG_QETCR, 0, 1);
489 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
492 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
494 if (!MLX5_CAP_GEN(mdev, ets))
497 memset(in, 0, sizeof(in));
498 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
499 MLX5_REG_QETCR, 0, 0);
502 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
504 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
507 memset(in, 0, sizeof(in));
509 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
510 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
511 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
514 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
516 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
518 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
520 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
523 memset(in, 0, sizeof(in));
525 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
526 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
527 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
530 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
532 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
534 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
538 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
542 memset(in, 0, sizeof(in));
544 MLX5_SET(qetc_reg, in, port_number, 1);
546 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
547 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
549 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
550 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
552 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
556 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
558 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
560 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
564 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
569 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
573 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
574 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
576 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
578 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
584 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
586 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
588 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
589 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
591 memset(in, 0, sizeof(in));
592 memset(out, 0, sizeof(out));
594 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
595 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
596 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
598 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
601 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
603 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
605 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
606 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
609 memset(in, 0, sizeof(in));
610 memset(out, 0, sizeof(out));
612 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
614 err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
618 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
622 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
624 static int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out,
627 u32 in[MLX5_ST_SZ_DW(pcmr_reg)];
629 memset(in, 0, sizeof(in));
630 MLX5_SET(pcmr_reg, in, local_port, 1);
632 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
633 outlen, MLX5_REG_PCMR, 0, 0);
636 static int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
638 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
640 return mlx5_core_access_reg(mdev, in, inlen, out,
641 sizeof(out), MLX5_REG_PCMR, 0, 1);
644 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
646 u32 in[MLX5_ST_SZ_DW(pcmr_reg)];
648 memset(in, 0, sizeof(in));
649 MLX5_SET(pcmr_reg, in, local_port, 1);
650 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
652 return mlx5_set_ports_check(mdev, in, sizeof(in));
655 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
658 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
659 /* Default values for FW which do not support MLX5_REG_PCMR */
663 if (!MLX5_CAP_GEN(mdev, ports_check))
666 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
669 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
670 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));