2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
40 int size_in, void *data_out, int size_out,
41 u16 reg_id, int arg, int write)
43 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
44 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
50 in = mlx5_vzalloc(inlen);
51 out = mlx5_vzalloc(outlen);
55 data = MLX5_ADDR_OF(access_register_in, in, register_data);
56 memcpy(data, data_in, size_in);
58 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
59 MLX5_SET(access_register_in, in, op_mod, !write);
60 MLX5_SET(access_register_in, in, argument, arg);
61 MLX5_SET(access_register_in, in, register_id, reg_id);
63 err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
67 data = MLX5_ADDR_OF(access_register_out, out, register_data);
68 memcpy(data_out, data, size_out);
75 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
77 struct mlx5_reg_pcap {
87 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
89 struct mlx5_reg_pcap in;
90 struct mlx5_reg_pcap out;
92 memset(&in, 0, sizeof(in));
93 in.caps_127_96 = cpu_to_be32(caps);
94 in.port_num = port_num;
96 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
97 sizeof(out), MLX5_REG_PCAP, 0, 1);
99 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
101 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
102 int ptys_size, int proto_mask, u8 local_port)
104 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
106 MLX5_SET(ptys_reg, in, local_port, local_port);
107 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
108 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
109 ptys_size, MLX5_REG_PTYS, 0, 0);
111 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
113 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
115 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
116 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
118 MLX5_SET(mlcr_reg, in, local_port, 1);
119 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
120 return mlx5_core_access_reg(dev, in, sizeof(in), out,
121 sizeof(out), MLX5_REG_MLCR, 0, 1);
124 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
125 u32 *proto_cap, int proto_mask)
127 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
130 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
134 if (proto_mask == MLX5_PTYS_EN)
135 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
137 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
141 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
143 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
144 u32 *proto_admin, int proto_mask)
146 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
149 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
153 if (proto_mask == MLX5_PTYS_EN)
154 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
156 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
160 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
162 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
163 u8 *link_width_oper, u8 local_port)
165 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
168 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
172 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
176 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
178 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
179 u8 *proto_oper, int proto_mask,
182 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
185 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
189 if (proto_mask == MLX5_PTYS_EN)
190 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
192 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
196 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
198 int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable,
199 u32 proto_admin, int proto_mask)
201 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
202 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
207 mlx5_query_port_autoneg(dev, proto_mask, &an_status,
208 &an_disable_cap, &an_disable_admin);
209 if (!an_disable_cap && an_disable)
212 memset(in, 0, sizeof(in));
214 MLX5_SET(ptys_reg, in, local_port, 1);
215 MLX5_SET(ptys_reg, in, an_disable_admin, an_disable);
216 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
217 if (proto_mask == MLX5_PTYS_EN)
218 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
220 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
222 return mlx5_core_access_reg(dev, in, sizeof(in), out,
223 sizeof(out), MLX5_REG_PTYS, 0, 1);
225 EXPORT_SYMBOL_GPL(mlx5_set_port_ptys);
227 /* This function should be used after setting a port register only */
228 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
230 enum mlx5_port_status ps;
232 mlx5_query_port_admin_status(dev, &ps);
233 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
234 if (ps == MLX5_PORT_UP)
235 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
237 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
239 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
240 enum mlx5_port_status status)
242 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
243 u32 out[MLX5_ST_SZ_DW(paos_reg)];
245 MLX5_SET(paos_reg, in, local_port, 1);
246 MLX5_SET(paos_reg, in, admin_status, status);
247 MLX5_SET(paos_reg, in, ase, 1);
248 return mlx5_core_access_reg(dev, in, sizeof(in), out,
249 sizeof(out), MLX5_REG_PAOS, 0, 1);
251 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
253 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
254 enum mlx5_port_status *status)
256 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
257 u32 out[MLX5_ST_SZ_DW(paos_reg)];
260 MLX5_SET(paos_reg, in, local_port, 1);
261 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
262 sizeof(out), MLX5_REG_PAOS, 0, 0);
265 *status = MLX5_GET(paos_reg, out, admin_status);
268 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
270 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
271 u16 *max_mtu, u16 *oper_mtu, u8 port)
273 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
274 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
276 MLX5_SET(pmtu_reg, in, local_port, port);
277 mlx5_core_access_reg(dev, in, sizeof(in), out,
278 sizeof(out), MLX5_REG_PMTU, 0, 0);
281 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
283 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
285 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
288 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
290 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
291 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
293 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
294 MLX5_SET(pmtu_reg, in, local_port, port);
295 return mlx5_core_access_reg(dev, in, sizeof(in), out,
296 sizeof(out), MLX5_REG_PMTU, 0, 1);
298 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
300 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
303 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
305 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
307 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
310 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
312 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
314 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
316 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
317 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
321 MLX5_SET(pmlp_reg, in, local_port, 1);
322 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
323 MLX5_REG_PMLP, 0, 0);
327 module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
328 *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
333 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
334 u16 offset, u16 size, u8 *data)
336 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
337 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
342 void *ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
344 err = mlx5_query_module_num(dev, &module_num);
348 memset(in, 0, sizeof(in));
349 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
351 if (offset < MLX5_EEPROM_PAGE_LENGTH &&
352 offset + size > MLX5_EEPROM_PAGE_LENGTH)
353 /* Cross pages read, read until offset 256 in low page */
354 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
356 i2c_addr = MLX5_I2C_ADDR_LOW;
357 if (offset >= MLX5_EEPROM_PAGE_LENGTH) {
358 i2c_addr = MLX5_I2C_ADDR_HIGH;
359 offset -= MLX5_EEPROM_PAGE_LENGTH;
362 MLX5_SET(mcia_reg, in, l, 0);
363 MLX5_SET(mcia_reg, in, module, module_num);
364 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
365 MLX5_SET(mcia_reg, in, page_number, 0);
366 MLX5_SET(mcia_reg, in, device_address, offset);
367 MLX5_SET(mcia_reg, in, size, size);
369 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
370 sizeof(out), MLX5_REG_MCIA, 0, 0);
374 status = MLX5_GET(mcia_reg, out, status);
376 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
381 memcpy(data, ptr, size);
385 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
387 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
388 int pvlc_size, u8 local_port)
390 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
392 MLX5_SET(pvlc_reg, in, local_port, local_port);
393 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
394 pvlc_size, MLX5_REG_PVLC, 0, 0);
397 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
398 u8 *vl_hw_cap, u8 local_port)
400 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
403 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
407 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
411 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
413 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
414 u8 port_num, void *out, size_t sz)
419 in = mlx5_vzalloc(sz);
425 MLX5_SET(ppcnt_reg, in, local_port, port_num);
427 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
428 err = mlx5_core_access_reg(dev, in, sz, out,
429 sz, MLX5_REG_PPCNT, 0, 0);
434 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
436 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
438 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
439 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
441 MLX5_SET(pfcc_reg, in, local_port, 1);
442 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
443 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
445 return mlx5_core_access_reg(dev, in, sizeof(in), out,
446 sizeof(out), MLX5_REG_PFCC, 0, 1);
448 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
450 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
451 u32 *rx_pause, u32 *tx_pause)
453 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
454 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
457 MLX5_SET(pfcc_reg, in, local_port, 1);
458 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
459 sizeof(out), MLX5_REG_PFCC, 0, 0);
464 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
467 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
471 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
473 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
475 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
476 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
478 MLX5_SET(pfcc_reg, in, local_port, 1);
479 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
480 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
481 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
482 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
484 return mlx5_core_access_reg(dev, in, sizeof(in), out,
485 sizeof(out), MLX5_REG_PFCC, 0, 1);
487 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
489 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
491 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
492 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
495 MLX5_SET(pfcc_reg, in, local_port, 1);
496 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
497 sizeof(out), MLX5_REG_PFCC, 0, 0);
502 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
505 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
509 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
511 void mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
513 u8 *an_disable_cap, u8 *an_disable_admin)
515 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
519 *an_disable_admin = 0;
521 if (mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1))
524 *an_status = MLX5_GET(ptys_reg, out, an_status);
525 *an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
526 *an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
528 EXPORT_SYMBOL_GPL(mlx5_query_port_autoneg);
530 int mlx5_max_tc(struct mlx5_core_dev *mdev)
532 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
537 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
539 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
540 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
544 for (i = 0; i < 8; i++) {
545 if (prio_tc[i] > mlx5_max_tc(mdev))
548 MLX5_SET(qtct_reg, in, prio, i);
549 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
551 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
552 sizeof(out), MLX5_REG_QTCT, 0, 1);
559 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
561 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
564 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
566 if (!MLX5_CAP_GEN(mdev, ets))
569 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
570 MLX5_REG_QETCR, 0, 1);
573 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
576 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
578 if (!MLX5_CAP_GEN(mdev, ets))
581 memset(in, 0, sizeof(in));
582 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
583 MLX5_REG_QETCR, 0, 0);
586 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
588 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
591 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
592 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
593 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
596 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
598 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
600 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
602 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
605 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
606 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
607 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
610 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
612 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
614 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
618 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
622 MLX5_SET(qetc_reg, in, port_number, 1);
624 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
625 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
627 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
628 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
630 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
634 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
636 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
638 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
642 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
647 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
651 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
652 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
654 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
656 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
662 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
664 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
666 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {0};
667 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)] = {0};
669 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
670 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
671 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
672 return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
674 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
676 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
678 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {0};
679 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {0};
682 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
683 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
685 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
689 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
691 static int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out,
694 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
696 MLX5_SET(pcmr_reg, in, local_port, 1);
697 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
698 outlen, MLX5_REG_PCMR, 0, 0);
701 static int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
703 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
705 return mlx5_core_access_reg(mdev, in, inlen, out,
706 sizeof(out), MLX5_REG_PCMR, 0, 1);
709 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
711 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
713 MLX5_SET(pcmr_reg, in, local_port, 1);
714 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
715 return mlx5_set_ports_check(mdev, in, sizeof(in));
718 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
721 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
722 /* Default values for FW which do not support MLX5_REG_PCMR */
726 if (!MLX5_CAP_GEN(mdev, ports_check))
729 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
732 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
733 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));