2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/mlx5/srq.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include "mlx5_core.h"
51 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
52 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
53 MODULE_LICENSE("Dual BSD/GPL");
54 MODULE_VERSION(DRIVER_VERSION);
56 int mlx5_core_debug_mask;
57 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
60 #define MLX5_DEFAULT_PROF 2
61 static int prof_sel = MLX5_DEFAULT_PROF;
62 module_param_named(prof_sel, prof_sel, int, 0444);
63 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
65 static LIST_HEAD(intf_list);
66 static LIST_HEAD(dev_list);
67 static DEFINE_MUTEX(intf_mutex);
69 struct mlx5_device_context {
70 struct list_head list;
71 struct mlx5_interface *intf;
75 static struct mlx5_profile profile[] = {
80 .mask = MLX5_PROF_MASK_QP_SIZE,
84 .mask = MLX5_PROF_MASK_QP_SIZE |
85 MLX5_PROF_MASK_MR_CACHE,
154 static int set_dma_caps(struct pci_dev *pdev)
158 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
160 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
161 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
163 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
168 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
171 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
175 "Can't set consistent PCI DMA mask, aborting\n");
180 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
184 static int request_bar(struct pci_dev *pdev)
188 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
189 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
193 err = pci_request_regions(pdev, DRIVER_NAME);
195 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
200 static void release_bar(struct pci_dev *pdev)
202 pci_release_regions(pdev);
205 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
207 struct mlx5_priv *priv = &dev->priv;
208 struct mlx5_eq_table *table = &priv->eq_table;
209 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
213 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
214 MLX5_EQ_VEC_COMP_BASE;
215 nvec = min_t(int, nvec, num_eqs);
216 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
219 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
221 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
222 if (!priv->msix_arr || !priv->irq_info)
225 for (i = 0; i < nvec; i++)
226 priv->msix_arr[i].entry = i;
228 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
229 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
233 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
238 kfree(priv->irq_info);
239 kfree(priv->msix_arr);
243 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
245 struct mlx5_priv *priv = &dev->priv;
247 pci_disable_msix(dev->pdev);
248 kfree(priv->irq_info);
249 kfree(priv->msix_arr);
252 struct mlx5_reg_host_endianess {
258 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
261 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
262 MLX5_DEV_CAP_FLAG_DCT,
265 static u16 to_fw_pkey_sz(u32 size)
281 pr_warn("invalid pkey table size %d\n", size);
286 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
287 enum mlx5_cap_mode cap_mode)
289 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
290 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
291 void *out, *hca_caps;
292 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
295 memset(in, 0, sizeof(in));
296 out = kzalloc(out_sz, GFP_KERNEL);
300 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
301 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
302 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
306 err = mlx5_cmd_status_to_err_v2(out);
309 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
310 cap_type, cap_mode, err);
314 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
317 case HCA_CAP_OPMOD_GET_MAX:
318 memcpy(dev->hca_caps_max[cap_type], hca_caps,
319 MLX5_UN_SZ_BYTES(hca_cap_union));
321 case HCA_CAP_OPMOD_GET_CUR:
322 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
323 MLX5_UN_SZ_BYTES(hca_cap_union));
327 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
337 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
339 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
342 memset(out, 0, sizeof(out));
344 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
345 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
349 err = mlx5_cmd_status_to_err_v2(out);
354 static int handle_hca_cap(struct mlx5_core_dev *dev)
356 void *set_ctx = NULL;
357 struct mlx5_profile *prof = dev->profile;
359 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
362 set_ctx = kzalloc(set_sz, GFP_KERNEL);
366 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
370 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
374 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
376 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
377 MLX5_ST_SZ_BYTES(cmd_hca_cap));
379 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
380 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
382 /* we limit the size of the pkey table to 128 entries for now */
383 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
386 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
387 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
390 /* disable cmdif checksum */
391 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
393 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
395 err = set_caps(dev, set_ctx, set_sz);
402 static int set_hca_ctrl(struct mlx5_core_dev *dev)
404 struct mlx5_reg_host_endianess he_in;
405 struct mlx5_reg_host_endianess he_out;
408 memset(&he_in, 0, sizeof(he_in));
409 he_in.he = MLX5_SET_HOST_ENDIANNESS;
410 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
411 &he_out, sizeof(he_out),
412 MLX5_REG_HOST_ENDIANNESS, 0, 1);
416 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
419 struct mlx5_enable_hca_mbox_in in;
420 struct mlx5_enable_hca_mbox_out out;
422 memset(&in, 0, sizeof(in));
423 memset(&out, 0, sizeof(out));
424 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
425 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
430 return mlx5_cmd_status_to_err(&out.hdr);
435 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
438 struct mlx5_disable_hca_mbox_in in;
439 struct mlx5_disable_hca_mbox_out out;
441 memset(&in, 0, sizeof(in));
442 memset(&out, 0, sizeof(out));
443 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
444 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
449 return mlx5_cmd_status_to_err(&out.hdr);
454 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
456 struct mlx5_priv *priv = &mdev->priv;
457 struct msix_entry *msix = priv->msix_arr;
458 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
459 int numa_node = priv->numa_node;
462 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
463 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
467 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
468 priv->irq_info[i].mask);
470 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
472 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
480 free_cpumask_var(priv->irq_info[i].mask);
484 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
486 struct mlx5_priv *priv = &mdev->priv;
487 struct msix_entry *msix = priv->msix_arr;
488 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
490 irq_set_affinity_hint(irq, NULL);
491 free_cpumask_var(priv->irq_info[i].mask);
494 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
499 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
500 err = mlx5_irq_set_affinity_hint(mdev, i);
508 for (i--; i >= 0; i--)
509 mlx5_irq_clear_affinity_hint(mdev, i);
514 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
518 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
519 mlx5_irq_clear_affinity_hint(mdev, i);
522 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
524 struct mlx5_eq_table *table = &dev->priv.eq_table;
525 struct mlx5_eq *eq, *n;
528 spin_lock(&table->lock);
529 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
530 if (eq->index == vector) {
537 spin_unlock(&table->lock);
541 EXPORT_SYMBOL(mlx5_vector2eqn);
543 static void free_comp_eqs(struct mlx5_core_dev *dev)
545 struct mlx5_eq_table *table = &dev->priv.eq_table;
546 struct mlx5_eq *eq, *n;
548 spin_lock(&table->lock);
549 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
551 spin_unlock(&table->lock);
552 if (mlx5_destroy_unmap_eq(dev, eq))
553 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
556 spin_lock(&table->lock);
558 spin_unlock(&table->lock);
561 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
563 struct mlx5_eq_table *table = &dev->priv.eq_table;
564 char name[MLX5_MAX_IRQ_NAME];
571 INIT_LIST_HEAD(&table->comp_eqs_list);
572 ncomp_vec = table->num_comp_vectors;
573 nent = MLX5_COMP_EQ_SIZE;
574 for (i = 0; i < ncomp_vec; i++) {
575 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
581 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
582 err = mlx5_create_map_eq(dev, eq,
583 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
584 name, &dev->priv.uuari.uars[0]);
589 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
591 spin_lock(&table->lock);
592 list_add_tail(&eq->list, &table->comp_eqs_list);
593 spin_unlock(&table->lock);
603 #ifdef CONFIG_MLX5_CORE_EN
604 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
606 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
607 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
608 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
609 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
613 memset(query_in, 0, sizeof(query_in));
614 memset(query_out, 0, sizeof(query_out));
616 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
618 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
619 query_out, sizeof(query_out));
621 if (((struct mlx5_outbox_hdr *)query_out)->status ==
622 MLX5_CMD_STAT_BAD_OP_ERR) {
623 pr_debug("Only ISSI 0 is supported\n");
627 pr_err("failed to query ISSI\n");
631 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
633 if (sup_issi & (1 << 1)) {
634 memset(set_in, 0, sizeof(set_in));
635 memset(set_out, 0, sizeof(set_out));
637 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
638 MLX5_SET(set_issi_in, set_in, current_issi, 1);
640 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
641 set_out, sizeof(set_out));
643 pr_err("failed to set ISSI=1\n");
650 } else if (sup_issi & (1 << 0) || !sup_issi) {
658 static int map_bf_area(struct mlx5_core_dev *dev)
660 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
661 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
663 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
665 return dev->priv.bf_mapping ? 0 : -ENOMEM;
668 static void unmap_bf_area(struct mlx5_core_dev *dev)
670 if (dev->priv.bf_mapping)
671 io_mapping_free(dev->priv.bf_mapping);
674 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
676 struct mlx5_device_context *dev_ctx;
677 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
679 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
683 dev_ctx->intf = intf;
684 dev_ctx->context = intf->add(dev);
686 if (dev_ctx->context) {
687 spin_lock_irq(&priv->ctx_lock);
688 list_add_tail(&dev_ctx->list, &priv->ctx_list);
689 spin_unlock_irq(&priv->ctx_lock);
695 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
697 struct mlx5_device_context *dev_ctx;
698 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
700 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
701 if (dev_ctx->intf == intf) {
702 spin_lock_irq(&priv->ctx_lock);
703 list_del(&dev_ctx->list);
704 spin_unlock_irq(&priv->ctx_lock);
706 intf->remove(dev, dev_ctx->context);
712 static int mlx5_register_device(struct mlx5_core_dev *dev)
714 struct mlx5_priv *priv = &dev->priv;
715 struct mlx5_interface *intf;
717 mutex_lock(&intf_mutex);
718 list_add_tail(&priv->dev_list, &dev_list);
719 list_for_each_entry(intf, &intf_list, list)
720 mlx5_add_device(intf, priv);
721 mutex_unlock(&intf_mutex);
726 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
728 struct mlx5_priv *priv = &dev->priv;
729 struct mlx5_interface *intf;
731 mutex_lock(&intf_mutex);
732 list_for_each_entry(intf, &intf_list, list)
733 mlx5_remove_device(intf, priv);
734 list_del(&priv->dev_list);
735 mutex_unlock(&intf_mutex);
738 int mlx5_register_interface(struct mlx5_interface *intf)
740 struct mlx5_priv *priv;
742 if (!intf->add || !intf->remove)
745 mutex_lock(&intf_mutex);
746 list_add_tail(&intf->list, &intf_list);
747 list_for_each_entry(priv, &dev_list, dev_list)
748 mlx5_add_device(intf, priv);
749 mutex_unlock(&intf_mutex);
753 EXPORT_SYMBOL(mlx5_register_interface);
755 void mlx5_unregister_interface(struct mlx5_interface *intf)
757 struct mlx5_priv *priv;
759 mutex_lock(&intf_mutex);
760 list_for_each_entry(priv, &dev_list, dev_list)
761 mlx5_remove_device(intf, priv);
762 list_del(&intf->list);
763 mutex_unlock(&intf_mutex);
765 EXPORT_SYMBOL(mlx5_unregister_interface);
767 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
769 struct mlx5_priv *priv = &mdev->priv;
770 struct mlx5_device_context *dev_ctx;
774 spin_lock_irqsave(&priv->ctx_lock, flags);
776 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
777 if ((dev_ctx->intf->protocol == protocol) &&
778 dev_ctx->intf->get_dev) {
779 result = dev_ctx->intf->get_dev(dev_ctx->context);
783 spin_unlock_irqrestore(&priv->ctx_lock, flags);
787 EXPORT_SYMBOL(mlx5_get_protocol_dev);
789 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
791 struct pci_dev *pdev = dev->pdev;
794 pci_set_drvdata(dev->pdev, dev);
795 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
796 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
798 mutex_init(&priv->pgdir_mutex);
799 INIT_LIST_HEAD(&priv->pgdir_list);
800 spin_lock_init(&priv->mkey_lock);
802 mutex_init(&priv->alloc_mutex);
804 priv->numa_node = dev_to_node(&dev->pdev->dev);
806 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
810 err = pci_enable_device(pdev);
812 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
816 err = request_bar(pdev);
818 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
822 pci_set_master(pdev);
824 err = set_dma_caps(pdev);
826 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
830 dev->iseg_base = pci_resource_start(dev->pdev, 0);
831 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
834 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
841 pci_clear_master(dev->pdev);
842 release_bar(dev->pdev);
844 pci_disable_device(dev->pdev);
847 debugfs_remove(priv->dbg_root);
851 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
854 pci_clear_master(dev->pdev);
855 release_bar(dev->pdev);
856 pci_disable_device(dev->pdev);
857 debugfs_remove(priv->dbg_root);
860 #define MLX5_IB_MOD "mlx5_ib"
861 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
863 struct pci_dev *pdev = dev->pdev;
866 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
867 fw_rev_min(dev), fw_rev_sub(dev));
869 err = mlx5_cmd_init(dev);
871 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
875 mlx5_pagealloc_init(dev);
877 err = mlx5_core_enable_hca(dev);
879 dev_err(&pdev->dev, "enable hca failed\n");
880 goto err_pagealloc_cleanup;
883 #ifdef CONFIG_MLX5_CORE_EN
884 err = mlx5_core_set_issi(dev);
886 dev_err(&pdev->dev, "failed to set issi\n");
887 goto err_disable_hca;
891 err = mlx5_satisfy_startup_pages(dev, 1);
893 dev_err(&pdev->dev, "failed to allocate boot pages\n");
894 goto err_disable_hca;
897 err = set_hca_ctrl(dev);
899 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
900 goto reclaim_boot_pages;
903 err = handle_hca_cap(dev);
905 dev_err(&pdev->dev, "handle_hca_cap failed\n");
906 goto reclaim_boot_pages;
909 err = mlx5_satisfy_startup_pages(dev, 0);
911 dev_err(&pdev->dev, "failed to allocate init pages\n");
912 goto reclaim_boot_pages;
915 err = mlx5_pagealloc_start(dev);
917 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
918 goto reclaim_boot_pages;
921 err = mlx5_cmd_init_hca(dev);
923 dev_err(&pdev->dev, "init hca failed\n");
924 goto err_pagealloc_stop;
927 mlx5_start_health_poll(dev);
929 err = mlx5_query_hca_caps(dev);
931 dev_err(&pdev->dev, "query hca failed\n");
935 err = mlx5_query_board_id(dev);
937 dev_err(&pdev->dev, "query board id failed\n");
941 err = mlx5_enable_msix(dev);
943 dev_err(&pdev->dev, "enable msix failed\n");
947 err = mlx5_eq_init(dev);
949 dev_err(&pdev->dev, "failed to initialize eq\n");
953 err = mlx5_alloc_uuars(dev, &priv->uuari);
955 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
959 err = mlx5_start_eqs(dev);
961 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
965 err = alloc_comp_eqs(dev);
967 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
971 if (map_bf_area(dev))
972 dev_err(&pdev->dev, "Failed to map blue flame area\n");
974 err = mlx5_irq_set_affinity_hints(dev);
976 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
977 goto err_unmap_bf_area;
980 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
982 mlx5_init_cq_table(dev);
983 mlx5_init_qp_table(dev);
984 mlx5_init_srq_table(dev);
985 mlx5_init_mr_table(dev);
987 err = mlx5_register_device(dev);
989 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
993 err = request_module_nowait(MLX5_IB_MOD);
995 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1000 mlx5_cleanup_mr_table(dev);
1001 mlx5_cleanup_srq_table(dev);
1002 mlx5_cleanup_qp_table(dev);
1003 mlx5_cleanup_cq_table(dev);
1004 mlx5_irq_clear_affinity_hints(dev);
1015 mlx5_free_uuars(dev, &priv->uuari);
1018 mlx5_eq_cleanup(dev);
1021 mlx5_disable_msix(dev);
1024 mlx5_stop_health_poll(dev);
1025 if (mlx5_cmd_teardown_hca(dev)) {
1026 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1031 mlx5_pagealloc_stop(dev);
1034 mlx5_reclaim_startup_pages(dev);
1037 mlx5_core_disable_hca(dev);
1039 err_pagealloc_cleanup:
1040 mlx5_pagealloc_cleanup(dev);
1041 mlx5_cmd_cleanup(dev);
1046 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1050 mlx5_unregister_device(dev);
1051 mlx5_cleanup_mr_table(dev);
1052 mlx5_cleanup_srq_table(dev);
1053 mlx5_cleanup_qp_table(dev);
1054 mlx5_cleanup_cq_table(dev);
1055 mlx5_irq_clear_affinity_hints(dev);
1059 mlx5_free_uuars(dev, &priv->uuari);
1060 mlx5_eq_cleanup(dev);
1061 mlx5_disable_msix(dev);
1062 mlx5_stop_health_poll(dev);
1063 err = mlx5_cmd_teardown_hca(dev);
1065 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1068 mlx5_pagealloc_stop(dev);
1069 mlx5_reclaim_startup_pages(dev);
1070 mlx5_core_disable_hca(dev);
1071 mlx5_pagealloc_cleanup(dev);
1072 mlx5_cmd_cleanup(dev);
1078 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1079 unsigned long param)
1081 struct mlx5_priv *priv = &dev->priv;
1082 struct mlx5_device_context *dev_ctx;
1083 unsigned long flags;
1085 spin_lock_irqsave(&priv->ctx_lock, flags);
1087 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1088 if (dev_ctx->intf->event)
1089 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1091 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1094 struct mlx5_core_event_handler {
1095 void (*event)(struct mlx5_core_dev *dev,
1096 enum mlx5_dev_event event,
1101 static int init_one(struct pci_dev *pdev,
1102 const struct pci_device_id *id)
1104 struct mlx5_core_dev *dev;
1105 struct mlx5_priv *priv;
1108 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1110 dev_err(&pdev->dev, "kzalloc failed\n");
1115 pci_set_drvdata(pdev, dev);
1117 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1118 pr_warn("selected profile out of range, selecting default (%d)\n",
1120 prof_sel = MLX5_DEFAULT_PROF;
1122 dev->profile = &profile[prof_sel];
1124 dev->event = mlx5_core_event;
1126 INIT_LIST_HEAD(&priv->ctx_list);
1127 spin_lock_init(&priv->ctx_lock);
1128 err = mlx5_pci_init(dev, priv);
1130 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1134 err = mlx5_health_init(dev);
1136 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1140 err = mlx5_load_one(dev, priv);
1142 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1149 mlx5_health_cleanup(dev);
1151 mlx5_pci_close(dev, priv);
1153 pci_set_drvdata(pdev, NULL);
1159 static void remove_one(struct pci_dev *pdev)
1161 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1162 struct mlx5_priv *priv = &dev->priv;
1164 if (mlx5_unload_one(dev, priv)) {
1165 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1166 mlx5_health_cleanup(dev);
1169 mlx5_health_cleanup(dev);
1170 mlx5_pci_close(dev, priv);
1171 pci_set_drvdata(pdev, NULL);
1175 static const struct pci_device_id mlx5_core_pci_table[] = {
1176 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1177 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1178 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1179 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1180 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1181 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1185 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1187 static struct pci_driver mlx5_core_driver = {
1188 .name = DRIVER_NAME,
1189 .id_table = mlx5_core_pci_table,
1191 .remove = remove_one
1194 static int __init init(void)
1198 mlx5_register_debugfs();
1200 err = pci_register_driver(&mlx5_core_driver);
1204 #ifdef CONFIG_MLX5_CORE_EN
1211 mlx5_unregister_debugfs();
1215 static void __exit cleanup(void)
1217 #ifdef CONFIG_MLX5_CORE_EN
1220 pci_unregister_driver(&mlx5_core_driver);
1221 mlx5_unregister_debugfs();
1225 module_exit(cleanup);