2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/qp.h>
44 #include <linux/mlx5/srq.h>
45 #include <linux/debugfs.h>
46 #include "mlx5_core.h"
48 #define DRIVER_NAME "mlx5_core"
49 #define DRIVER_VERSION "2.2-1"
50 #define DRIVER_RELDATE "Feb 2014"
52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53 MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
54 MODULE_LICENSE("Dual BSD/GPL");
55 MODULE_VERSION(DRIVER_VERSION);
57 int mlx5_core_debug_mask;
58 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
59 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61 struct workqueue_struct *mlx5_core_wq;
63 static int set_dma_caps(struct pci_dev *pdev)
67 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
69 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
70 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
77 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
80 "Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
81 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
84 "Can't set consistent PCI DMA mask, aborting.\n");
89 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
93 static int request_bar(struct pci_dev *pdev)
97 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
98 dev_err(&pdev->dev, "Missing registers BAR, aborting.\n");
102 err = pci_request_regions(pdev, DRIVER_NAME);
104 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
109 static void release_bar(struct pci_dev *pdev)
111 pci_release_regions(pdev);
114 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
116 struct mlx5_eq_table *table = &dev->priv.eq_table;
117 int num_eqs = 1 << dev->caps.log_max_eq;
121 nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
122 nvec = min_t(int, nvec, num_eqs);
123 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
126 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
127 if (!table->msix_arr)
130 for (i = 0; i < nvec; i++)
131 table->msix_arr[i].entry = i;
133 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
134 MLX5_EQ_VEC_COMP_BASE, nvec);
138 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
143 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
145 struct mlx5_eq_table *table = &dev->priv.eq_table;
147 pci_disable_msix(dev->pdev);
148 kfree(table->msix_arr);
151 struct mlx5_reg_host_endianess {
157 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
160 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
161 CAP_MASK(MLX5_CAP_OFF_DCT, 1),
164 /* selectively copy writable fields clearing any reserved area
166 static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from)
170 to->log_max_qp = from->log_max_qp & 0x1f;
171 to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f;
172 to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f;
173 to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f;
174 to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f;
175 to->log_max_atomic_size_qp = from->log_max_atomic_size_qp;
176 to->log_max_atomic_size_dc = from->log_max_atomic_size_dc;
177 v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK;
178 to->flags = cpu_to_be64(v64);
182 HCA_CAP_OPMOD_GET_MAX = 0,
183 HCA_CAP_OPMOD_GET_CUR = 1,
186 static int handle_hca_cap(struct mlx5_core_dev *dev)
188 struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
189 struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
190 struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
191 struct mlx5_cmd_set_hca_cap_mbox_out set_out;
195 memset(&query_ctx, 0, sizeof(query_ctx));
196 query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
200 set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
206 query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
207 query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR);
208 err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
209 query_out, sizeof(*query_out));
213 err = mlx5_cmd_status_to_err(&query_out->hdr);
215 mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
219 copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap);
221 if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
222 set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
224 flags = be64_to_cpu(query_out->hca_cap.flags);
225 /* disable checksum */
226 flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
228 set_ctx->hca_cap.flags = cpu_to_be64(flags);
229 memset(&set_out, 0, sizeof(set_out));
230 set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
231 set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
232 err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
233 &set_out, sizeof(set_out));
235 mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
239 err = mlx5_cmd_status_to_err(&set_out.hdr);
250 static int set_hca_ctrl(struct mlx5_core_dev *dev)
252 struct mlx5_reg_host_endianess he_in;
253 struct mlx5_reg_host_endianess he_out;
256 memset(&he_in, 0, sizeof(he_in));
257 he_in.he = MLX5_SET_HOST_ENDIANNESS;
258 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
259 &he_out, sizeof(he_out),
260 MLX5_REG_HOST_ENDIANNESS, 0, 1);
264 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
267 struct mlx5_enable_hca_mbox_in in;
268 struct mlx5_enable_hca_mbox_out out;
270 memset(&in, 0, sizeof(in));
271 memset(&out, 0, sizeof(out));
272 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
273 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
278 return mlx5_cmd_status_to_err(&out.hdr);
283 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
286 struct mlx5_disable_hca_mbox_in in;
287 struct mlx5_disable_hca_mbox_out out;
289 memset(&in, 0, sizeof(in));
290 memset(&out, 0, sizeof(out));
291 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
292 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
297 return mlx5_cmd_status_to_err(&out.hdr);
302 int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
304 struct mlx5_priv *priv = &dev->priv;
308 pci_set_drvdata(dev->pdev, dev);
309 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
310 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
312 mutex_init(&priv->pgdir_mutex);
313 INIT_LIST_HEAD(&priv->pgdir_list);
314 spin_lock_init(&priv->mkey_lock);
316 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
320 err = pci_enable_device(pdev);
322 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
326 err = request_bar(pdev);
328 dev_err(&pdev->dev, "error requesting BARs, aborting.\n");
332 pci_set_master(pdev);
334 err = set_dma_caps(pdev);
336 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
340 dev->iseg_base = pci_resource_start(dev->pdev, 0);
341 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
344 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
347 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
348 fw_rev_min(dev), fw_rev_sub(dev));
350 err = mlx5_cmd_init(dev);
352 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
356 mlx5_pagealloc_init(dev);
358 err = mlx5_core_enable_hca(dev);
360 dev_err(&pdev->dev, "enable hca failed\n");
361 goto err_pagealloc_cleanup;
364 err = mlx5_satisfy_startup_pages(dev, 1);
366 dev_err(&pdev->dev, "failed to allocate boot pages\n");
367 goto err_disable_hca;
370 err = set_hca_ctrl(dev);
372 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
373 goto reclaim_boot_pages;
376 err = handle_hca_cap(dev);
378 dev_err(&pdev->dev, "handle_hca_cap failed\n");
379 goto reclaim_boot_pages;
382 err = mlx5_satisfy_startup_pages(dev, 0);
384 dev_err(&pdev->dev, "failed to allocate init pages\n");
385 goto reclaim_boot_pages;
388 err = mlx5_pagealloc_start(dev);
390 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
391 goto reclaim_boot_pages;
394 err = mlx5_cmd_init_hca(dev);
396 dev_err(&pdev->dev, "init hca failed\n");
397 goto err_pagealloc_stop;
400 mlx5_start_health_poll(dev);
402 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
404 dev_err(&pdev->dev, "query hca failed\n");
408 err = mlx5_cmd_query_adapter(dev);
410 dev_err(&pdev->dev, "query adapter failed\n");
414 err = mlx5_enable_msix(dev);
416 dev_err(&pdev->dev, "enable msix failed\n");
420 err = mlx5_eq_init(dev);
422 dev_err(&pdev->dev, "failed to initialize eq\n");
426 err = mlx5_alloc_uuars(dev, &priv->uuari);
428 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
432 err = mlx5_start_eqs(dev);
434 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
438 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
440 mlx5_init_cq_table(dev);
441 mlx5_init_qp_table(dev);
442 mlx5_init_srq_table(dev);
443 mlx5_init_mr_table(dev);
448 mlx5_free_uuars(dev, &priv->uuari);
451 mlx5_eq_cleanup(dev);
454 mlx5_disable_msix(dev);
457 mlx5_stop_health_poll(dev);
458 if (mlx5_cmd_teardown_hca(dev)) {
459 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
464 mlx5_pagealloc_stop(dev);
467 mlx5_reclaim_startup_pages(dev);
470 mlx5_core_disable_hca(dev);
472 err_pagealloc_cleanup:
473 mlx5_pagealloc_cleanup(dev);
474 mlx5_cmd_cleanup(dev);
480 pci_clear_master(dev->pdev);
481 release_bar(dev->pdev);
484 pci_disable_device(dev->pdev);
487 debugfs_remove(priv->dbg_root);
490 EXPORT_SYMBOL(mlx5_dev_init);
492 void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
494 struct mlx5_priv *priv = &dev->priv;
496 mlx5_cleanup_srq_table(dev);
497 mlx5_cleanup_qp_table(dev);
498 mlx5_cleanup_cq_table(dev);
500 mlx5_free_uuars(dev, &priv->uuari);
501 mlx5_eq_cleanup(dev);
502 mlx5_disable_msix(dev);
503 mlx5_stop_health_poll(dev);
504 if (mlx5_cmd_teardown_hca(dev)) {
505 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
508 mlx5_pagealloc_stop(dev);
509 mlx5_reclaim_startup_pages(dev);
510 mlx5_core_disable_hca(dev);
511 mlx5_pagealloc_cleanup(dev);
512 mlx5_cmd_cleanup(dev);
514 pci_clear_master(dev->pdev);
515 release_bar(dev->pdev);
516 pci_disable_device(dev->pdev);
517 debugfs_remove(priv->dbg_root);
519 EXPORT_SYMBOL(mlx5_dev_cleanup);
521 static int __init init(void)
525 mlx5_register_debugfs();
526 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
536 mlx5_unregister_debugfs();
540 static void __exit cleanup(void)
542 mlx5_health_cleanup();
543 destroy_workqueue(mlx5_core_wq);
544 mlx5_unregister_debugfs();
548 module_exit(cleanup);