2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
63 #include "fpga/core.h"
64 #include "fpga/ipsec.h"
65 #include "accel/ipsec.h"
66 #include "accel/tls.h"
67 #include "lib/clock.h"
68 #include "lib/vxlan.h"
69 #include "lib/geneve.h"
70 #include "lib/devcom.h"
71 #include "lib/pci_vsc.h"
72 #include "diag/fw_tracer.h"
74 #include "lib/hv_vhca.h"
75 #include "diag/rsc_dump.h"
77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
79 MODULE_LICENSE("Dual BSD/GPL");
81 unsigned int mlx5_core_debug_mask;
82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85 #define MLX5_DEFAULT_PROF 2
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
90 static u32 sw_owner_id[4];
93 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
94 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 static struct mlx5_profile profile[] = {
102 .mask = MLX5_PROF_MASK_QP_SIZE,
106 .mask = MLX5_PROF_MASK_QP_SIZE |
107 MLX5_PROF_MASK_MR_CACHE,
176 #define FW_INIT_TIMEOUT_MILI 2000
177 #define FW_INIT_WAIT_MS 2
178 #define FW_PRE_INIT_TIMEOUT_MILI 120000
179 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
181 static int fw_initializing(struct mlx5_core_dev *dev)
183 return ioread32be(&dev->iseg->initializing) >> 31;
186 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
189 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
190 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
193 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
195 while (fw_initializing(dev)) {
196 if (time_after(jiffies, end)) {
200 if (warn_time_mili && time_after(jiffies, warn)) {
201 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
202 jiffies_to_msecs(end - warn) / 1000);
203 warn = jiffies + msecs_to_jiffies(warn_time_mili);
205 msleep(FW_INIT_WAIT_MS);
211 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
213 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
215 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
216 int remaining_size = driver_ver_sz;
219 if (!MLX5_CAP_GEN(dev, driver_version))
222 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
224 strncpy(string, "Linux", remaining_size);
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, KBUILD_MODNAME, remaining_size);
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
233 strncat(string, ",", remaining_size);
235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
237 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
238 (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff),
239 (u16)(LINUX_VERSION_CODE & 0xffff));
242 MLX5_SET(set_driver_version_in, in, opcode,
243 MLX5_CMD_OP_SET_DRIVER_VERSION);
245 mlx5_cmd_exec_in(dev, set_driver_version, in);
248 static int set_dma_caps(struct pci_dev *pdev)
252 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
254 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
255 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
257 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
262 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
265 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
266 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
269 "Can't set consistent PCI DMA mask, aborting\n");
274 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
278 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
280 struct pci_dev *pdev = dev->pdev;
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
285 err = pci_enable_device(pdev);
287 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
289 mutex_unlock(&dev->pci_status_mutex);
294 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
296 struct pci_dev *pdev = dev->pdev;
298 mutex_lock(&dev->pci_status_mutex);
299 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
300 pci_disable_device(pdev);
301 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
303 mutex_unlock(&dev->pci_status_mutex);
306 static int request_bar(struct pci_dev *pdev)
310 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
311 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
315 err = pci_request_regions(pdev, KBUILD_MODNAME);
317 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
322 static void release_bar(struct pci_dev *pdev)
324 pci_release_regions(pdev);
327 struct mlx5_reg_host_endianness {
332 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
335 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
336 MLX5_DEV_CAP_FLAG_DCT,
339 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
355 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
360 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
361 enum mlx5_cap_type cap_type,
362 enum mlx5_cap_mode cap_mode)
364 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
365 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
366 void *out, *hca_caps;
367 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
370 memset(in, 0, sizeof(in));
371 out = kzalloc(out_sz, GFP_KERNEL);
375 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
376 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
377 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
380 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
381 cap_type, cap_mode, err);
385 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
388 case HCA_CAP_OPMOD_GET_MAX:
389 memcpy(dev->caps.hca_max[cap_type], hca_caps,
390 MLX5_UN_SZ_BYTES(hca_cap_union));
392 case HCA_CAP_OPMOD_GET_CUR:
393 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
394 MLX5_UN_SZ_BYTES(hca_cap_union));
398 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
408 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
412 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
415 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
418 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
420 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
421 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
422 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
425 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
431 if (!MLX5_CAP_GEN(dev, atomic))
434 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
440 supported_atomic_req_8B_endianness_mode_1);
442 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
445 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
447 /* Set requestor to host endianness */
448 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
449 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
451 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
454 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
460 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
461 !MLX5_CAP_GEN(dev, pg))
464 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
468 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
469 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
470 MLX5_ST_SZ_BYTES(odp_cap));
472 #define ODP_CAP_SET_MAX(dev, field) \
474 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
477 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
481 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
482 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
489 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
490 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
492 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
499 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
502 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
504 struct mlx5_profile *prof = dev->profile;
508 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
512 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
514 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
515 MLX5_ST_SZ_BYTES(cmd_hca_cap));
517 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
518 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
520 /* we limit the size of the pkey table to 128 entries for now */
521 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
522 to_fw_pkey_sz(dev, 128));
524 /* Check log_max_qp from HCA caps to set in current profile */
525 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
526 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
527 profile[prof_sel].log_max_qp,
528 MLX5_CAP_GEN_MAX(dev, log_max_qp));
529 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
531 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
532 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
535 /* disable cmdif checksum */
536 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
538 /* Enable 4K UAR only when HCA supports it and page size is bigger
541 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
542 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
544 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
546 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
547 MLX5_SET(cmd_hca_cap,
550 cache_line_size() >= 128 ? 1 : 0);
552 if (MLX5_CAP_GEN_MAX(dev, dct))
553 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
555 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
556 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
558 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
559 MLX5_SET(cmd_hca_cap,
562 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
564 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
565 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
567 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
568 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
570 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
573 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
578 if (!MLX5_CAP_GEN(dev, roce))
581 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
585 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
586 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
589 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
590 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
591 MLX5_ST_SZ_BYTES(roce_cap));
592 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
594 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
598 static int set_hca_cap(struct mlx5_core_dev *dev)
600 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
604 set_ctx = kzalloc(set_sz, GFP_KERNEL);
608 err = handle_hca_cap(dev, set_ctx);
610 mlx5_core_err(dev, "handle_hca_cap failed\n");
614 memset(set_ctx, 0, set_sz);
615 err = handle_hca_cap_atomic(dev, set_ctx);
617 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
621 memset(set_ctx, 0, set_sz);
622 err = handle_hca_cap_odp(dev, set_ctx);
624 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
628 memset(set_ctx, 0, set_sz);
629 err = handle_hca_cap_roce(dev, set_ctx);
631 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
640 static int set_hca_ctrl(struct mlx5_core_dev *dev)
642 struct mlx5_reg_host_endianness he_in;
643 struct mlx5_reg_host_endianness he_out;
646 if (!mlx5_core_is_pf(dev))
649 memset(&he_in, 0, sizeof(he_in));
650 he_in.he = MLX5_SET_HOST_ENDIANNESS;
651 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
652 &he_out, sizeof(he_out),
653 MLX5_REG_HOST_ENDIANNESS, 0, 1);
657 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
661 /* Disable local_lb by default */
662 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
663 ret = mlx5_nic_vport_update_local_lb(dev, false);
668 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
670 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
672 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
673 MLX5_SET(enable_hca_in, in, function_id, func_id);
674 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
675 dev->caps.embedded_cpu);
676 return mlx5_cmd_exec_in(dev, enable_hca, in);
679 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
681 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
683 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
684 MLX5_SET(disable_hca_in, in, function_id, func_id);
685 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
686 dev->caps.embedded_cpu);
687 return mlx5_cmd_exec_in(dev, disable_hca, in);
690 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
692 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
693 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
697 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
698 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
703 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
704 if (!status || syndrome == MLX5_DRIVER_SYND) {
705 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
706 err, status, syndrome);
710 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
715 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
717 if (sup_issi & (1 << 1)) {
718 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
720 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
721 MLX5_SET(set_issi_in, set_in, current_issi, 1);
722 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
724 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
732 } else if (sup_issi & (1 << 0) || !sup_issi) {
739 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
740 const struct pci_device_id *id)
742 struct mlx5_priv *priv = &dev->priv;
745 mutex_init(&dev->pci_status_mutex);
746 pci_set_drvdata(dev->pdev, dev);
748 dev->bar_addr = pci_resource_start(pdev, 0);
749 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
751 err = mlx5_pci_enable_device(dev);
753 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
757 err = request_bar(pdev);
759 mlx5_core_err(dev, "error requesting BARs, aborting\n");
763 pci_set_master(pdev);
765 err = set_dma_caps(pdev);
767 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
771 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
774 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
776 dev->iseg_base = dev->bar_addr;
777 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
780 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
784 mlx5_pci_vsc_init(dev);
785 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
789 pci_clear_master(dev->pdev);
790 release_bar(dev->pdev);
792 mlx5_pci_disable_device(dev);
796 static void mlx5_pci_close(struct mlx5_core_dev *dev)
798 /* health work might still be active, and it needs pci bar in
799 * order to know the NIC state. Therefore, drain the health WQ
800 * before removing the pci bars
802 mlx5_drain_health_wq(dev);
804 pci_clear_master(dev->pdev);
805 release_bar(dev->pdev);
806 mlx5_pci_disable_device(dev);
809 static int mlx5_init_once(struct mlx5_core_dev *dev)
813 dev->priv.devcom = mlx5_devcom_register_device(dev);
814 if (IS_ERR(dev->priv.devcom))
815 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
818 err = mlx5_query_board_id(dev);
820 mlx5_core_err(dev, "query board id failed\n");
824 err = mlx5_irq_table_init(dev);
826 mlx5_core_err(dev, "failed to initialize irq table\n");
830 err = mlx5_eq_table_init(dev);
832 mlx5_core_err(dev, "failed to initialize eq\n");
833 goto err_irq_cleanup;
836 err = mlx5_events_init(dev);
838 mlx5_core_err(dev, "failed to initialize events\n");
842 err = mlx5_fw_reset_init(dev);
844 mlx5_core_err(dev, "failed to initialize fw reset events\n");
845 goto err_events_cleanup;
848 mlx5_cq_debugfs_init(dev);
850 mlx5_init_reserved_gids(dev);
852 mlx5_init_clock(dev);
854 dev->vxlan = mlx5_vxlan_create(dev);
855 dev->geneve = mlx5_geneve_create(dev);
857 err = mlx5_init_rl_table(dev);
859 mlx5_core_err(dev, "Failed to init rate limiting\n");
860 goto err_tables_cleanup;
863 err = mlx5_mpfs_init(dev);
865 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
869 err = mlx5_sriov_init(dev);
871 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
872 goto err_mpfs_cleanup;
875 err = mlx5_eswitch_init(dev);
877 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
878 goto err_sriov_cleanup;
881 err = mlx5_fpga_init(dev);
883 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
884 goto err_eswitch_cleanup;
887 dev->dm = mlx5_dm_create(dev);
889 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
891 dev->tracer = mlx5_fw_tracer_create(dev);
892 dev->hv_vhca = mlx5_hv_vhca_create(dev);
893 dev->rsc_dump = mlx5_rsc_dump_create(dev);
898 mlx5_eswitch_cleanup(dev->priv.eswitch);
900 mlx5_sriov_cleanup(dev);
902 mlx5_mpfs_cleanup(dev);
904 mlx5_cleanup_rl_table(dev);
906 mlx5_geneve_destroy(dev->geneve);
907 mlx5_vxlan_destroy(dev->vxlan);
908 mlx5_cq_debugfs_cleanup(dev);
909 mlx5_fw_reset_cleanup(dev);
911 mlx5_events_cleanup(dev);
913 mlx5_eq_table_cleanup(dev);
915 mlx5_irq_table_cleanup(dev);
917 mlx5_devcom_unregister_device(dev->priv.devcom);
922 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
924 mlx5_rsc_dump_destroy(dev);
925 mlx5_hv_vhca_destroy(dev->hv_vhca);
926 mlx5_fw_tracer_destroy(dev->tracer);
927 mlx5_dm_cleanup(dev);
928 mlx5_fpga_cleanup(dev);
929 mlx5_eswitch_cleanup(dev->priv.eswitch);
930 mlx5_sriov_cleanup(dev);
931 mlx5_mpfs_cleanup(dev);
932 mlx5_cleanup_rl_table(dev);
933 mlx5_geneve_destroy(dev->geneve);
934 mlx5_vxlan_destroy(dev->vxlan);
935 mlx5_cleanup_clock(dev);
936 mlx5_cleanup_reserved_gids(dev);
937 mlx5_cq_debugfs_cleanup(dev);
938 mlx5_fw_reset_cleanup(dev);
939 mlx5_events_cleanup(dev);
940 mlx5_eq_table_cleanup(dev);
941 mlx5_irq_table_cleanup(dev);
942 mlx5_devcom_unregister_device(dev->priv.devcom);
945 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
949 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
950 fw_rev_min(dev), fw_rev_sub(dev));
952 /* Only PFs hold the relevant PCIe information for this query */
953 if (mlx5_core_is_pf(dev))
954 pcie_print_link_status(dev->pdev);
956 /* wait for firmware to accept initialization segments configurations
958 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
960 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
961 FW_PRE_INIT_TIMEOUT_MILI);
965 err = mlx5_cmd_init(dev);
967 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
971 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
973 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
974 FW_INIT_TIMEOUT_MILI);
975 goto err_cmd_cleanup;
978 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
980 err = mlx5_core_enable_hca(dev, 0);
982 mlx5_core_err(dev, "enable hca failed\n");
983 goto err_cmd_cleanup;
986 err = mlx5_core_set_issi(dev);
988 mlx5_core_err(dev, "failed to set issi\n");
989 goto err_disable_hca;
992 err = mlx5_satisfy_startup_pages(dev, 1);
994 mlx5_core_err(dev, "failed to allocate boot pages\n");
995 goto err_disable_hca;
998 err = set_hca_ctrl(dev);
1000 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1001 goto reclaim_boot_pages;
1004 err = set_hca_cap(dev);
1006 mlx5_core_err(dev, "set_hca_cap failed\n");
1007 goto reclaim_boot_pages;
1010 err = mlx5_satisfy_startup_pages(dev, 0);
1012 mlx5_core_err(dev, "failed to allocate init pages\n");
1013 goto reclaim_boot_pages;
1016 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1018 mlx5_core_err(dev, "init hca failed\n");
1019 goto reclaim_boot_pages;
1022 mlx5_set_driver_version(dev);
1024 mlx5_start_health_poll(dev);
1026 err = mlx5_query_hca_caps(dev);
1028 mlx5_core_err(dev, "query hca failed\n");
1035 mlx5_stop_health_poll(dev, boot);
1037 mlx5_reclaim_startup_pages(dev);
1039 mlx5_core_disable_hca(dev, 0);
1041 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1042 mlx5_cmd_cleanup(dev);
1047 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1051 mlx5_stop_health_poll(dev, boot);
1052 err = mlx5_cmd_teardown_hca(dev);
1054 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1057 mlx5_reclaim_startup_pages(dev);
1058 mlx5_core_disable_hca(dev, 0);
1059 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1060 mlx5_cmd_cleanup(dev);
1065 static int mlx5_load(struct mlx5_core_dev *dev)
1069 dev->priv.uar = mlx5_get_uars_page(dev);
1070 if (IS_ERR(dev->priv.uar)) {
1071 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1072 err = PTR_ERR(dev->priv.uar);
1076 mlx5_events_start(dev);
1077 mlx5_pagealloc_start(dev);
1079 err = mlx5_irq_table_create(dev);
1081 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1085 err = mlx5_eq_table_create(dev);
1087 mlx5_core_err(dev, "Failed to create EQs\n");
1091 err = mlx5_fw_tracer_init(dev->tracer);
1093 mlx5_core_err(dev, "Failed to init FW tracer\n");
1097 mlx5_fw_reset_events_start(dev);
1098 mlx5_hv_vhca_init(dev->hv_vhca);
1100 err = mlx5_rsc_dump_init(dev);
1102 mlx5_core_err(dev, "Failed to init Resource dump\n");
1106 err = mlx5_fpga_device_start(dev);
1108 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1109 goto err_fpga_start;
1112 mlx5_accel_ipsec_init(dev);
1114 err = mlx5_accel_tls_init(dev);
1116 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1120 err = mlx5_init_fs(dev);
1122 mlx5_core_err(dev, "Failed to init flow steering\n");
1126 err = mlx5_core_set_hca_defaults(dev);
1128 mlx5_core_err(dev, "Failed to set hca defaults\n");
1132 err = mlx5_ec_init(dev);
1134 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1138 err = mlx5_sriov_attach(dev);
1140 mlx5_core_err(dev, "sriov init failed %d\n", err);
1147 mlx5_ec_cleanup(dev);
1149 mlx5_cleanup_fs(dev);
1151 mlx5_accel_tls_cleanup(dev);
1153 mlx5_accel_ipsec_cleanup(dev);
1154 mlx5_fpga_device_stop(dev);
1156 mlx5_rsc_dump_cleanup(dev);
1158 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1159 mlx5_fw_reset_events_stop(dev);
1160 mlx5_fw_tracer_cleanup(dev->tracer);
1162 mlx5_eq_table_destroy(dev);
1164 mlx5_irq_table_destroy(dev);
1166 mlx5_pagealloc_stop(dev);
1167 mlx5_events_stop(dev);
1168 mlx5_put_uars_page(dev, dev->priv.uar);
1172 static void mlx5_unload(struct mlx5_core_dev *dev)
1174 mlx5_sriov_detach(dev);
1175 mlx5_ec_cleanup(dev);
1176 mlx5_cleanup_fs(dev);
1177 mlx5_accel_ipsec_cleanup(dev);
1178 mlx5_accel_tls_cleanup(dev);
1179 mlx5_fpga_device_stop(dev);
1180 mlx5_rsc_dump_cleanup(dev);
1181 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1182 mlx5_fw_reset_events_stop(dev);
1183 mlx5_fw_tracer_cleanup(dev->tracer);
1184 mlx5_eq_table_destroy(dev);
1185 mlx5_irq_table_destroy(dev);
1186 mlx5_pagealloc_stop(dev);
1187 mlx5_events_stop(dev);
1188 mlx5_put_uars_page(dev, dev->priv.uar);
1191 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1195 mutex_lock(&dev->intf_state_mutex);
1196 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1197 mlx5_core_warn(dev, "interface is up, NOP\n");
1200 /* remove any previous indication of internal error */
1201 dev->state = MLX5_DEVICE_STATE_UP;
1203 err = mlx5_function_setup(dev, boot);
1208 err = mlx5_init_once(dev);
1210 mlx5_core_err(dev, "sw objs init failed\n");
1211 goto function_teardown;
1215 err = mlx5_load(dev);
1219 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1222 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1224 goto err_devlink_reg;
1226 err = mlx5_register_device(dev);
1228 err = mlx5_attach_device(dev);
1234 mutex_unlock(&dev->intf_state_mutex);
1239 mlx5_devlink_unregister(priv_to_devlink(dev));
1241 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1245 mlx5_cleanup_once(dev);
1247 mlx5_function_teardown(dev, boot);
1249 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1251 mutex_unlock(&dev->intf_state_mutex);
1255 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1257 mutex_lock(&dev->intf_state_mutex);
1260 mlx5_unregister_device(dev);
1261 mlx5_devlink_unregister(priv_to_devlink(dev));
1263 mlx5_detach_device(dev);
1266 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1267 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1270 mlx5_cleanup_once(dev);
1274 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1279 mlx5_cleanup_once(dev);
1281 mlx5_function_teardown(dev, cleanup);
1283 mutex_unlock(&dev->intf_state_mutex);
1286 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1288 struct mlx5_priv *priv = &dev->priv;
1291 dev->profile = &profile[profile_idx];
1293 INIT_LIST_HEAD(&priv->ctx_list);
1294 spin_lock_init(&priv->ctx_lock);
1295 mutex_init(&dev->intf_state_mutex);
1297 mutex_init(&priv->bfregs.reg_head.lock);
1298 mutex_init(&priv->bfregs.wc_head.lock);
1299 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1300 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1302 mutex_init(&priv->alloc_mutex);
1303 mutex_init(&priv->pgdir_mutex);
1304 INIT_LIST_HEAD(&priv->pgdir_list);
1306 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1308 err = mlx5_health_init(dev);
1310 goto err_health_init;
1312 err = mlx5_pagealloc_init(dev);
1314 goto err_pagealloc_init;
1316 err = mlx5_adev_init(dev);
1323 mlx5_pagealloc_cleanup(dev);
1325 mlx5_health_cleanup(dev);
1327 debugfs_remove(dev->priv.dbg_root);
1328 mutex_destroy(&priv->pgdir_mutex);
1329 mutex_destroy(&priv->alloc_mutex);
1330 mutex_destroy(&priv->bfregs.wc_head.lock);
1331 mutex_destroy(&priv->bfregs.reg_head.lock);
1332 mutex_destroy(&dev->intf_state_mutex);
1336 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1338 struct mlx5_priv *priv = &dev->priv;
1340 mlx5_adev_cleanup(dev);
1341 mlx5_pagealloc_cleanup(dev);
1342 mlx5_health_cleanup(dev);
1343 debugfs_remove_recursive(dev->priv.dbg_root);
1344 mutex_destroy(&priv->pgdir_mutex);
1345 mutex_destroy(&priv->alloc_mutex);
1346 mutex_destroy(&priv->bfregs.wc_head.lock);
1347 mutex_destroy(&priv->bfregs.reg_head.lock);
1348 mutex_destroy(&dev->intf_state_mutex);
1351 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1353 struct mlx5_core_dev *dev;
1354 struct devlink *devlink;
1357 devlink = mlx5_devlink_alloc();
1359 dev_err(&pdev->dev, "devlink alloc failed\n");
1363 dev = devlink_priv(devlink);
1364 dev->device = &pdev->dev;
1367 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1368 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1370 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1371 if (dev->priv.adev_idx < 0)
1372 return dev->priv.adev_idx;
1374 err = mlx5_mdev_init(dev, prof_sel);
1378 err = mlx5_pci_init(dev, pdev, id);
1380 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1385 err = mlx5_load_one(dev, true);
1387 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1392 err = mlx5_crdump_enable(dev);
1394 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1396 pci_save_state(pdev);
1397 devlink_reload_enable(devlink);
1401 mlx5_pci_close(dev);
1403 mlx5_mdev_uninit(dev);
1405 mlx5_adev_idx_free(dev->priv.adev_idx);
1406 mlx5_devlink_free(devlink);
1411 static void remove_one(struct pci_dev *pdev)
1413 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1414 struct devlink *devlink = priv_to_devlink(dev);
1416 devlink_reload_disable(devlink);
1417 mlx5_crdump_disable(dev);
1418 mlx5_drain_health_wq(dev);
1419 mlx5_unload_one(dev, true);
1420 mlx5_pci_close(dev);
1421 mlx5_mdev_uninit(dev);
1422 mlx5_adev_idx_free(dev->priv.adev_idx);
1423 mlx5_devlink_free(devlink);
1426 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1427 pci_channel_state_t state)
1429 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1431 mlx5_core_info(dev, "%s was called\n", __func__);
1433 mlx5_enter_error_state(dev, false);
1434 mlx5_error_sw_reset(dev);
1435 mlx5_unload_one(dev, false);
1436 mlx5_drain_health_wq(dev);
1437 mlx5_pci_disable_device(dev);
1439 return state == pci_channel_io_perm_failure ?
1440 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1443 /* wait for the device to show vital signs by waiting
1444 * for the health counter to start counting.
1446 static int wait_vital(struct pci_dev *pdev)
1448 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1449 struct mlx5_core_health *health = &dev->priv.health;
1450 const int niter = 100;
1455 for (i = 0; i < niter; i++) {
1456 count = ioread32be(health->health_counter);
1457 if (count && count != 0xffffffff) {
1458 if (last_count && last_count != count) {
1460 "wait vital counter value 0x%x after %d iterations\n",
1472 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1474 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1477 mlx5_core_info(dev, "%s was called\n", __func__);
1479 err = mlx5_pci_enable_device(dev);
1481 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1483 return PCI_ERS_RESULT_DISCONNECT;
1486 pci_set_master(pdev);
1487 pci_restore_state(pdev);
1488 pci_save_state(pdev);
1490 if (wait_vital(pdev)) {
1491 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1492 return PCI_ERS_RESULT_DISCONNECT;
1495 return PCI_ERS_RESULT_RECOVERED;
1498 static void mlx5_pci_resume(struct pci_dev *pdev)
1500 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1503 mlx5_core_info(dev, "%s was called\n", __func__);
1505 err = mlx5_load_one(dev, false);
1507 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1510 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1513 static const struct pci_error_handlers mlx5_err_handler = {
1514 .error_detected = mlx5_pci_err_detected,
1515 .slot_reset = mlx5_pci_slot_reset,
1516 .resume = mlx5_pci_resume
1519 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1521 bool fast_teardown = false, force_teardown = false;
1524 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1525 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1527 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1528 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1530 if (!fast_teardown && !force_teardown)
1533 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1534 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1538 /* Panic tear down fw command will stop the PCI bus communication
1539 * with the HCA, so the health polll is no longer needed.
1541 mlx5_drain_health_wq(dev);
1542 mlx5_stop_health_poll(dev, false);
1544 ret = mlx5_cmd_fast_teardown_hca(dev);
1548 ret = mlx5_cmd_force_teardown_hca(dev);
1552 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1553 mlx5_start_health_poll(dev);
1557 mlx5_enter_error_state(dev, true);
1559 /* Some platforms requiring freeing the IRQ's in the shutdown
1560 * flow. If they aren't freed they can't be allocated after
1561 * kexec. There is no need to cleanup the mlx5_core software
1564 mlx5_core_eq_free_irqs(dev);
1569 static void shutdown(struct pci_dev *pdev)
1571 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1574 mlx5_core_info(dev, "Shutdown was called\n");
1575 err = mlx5_try_fast_unload(dev);
1577 mlx5_unload_one(dev, false);
1578 mlx5_pci_disable_device(dev);
1581 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1583 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1585 mlx5_unload_one(dev, false);
1590 static int mlx5_resume(struct pci_dev *pdev)
1592 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1594 return mlx5_load_one(dev, false);
1597 static const struct pci_device_id mlx5_core_pci_table[] = {
1598 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1599 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1600 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1601 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1602 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1603 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1604 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1605 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1606 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1607 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1608 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1609 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1610 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1611 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1612 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1613 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1614 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1615 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1616 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1617 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1621 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1623 void mlx5_disable_device(struct mlx5_core_dev *dev)
1625 mlx5_error_sw_reset(dev);
1626 mlx5_unload_one(dev, false);
1629 void mlx5_recover_device(struct mlx5_core_dev *dev)
1631 mlx5_pci_disable_device(dev);
1632 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1633 mlx5_pci_resume(dev->pdev);
1636 static struct pci_driver mlx5_core_driver = {
1637 .name = KBUILD_MODNAME,
1638 .id_table = mlx5_core_pci_table,
1640 .remove = remove_one,
1641 .suspend = mlx5_suspend,
1642 .resume = mlx5_resume,
1643 .shutdown = shutdown,
1644 .err_handler = &mlx5_err_handler,
1645 .sriov_configure = mlx5_core_sriov_configure,
1648 static void mlx5_core_verify_params(void)
1650 if (prof_sel >= ARRAY_SIZE(profile)) {
1651 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1653 ARRAY_SIZE(profile) - 1,
1655 prof_sel = MLX5_DEFAULT_PROF;
1659 static int __init init(void)
1663 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1664 "mlx5_core name not in sync with kernel module name");
1666 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1668 mlx5_core_verify_params();
1669 mlx5_fpga_ipsec_build_fs_cmds();
1670 mlx5_register_debugfs();
1672 err = pci_register_driver(&mlx5_core_driver);
1676 #ifdef CONFIG_MLX5_CORE_EN
1679 pci_unregister_driver(&mlx5_core_driver);
1687 mlx5_unregister_debugfs();
1691 static void __exit cleanup(void)
1693 #ifdef CONFIG_MLX5_CORE_EN
1696 pci_unregister_driver(&mlx5_core_driver);
1697 mlx5_unregister_debugfs();
1701 module_exit(cleanup);