2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #include "mlx5_core.h"
53 #ifdef CONFIG_MLX5_CORE_EN
57 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
58 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
59 MODULE_LICENSE("Dual BSD/GPL");
60 MODULE_VERSION(DRIVER_VERSION);
62 int mlx5_core_debug_mask;
63 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
64 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
66 #define MLX5_DEFAULT_PROF 2
67 static int prof_sel = MLX5_DEFAULT_PROF;
68 module_param_named(prof_sel, prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
71 static LIST_HEAD(intf_list);
72 static LIST_HEAD(dev_list);
73 static DEFINE_MUTEX(intf_mutex);
75 struct mlx5_device_context {
76 struct list_head list;
77 struct mlx5_interface *intf;
82 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
83 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
86 static struct mlx5_profile profile[] = {
91 .mask = MLX5_PROF_MASK_QP_SIZE,
95 .mask = MLX5_PROF_MASK_QP_SIZE |
96 MLX5_PROF_MASK_MR_CACHE,
165 #define FW_INIT_TIMEOUT_MILI 2000
166 #define FW_INIT_WAIT_MS 2
168 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
170 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
173 while (fw_initializing(dev)) {
174 if (time_after(jiffies, end)) {
178 msleep(FW_INIT_WAIT_MS);
184 static int set_dma_caps(struct pci_dev *pdev)
188 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
190 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
191 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
193 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
198 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
201 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
205 "Can't set consistent PCI DMA mask, aborting\n");
210 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
214 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
216 struct pci_dev *pdev = dev->pdev;
219 mutex_lock(&dev->pci_status_mutex);
220 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
221 err = pci_enable_device(pdev);
223 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
225 mutex_unlock(&dev->pci_status_mutex);
230 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
232 struct pci_dev *pdev = dev->pdev;
234 mutex_lock(&dev->pci_status_mutex);
235 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
236 pci_disable_device(pdev);
237 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
239 mutex_unlock(&dev->pci_status_mutex);
242 static int request_bar(struct pci_dev *pdev)
246 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
247 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
251 err = pci_request_regions(pdev, DRIVER_NAME);
253 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
258 static void release_bar(struct pci_dev *pdev)
260 pci_release_regions(pdev);
263 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
265 struct mlx5_priv *priv = &dev->priv;
266 struct mlx5_eq_table *table = &priv->eq_table;
267 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
271 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
272 MLX5_EQ_VEC_COMP_BASE;
273 nvec = min_t(int, nvec, num_eqs);
274 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
277 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
279 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
280 if (!priv->msix_arr || !priv->irq_info)
283 for (i = 0; i < nvec; i++)
284 priv->msix_arr[i].entry = i;
286 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
287 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
291 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
296 kfree(priv->irq_info);
297 kfree(priv->msix_arr);
301 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
303 struct mlx5_priv *priv = &dev->priv;
305 pci_disable_msix(dev->pdev);
306 kfree(priv->irq_info);
307 kfree(priv->msix_arr);
310 struct mlx5_reg_host_endianess {
316 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
319 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
320 MLX5_DEV_CAP_FLAG_DCT,
323 static u16 to_fw_pkey_sz(u32 size)
339 pr_warn("invalid pkey table size %d\n", size);
344 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
345 enum mlx5_cap_type cap_type,
346 enum mlx5_cap_mode cap_mode)
348 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
349 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
350 void *out, *hca_caps;
351 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
354 memset(in, 0, sizeof(in));
355 out = kzalloc(out_sz, GFP_KERNEL);
359 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
360 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
361 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
365 err = mlx5_cmd_status_to_err_v2(out);
368 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
369 cap_type, cap_mode, err);
373 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
376 case HCA_CAP_OPMOD_GET_MAX:
377 memcpy(dev->hca_caps_max[cap_type], hca_caps,
378 MLX5_UN_SZ_BYTES(hca_cap_union));
380 case HCA_CAP_OPMOD_GET_CUR:
381 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
382 MLX5_UN_SZ_BYTES(hca_cap_union));
386 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
396 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
400 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
403 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
406 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
408 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
411 memset(out, 0, sizeof(out));
413 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
414 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
415 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
419 err = mlx5_cmd_status_to_err_v2(out);
424 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
428 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
432 if (MLX5_CAP_GEN(dev, atomic)) {
433 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
442 supported_atomic_req_8B_endianess_mode_1);
444 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
447 set_ctx = kzalloc(set_sz, GFP_KERNEL);
451 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
453 /* Set requestor to host endianness */
454 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
455 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
457 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
463 static int handle_hca_cap(struct mlx5_core_dev *dev)
465 void *set_ctx = NULL;
466 struct mlx5_profile *prof = dev->profile;
468 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
471 set_ctx = kzalloc(set_sz, GFP_KERNEL);
475 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
479 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
481 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
482 MLX5_ST_SZ_BYTES(cmd_hca_cap));
484 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
485 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
487 /* we limit the size of the pkey table to 128 entries for now */
488 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
491 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
492 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
495 /* disable cmdif checksum */
496 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
498 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
500 err = set_caps(dev, set_ctx, set_sz,
501 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
508 static int set_hca_ctrl(struct mlx5_core_dev *dev)
510 struct mlx5_reg_host_endianess he_in;
511 struct mlx5_reg_host_endianess he_out;
514 if (!mlx5_core_is_pf(dev))
517 memset(&he_in, 0, sizeof(he_in));
518 he_in.he = MLX5_SET_HOST_ENDIANNESS;
519 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
520 &he_out, sizeof(he_out),
521 MLX5_REG_HOST_ENDIANNESS, 0, 1);
525 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
527 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
528 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
531 memset(in, 0, sizeof(in));
532 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
533 MLX5_SET(enable_hca_in, in, function_id, func_id);
534 memset(out, 0, sizeof(out));
536 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
540 return mlx5_cmd_status_to_err_v2(out);
543 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
545 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
546 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
549 memset(in, 0, sizeof(in));
550 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
551 MLX5_SET(disable_hca_in, in, function_id, func_id);
552 memset(out, 0, sizeof(out));
553 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
557 return mlx5_cmd_status_to_err_v2(out);
560 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
562 u32 timer_h, timer_h1, timer_l;
564 timer_h = ioread32be(&dev->iseg->internal_timer_h);
565 timer_l = ioread32be(&dev->iseg->internal_timer_l);
566 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
567 if (timer_h != timer_h1) /* wrap around */
568 timer_l = ioread32be(&dev->iseg->internal_timer_l);
570 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
573 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
575 struct mlx5_priv *priv = &mdev->priv;
576 struct msix_entry *msix = priv->msix_arr;
577 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
578 int numa_node = priv->numa_node;
581 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
582 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
586 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
587 priv->irq_info[i].mask);
589 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
591 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
599 free_cpumask_var(priv->irq_info[i].mask);
603 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
605 struct mlx5_priv *priv = &mdev->priv;
606 struct msix_entry *msix = priv->msix_arr;
607 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
609 irq_set_affinity_hint(irq, NULL);
610 free_cpumask_var(priv->irq_info[i].mask);
613 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
618 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
619 err = mlx5_irq_set_affinity_hint(mdev, i);
627 for (i--; i >= 0; i--)
628 mlx5_irq_clear_affinity_hint(mdev, i);
633 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
637 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
638 mlx5_irq_clear_affinity_hint(mdev, i);
641 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
644 struct mlx5_eq_table *table = &dev->priv.eq_table;
645 struct mlx5_eq *eq, *n;
648 spin_lock(&table->lock);
649 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
650 if (eq->index == vector) {
657 spin_unlock(&table->lock);
661 EXPORT_SYMBOL(mlx5_vector2eqn);
663 static void free_comp_eqs(struct mlx5_core_dev *dev)
665 struct mlx5_eq_table *table = &dev->priv.eq_table;
666 struct mlx5_eq *eq, *n;
668 spin_lock(&table->lock);
669 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
671 spin_unlock(&table->lock);
672 if (mlx5_destroy_unmap_eq(dev, eq))
673 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
676 spin_lock(&table->lock);
678 spin_unlock(&table->lock);
681 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
683 struct mlx5_eq_table *table = &dev->priv.eq_table;
684 char name[MLX5_MAX_IRQ_NAME];
691 INIT_LIST_HEAD(&table->comp_eqs_list);
692 ncomp_vec = table->num_comp_vectors;
693 nent = MLX5_COMP_EQ_SIZE;
694 for (i = 0; i < ncomp_vec; i++) {
695 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
701 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
702 err = mlx5_create_map_eq(dev, eq,
703 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
704 name, &dev->priv.uuari.uars[0]);
709 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
711 spin_lock(&table->lock);
712 list_add_tail(&eq->list, &table->comp_eqs_list);
713 spin_unlock(&table->lock);
723 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
725 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
726 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
727 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
728 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
732 memset(query_in, 0, sizeof(query_in));
733 memset(query_out, 0, sizeof(query_out));
735 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
737 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
738 query_out, sizeof(query_out));
740 if (((struct mlx5_outbox_hdr *)query_out)->status ==
741 MLX5_CMD_STAT_BAD_OP_ERR) {
742 pr_debug("Only ISSI 0 is supported\n");
746 pr_err("failed to query ISSI\n");
750 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
752 if (sup_issi & (1 << 1)) {
753 memset(set_in, 0, sizeof(set_in));
754 memset(set_out, 0, sizeof(set_out));
756 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
757 MLX5_SET(set_issi_in, set_in, current_issi, 1);
759 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
760 set_out, sizeof(set_out));
762 pr_err("failed to set ISSI=1\n");
769 } else if (sup_issi & (1 << 0) || !sup_issi) {
776 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
778 struct mlx5_device_context *dev_ctx;
779 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
781 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
785 dev_ctx->intf = intf;
786 dev_ctx->context = intf->add(dev);
788 if (dev_ctx->context) {
789 spin_lock_irq(&priv->ctx_lock);
790 list_add_tail(&dev_ctx->list, &priv->ctx_list);
791 spin_unlock_irq(&priv->ctx_lock);
797 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
799 struct mlx5_device_context *dev_ctx;
800 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
802 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
803 if (dev_ctx->intf == intf) {
804 spin_lock_irq(&priv->ctx_lock);
805 list_del(&dev_ctx->list);
806 spin_unlock_irq(&priv->ctx_lock);
808 intf->remove(dev, dev_ctx->context);
814 static int mlx5_register_device(struct mlx5_core_dev *dev)
816 struct mlx5_priv *priv = &dev->priv;
817 struct mlx5_interface *intf;
819 mutex_lock(&intf_mutex);
820 list_add_tail(&priv->dev_list, &dev_list);
821 list_for_each_entry(intf, &intf_list, list)
822 mlx5_add_device(intf, priv);
823 mutex_unlock(&intf_mutex);
828 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
830 struct mlx5_priv *priv = &dev->priv;
831 struct mlx5_interface *intf;
833 mutex_lock(&intf_mutex);
834 list_for_each_entry(intf, &intf_list, list)
835 mlx5_remove_device(intf, priv);
836 list_del(&priv->dev_list);
837 mutex_unlock(&intf_mutex);
840 int mlx5_register_interface(struct mlx5_interface *intf)
842 struct mlx5_priv *priv;
844 if (!intf->add || !intf->remove)
847 mutex_lock(&intf_mutex);
848 list_add_tail(&intf->list, &intf_list);
849 list_for_each_entry(priv, &dev_list, dev_list)
850 mlx5_add_device(intf, priv);
851 mutex_unlock(&intf_mutex);
855 EXPORT_SYMBOL(mlx5_register_interface);
857 void mlx5_unregister_interface(struct mlx5_interface *intf)
859 struct mlx5_priv *priv;
861 mutex_lock(&intf_mutex);
862 list_for_each_entry(priv, &dev_list, dev_list)
863 mlx5_remove_device(intf, priv);
864 list_del(&intf->list);
865 mutex_unlock(&intf_mutex);
867 EXPORT_SYMBOL(mlx5_unregister_interface);
869 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
871 struct mlx5_priv *priv = &mdev->priv;
872 struct mlx5_device_context *dev_ctx;
876 spin_lock_irqsave(&priv->ctx_lock, flags);
878 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
879 if ((dev_ctx->intf->protocol == protocol) &&
880 dev_ctx->intf->get_dev) {
881 result = dev_ctx->intf->get_dev(dev_ctx->context);
885 spin_unlock_irqrestore(&priv->ctx_lock, flags);
889 EXPORT_SYMBOL(mlx5_get_protocol_dev);
891 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
893 struct pci_dev *pdev = dev->pdev;
896 pci_set_drvdata(dev->pdev, dev);
897 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
898 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
900 mutex_init(&priv->pgdir_mutex);
901 INIT_LIST_HEAD(&priv->pgdir_list);
902 spin_lock_init(&priv->mkey_lock);
904 mutex_init(&priv->alloc_mutex);
906 priv->numa_node = dev_to_node(&dev->pdev->dev);
908 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
912 err = mlx5_pci_enable_device(dev);
914 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
918 err = request_bar(pdev);
920 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
924 pci_set_master(pdev);
926 err = set_dma_caps(pdev);
928 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
932 dev->iseg_base = pci_resource_start(dev->pdev, 0);
933 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
936 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
943 pci_clear_master(dev->pdev);
944 release_bar(dev->pdev);
946 mlx5_pci_disable_device(dev);
949 debugfs_remove(priv->dbg_root);
953 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
956 pci_clear_master(dev->pdev);
957 release_bar(dev->pdev);
958 mlx5_pci_disable_device(dev);
959 debugfs_remove(priv->dbg_root);
962 #define MLX5_IB_MOD "mlx5_ib"
963 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
965 struct pci_dev *pdev = dev->pdev;
968 mutex_lock(&dev->intf_state_mutex);
969 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
970 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
975 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
976 fw_rev_min(dev), fw_rev_sub(dev));
978 /* on load removing any previous indication of internal error, device is
981 dev->state = MLX5_DEVICE_STATE_UP;
983 err = mlx5_cmd_init(dev);
985 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
989 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
991 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
992 FW_INIT_TIMEOUT_MILI);
996 mlx5_pagealloc_init(dev);
998 err = mlx5_core_enable_hca(dev, 0);
1000 dev_err(&pdev->dev, "enable hca failed\n");
1001 goto err_pagealloc_cleanup;
1004 err = mlx5_core_set_issi(dev);
1006 dev_err(&pdev->dev, "failed to set issi\n");
1007 goto err_disable_hca;
1010 err = mlx5_satisfy_startup_pages(dev, 1);
1012 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1013 goto err_disable_hca;
1016 err = set_hca_ctrl(dev);
1018 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1019 goto reclaim_boot_pages;
1022 err = handle_hca_cap(dev);
1024 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1025 goto reclaim_boot_pages;
1028 err = handle_hca_cap_atomic(dev);
1030 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1031 goto reclaim_boot_pages;
1034 err = mlx5_satisfy_startup_pages(dev, 0);
1036 dev_err(&pdev->dev, "failed to allocate init pages\n");
1037 goto reclaim_boot_pages;
1040 err = mlx5_pagealloc_start(dev);
1042 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1043 goto reclaim_boot_pages;
1046 err = mlx5_cmd_init_hca(dev);
1048 dev_err(&pdev->dev, "init hca failed\n");
1049 goto err_pagealloc_stop;
1052 mlx5_start_health_poll(dev);
1054 err = mlx5_query_hca_caps(dev);
1056 dev_err(&pdev->dev, "query hca failed\n");
1060 err = mlx5_query_board_id(dev);
1062 dev_err(&pdev->dev, "query board id failed\n");
1066 err = mlx5_enable_msix(dev);
1068 dev_err(&pdev->dev, "enable msix failed\n");
1072 err = mlx5_eq_init(dev);
1074 dev_err(&pdev->dev, "failed to initialize eq\n");
1078 err = mlx5_alloc_uuars(dev, &priv->uuari);
1080 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1081 goto err_eq_cleanup;
1084 err = mlx5_start_eqs(dev);
1086 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1090 err = alloc_comp_eqs(dev);
1092 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1096 err = mlx5_irq_set_affinity_hints(dev);
1098 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1100 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1102 mlx5_init_cq_table(dev);
1103 mlx5_init_qp_table(dev);
1104 mlx5_init_srq_table(dev);
1105 mlx5_init_mkey_table(dev);
1107 err = mlx5_init_fs(dev);
1109 dev_err(&pdev->dev, "Failed to init flow steering\n");
1112 #ifdef CONFIG_MLX5_CORE_EN
1113 err = mlx5_eswitch_init(dev);
1115 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1120 err = mlx5_sriov_init(dev);
1122 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1126 err = mlx5_register_device(dev);
1128 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1132 err = request_module_nowait(MLX5_IB_MOD);
1134 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1136 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1138 mutex_unlock(&dev->intf_state_mutex);
1143 if (mlx5_sriov_cleanup(dev))
1144 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1146 #ifdef CONFIG_MLX5_CORE_EN
1147 mlx5_eswitch_cleanup(dev->priv.eswitch);
1150 mlx5_cleanup_fs(dev);
1152 mlx5_cleanup_mkey_table(dev);
1153 mlx5_cleanup_srq_table(dev);
1154 mlx5_cleanup_qp_table(dev);
1155 mlx5_cleanup_cq_table(dev);
1156 mlx5_irq_clear_affinity_hints(dev);
1163 mlx5_free_uuars(dev, &priv->uuari);
1166 mlx5_eq_cleanup(dev);
1169 mlx5_disable_msix(dev);
1172 mlx5_stop_health_poll(dev);
1173 if (mlx5_cmd_teardown_hca(dev)) {
1174 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1179 mlx5_pagealloc_stop(dev);
1182 mlx5_reclaim_startup_pages(dev);
1185 mlx5_core_disable_hca(dev, 0);
1187 err_pagealloc_cleanup:
1188 mlx5_pagealloc_cleanup(dev);
1189 mlx5_cmd_cleanup(dev);
1192 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1193 mutex_unlock(&dev->intf_state_mutex);
1198 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1202 err = mlx5_sriov_cleanup(dev);
1204 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1209 mutex_lock(&dev->intf_state_mutex);
1210 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1211 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1215 mlx5_unregister_device(dev);
1216 #ifdef CONFIG_MLX5_CORE_EN
1217 mlx5_eswitch_cleanup(dev->priv.eswitch);
1220 mlx5_cleanup_fs(dev);
1221 mlx5_cleanup_mkey_table(dev);
1222 mlx5_cleanup_srq_table(dev);
1223 mlx5_cleanup_qp_table(dev);
1224 mlx5_cleanup_cq_table(dev);
1225 mlx5_irq_clear_affinity_hints(dev);
1228 mlx5_free_uuars(dev, &priv->uuari);
1229 mlx5_eq_cleanup(dev);
1230 mlx5_disable_msix(dev);
1231 mlx5_stop_health_poll(dev);
1232 err = mlx5_cmd_teardown_hca(dev);
1234 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1237 mlx5_pagealloc_stop(dev);
1238 mlx5_reclaim_startup_pages(dev);
1239 mlx5_core_disable_hca(dev, 0);
1240 mlx5_pagealloc_cleanup(dev);
1241 mlx5_cmd_cleanup(dev);
1244 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1245 mutex_unlock(&dev->intf_state_mutex);
1249 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1250 unsigned long param)
1252 struct mlx5_priv *priv = &dev->priv;
1253 struct mlx5_device_context *dev_ctx;
1254 unsigned long flags;
1256 spin_lock_irqsave(&priv->ctx_lock, flags);
1258 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1259 if (dev_ctx->intf->event)
1260 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1262 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1265 struct mlx5_core_event_handler {
1266 void (*event)(struct mlx5_core_dev *dev,
1267 enum mlx5_dev_event event,
1272 static int init_one(struct pci_dev *pdev,
1273 const struct pci_device_id *id)
1275 struct mlx5_core_dev *dev;
1276 struct mlx5_priv *priv;
1279 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1281 dev_err(&pdev->dev, "kzalloc failed\n");
1285 priv->pci_dev_data = id->driver_data;
1287 pci_set_drvdata(pdev, dev);
1289 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1290 pr_warn("selected profile out of range, selecting default (%d)\n",
1292 prof_sel = MLX5_DEFAULT_PROF;
1294 dev->profile = &profile[prof_sel];
1296 dev->event = mlx5_core_event;
1298 INIT_LIST_HEAD(&priv->ctx_list);
1299 spin_lock_init(&priv->ctx_lock);
1300 mutex_init(&dev->pci_status_mutex);
1301 mutex_init(&dev->intf_state_mutex);
1302 err = mlx5_pci_init(dev, priv);
1304 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1308 err = mlx5_health_init(dev);
1310 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1314 err = mlx5_load_one(dev, priv);
1316 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1323 mlx5_health_cleanup(dev);
1325 mlx5_pci_close(dev, priv);
1327 pci_set_drvdata(pdev, NULL);
1333 static void remove_one(struct pci_dev *pdev)
1335 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1336 struct mlx5_priv *priv = &dev->priv;
1338 if (mlx5_unload_one(dev, priv)) {
1339 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1340 mlx5_health_cleanup(dev);
1343 mlx5_health_cleanup(dev);
1344 mlx5_pci_close(dev, priv);
1345 pci_set_drvdata(pdev, NULL);
1349 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1350 pci_channel_state_t state)
1352 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1353 struct mlx5_priv *priv = &dev->priv;
1355 dev_info(&pdev->dev, "%s was called\n", __func__);
1356 mlx5_enter_error_state(dev);
1357 mlx5_unload_one(dev, priv);
1358 mlx5_pci_disable_device(dev);
1359 return state == pci_channel_io_perm_failure ?
1360 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1363 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1365 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1368 dev_info(&pdev->dev, "%s was called\n", __func__);
1370 err = mlx5_pci_enable_device(dev);
1372 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1374 return PCI_ERS_RESULT_DISCONNECT;
1376 pci_set_master(pdev);
1377 pci_set_power_state(pdev, PCI_D0);
1378 pci_restore_state(pdev);
1380 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1383 void mlx5_disable_device(struct mlx5_core_dev *dev)
1385 mlx5_pci_err_detected(dev->pdev, 0);
1388 /* wait for the device to show vital signs. For now we check
1389 * that we can read the device ID and that the health buffer
1390 * shows a non zero value which is different than 0xffffffff
1392 static void wait_vital(struct pci_dev *pdev)
1394 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1395 struct mlx5_core_health *health = &dev->priv.health;
1396 const int niter = 100;
1401 /* Wait for firmware to be ready after reset */
1403 for (i = 0; i < niter; i++) {
1404 if (pci_read_config_word(pdev, 2, &did)) {
1405 dev_warn(&pdev->dev, "failed reading config word\n");
1408 if (did == pdev->device) {
1409 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1415 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1417 for (i = 0; i < niter; i++) {
1418 count = ioread32be(health->health_counter);
1419 if (count && count != 0xffffffff) {
1420 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1427 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1430 static void mlx5_pci_resume(struct pci_dev *pdev)
1432 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1433 struct mlx5_priv *priv = &dev->priv;
1436 dev_info(&pdev->dev, "%s was called\n", __func__);
1438 pci_save_state(pdev);
1441 err = mlx5_load_one(dev, priv);
1443 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1446 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1449 static const struct pci_error_handlers mlx5_err_handler = {
1450 .error_detected = mlx5_pci_err_detected,
1451 .slot_reset = mlx5_pci_slot_reset,
1452 .resume = mlx5_pci_resume
1455 static const struct pci_device_id mlx5_core_pci_table[] = {
1456 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1457 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1458 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1459 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1460 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1461 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1465 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1467 static struct pci_driver mlx5_core_driver = {
1468 .name = DRIVER_NAME,
1469 .id_table = mlx5_core_pci_table,
1471 .remove = remove_one,
1472 .err_handler = &mlx5_err_handler,
1473 .sriov_configure = mlx5_core_sriov_configure,
1476 static int __init init(void)
1480 mlx5_register_debugfs();
1482 err = pci_register_driver(&mlx5_core_driver);
1486 #ifdef CONFIG_MLX5_CORE_EN
1493 mlx5_unregister_debugfs();
1497 static void __exit cleanup(void)
1499 #ifdef CONFIG_MLX5_CORE_EN
1502 pci_unregister_driver(&mlx5_core_driver);
1503 mlx5_unregister_debugfs();
1507 module_exit(cleanup);