2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/qp.h>
44 #include <linux/mlx5/srq.h>
45 #include <linux/debugfs.h>
46 #include "mlx5_core.h"
48 #define DRIVER_NAME "mlx5_core"
49 #define DRIVER_VERSION "2.2-1"
50 #define DRIVER_RELDATE "Feb 2014"
52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53 MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
54 MODULE_LICENSE("Dual BSD/GPL");
55 MODULE_VERSION(DRIVER_VERSION);
57 int mlx5_core_debug_mask;
58 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
59 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61 #define MLX5_DEFAULT_PROF 2
62 static int prof_sel = MLX5_DEFAULT_PROF;
63 module_param_named(prof_sel, prof_sel, int, 0444);
64 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
66 struct workqueue_struct *mlx5_core_wq;
67 static LIST_HEAD(intf_list);
68 static LIST_HEAD(dev_list);
69 static DEFINE_MUTEX(intf_mutex);
71 struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
77 static struct mlx5_profile profile[] = {
82 .mask = MLX5_PROF_MASK_QP_SIZE,
86 .mask = MLX5_PROF_MASK_QP_SIZE |
87 MLX5_PROF_MASK_MR_CACHE,
156 static int set_dma_caps(struct pci_dev *pdev)
160 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
162 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
163 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
165 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
170 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
173 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
177 "Can't set consistent PCI DMA mask, aborting\n");
182 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
186 static int request_bar(struct pci_dev *pdev)
190 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
191 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
195 err = pci_request_regions(pdev, DRIVER_NAME);
197 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
202 static void release_bar(struct pci_dev *pdev)
204 pci_release_regions(pdev);
207 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
209 struct mlx5_eq_table *table = &dev->priv.eq_table;
210 int num_eqs = 1 << dev->caps.log_max_eq;
214 nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
215 nvec = min_t(int, nvec, num_eqs);
216 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
219 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
220 if (!table->msix_arr)
223 for (i = 0; i < nvec; i++)
224 table->msix_arr[i].entry = i;
226 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
227 MLX5_EQ_VEC_COMP_BASE, nvec);
231 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
236 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
238 struct mlx5_eq_table *table = &dev->priv.eq_table;
240 pci_disable_msix(dev->pdev);
241 kfree(table->msix_arr);
244 struct mlx5_reg_host_endianess {
250 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
253 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
254 CAP_MASK(MLX5_CAP_OFF_DCT, 1),
257 /* selectively copy writable fields clearing any reserved area
259 static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from)
263 to->log_max_qp = from->log_max_qp & 0x1f;
264 to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f;
265 to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f;
266 to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f;
267 to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f;
268 to->log_max_atomic_size_qp = from->log_max_atomic_size_qp;
269 to->log_max_atomic_size_dc = from->log_max_atomic_size_dc;
270 v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK;
271 to->flags = cpu_to_be64(v64);
275 HCA_CAP_OPMOD_GET_MAX = 0,
276 HCA_CAP_OPMOD_GET_CUR = 1,
279 static int handle_hca_cap(struct mlx5_core_dev *dev)
281 struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
282 struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
283 struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
284 struct mlx5_cmd_set_hca_cap_mbox_out set_out;
288 memset(&query_ctx, 0, sizeof(query_ctx));
289 query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
293 set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
299 query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
300 query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR);
301 err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
302 query_out, sizeof(*query_out));
306 err = mlx5_cmd_status_to_err(&query_out->hdr);
308 mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
312 copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap);
314 if (dev->profile && dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
315 set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
317 flags = be64_to_cpu(query_out->hca_cap.flags);
318 /* disable checksum */
319 flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
321 set_ctx->hca_cap.flags = cpu_to_be64(flags);
322 memset(&set_out, 0, sizeof(set_out));
323 set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
324 set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
325 err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
326 &set_out, sizeof(set_out));
328 mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
332 err = mlx5_cmd_status_to_err(&set_out.hdr);
343 static int set_hca_ctrl(struct mlx5_core_dev *dev)
345 struct mlx5_reg_host_endianess he_in;
346 struct mlx5_reg_host_endianess he_out;
349 memset(&he_in, 0, sizeof(he_in));
350 he_in.he = MLX5_SET_HOST_ENDIANNESS;
351 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
352 &he_out, sizeof(he_out),
353 MLX5_REG_HOST_ENDIANNESS, 0, 1);
357 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
360 struct mlx5_enable_hca_mbox_in in;
361 struct mlx5_enable_hca_mbox_out out;
363 memset(&in, 0, sizeof(in));
364 memset(&out, 0, sizeof(out));
365 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
366 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
371 return mlx5_cmd_status_to_err(&out.hdr);
376 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
379 struct mlx5_disable_hca_mbox_in in;
380 struct mlx5_disable_hca_mbox_out out;
382 memset(&in, 0, sizeof(in));
383 memset(&out, 0, sizeof(out));
384 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
385 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
390 return mlx5_cmd_status_to_err(&out.hdr);
395 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
397 struct mlx5_priv *priv = &dev->priv;
401 pci_set_drvdata(dev->pdev, dev);
402 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
403 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
405 mutex_init(&priv->pgdir_mutex);
406 INIT_LIST_HEAD(&priv->pgdir_list);
407 spin_lock_init(&priv->mkey_lock);
409 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
413 err = pci_enable_device(pdev);
415 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
419 err = request_bar(pdev);
421 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
425 pci_set_master(pdev);
427 err = set_dma_caps(pdev);
429 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
433 dev->iseg_base = pci_resource_start(dev->pdev, 0);
434 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
437 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
440 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
441 fw_rev_min(dev), fw_rev_sub(dev));
443 err = mlx5_cmd_init(dev);
445 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
449 mlx5_pagealloc_init(dev);
451 err = mlx5_core_enable_hca(dev);
453 dev_err(&pdev->dev, "enable hca failed\n");
454 goto err_pagealloc_cleanup;
457 err = mlx5_satisfy_startup_pages(dev, 1);
459 dev_err(&pdev->dev, "failed to allocate boot pages\n");
460 goto err_disable_hca;
463 err = set_hca_ctrl(dev);
465 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
466 goto reclaim_boot_pages;
469 err = handle_hca_cap(dev);
471 dev_err(&pdev->dev, "handle_hca_cap failed\n");
472 goto reclaim_boot_pages;
475 err = mlx5_satisfy_startup_pages(dev, 0);
477 dev_err(&pdev->dev, "failed to allocate init pages\n");
478 goto reclaim_boot_pages;
481 err = mlx5_pagealloc_start(dev);
483 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
484 goto reclaim_boot_pages;
487 err = mlx5_cmd_init_hca(dev);
489 dev_err(&pdev->dev, "init hca failed\n");
490 goto err_pagealloc_stop;
493 mlx5_start_health_poll(dev);
495 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
497 dev_err(&pdev->dev, "query hca failed\n");
501 err = mlx5_cmd_query_adapter(dev);
503 dev_err(&pdev->dev, "query adapter failed\n");
507 err = mlx5_enable_msix(dev);
509 dev_err(&pdev->dev, "enable msix failed\n");
513 err = mlx5_eq_init(dev);
515 dev_err(&pdev->dev, "failed to initialize eq\n");
519 err = mlx5_alloc_uuars(dev, &priv->uuari);
521 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
525 err = mlx5_start_eqs(dev);
527 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
531 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
533 mlx5_init_cq_table(dev);
534 mlx5_init_qp_table(dev);
535 mlx5_init_srq_table(dev);
536 mlx5_init_mr_table(dev);
541 mlx5_free_uuars(dev, &priv->uuari);
544 mlx5_eq_cleanup(dev);
547 mlx5_disable_msix(dev);
550 mlx5_stop_health_poll(dev);
551 if (mlx5_cmd_teardown_hca(dev)) {
552 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
557 mlx5_pagealloc_stop(dev);
560 mlx5_reclaim_startup_pages(dev);
563 mlx5_core_disable_hca(dev);
565 err_pagealloc_cleanup:
566 mlx5_pagealloc_cleanup(dev);
567 mlx5_cmd_cleanup(dev);
573 pci_clear_master(dev->pdev);
574 release_bar(dev->pdev);
577 pci_disable_device(dev->pdev);
580 debugfs_remove(priv->dbg_root);
583 EXPORT_SYMBOL(mlx5_dev_init);
585 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
587 struct mlx5_priv *priv = &dev->priv;
589 mlx5_cleanup_srq_table(dev);
590 mlx5_cleanup_qp_table(dev);
591 mlx5_cleanup_cq_table(dev);
593 mlx5_free_uuars(dev, &priv->uuari);
594 mlx5_eq_cleanup(dev);
595 mlx5_disable_msix(dev);
596 mlx5_stop_health_poll(dev);
597 if (mlx5_cmd_teardown_hca(dev)) {
598 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
601 mlx5_pagealloc_stop(dev);
602 mlx5_reclaim_startup_pages(dev);
603 mlx5_core_disable_hca(dev);
604 mlx5_pagealloc_cleanup(dev);
605 mlx5_cmd_cleanup(dev);
607 pci_clear_master(dev->pdev);
608 release_bar(dev->pdev);
609 pci_disable_device(dev->pdev);
610 debugfs_remove(priv->dbg_root);
613 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
615 struct mlx5_device_context *dev_ctx;
616 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
618 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
620 pr_warn("mlx5_add_device: alloc context failed\n");
624 dev_ctx->intf = intf;
625 dev_ctx->context = intf->add(dev);
627 if (dev_ctx->context) {
628 spin_lock_irq(&priv->ctx_lock);
629 list_add_tail(&dev_ctx->list, &priv->ctx_list);
630 spin_unlock_irq(&priv->ctx_lock);
636 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
638 struct mlx5_device_context *dev_ctx;
639 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
641 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
642 if (dev_ctx->intf == intf) {
643 spin_lock_irq(&priv->ctx_lock);
644 list_del(&dev_ctx->list);
645 spin_unlock_irq(&priv->ctx_lock);
647 intf->remove(dev, dev_ctx->context);
652 static int mlx5_register_device(struct mlx5_core_dev *dev)
654 struct mlx5_priv *priv = &dev->priv;
655 struct mlx5_interface *intf;
657 mutex_lock(&intf_mutex);
658 list_add_tail(&priv->dev_list, &dev_list);
659 list_for_each_entry(intf, &intf_list, list)
660 mlx5_add_device(intf, priv);
661 mutex_unlock(&intf_mutex);
665 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
667 struct mlx5_priv *priv = &dev->priv;
668 struct mlx5_interface *intf;
670 mutex_lock(&intf_mutex);
671 list_for_each_entry(intf, &intf_list, list)
672 mlx5_remove_device(intf, priv);
673 list_del(&priv->dev_list);
674 mutex_unlock(&intf_mutex);
677 int mlx5_register_interface(struct mlx5_interface *intf)
679 struct mlx5_priv *priv;
681 if (!intf->add || !intf->remove)
684 mutex_lock(&intf_mutex);
685 list_add_tail(&intf->list, &intf_list);
686 list_for_each_entry(priv, &dev_list, dev_list)
687 mlx5_add_device(intf, priv);
688 mutex_unlock(&intf_mutex);
692 EXPORT_SYMBOL(mlx5_register_interface);
694 void mlx5_unregister_interface(struct mlx5_interface *intf)
696 struct mlx5_priv *priv;
698 mutex_lock(&intf_mutex);
699 list_for_each_entry(priv, &dev_list, dev_list)
700 mlx5_remove_device(intf, priv);
701 list_del(&intf->list);
702 mutex_unlock(&intf_mutex);
704 EXPORT_SYMBOL(mlx5_unregister_interface);
706 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
709 struct mlx5_priv *priv = &dev->priv;
710 struct mlx5_device_context *dev_ctx;
713 spin_lock_irqsave(&priv->ctx_lock, flags);
715 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
716 if (dev_ctx->intf->event)
717 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
719 spin_unlock_irqrestore(&priv->ctx_lock, flags);
722 struct mlx5_core_event_handler {
723 void (*event)(struct mlx5_core_dev *dev,
724 enum mlx5_dev_event event,
728 static int init_one(struct pci_dev *pdev,
729 const struct pci_device_id *id)
731 struct mlx5_core_dev *dev;
732 struct mlx5_priv *priv;
735 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
737 dev_err(&pdev->dev, "kzalloc failed\n");
742 pci_set_drvdata(pdev, dev);
744 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
745 pr_warn("selected profile out of range, selecting default (%d)\n",
747 prof_sel = MLX5_DEFAULT_PROF;
749 dev->profile = &profile[prof_sel];
750 dev->event = mlx5_core_event;
752 err = mlx5_dev_init(dev, pdev);
754 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
758 INIT_LIST_HEAD(&priv->ctx_list);
759 spin_lock_init(&priv->ctx_lock);
760 err = mlx5_register_device(dev);
762 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
769 mlx5_dev_cleanup(dev);
774 static void remove_one(struct pci_dev *pdev)
776 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
778 mlx5_unregister_device(dev);
779 mlx5_dev_cleanup(dev);
783 static const struct pci_device_id mlx5_core_pci_table[] = {
784 { PCI_VDEVICE(MELLANOX, 4113) }, /* MT4113 Connect-IB */
788 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
790 static struct pci_driver mlx5_core_driver = {
792 .id_table = mlx5_core_pci_table,
797 static int __init init(void)
801 mlx5_register_debugfs();
802 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
809 err = pci_register_driver(&mlx5_core_driver);
816 mlx5_health_cleanup();
817 destroy_workqueue(mlx5_core_wq);
819 mlx5_unregister_debugfs();
823 static void __exit cleanup(void)
825 pci_unregister_driver(&mlx5_core_driver);
826 mlx5_health_cleanup();
827 destroy_workqueue(mlx5_core_wq);
828 mlx5_unregister_debugfs();
832 module_exit(cleanup);