2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/qp.h>
44 #include <linux/mlx5/srq.h>
45 #include <linux/debugfs.h>
46 #include "mlx5_core.h"
48 #define DRIVER_NAME "mlx5_core"
49 #define DRIVER_VERSION "1.0"
50 #define DRIVER_RELDATE "June 2013"
52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53 MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
54 MODULE_LICENSE("Dual BSD/GPL");
55 MODULE_VERSION(DRIVER_VERSION);
57 int mlx5_core_debug_mask;
58 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
59 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61 struct workqueue_struct *mlx5_core_wq;
63 static int set_dma_caps(struct pci_dev *pdev)
67 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
69 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
70 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
77 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
80 "Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
81 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
84 "Can't set consistent PCI DMA mask, aborting.\n");
89 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
93 static int request_bar(struct pci_dev *pdev)
97 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
98 dev_err(&pdev->dev, "Missing registers BAR, aborting.\n");
102 err = pci_request_regions(pdev, DRIVER_NAME);
104 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
109 static void release_bar(struct pci_dev *pdev)
111 pci_release_regions(pdev);
114 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
116 struct mlx5_eq_table *table = &dev->priv.eq_table;
117 int num_eqs = 1 << dev->caps.log_max_eq;
122 nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
123 nvec = min_t(int, nvec, num_eqs);
124 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
127 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
128 if (!table->msix_arr)
131 for (i = 0; i < nvec; i++)
132 table->msix_arr[i].entry = i;
135 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
136 err = pci_enable_msix(dev->pdev, table->msix_arr, nvec);
139 } else if (err > 2) {
144 mlx5_core_dbg(dev, "received %d MSI vectors out of %d requested\n", err, nvec);
149 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
151 struct mlx5_eq_table *table = &dev->priv.eq_table;
153 pci_disable_msix(dev->pdev);
154 kfree(table->msix_arr);
157 struct mlx5_reg_host_endianess {
162 static int handle_hca_cap(struct mlx5_core_dev *dev)
164 struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
165 struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
166 struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
167 struct mlx5_cmd_set_hca_cap_mbox_out set_out;
168 struct mlx5_profile *prof = dev->profile;
173 memset(&query_ctx, 0, sizeof(query_ctx));
174 query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
178 set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
184 query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
185 query_ctx.hdr.opmod = cpu_to_be16(0x1);
186 err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
187 query_out, sizeof(*query_out));
191 err = mlx5_cmd_status_to_err(&query_out->hdr);
193 mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
197 memcpy(&set_ctx->hca_cap, &query_out->hca_cap,
198 sizeof(set_ctx->hca_cap));
200 if (prof->mask & MLX5_PROF_MASK_CMDIF_CSUM) {
201 csum = !!prof->cmdif_csum;
202 flags = be64_to_cpu(set_ctx->hca_cap.flags);
204 flags |= MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
206 flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
208 set_ctx->hca_cap.flags = cpu_to_be64(flags);
211 if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
212 set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
214 memset(&set_out, 0, sizeof(set_out));
215 set_ctx->hca_cap.uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
216 set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
217 err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
218 &set_out, sizeof(set_out));
220 mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
224 err = mlx5_cmd_status_to_err(&set_out.hdr);
229 dev->cmd.checksum_disabled = 1;
238 static int set_hca_ctrl(struct mlx5_core_dev *dev)
240 struct mlx5_reg_host_endianess he_in;
241 struct mlx5_reg_host_endianess he_out;
244 memset(&he_in, 0, sizeof(he_in));
245 he_in.he = MLX5_SET_HOST_ENDIANNESS;
246 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
247 &he_out, sizeof(he_out),
248 MLX5_REG_HOST_ENDIANNESS, 0, 1);
252 int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
254 struct mlx5_priv *priv = &dev->priv;
258 pci_set_drvdata(dev->pdev, dev);
259 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
260 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
262 mutex_init(&priv->pgdir_mutex);
263 INIT_LIST_HEAD(&priv->pgdir_list);
264 spin_lock_init(&priv->mkey_lock);
266 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
270 err = pci_enable_device(pdev);
272 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
276 err = request_bar(pdev);
278 dev_err(&pdev->dev, "error requesting BARs, aborting.\n");
282 pci_set_master(pdev);
284 err = set_dma_caps(pdev);
286 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
290 dev->iseg_base = pci_resource_start(dev->pdev, 0);
291 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
294 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
297 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
298 fw_rev_min(dev), fw_rev_sub(dev));
300 err = mlx5_cmd_init(dev);
302 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
306 mlx5_pagealloc_init(dev);
307 err = set_hca_ctrl(dev);
309 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
310 goto err_pagealloc_cleanup;
313 err = handle_hca_cap(dev);
315 dev_err(&pdev->dev, "handle_hca_cap failed\n");
316 goto err_pagealloc_cleanup;
319 err = mlx5_satisfy_startup_pages(dev);
321 dev_err(&pdev->dev, "failed to allocate startup pages\n");
322 goto err_pagealloc_cleanup;
325 err = mlx5_pagealloc_start(dev);
327 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
328 goto err_reclaim_pages;
331 err = mlx5_cmd_init_hca(dev);
333 dev_err(&pdev->dev, "init hca failed\n");
334 goto err_pagealloc_stop;
337 mlx5_start_health_poll(dev);
339 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
341 dev_err(&pdev->dev, "query hca failed\n");
345 err = mlx5_cmd_query_adapter(dev);
347 dev_err(&pdev->dev, "query adapter failed\n");
351 err = mlx5_enable_msix(dev);
353 dev_err(&pdev->dev, "enable msix failed\n");
357 err = mlx5_eq_init(dev);
359 dev_err(&pdev->dev, "failed to initialize eq\n");
363 err = mlx5_alloc_uuars(dev, &priv->uuari);
365 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
369 err = mlx5_start_eqs(dev);
371 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
375 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
377 mlx5_init_cq_table(dev);
378 mlx5_init_qp_table(dev);
379 mlx5_init_srq_table(dev);
384 mlx5_free_uuars(dev, &priv->uuari);
387 mlx5_eq_cleanup(dev);
390 mlx5_disable_msix(dev);
393 mlx5_stop_health_poll(dev);
394 mlx5_cmd_teardown_hca(dev);
397 mlx5_pagealloc_stop(dev);
400 mlx5_reclaim_startup_pages(dev);
402 err_pagealloc_cleanup:
403 mlx5_pagealloc_cleanup(dev);
404 mlx5_cmd_cleanup(dev);
410 pci_clear_master(dev->pdev);
411 release_bar(dev->pdev);
414 pci_disable_device(dev->pdev);
417 debugfs_remove(priv->dbg_root);
420 EXPORT_SYMBOL(mlx5_dev_init);
422 void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
424 struct mlx5_priv *priv = &dev->priv;
426 mlx5_cleanup_srq_table(dev);
427 mlx5_cleanup_qp_table(dev);
428 mlx5_cleanup_cq_table(dev);
430 mlx5_free_uuars(dev, &priv->uuari);
431 mlx5_eq_cleanup(dev);
432 mlx5_disable_msix(dev);
433 mlx5_stop_health_poll(dev);
434 mlx5_cmd_teardown_hca(dev);
435 mlx5_pagealloc_stop(dev);
436 mlx5_reclaim_startup_pages(dev);
437 mlx5_pagealloc_cleanup(dev);
438 mlx5_cmd_cleanup(dev);
440 pci_clear_master(dev->pdev);
441 release_bar(dev->pdev);
442 pci_disable_device(dev->pdev);
443 debugfs_remove(priv->dbg_root);
445 EXPORT_SYMBOL(mlx5_dev_cleanup);
447 static int __init init(void)
451 mlx5_register_debugfs();
452 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
461 mlx5_health_cleanup();
463 mlx5_unregister_debugfs();
467 static void __exit cleanup(void)
469 mlx5_health_cleanup();
470 destroy_workqueue(mlx5_core_wq);
471 mlx5_unregister_debugfs();
475 module_exit(cleanup);