2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
64 #include "fpga/core.h"
65 #include "fpga/ipsec.h"
66 #include "accel/ipsec.h"
67 #include "accel/tls.h"
68 #include "lib/clock.h"
69 #include "lib/vxlan.h"
70 #include "lib/geneve.h"
71 #include "lib/devcom.h"
72 #include "lib/pci_vsc.h"
73 #include "diag/fw_tracer.h"
75 #include "lib/hv_vhca.h"
76 #include "diag/rsc_dump.h"
77 #include "sf/vhca_event.h"
78 #include "sf/dev/dev.h"
82 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
83 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
84 MODULE_LICENSE("Dual BSD/GPL");
86 unsigned int mlx5_core_debug_mask;
87 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
88 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
90 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
91 module_param_named(prof_sel, prof_sel, uint, 0444);
92 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
94 static u32 sw_owner_id[4];
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
101 static struct mlx5_profile profile[] = {
106 .mask = MLX5_PROF_MASK_QP_SIZE,
110 .mask = MLX5_PROF_MASK_QP_SIZE |
111 MLX5_PROF_MASK_MR_CACHE,
180 static int fw_initializing(struct mlx5_core_dev *dev)
182 return ioread32be(&dev->iseg->initializing) >> 31;
185 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
188 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
189 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
192 while (fw_initializing(dev)) {
193 if (time_after(jiffies, end)) {
197 if (warn_time_mili && time_after(jiffies, warn)) {
198 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
199 jiffies_to_msecs(end - warn) / 1000);
200 warn = jiffies + msecs_to_jiffies(warn_time_mili);
202 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
208 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
213 int remaining_size = driver_ver_sz;
216 if (!MLX5_CAP_GEN(dev, driver_version))
219 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
221 strncpy(string, "Linux", remaining_size);
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, ",", remaining_size);
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, KBUILD_MODNAME, remaining_size);
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, ",", remaining_size);
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
235 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
236 LINUX_VERSION_SUBLEVEL);
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
245 static int set_dma_caps(struct pci_dev *pdev)
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
265 struct pci_dev *pdev = dev->pdev;
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
274 mutex_unlock(&dev->pci_status_mutex);
279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
281 struct pci_dev *pdev = dev->pdev;
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
288 mutex_unlock(&dev->pci_status_mutex);
291 static int request_bar(struct pci_dev *pdev)
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
307 static void release_bar(struct pci_dev *pdev)
309 pci_release_regions(pdev);
312 struct mlx5_reg_host_endianness {
317 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
320 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
321 MLX5_DEV_CAP_FLAG_DCT,
324 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
340 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
345 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
346 enum mlx5_cap_type cap_type,
347 enum mlx5_cap_mode cap_mode)
349 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
350 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
351 void *out, *hca_caps;
352 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
355 memset(in, 0, sizeof(in));
356 out = kzalloc(out_sz, GFP_KERNEL);
360 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
361 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
362 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
365 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
366 cap_type, cap_mode, err);
370 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
373 case HCA_CAP_OPMOD_GET_MAX:
374 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
375 MLX5_UN_SZ_BYTES(hca_cap_union));
377 case HCA_CAP_OPMOD_GET_CUR:
378 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
379 MLX5_UN_SZ_BYTES(hca_cap_union));
383 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
393 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
397 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
400 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
403 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
405 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
406 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
407 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
410 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
416 if (!MLX5_CAP_GEN(dev, atomic))
419 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
425 supported_atomic_req_8B_endianness_mode_1);
427 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
430 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
432 /* Set requestor to host endianness */
433 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
434 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
436 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
439 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
445 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
446 !MLX5_CAP_GEN(dev, pg))
449 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
453 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
454 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
455 MLX5_ST_SZ_BYTES(odp_cap));
457 #define ODP_CAP_SET_MAX(dev, field) \
459 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
462 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
466 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
467 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
468 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
474 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
475 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
484 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
487 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
489 struct mlx5_profile *prof = &dev->profile;
493 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
497 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
499 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
500 MLX5_ST_SZ_BYTES(cmd_hca_cap));
502 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
503 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
505 /* we limit the size of the pkey table to 128 entries for now */
506 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
507 to_fw_pkey_sz(dev, 128));
509 /* Check log_max_qp from HCA caps to set in current profile */
510 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
511 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
513 MLX5_CAP_GEN_MAX(dev, log_max_qp));
514 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
516 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
517 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
520 /* disable cmdif checksum */
521 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
523 /* Enable 4K UAR only when HCA supports it and page size is bigger
526 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
527 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
529 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
531 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
532 MLX5_SET(cmd_hca_cap,
535 cache_line_size() >= 128 ? 1 : 0);
537 if (MLX5_CAP_GEN_MAX(dev, dct))
538 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
540 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
541 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
543 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
544 MLX5_SET(cmd_hca_cap,
547 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
549 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
550 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
552 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
553 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
555 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
557 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
559 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
561 if (MLX5_CAP_GEN(dev, roce_rw_supported))
562 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));
564 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
567 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
569 * In case RoCE cap is writable in FW and user/devlink requested to change the
570 * cap, we are yet to query the final state of the above cap.
571 * Hence, the need for this function.
575 * 1) RoCE cap is read only in FW and already disabled
577 * 2) RoCE cap is writable in FW and user/devlink requested it off.
579 * In any other case, return False.
581 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
583 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||
584 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
587 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
592 if (is_roce_fw_disabled(dev))
595 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
599 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
600 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
603 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
604 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
605 MLX5_ST_SZ_BYTES(roce_cap));
606 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
608 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
612 static int set_hca_cap(struct mlx5_core_dev *dev)
614 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
618 set_ctx = kzalloc(set_sz, GFP_KERNEL);
622 err = handle_hca_cap(dev, set_ctx);
624 mlx5_core_err(dev, "handle_hca_cap failed\n");
628 memset(set_ctx, 0, set_sz);
629 err = handle_hca_cap_atomic(dev, set_ctx);
631 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
635 memset(set_ctx, 0, set_sz);
636 err = handle_hca_cap_odp(dev, set_ctx);
638 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
642 memset(set_ctx, 0, set_sz);
643 err = handle_hca_cap_roce(dev, set_ctx);
645 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
654 static int set_hca_ctrl(struct mlx5_core_dev *dev)
656 struct mlx5_reg_host_endianness he_in;
657 struct mlx5_reg_host_endianness he_out;
660 if (!mlx5_core_is_pf(dev))
663 memset(&he_in, 0, sizeof(he_in));
664 he_in.he = MLX5_SET_HOST_ENDIANNESS;
665 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
666 &he_out, sizeof(he_out),
667 MLX5_REG_HOST_ENDIANNESS, 0, 1);
671 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
675 /* Disable local_lb by default */
676 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
677 ret = mlx5_nic_vport_update_local_lb(dev, false);
682 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
684 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
686 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
687 MLX5_SET(enable_hca_in, in, function_id, func_id);
688 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
689 dev->caps.embedded_cpu);
690 return mlx5_cmd_exec_in(dev, enable_hca, in);
693 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
695 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
697 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
698 MLX5_SET(disable_hca_in, in, function_id, func_id);
699 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
700 dev->caps.embedded_cpu);
701 return mlx5_cmd_exec_in(dev, disable_hca, in);
704 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
706 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
707 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
711 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
712 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
717 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
718 if (!status || syndrome == MLX5_DRIVER_SYND) {
719 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
720 err, status, syndrome);
724 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
729 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
731 if (sup_issi & (1 << 1)) {
732 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
734 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
735 MLX5_SET(set_issi_in, set_in, current_issi, 1);
736 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
738 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
746 } else if (sup_issi & (1 << 0) || !sup_issi) {
753 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
754 const struct pci_device_id *id)
758 mutex_init(&dev->pci_status_mutex);
759 pci_set_drvdata(dev->pdev, dev);
761 dev->bar_addr = pci_resource_start(pdev, 0);
763 err = mlx5_pci_enable_device(dev);
765 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
769 err = request_bar(pdev);
771 mlx5_core_err(dev, "error requesting BARs, aborting\n");
775 pci_set_master(pdev);
777 err = set_dma_caps(pdev);
779 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
783 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
784 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
785 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
786 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
788 dev->iseg_base = dev->bar_addr;
789 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
792 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
796 mlx5_pci_vsc_init(dev);
797 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
801 pci_clear_master(dev->pdev);
802 release_bar(dev->pdev);
804 mlx5_pci_disable_device(dev);
808 static void mlx5_pci_close(struct mlx5_core_dev *dev)
810 /* health work might still be active, and it needs pci bar in
811 * order to know the NIC state. Therefore, drain the health WQ
812 * before removing the pci bars
814 mlx5_drain_health_wq(dev);
816 pci_clear_master(dev->pdev);
817 release_bar(dev->pdev);
818 mlx5_pci_disable_device(dev);
821 static int mlx5_init_once(struct mlx5_core_dev *dev)
825 dev->priv.devcom = mlx5_devcom_register_device(dev);
826 if (IS_ERR(dev->priv.devcom))
827 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
830 err = mlx5_query_board_id(dev);
832 mlx5_core_err(dev, "query board id failed\n");
836 err = mlx5_irq_table_init(dev);
838 mlx5_core_err(dev, "failed to initialize irq table\n");
842 err = mlx5_eq_table_init(dev);
844 mlx5_core_err(dev, "failed to initialize eq\n");
845 goto err_irq_cleanup;
848 err = mlx5_events_init(dev);
850 mlx5_core_err(dev, "failed to initialize events\n");
854 err = mlx5_fw_reset_init(dev);
856 mlx5_core_err(dev, "failed to initialize fw reset events\n");
857 goto err_events_cleanup;
860 mlx5_cq_debugfs_init(dev);
862 mlx5_init_reserved_gids(dev);
864 mlx5_init_clock(dev);
866 dev->vxlan = mlx5_vxlan_create(dev);
867 dev->geneve = mlx5_geneve_create(dev);
869 err = mlx5_init_rl_table(dev);
871 mlx5_core_err(dev, "Failed to init rate limiting\n");
872 goto err_tables_cleanup;
875 err = mlx5_mpfs_init(dev);
877 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
881 err = mlx5_sriov_init(dev);
883 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
884 goto err_mpfs_cleanup;
887 err = mlx5_eswitch_init(dev);
889 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
890 goto err_sriov_cleanup;
893 err = mlx5_fpga_init(dev);
895 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
896 goto err_eswitch_cleanup;
899 err = mlx5_vhca_event_init(dev);
901 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
902 goto err_fpga_cleanup;
905 err = mlx5_sf_hw_table_init(dev);
907 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
908 goto err_sf_hw_table_cleanup;
911 err = mlx5_sf_table_init(dev);
913 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
914 goto err_sf_table_cleanup;
917 dev->dm = mlx5_dm_create(dev);
919 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
921 dev->tracer = mlx5_fw_tracer_create(dev);
922 dev->hv_vhca = mlx5_hv_vhca_create(dev);
923 dev->rsc_dump = mlx5_rsc_dump_create(dev);
927 err_sf_table_cleanup:
928 mlx5_sf_hw_table_cleanup(dev);
929 err_sf_hw_table_cleanup:
930 mlx5_vhca_event_cleanup(dev);
932 mlx5_fpga_cleanup(dev);
934 mlx5_eswitch_cleanup(dev->priv.eswitch);
936 mlx5_sriov_cleanup(dev);
938 mlx5_mpfs_cleanup(dev);
940 mlx5_cleanup_rl_table(dev);
942 mlx5_geneve_destroy(dev->geneve);
943 mlx5_vxlan_destroy(dev->vxlan);
944 mlx5_cq_debugfs_cleanup(dev);
945 mlx5_fw_reset_cleanup(dev);
947 mlx5_events_cleanup(dev);
949 mlx5_eq_table_cleanup(dev);
951 mlx5_irq_table_cleanup(dev);
953 mlx5_devcom_unregister_device(dev->priv.devcom);
958 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
960 mlx5_rsc_dump_destroy(dev);
961 mlx5_hv_vhca_destroy(dev->hv_vhca);
962 mlx5_fw_tracer_destroy(dev->tracer);
963 mlx5_dm_cleanup(dev);
964 mlx5_sf_table_cleanup(dev);
965 mlx5_sf_hw_table_cleanup(dev);
966 mlx5_vhca_event_cleanup(dev);
967 mlx5_fpga_cleanup(dev);
968 mlx5_eswitch_cleanup(dev->priv.eswitch);
969 mlx5_sriov_cleanup(dev);
970 mlx5_mpfs_cleanup(dev);
971 mlx5_cleanup_rl_table(dev);
972 mlx5_geneve_destroy(dev->geneve);
973 mlx5_vxlan_destroy(dev->vxlan);
974 mlx5_cleanup_clock(dev);
975 mlx5_cleanup_reserved_gids(dev);
976 mlx5_cq_debugfs_cleanup(dev);
977 mlx5_fw_reset_cleanup(dev);
978 mlx5_events_cleanup(dev);
979 mlx5_eq_table_cleanup(dev);
980 mlx5_irq_table_cleanup(dev);
981 mlx5_devcom_unregister_device(dev->priv.devcom);
984 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
988 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
989 fw_rev_min(dev), fw_rev_sub(dev));
991 /* Only PFs hold the relevant PCIe information for this query */
992 if (mlx5_core_is_pf(dev))
993 pcie_print_link_status(dev->pdev);
995 mlx5_tout_set_def_val(dev);
997 /* wait for firmware to accept initialization segments configurations
999 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT),
1000 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1002 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1003 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1007 err = mlx5_cmd_init(dev);
1009 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1013 mlx5_tout_query_iseg(dev);
1015 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1017 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1018 mlx5_tout_ms(dev, FW_INIT));
1019 goto err_cmd_cleanup;
1022 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1024 err = mlx5_core_enable_hca(dev, 0);
1026 mlx5_core_err(dev, "enable hca failed\n");
1027 goto err_cmd_cleanup;
1030 err = mlx5_core_set_issi(dev);
1032 mlx5_core_err(dev, "failed to set issi\n");
1033 goto err_disable_hca;
1036 err = mlx5_satisfy_startup_pages(dev, 1);
1038 mlx5_core_err(dev, "failed to allocate boot pages\n");
1039 goto err_disable_hca;
1042 err = mlx5_tout_query_dtor(dev);
1044 mlx5_core_err(dev, "failed to read dtor\n");
1045 goto reclaim_boot_pages;
1048 err = set_hca_ctrl(dev);
1050 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1051 goto reclaim_boot_pages;
1054 err = set_hca_cap(dev);
1056 mlx5_core_err(dev, "set_hca_cap failed\n");
1057 goto reclaim_boot_pages;
1060 err = mlx5_satisfy_startup_pages(dev, 0);
1062 mlx5_core_err(dev, "failed to allocate init pages\n");
1063 goto reclaim_boot_pages;
1066 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1068 mlx5_core_err(dev, "init hca failed\n");
1069 goto reclaim_boot_pages;
1072 mlx5_set_driver_version(dev);
1074 err = mlx5_query_hca_caps(dev);
1076 mlx5_core_err(dev, "query hca failed\n");
1077 goto reclaim_boot_pages;
1080 mlx5_start_health_poll(dev);
1085 mlx5_reclaim_startup_pages(dev);
1087 mlx5_core_disable_hca(dev, 0);
1089 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1090 mlx5_cmd_cleanup(dev);
1095 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1099 mlx5_stop_health_poll(dev, boot);
1100 err = mlx5_cmd_teardown_hca(dev);
1102 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1105 mlx5_reclaim_startup_pages(dev);
1106 mlx5_core_disable_hca(dev, 0);
1107 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1108 mlx5_cmd_cleanup(dev);
1113 static int mlx5_load(struct mlx5_core_dev *dev)
1117 dev->priv.uar = mlx5_get_uars_page(dev);
1118 if (IS_ERR(dev->priv.uar)) {
1119 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1120 err = PTR_ERR(dev->priv.uar);
1124 mlx5_events_start(dev);
1125 mlx5_pagealloc_start(dev);
1127 err = mlx5_irq_table_create(dev);
1129 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1133 err = mlx5_eq_table_create(dev);
1135 mlx5_core_err(dev, "Failed to create EQs\n");
1139 err = mlx5_fw_tracer_init(dev->tracer);
1141 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1142 mlx5_fw_tracer_destroy(dev->tracer);
1146 mlx5_fw_reset_events_start(dev);
1147 mlx5_hv_vhca_init(dev->hv_vhca);
1149 err = mlx5_rsc_dump_init(dev);
1151 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1152 mlx5_rsc_dump_destroy(dev);
1153 dev->rsc_dump = NULL;
1156 err = mlx5_fpga_device_start(dev);
1158 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1159 goto err_fpga_start;
1162 mlx5_accel_ipsec_init(dev);
1164 err = mlx5_accel_tls_init(dev);
1166 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1170 err = mlx5_init_fs(dev);
1172 mlx5_core_err(dev, "Failed to init flow steering\n");
1176 err = mlx5_core_set_hca_defaults(dev);
1178 mlx5_core_err(dev, "Failed to set hca defaults\n");
1182 mlx5_vhca_event_start(dev);
1184 err = mlx5_sf_hw_table_create(dev);
1186 mlx5_core_err(dev, "sf table create failed %d\n", err);
1190 err = mlx5_ec_init(dev);
1192 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1196 mlx5_lag_add_mdev(dev);
1197 err = mlx5_sriov_attach(dev);
1199 mlx5_core_err(dev, "sriov init failed %d\n", err);
1203 mlx5_sf_dev_table_create(dev);
1208 mlx5_lag_remove_mdev(dev);
1209 mlx5_ec_cleanup(dev);
1211 mlx5_sf_hw_table_destroy(dev);
1213 mlx5_vhca_event_stop(dev);
1215 mlx5_cleanup_fs(dev);
1217 mlx5_accel_tls_cleanup(dev);
1219 mlx5_accel_ipsec_cleanup(dev);
1220 mlx5_fpga_device_stop(dev);
1222 mlx5_rsc_dump_cleanup(dev);
1223 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1224 mlx5_fw_reset_events_stop(dev);
1225 mlx5_fw_tracer_cleanup(dev->tracer);
1226 mlx5_eq_table_destroy(dev);
1228 mlx5_irq_table_destroy(dev);
1230 mlx5_pagealloc_stop(dev);
1231 mlx5_events_stop(dev);
1232 mlx5_put_uars_page(dev, dev->priv.uar);
1236 static void mlx5_unload(struct mlx5_core_dev *dev)
1238 mlx5_sf_dev_table_destroy(dev);
1239 mlx5_sriov_detach(dev);
1240 mlx5_lag_remove_mdev(dev);
1241 mlx5_ec_cleanup(dev);
1242 mlx5_sf_hw_table_destroy(dev);
1243 mlx5_vhca_event_stop(dev);
1244 mlx5_cleanup_fs(dev);
1245 mlx5_accel_ipsec_cleanup(dev);
1246 mlx5_accel_tls_cleanup(dev);
1247 mlx5_fpga_device_stop(dev);
1248 mlx5_rsc_dump_cleanup(dev);
1249 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1250 mlx5_fw_reset_events_stop(dev);
1251 mlx5_fw_tracer_cleanup(dev->tracer);
1252 mlx5_eq_table_destroy(dev);
1253 mlx5_irq_table_destroy(dev);
1254 mlx5_pagealloc_stop(dev);
1255 mlx5_events_stop(dev);
1256 mlx5_put_uars_page(dev, dev->priv.uar);
1259 int mlx5_init_one(struct mlx5_core_dev *dev)
1263 mutex_lock(&dev->intf_state_mutex);
1264 dev->state = MLX5_DEVICE_STATE_UP;
1266 err = mlx5_function_setup(dev, true);
1270 err = mlx5_init_once(dev);
1272 mlx5_core_err(dev, "sw objs init failed\n");
1273 goto function_teardown;
1276 err = mlx5_load(dev);
1280 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1282 err = mlx5_devlink_register(priv_to_devlink(dev));
1284 goto err_devlink_reg;
1286 err = mlx5_register_device(dev);
1290 mutex_unlock(&dev->intf_state_mutex);
1294 mlx5_devlink_unregister(priv_to_devlink(dev));
1296 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1299 mlx5_cleanup_once(dev);
1301 mlx5_function_teardown(dev, true);
1303 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1304 mutex_unlock(&dev->intf_state_mutex);
1308 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1310 mutex_lock(&dev->intf_state_mutex);
1312 mlx5_unregister_device(dev);
1313 mlx5_devlink_unregister(priv_to_devlink(dev));
1315 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1316 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1318 mlx5_cleanup_once(dev);
1322 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1324 mlx5_cleanup_once(dev);
1325 mlx5_function_teardown(dev, true);
1327 mutex_unlock(&dev->intf_state_mutex);
1330 int mlx5_load_one(struct mlx5_core_dev *dev)
1334 mutex_lock(&dev->intf_state_mutex);
1335 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1336 mlx5_core_warn(dev, "interface is up, NOP\n");
1339 /* remove any previous indication of internal error */
1340 dev->state = MLX5_DEVICE_STATE_UP;
1342 err = mlx5_function_setup(dev, false);
1346 err = mlx5_load(dev);
1350 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1352 err = mlx5_attach_device(dev);
1356 mutex_unlock(&dev->intf_state_mutex);
1360 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1363 mlx5_function_teardown(dev, false);
1365 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1367 mutex_unlock(&dev->intf_state_mutex);
1371 void mlx5_unload_one(struct mlx5_core_dev *dev)
1373 mutex_lock(&dev->intf_state_mutex);
1375 mlx5_detach_device(dev);
1377 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1378 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1383 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1385 mlx5_function_teardown(dev, false);
1387 mutex_unlock(&dev->intf_state_mutex);
1390 static const int types[] = {
1393 MLX5_CAP_ETHERNET_OFFLOADS,
1394 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1398 MLX5_CAP_IPOIB_OFFLOADS,
1399 MLX5_CAP_FLOW_TABLE,
1400 MLX5_CAP_ESWITCH_FLOW_TABLE,
1402 MLX5_CAP_VECTOR_CALC,
1408 MLX5_CAP_VDPA_EMULATION,
1410 MLX5_CAP_PORT_SELECTION,
1411 MLX5_CAP_DEV_SHAMPO,
1414 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1419 for (i = 0; i < ARRAY_SIZE(types); i++) {
1421 kfree(dev->caps.hca[type]);
1425 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1427 struct mlx5_hca_cap *cap;
1431 for (i = 0; i < ARRAY_SIZE(types); i++) {
1432 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1436 dev->caps.hca[type] = cap;
1442 mlx5_hca_caps_free(dev);
1446 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1448 struct mlx5_priv *priv = &dev->priv;
1451 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1452 INIT_LIST_HEAD(&priv->ctx_list);
1453 spin_lock_init(&priv->ctx_lock);
1454 mutex_init(&dev->intf_state_mutex);
1456 mutex_init(&priv->bfregs.reg_head.lock);
1457 mutex_init(&priv->bfregs.wc_head.lock);
1458 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1459 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1461 mutex_init(&priv->alloc_mutex);
1462 mutex_init(&priv->pgdir_mutex);
1463 INIT_LIST_HEAD(&priv->pgdir_list);
1465 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1466 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1468 INIT_LIST_HEAD(&priv->traps);
1470 err = mlx5_tout_init(dev);
1472 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1473 goto err_timeout_init;
1476 err = mlx5_health_init(dev);
1478 goto err_health_init;
1480 err = mlx5_pagealloc_init(dev);
1482 goto err_pagealloc_init;
1484 err = mlx5_adev_init(dev);
1488 err = mlx5_hca_caps_alloc(dev);
1495 mlx5_adev_cleanup(dev);
1497 mlx5_pagealloc_cleanup(dev);
1499 mlx5_health_cleanup(dev);
1501 mlx5_tout_cleanup(dev);
1503 debugfs_remove(dev->priv.dbg_root);
1504 mutex_destroy(&priv->pgdir_mutex);
1505 mutex_destroy(&priv->alloc_mutex);
1506 mutex_destroy(&priv->bfregs.wc_head.lock);
1507 mutex_destroy(&priv->bfregs.reg_head.lock);
1508 mutex_destroy(&dev->intf_state_mutex);
1512 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1514 struct mlx5_priv *priv = &dev->priv;
1516 mlx5_hca_caps_free(dev);
1517 mlx5_adev_cleanup(dev);
1518 mlx5_pagealloc_cleanup(dev);
1519 mlx5_health_cleanup(dev);
1520 mlx5_tout_cleanup(dev);
1521 debugfs_remove_recursive(dev->priv.dbg_root);
1522 mutex_destroy(&priv->pgdir_mutex);
1523 mutex_destroy(&priv->alloc_mutex);
1524 mutex_destroy(&priv->bfregs.wc_head.lock);
1525 mutex_destroy(&priv->bfregs.reg_head.lock);
1526 mutex_destroy(&dev->intf_state_mutex);
1529 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1531 struct mlx5_core_dev *dev;
1532 struct devlink *devlink;
1535 devlink = mlx5_devlink_alloc(&pdev->dev);
1537 dev_err(&pdev->dev, "devlink alloc failed\n");
1541 dev = devlink_priv(devlink);
1542 dev->device = &pdev->dev;
1545 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1546 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1548 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1549 if (dev->priv.adev_idx < 0) {
1550 err = dev->priv.adev_idx;
1554 err = mlx5_mdev_init(dev, prof_sel);
1558 err = mlx5_pci_init(dev, pdev, id);
1560 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1565 err = mlx5_init_one(dev);
1567 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1572 err = mlx5_crdump_enable(dev);
1574 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1576 pci_save_state(pdev);
1577 devlink_register(devlink);
1581 mlx5_pci_close(dev);
1583 mlx5_mdev_uninit(dev);
1585 mlx5_adev_idx_free(dev->priv.adev_idx);
1587 mlx5_devlink_free(devlink);
1592 static void remove_one(struct pci_dev *pdev)
1594 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1595 struct devlink *devlink = priv_to_devlink(dev);
1597 devlink_unregister(devlink);
1598 mlx5_crdump_disable(dev);
1599 mlx5_drain_health_wq(dev);
1600 mlx5_uninit_one(dev);
1601 mlx5_pci_close(dev);
1602 mlx5_mdev_uninit(dev);
1603 mlx5_adev_idx_free(dev->priv.adev_idx);
1604 mlx5_devlink_free(devlink);
1607 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1608 struct mlx5_core_dev *__dev = (dev); \
1609 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1610 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1611 __dev->pci_status, ##__VA_ARGS__); \
1614 static const char *result2str(enum pci_ers_result result)
1616 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1617 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1618 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1622 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1623 pci_channel_state_t state)
1625 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1626 enum pci_ers_result res;
1628 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1630 mlx5_enter_error_state(dev, false);
1631 mlx5_error_sw_reset(dev);
1632 mlx5_unload_one(dev);
1633 mlx5_drain_health_wq(dev);
1634 mlx5_pci_disable_device(dev);
1636 res = state == pci_channel_io_perm_failure ?
1637 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1639 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res));
1643 /* wait for the device to show vital signs by waiting
1644 * for the health counter to start counting.
1646 static int wait_vital(struct pci_dev *pdev)
1648 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1649 struct mlx5_core_health *health = &dev->priv.health;
1650 const int niter = 100;
1655 for (i = 0; i < niter; i++) {
1656 count = ioread32be(health->health_counter);
1657 if (count && count != 0xffffffff) {
1658 if (last_count && last_count != count) {
1660 "wait vital counter value 0x%x after %d iterations\n",
1672 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1674 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1675 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1678 mlx5_pci_trace(dev, "Enter\n");
1680 err = mlx5_pci_enable_device(dev);
1682 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1687 pci_set_master(pdev);
1688 pci_restore_state(pdev);
1689 pci_save_state(pdev);
1691 err = wait_vital(pdev);
1693 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1698 res = PCI_ERS_RESULT_RECOVERED;
1700 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res));
1704 static void mlx5_pci_resume(struct pci_dev *pdev)
1706 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1709 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1711 err = mlx5_load_one(dev);
1713 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1714 !err ? "recovered" : "Failed");
1717 static const struct pci_error_handlers mlx5_err_handler = {
1718 .error_detected = mlx5_pci_err_detected,
1719 .slot_reset = mlx5_pci_slot_reset,
1720 .resume = mlx5_pci_resume
1723 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1725 bool fast_teardown = false, force_teardown = false;
1728 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1729 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1731 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1732 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1734 if (!fast_teardown && !force_teardown)
1737 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1738 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1742 /* Panic tear down fw command will stop the PCI bus communication
1743 * with the HCA, so the health polll is no longer needed.
1745 mlx5_drain_health_wq(dev);
1746 mlx5_stop_health_poll(dev, false);
1748 ret = mlx5_cmd_fast_teardown_hca(dev);
1752 ret = mlx5_cmd_force_teardown_hca(dev);
1756 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1757 mlx5_start_health_poll(dev);
1761 mlx5_enter_error_state(dev, true);
1763 /* Some platforms requiring freeing the IRQ's in the shutdown
1764 * flow. If they aren't freed they can't be allocated after
1765 * kexec. There is no need to cleanup the mlx5_core software
1768 mlx5_core_eq_free_irqs(dev);
1773 static void shutdown(struct pci_dev *pdev)
1775 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1778 mlx5_core_info(dev, "Shutdown was called\n");
1779 err = mlx5_try_fast_unload(dev);
1781 mlx5_unload_one(dev);
1782 mlx5_pci_disable_device(dev);
1785 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1787 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1789 mlx5_unload_one(dev);
1794 static int mlx5_resume(struct pci_dev *pdev)
1796 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1798 return mlx5_load_one(dev);
1801 static const struct pci_device_id mlx5_core_pci_table[] = {
1802 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1803 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1804 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1805 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1806 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1807 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1808 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1809 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1810 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1811 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1812 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1813 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1814 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1815 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1816 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1817 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1818 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1819 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1820 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1821 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1825 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1827 void mlx5_disable_device(struct mlx5_core_dev *dev)
1829 mlx5_error_sw_reset(dev);
1830 mlx5_unload_one(dev);
1833 int mlx5_recover_device(struct mlx5_core_dev *dev)
1837 mlx5_pci_disable_device(dev);
1838 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1839 ret = mlx5_load_one(dev);
1843 static struct pci_driver mlx5_core_driver = {
1844 .name = KBUILD_MODNAME,
1845 .id_table = mlx5_core_pci_table,
1847 .remove = remove_one,
1848 .suspend = mlx5_suspend,
1849 .resume = mlx5_resume,
1850 .shutdown = shutdown,
1851 .err_handler = &mlx5_err_handler,
1852 .sriov_configure = mlx5_core_sriov_configure,
1853 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1854 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1857 static void mlx5_core_verify_params(void)
1859 if (prof_sel >= ARRAY_SIZE(profile)) {
1860 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1862 ARRAY_SIZE(profile) - 1,
1864 prof_sel = MLX5_DEFAULT_PROF;
1868 static int __init init(void)
1872 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1873 "mlx5_core name not in sync with kernel module name");
1875 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1877 mlx5_core_verify_params();
1878 mlx5_fpga_ipsec_build_fs_cmds();
1879 mlx5_register_debugfs();
1881 err = pci_register_driver(&mlx5_core_driver);
1885 err = mlx5_sf_driver_register();
1896 mlx5_sf_driver_unregister();
1898 pci_unregister_driver(&mlx5_core_driver);
1900 mlx5_unregister_debugfs();
1904 static void __exit cleanup(void)
1907 mlx5_sf_driver_unregister();
1908 pci_unregister_driver(&mlx5_core_driver);
1909 mlx5_unregister_debugfs();
1913 module_exit(cleanup);