2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #include <linux/mlx5/vport.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
60 #include "fpga/core.h"
61 #include "fpga/ipsec.h"
62 #include "accel/ipsec.h"
63 #include "accel/tls.h"
64 #include "lib/clock.h"
65 #include "lib/vxlan.h"
66 #include "diag/fw_tracer.h"
68 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
69 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
70 MODULE_LICENSE("Dual BSD/GPL");
71 MODULE_VERSION(DRIVER_VERSION);
73 unsigned int mlx5_core_debug_mask;
74 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
75 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
77 #define MLX5_DEFAULT_PROF 2
78 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
79 module_param_named(prof_sel, prof_sel, uint, 0444);
80 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
82 static u32 sw_owner_id[4];
85 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
86 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
89 static struct mlx5_profile profile[] = {
94 .mask = MLX5_PROF_MASK_QP_SIZE,
98 .mask = MLX5_PROF_MASK_QP_SIZE |
99 MLX5_PROF_MASK_MR_CACHE,
188 #define FW_INIT_TIMEOUT_MILI 2000
189 #define FW_INIT_WAIT_MS 2
190 #define FW_PRE_INIT_TIMEOUT_MILI 10000
192 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
194 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
197 while (fw_initializing(dev)) {
198 if (time_after(jiffies, end)) {
202 msleep(FW_INIT_WAIT_MS);
208 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
213 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
214 int remaining_size = driver_ver_sz;
217 if (!MLX5_CAP_GEN(dev, driver_version))
220 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
222 strncpy(string, "Linux", remaining_size);
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, ",", remaining_size);
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, DRIVER_NAME, remaining_size);
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, ",", remaining_size);
233 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234 strncat(string, DRIVER_VERSION, remaining_size);
237 MLX5_SET(set_driver_version_in, in, opcode,
238 MLX5_CMD_OP_SET_DRIVER_VERSION);
240 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
243 static int set_dma_caps(struct pci_dev *pdev)
247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
249 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
250 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
252 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
260 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
261 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
264 "Can't set consistent PCI DMA mask, aborting\n");
269 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
273 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
275 struct pci_dev *pdev = dev->pdev;
278 mutex_lock(&dev->pci_status_mutex);
279 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
280 err = pci_enable_device(pdev);
282 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
284 mutex_unlock(&dev->pci_status_mutex);
289 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
291 struct pci_dev *pdev = dev->pdev;
293 mutex_lock(&dev->pci_status_mutex);
294 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
295 pci_disable_device(pdev);
296 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
298 mutex_unlock(&dev->pci_status_mutex);
301 static int request_bar(struct pci_dev *pdev)
305 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
306 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
310 err = pci_request_regions(pdev, DRIVER_NAME);
312 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
317 static void release_bar(struct pci_dev *pdev)
319 pci_release_regions(pdev);
322 static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
324 struct mlx5_priv *priv = &dev->priv;
325 struct mlx5_eq_table *table = &priv->eq_table;
326 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
327 MLX5_CAP_GEN(dev, max_num_eqs) :
328 1 << MLX5_CAP_GEN(dev, log_max_eq);
332 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
333 MLX5_EQ_VEC_COMP_BASE;
334 nvec = min_t(int, nvec, num_eqs);
335 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
338 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
342 nvec = pci_alloc_irq_vectors(dev->pdev,
343 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
347 goto err_free_irq_info;
350 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
355 kfree(priv->irq_info);
359 static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
361 struct mlx5_priv *priv = &dev->priv;
363 pci_free_irq_vectors(dev->pdev);
364 kfree(priv->irq_info);
367 struct mlx5_reg_host_endianness {
372 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
375 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
376 MLX5_DEV_CAP_FLAG_DCT,
379 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
395 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
400 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
401 enum mlx5_cap_type cap_type,
402 enum mlx5_cap_mode cap_mode)
404 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
405 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
406 void *out, *hca_caps;
407 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
410 memset(in, 0, sizeof(in));
411 out = kzalloc(out_sz, GFP_KERNEL);
415 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
416 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
417 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
420 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
421 cap_type, cap_mode, err);
425 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
428 case HCA_CAP_OPMOD_GET_MAX:
429 memcpy(dev->caps.hca_max[cap_type], hca_caps,
430 MLX5_UN_SZ_BYTES(hca_cap_union));
432 case HCA_CAP_OPMOD_GET_CUR:
433 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
434 MLX5_UN_SZ_BYTES(hca_cap_union));
438 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
448 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
452 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
455 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
458 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
460 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
462 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
463 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
464 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
467 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
471 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
475 if (MLX5_CAP_GEN(dev, atomic)) {
476 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
485 supported_atomic_req_8B_endianness_mode_1);
487 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
490 set_ctx = kzalloc(set_sz, GFP_KERNEL);
494 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
496 /* Set requestor to host endianness */
497 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
498 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
500 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
506 static int handle_hca_cap(struct mlx5_core_dev *dev)
508 void *set_ctx = NULL;
509 struct mlx5_profile *prof = dev->profile;
511 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
514 set_ctx = kzalloc(set_sz, GFP_KERNEL);
518 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
522 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
524 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
525 MLX5_ST_SZ_BYTES(cmd_hca_cap));
527 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
528 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
530 /* we limit the size of the pkey table to 128 entries for now */
531 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
532 to_fw_pkey_sz(dev, 128));
534 /* Check log_max_qp from HCA caps to set in current profile */
535 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
536 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
537 profile[prof_sel].log_max_qp,
538 MLX5_CAP_GEN_MAX(dev, log_max_qp));
539 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
541 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
542 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
545 /* disable cmdif checksum */
546 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
548 /* Enable 4K UAR only when HCA supports it and page size is bigger
551 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
552 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
554 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
556 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
557 MLX5_SET(cmd_hca_cap,
560 cache_line_size() >= 128 ? 1 : 0);
562 if (MLX5_CAP_GEN_MAX(dev, dct))
563 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
565 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
566 MLX5_SET(cmd_hca_cap,
569 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
571 err = set_caps(dev, set_ctx, set_sz,
572 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
579 static int set_hca_ctrl(struct mlx5_core_dev *dev)
581 struct mlx5_reg_host_endianness he_in;
582 struct mlx5_reg_host_endianness he_out;
585 if (!mlx5_core_is_pf(dev))
588 memset(&he_in, 0, sizeof(he_in));
589 he_in.he = MLX5_SET_HOST_ENDIANNESS;
590 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
591 &he_out, sizeof(he_out),
592 MLX5_REG_HOST_ENDIANNESS, 0, 1);
596 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
600 /* Disable local_lb by default */
601 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
602 ret = mlx5_nic_vport_update_local_lb(dev, false);
607 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
609 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
610 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
612 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
613 MLX5_SET(enable_hca_in, in, function_id, func_id);
614 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
617 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
619 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
620 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
622 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
623 MLX5_SET(disable_hca_in, in, function_id, func_id);
624 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
627 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
629 u32 timer_h, timer_h1, timer_l;
631 timer_h = ioread32be(&dev->iseg->internal_timer_h);
632 timer_l = ioread32be(&dev->iseg->internal_timer_l);
633 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
634 if (timer_h != timer_h1) /* wrap around */
635 timer_l = ioread32be(&dev->iseg->internal_timer_l);
637 return (u64)timer_l | (u64)timer_h1 << 32;
640 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
642 struct mlx5_priv *priv = &mdev->priv;
643 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
645 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
646 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
650 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
651 priv->irq_info[i].mask);
653 if (IS_ENABLED(CONFIG_SMP) &&
654 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
655 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
660 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
662 struct mlx5_priv *priv = &mdev->priv;
663 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
665 irq_set_affinity_hint(irq, NULL);
666 free_cpumask_var(priv->irq_info[i].mask);
669 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
674 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
675 err = mlx5_irq_set_affinity_hint(mdev, i);
683 for (i--; i >= 0; i--)
684 mlx5_irq_clear_affinity_hint(mdev, i);
689 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
693 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
694 mlx5_irq_clear_affinity_hint(mdev, i);
697 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
700 struct mlx5_eq_table *table = &dev->priv.eq_table;
701 struct mlx5_eq *eq, *n;
704 spin_lock(&table->lock);
705 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
706 if (eq->index == vector) {
713 spin_unlock(&table->lock);
717 EXPORT_SYMBOL(mlx5_vector2eqn);
719 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
721 struct mlx5_eq_table *table = &dev->priv.eq_table;
724 spin_lock(&table->lock);
725 list_for_each_entry(eq, &table->comp_eqs_list, list)
726 if (eq->eqn == eqn) {
727 spin_unlock(&table->lock);
731 spin_unlock(&table->lock);
733 return ERR_PTR(-ENOENT);
736 static void free_comp_eqs(struct mlx5_core_dev *dev)
738 struct mlx5_eq_table *table = &dev->priv.eq_table;
739 struct mlx5_eq *eq, *n;
741 #ifdef CONFIG_RFS_ACCEL
743 free_irq_cpu_rmap(dev->rmap);
747 spin_lock(&table->lock);
748 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
750 spin_unlock(&table->lock);
751 if (mlx5_destroy_unmap_eq(dev, eq))
752 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
755 spin_lock(&table->lock);
757 spin_unlock(&table->lock);
760 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
762 struct mlx5_eq_table *table = &dev->priv.eq_table;
763 char name[MLX5_MAX_IRQ_NAME];
770 INIT_LIST_HEAD(&table->comp_eqs_list);
771 ncomp_vec = table->num_comp_vectors;
772 nent = MLX5_COMP_EQ_SIZE;
773 #ifdef CONFIG_RFS_ACCEL
774 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
778 for (i = 0; i < ncomp_vec; i++) {
779 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
785 #ifdef CONFIG_RFS_ACCEL
786 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
787 MLX5_EQ_VEC_COMP_BASE + i));
789 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
790 err = mlx5_create_map_eq(dev, eq,
791 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
792 name, MLX5_EQ_TYPE_COMP);
797 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
799 spin_lock(&table->lock);
800 list_add_tail(&eq->list, &table->comp_eqs_list);
801 spin_unlock(&table->lock);
811 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
813 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
814 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
818 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
819 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
820 query_out, sizeof(query_out));
825 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
826 if (!status || syndrome == MLX5_DRIVER_SYND) {
827 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
828 err, status, syndrome);
832 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
837 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
839 if (sup_issi & (1 << 1)) {
840 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
841 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
843 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
844 MLX5_SET(set_issi_in, set_in, current_issi, 1);
845 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
846 set_out, sizeof(set_out));
848 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
856 } else if (sup_issi & (1 << 0) || !sup_issi) {
863 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
865 struct pci_dev *pdev = dev->pdev;
868 pci_set_drvdata(dev->pdev, dev);
869 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
870 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
872 mutex_init(&priv->pgdir_mutex);
873 INIT_LIST_HEAD(&priv->pgdir_list);
874 spin_lock_init(&priv->mkey_lock);
876 mutex_init(&priv->alloc_mutex);
878 priv->numa_node = dev_to_node(&dev->pdev->dev);
880 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
884 err = mlx5_pci_enable_device(dev);
886 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
890 err = request_bar(pdev);
892 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
896 pci_set_master(pdev);
898 err = set_dma_caps(pdev);
900 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
904 dev->iseg_base = pci_resource_start(dev->pdev, 0);
905 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
908 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
915 pci_clear_master(dev->pdev);
916 release_bar(dev->pdev);
918 mlx5_pci_disable_device(dev);
921 debugfs_remove(priv->dbg_root);
925 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
928 pci_clear_master(dev->pdev);
929 release_bar(dev->pdev);
930 mlx5_pci_disable_device(dev);
931 debugfs_remove(priv->dbg_root);
934 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
936 struct pci_dev *pdev = dev->pdev;
939 err = mlx5_query_board_id(dev);
941 dev_err(&pdev->dev, "query board id failed\n");
945 err = mlx5_eq_init(dev);
947 dev_err(&pdev->dev, "failed to initialize eq\n");
951 err = mlx5_cq_debugfs_init(dev);
953 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
957 mlx5_init_qp_table(dev);
959 mlx5_init_srq_table(dev);
961 mlx5_init_mkey_table(dev);
963 mlx5_init_reserved_gids(dev);
965 mlx5_init_clock(dev);
967 dev->vxlan = mlx5_vxlan_create(dev);
969 err = mlx5_init_rl_table(dev);
971 dev_err(&pdev->dev, "Failed to init rate limiting\n");
972 goto err_tables_cleanup;
975 err = mlx5_mpfs_init(dev);
977 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
981 err = mlx5_eswitch_init(dev);
983 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
984 goto err_mpfs_cleanup;
987 err = mlx5_sriov_init(dev);
989 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
990 goto err_eswitch_cleanup;
993 err = mlx5_fpga_init(dev);
995 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
996 goto err_sriov_cleanup;
999 dev->tracer = mlx5_fw_tracer_create(dev);
1004 mlx5_sriov_cleanup(dev);
1005 err_eswitch_cleanup:
1006 mlx5_eswitch_cleanup(dev->priv.eswitch);
1008 mlx5_mpfs_cleanup(dev);
1010 mlx5_cleanup_rl_table(dev);
1012 mlx5_vxlan_destroy(dev->vxlan);
1013 mlx5_cleanup_mkey_table(dev);
1014 mlx5_cleanup_srq_table(dev);
1015 mlx5_cleanup_qp_table(dev);
1016 mlx5_cq_debugfs_cleanup(dev);
1019 mlx5_eq_cleanup(dev);
1025 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1027 mlx5_fw_tracer_destroy(dev->tracer);
1028 mlx5_fpga_cleanup(dev);
1029 mlx5_sriov_cleanup(dev);
1030 mlx5_eswitch_cleanup(dev->priv.eswitch);
1031 mlx5_mpfs_cleanup(dev);
1032 mlx5_cleanup_rl_table(dev);
1033 mlx5_vxlan_destroy(dev->vxlan);
1034 mlx5_cleanup_clock(dev);
1035 mlx5_cleanup_reserved_gids(dev);
1036 mlx5_cleanup_mkey_table(dev);
1037 mlx5_cleanup_srq_table(dev);
1038 mlx5_cleanup_qp_table(dev);
1039 mlx5_cq_debugfs_cleanup(dev);
1040 mlx5_eq_cleanup(dev);
1043 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1046 struct pci_dev *pdev = dev->pdev;
1049 mutex_lock(&dev->intf_state_mutex);
1050 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1051 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1056 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1057 fw_rev_min(dev), fw_rev_sub(dev));
1059 /* Only PFs hold the relevant PCIe information for this query */
1060 if (mlx5_core_is_pf(dev))
1061 pcie_print_link_status(dev->pdev);
1063 /* on load removing any previous indication of internal error, device is
1066 dev->state = MLX5_DEVICE_STATE_UP;
1068 /* wait for firmware to accept initialization segments configurations
1070 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1072 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1073 FW_PRE_INIT_TIMEOUT_MILI);
1077 err = mlx5_cmd_init(dev);
1079 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1083 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1085 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1086 FW_INIT_TIMEOUT_MILI);
1087 goto err_cmd_cleanup;
1090 err = mlx5_core_enable_hca(dev, 0);
1092 dev_err(&pdev->dev, "enable hca failed\n");
1093 goto err_cmd_cleanup;
1096 err = mlx5_core_set_issi(dev);
1098 dev_err(&pdev->dev, "failed to set issi\n");
1099 goto err_disable_hca;
1102 err = mlx5_satisfy_startup_pages(dev, 1);
1104 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1105 goto err_disable_hca;
1108 err = set_hca_ctrl(dev);
1110 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1111 goto reclaim_boot_pages;
1114 err = handle_hca_cap(dev);
1116 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1117 goto reclaim_boot_pages;
1120 err = handle_hca_cap_atomic(dev);
1122 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1123 goto reclaim_boot_pages;
1126 err = mlx5_satisfy_startup_pages(dev, 0);
1128 dev_err(&pdev->dev, "failed to allocate init pages\n");
1129 goto reclaim_boot_pages;
1132 err = mlx5_pagealloc_start(dev);
1134 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1135 goto reclaim_boot_pages;
1138 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1140 dev_err(&pdev->dev, "init hca failed\n");
1141 goto err_pagealloc_stop;
1144 mlx5_set_driver_version(dev);
1146 mlx5_start_health_poll(dev);
1148 err = mlx5_query_hca_caps(dev);
1150 dev_err(&pdev->dev, "query hca failed\n");
1155 err = mlx5_init_once(dev, priv);
1157 dev_err(&pdev->dev, "sw objs init failed\n");
1162 err = mlx5_alloc_irq_vectors(dev);
1164 dev_err(&pdev->dev, "alloc irq vectors failed\n");
1165 goto err_cleanup_once;
1168 dev->priv.uar = mlx5_get_uars_page(dev);
1169 if (IS_ERR(dev->priv.uar)) {
1170 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1171 err = PTR_ERR(dev->priv.uar);
1172 goto err_disable_msix;
1175 err = mlx5_start_eqs(dev);
1177 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1181 err = mlx5_fw_tracer_init(dev->tracer);
1183 dev_err(&pdev->dev, "Failed to init FW tracer\n");
1187 err = alloc_comp_eqs(dev);
1189 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1193 err = mlx5_irq_set_affinity_hints(dev);
1195 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1196 goto err_affinity_hints;
1199 err = mlx5_fpga_device_start(dev);
1201 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1202 goto err_fpga_start;
1205 err = mlx5_accel_ipsec_init(dev);
1207 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1208 goto err_ipsec_start;
1211 err = mlx5_accel_tls_init(dev);
1213 dev_err(&pdev->dev, "TLS device start failed %d\n", err);
1217 err = mlx5_init_fs(dev);
1219 dev_err(&pdev->dev, "Failed to init flow steering\n");
1223 err = mlx5_core_set_hca_defaults(dev);
1225 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1229 err = mlx5_sriov_attach(dev);
1231 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1235 if (mlx5_device_registered(dev)) {
1236 mlx5_attach_device(dev);
1238 err = mlx5_register_device(dev);
1240 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1245 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1247 mutex_unlock(&dev->intf_state_mutex);
1252 mlx5_sriov_detach(dev);
1255 mlx5_cleanup_fs(dev);
1258 mlx5_accel_tls_cleanup(dev);
1261 mlx5_accel_ipsec_cleanup(dev);
1264 mlx5_fpga_device_stop(dev);
1267 mlx5_irq_clear_affinity_hints(dev);
1273 mlx5_fw_tracer_cleanup(dev->tracer);
1279 mlx5_put_uars_page(dev, priv->uar);
1282 mlx5_free_irq_vectors(dev);
1286 mlx5_cleanup_once(dev);
1289 mlx5_stop_health_poll(dev);
1290 if (mlx5_cmd_teardown_hca(dev)) {
1291 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1296 mlx5_pagealloc_stop(dev);
1299 mlx5_reclaim_startup_pages(dev);
1302 mlx5_core_disable_hca(dev, 0);
1305 mlx5_cmd_cleanup(dev);
1308 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1309 mutex_unlock(&dev->intf_state_mutex);
1314 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1320 mlx5_drain_health_recovery(dev);
1322 mutex_lock(&dev->intf_state_mutex);
1323 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1324 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1327 mlx5_cleanup_once(dev);
1331 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1333 if (mlx5_device_registered(dev))
1334 mlx5_detach_device(dev);
1336 mlx5_sriov_detach(dev);
1337 mlx5_cleanup_fs(dev);
1338 mlx5_accel_ipsec_cleanup(dev);
1339 mlx5_accel_tls_cleanup(dev);
1340 mlx5_fpga_device_stop(dev);
1341 mlx5_irq_clear_affinity_hints(dev);
1343 mlx5_fw_tracer_cleanup(dev->tracer);
1345 mlx5_put_uars_page(dev, priv->uar);
1346 mlx5_free_irq_vectors(dev);
1348 mlx5_cleanup_once(dev);
1349 mlx5_stop_health_poll(dev);
1350 err = mlx5_cmd_teardown_hca(dev);
1352 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1355 mlx5_pagealloc_stop(dev);
1356 mlx5_reclaim_startup_pages(dev);
1357 mlx5_core_disable_hca(dev, 0);
1358 mlx5_cmd_cleanup(dev);
1361 mutex_unlock(&dev->intf_state_mutex);
1365 struct mlx5_core_event_handler {
1366 void (*event)(struct mlx5_core_dev *dev,
1367 enum mlx5_dev_event event,
1371 static const struct devlink_ops mlx5_devlink_ops = {
1372 #ifdef CONFIG_MLX5_ESWITCH
1373 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1374 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1375 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1376 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1377 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1378 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1382 #define MLX5_IB_MOD "mlx5_ib"
1383 static int init_one(struct pci_dev *pdev,
1384 const struct pci_device_id *id)
1386 struct mlx5_core_dev *dev;
1387 struct devlink *devlink;
1388 struct mlx5_priv *priv;
1391 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1393 dev_err(&pdev->dev, "kzalloc failed\n");
1397 dev = devlink_priv(devlink);
1399 priv->pci_dev_data = id->driver_data;
1401 pci_set_drvdata(pdev, dev);
1404 dev->event = mlx5_core_event;
1405 dev->profile = &profile[prof_sel];
1407 INIT_LIST_HEAD(&priv->ctx_list);
1408 spin_lock_init(&priv->ctx_lock);
1409 mutex_init(&dev->pci_status_mutex);
1410 mutex_init(&dev->intf_state_mutex);
1412 INIT_LIST_HEAD(&priv->waiting_events_list);
1413 priv->is_accum_events = false;
1415 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1416 err = init_srcu_struct(&priv->pfault_srcu);
1418 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1423 mutex_init(&priv->bfregs.reg_head.lock);
1424 mutex_init(&priv->bfregs.wc_head.lock);
1425 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1426 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1428 err = mlx5_pci_init(dev, priv);
1430 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1434 err = mlx5_health_init(dev);
1436 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1440 mlx5_pagealloc_init(dev);
1442 err = mlx5_load_one(dev, priv, true);
1444 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1448 request_module_nowait(MLX5_IB_MOD);
1450 err = devlink_register(devlink, &pdev->dev);
1454 pci_save_state(pdev);
1458 mlx5_unload_one(dev, priv, true);
1460 mlx5_pagealloc_cleanup(dev);
1461 mlx5_health_cleanup(dev);
1463 mlx5_pci_close(dev, priv);
1465 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1466 cleanup_srcu_struct(&priv->pfault_srcu);
1469 devlink_free(devlink);
1474 static void remove_one(struct pci_dev *pdev)
1476 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1477 struct devlink *devlink = priv_to_devlink(dev);
1478 struct mlx5_priv *priv = &dev->priv;
1480 devlink_unregister(devlink);
1481 mlx5_unregister_device(dev);
1483 if (mlx5_unload_one(dev, priv, true)) {
1484 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1485 mlx5_health_cleanup(dev);
1489 mlx5_pagealloc_cleanup(dev);
1490 mlx5_health_cleanup(dev);
1491 mlx5_pci_close(dev, priv);
1492 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1493 cleanup_srcu_struct(&priv->pfault_srcu);
1495 devlink_free(devlink);
1498 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1499 pci_channel_state_t state)
1501 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1502 struct mlx5_priv *priv = &dev->priv;
1504 dev_info(&pdev->dev, "%s was called\n", __func__);
1506 mlx5_enter_error_state(dev, false);
1507 mlx5_unload_one(dev, priv, false);
1508 /* In case of kernel call drain the health wq */
1510 mlx5_drain_health_wq(dev);
1511 mlx5_pci_disable_device(dev);
1514 return state == pci_channel_io_perm_failure ?
1515 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1518 /* wait for the device to show vital signs by waiting
1519 * for the health counter to start counting.
1521 static int wait_vital(struct pci_dev *pdev)
1523 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1524 struct mlx5_core_health *health = &dev->priv.health;
1525 const int niter = 100;
1530 for (i = 0; i < niter; i++) {
1531 count = ioread32be(health->health_counter);
1532 if (count && count != 0xffffffff) {
1533 if (last_count && last_count != count) {
1534 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1545 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1547 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1550 dev_info(&pdev->dev, "%s was called\n", __func__);
1552 err = mlx5_pci_enable_device(dev);
1554 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1556 return PCI_ERS_RESULT_DISCONNECT;
1559 pci_set_master(pdev);
1560 pci_restore_state(pdev);
1561 pci_save_state(pdev);
1563 if (wait_vital(pdev)) {
1564 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1565 return PCI_ERS_RESULT_DISCONNECT;
1568 return PCI_ERS_RESULT_RECOVERED;
1571 static void mlx5_pci_resume(struct pci_dev *pdev)
1573 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1574 struct mlx5_priv *priv = &dev->priv;
1577 dev_info(&pdev->dev, "%s was called\n", __func__);
1579 err = mlx5_load_one(dev, priv, false);
1581 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1584 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1587 static const struct pci_error_handlers mlx5_err_handler = {
1588 .error_detected = mlx5_pci_err_detected,
1589 .slot_reset = mlx5_pci_slot_reset,
1590 .resume = mlx5_pci_resume
1593 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1597 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1598 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1602 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1603 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1607 /* Panic tear down fw command will stop the PCI bus communication
1608 * with the HCA, so the health polll is no longer needed.
1610 mlx5_drain_health_wq(dev);
1611 mlx5_stop_health_poll(dev);
1613 ret = mlx5_cmd_force_teardown_hca(dev);
1615 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1616 mlx5_start_health_poll(dev);
1620 mlx5_enter_error_state(dev, true);
1622 /* Some platforms requiring freeing the IRQ's in the shutdown
1623 * flow. If they aren't freed they can't be allocated after
1624 * kexec. There is no need to cleanup the mlx5_core software
1627 mlx5_irq_clear_affinity_hints(dev);
1628 mlx5_core_eq_free_irqs(dev);
1633 static void shutdown(struct pci_dev *pdev)
1635 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1636 struct mlx5_priv *priv = &dev->priv;
1639 dev_info(&pdev->dev, "Shutdown was called\n");
1640 err = mlx5_try_fast_unload(dev);
1642 mlx5_unload_one(dev, priv, false);
1643 mlx5_pci_disable_device(dev);
1646 static const struct pci_device_id mlx5_core_pci_table[] = {
1647 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1648 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1649 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1650 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1651 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1652 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1653 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1654 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1655 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1656 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1657 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1658 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1659 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1660 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1664 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1666 void mlx5_disable_device(struct mlx5_core_dev *dev)
1668 mlx5_pci_err_detected(dev->pdev, 0);
1671 void mlx5_recover_device(struct mlx5_core_dev *dev)
1673 mlx5_pci_disable_device(dev);
1674 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1675 mlx5_pci_resume(dev->pdev);
1678 static struct pci_driver mlx5_core_driver = {
1679 .name = DRIVER_NAME,
1680 .id_table = mlx5_core_pci_table,
1682 .remove = remove_one,
1683 .shutdown = shutdown,
1684 .err_handler = &mlx5_err_handler,
1685 .sriov_configure = mlx5_core_sriov_configure,
1688 static void mlx5_core_verify_params(void)
1690 if (prof_sel >= ARRAY_SIZE(profile)) {
1691 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1693 ARRAY_SIZE(profile) - 1,
1695 prof_sel = MLX5_DEFAULT_PROF;
1699 static int __init init(void)
1703 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1705 mlx5_core_verify_params();
1706 mlx5_fpga_ipsec_build_fs_cmds();
1707 mlx5_register_debugfs();
1709 err = pci_register_driver(&mlx5_core_driver);
1713 #ifdef CONFIG_MLX5_CORE_EN
1720 mlx5_unregister_debugfs();
1724 static void __exit cleanup(void)
1726 #ifdef CONFIG_MLX5_CORE_EN
1729 pci_unregister_driver(&mlx5_core_driver);
1730 mlx5_unregister_debugfs();
1734 module_exit(cleanup);