2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #include "mlx5_core.h"
52 #ifdef CONFIG_MLX5_CORE_EN
56 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
57 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
58 MODULE_LICENSE("Dual BSD/GPL");
59 MODULE_VERSION(DRIVER_VERSION);
61 int mlx5_core_debug_mask;
62 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
63 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
65 #define MLX5_DEFAULT_PROF 2
66 static int prof_sel = MLX5_DEFAULT_PROF;
67 module_param_named(prof_sel, prof_sel, int, 0444);
68 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
70 static LIST_HEAD(intf_list);
71 static LIST_HEAD(dev_list);
72 static DEFINE_MUTEX(intf_mutex);
74 struct mlx5_device_context {
75 struct list_head list;
76 struct mlx5_interface *intf;
80 static struct mlx5_profile profile[] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE,
89 .mask = MLX5_PROF_MASK_QP_SIZE |
90 MLX5_PROF_MASK_MR_CACHE,
159 #define FW_INIT_TIMEOUT_MILI 2000
160 #define FW_INIT_WAIT_MS 2
162 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
164 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
167 while (fw_initializing(dev)) {
168 if (time_after(jiffies, end)) {
172 msleep(FW_INIT_WAIT_MS);
178 static int set_dma_caps(struct pci_dev *pdev)
182 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
184 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
185 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
187 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
192 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
195 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
196 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
199 "Can't set consistent PCI DMA mask, aborting\n");
204 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
208 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
210 struct pci_dev *pdev = dev->pdev;
213 mutex_lock(&dev->pci_status_mutex);
214 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
215 err = pci_enable_device(pdev);
217 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
219 mutex_unlock(&dev->pci_status_mutex);
224 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
226 struct pci_dev *pdev = dev->pdev;
228 mutex_lock(&dev->pci_status_mutex);
229 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
230 pci_disable_device(pdev);
231 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
233 mutex_unlock(&dev->pci_status_mutex);
236 static int request_bar(struct pci_dev *pdev)
240 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
241 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
245 err = pci_request_regions(pdev, DRIVER_NAME);
247 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
252 static void release_bar(struct pci_dev *pdev)
254 pci_release_regions(pdev);
257 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
259 struct mlx5_priv *priv = &dev->priv;
260 struct mlx5_eq_table *table = &priv->eq_table;
261 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
265 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
266 MLX5_EQ_VEC_COMP_BASE;
267 nvec = min_t(int, nvec, num_eqs);
268 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
271 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
273 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
274 if (!priv->msix_arr || !priv->irq_info)
277 for (i = 0; i < nvec; i++)
278 priv->msix_arr[i].entry = i;
280 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
281 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
285 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
290 kfree(priv->irq_info);
291 kfree(priv->msix_arr);
295 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
297 struct mlx5_priv *priv = &dev->priv;
299 pci_disable_msix(dev->pdev);
300 kfree(priv->irq_info);
301 kfree(priv->msix_arr);
304 struct mlx5_reg_host_endianess {
310 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
313 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
314 MLX5_DEV_CAP_FLAG_DCT,
317 static u16 to_fw_pkey_sz(u32 size)
333 pr_warn("invalid pkey table size %d\n", size);
338 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
339 enum mlx5_cap_mode cap_mode)
341 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
342 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
343 void *out, *hca_caps;
344 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
347 memset(in, 0, sizeof(in));
348 out = kzalloc(out_sz, GFP_KERNEL);
352 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
353 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
354 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
358 err = mlx5_cmd_status_to_err_v2(out);
361 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
362 cap_type, cap_mode, err);
366 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
369 case HCA_CAP_OPMOD_GET_MAX:
370 memcpy(dev->hca_caps_max[cap_type], hca_caps,
371 MLX5_UN_SZ_BYTES(hca_cap_union));
373 case HCA_CAP_OPMOD_GET_CUR:
374 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
375 MLX5_UN_SZ_BYTES(hca_cap_union));
379 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
389 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
391 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
394 memset(out, 0, sizeof(out));
396 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
397 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
401 err = mlx5_cmd_status_to_err_v2(out);
406 static int handle_hca_cap(struct mlx5_core_dev *dev)
408 void *set_ctx = NULL;
409 struct mlx5_profile *prof = dev->profile;
411 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
414 set_ctx = kzalloc(set_sz, GFP_KERNEL);
418 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
422 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
426 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
428 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
429 MLX5_ST_SZ_BYTES(cmd_hca_cap));
431 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
432 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
434 /* we limit the size of the pkey table to 128 entries for now */
435 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
438 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
439 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
442 /* disable cmdif checksum */
443 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
445 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
447 err = set_caps(dev, set_ctx, set_sz);
454 static int set_hca_ctrl(struct mlx5_core_dev *dev)
456 struct mlx5_reg_host_endianess he_in;
457 struct mlx5_reg_host_endianess he_out;
460 if (!mlx5_core_is_pf(dev))
463 memset(&he_in, 0, sizeof(he_in));
464 he_in.he = MLX5_SET_HOST_ENDIANNESS;
465 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
466 &he_out, sizeof(he_out),
467 MLX5_REG_HOST_ENDIANNESS, 0, 1);
471 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
473 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
474 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
477 memset(in, 0, sizeof(in));
478 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
479 MLX5_SET(enable_hca_in, in, function_id, func_id);
480 memset(out, 0, sizeof(out));
482 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
486 return mlx5_cmd_status_to_err_v2(out);
489 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
491 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
492 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
495 memset(in, 0, sizeof(in));
496 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
497 MLX5_SET(disable_hca_in, in, function_id, func_id);
498 memset(out, 0, sizeof(out));
499 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
503 return mlx5_cmd_status_to_err_v2(out);
506 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
508 struct mlx5_priv *priv = &mdev->priv;
509 struct msix_entry *msix = priv->msix_arr;
510 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
511 int numa_node = priv->numa_node;
514 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
515 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
519 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
520 priv->irq_info[i].mask);
522 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
524 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
532 free_cpumask_var(priv->irq_info[i].mask);
536 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
538 struct mlx5_priv *priv = &mdev->priv;
539 struct msix_entry *msix = priv->msix_arr;
540 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
542 irq_set_affinity_hint(irq, NULL);
543 free_cpumask_var(priv->irq_info[i].mask);
546 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
551 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
552 err = mlx5_irq_set_affinity_hint(mdev, i);
560 for (i--; i >= 0; i--)
561 mlx5_irq_clear_affinity_hint(mdev, i);
566 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
570 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
571 mlx5_irq_clear_affinity_hint(mdev, i);
574 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
576 struct mlx5_eq_table *table = &dev->priv.eq_table;
577 struct mlx5_eq *eq, *n;
580 spin_lock(&table->lock);
581 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
582 if (eq->index == vector) {
589 spin_unlock(&table->lock);
593 EXPORT_SYMBOL(mlx5_vector2eqn);
595 static void free_comp_eqs(struct mlx5_core_dev *dev)
597 struct mlx5_eq_table *table = &dev->priv.eq_table;
598 struct mlx5_eq *eq, *n;
600 spin_lock(&table->lock);
601 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
603 spin_unlock(&table->lock);
604 if (mlx5_destroy_unmap_eq(dev, eq))
605 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
608 spin_lock(&table->lock);
610 spin_unlock(&table->lock);
613 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
615 struct mlx5_eq_table *table = &dev->priv.eq_table;
616 char name[MLX5_MAX_IRQ_NAME];
623 INIT_LIST_HEAD(&table->comp_eqs_list);
624 ncomp_vec = table->num_comp_vectors;
625 nent = MLX5_COMP_EQ_SIZE;
626 for (i = 0; i < ncomp_vec; i++) {
627 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
633 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
634 err = mlx5_create_map_eq(dev, eq,
635 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
636 name, &dev->priv.uuari.uars[0]);
641 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
643 spin_lock(&table->lock);
644 list_add_tail(&eq->list, &table->comp_eqs_list);
645 spin_unlock(&table->lock);
655 #ifdef CONFIG_MLX5_CORE_EN
656 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
658 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
659 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
660 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
661 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
665 memset(query_in, 0, sizeof(query_in));
666 memset(query_out, 0, sizeof(query_out));
668 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
670 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
671 query_out, sizeof(query_out));
673 if (((struct mlx5_outbox_hdr *)query_out)->status ==
674 MLX5_CMD_STAT_BAD_OP_ERR) {
675 pr_debug("Only ISSI 0 is supported\n");
679 pr_err("failed to query ISSI\n");
683 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
685 if (sup_issi & (1 << 1)) {
686 memset(set_in, 0, sizeof(set_in));
687 memset(set_out, 0, sizeof(set_out));
689 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
690 MLX5_SET(set_issi_in, set_in, current_issi, 1);
692 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
693 set_out, sizeof(set_out));
695 pr_err("failed to set ISSI=1\n");
702 } else if (sup_issi & (1 << 0) || !sup_issi) {
710 static int map_bf_area(struct mlx5_core_dev *dev)
712 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
713 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
715 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
717 return dev->priv.bf_mapping ? 0 : -ENOMEM;
720 static void unmap_bf_area(struct mlx5_core_dev *dev)
722 if (dev->priv.bf_mapping)
723 io_mapping_free(dev->priv.bf_mapping);
726 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
728 struct mlx5_device_context *dev_ctx;
729 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
731 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
735 dev_ctx->intf = intf;
736 dev_ctx->context = intf->add(dev);
738 if (dev_ctx->context) {
739 spin_lock_irq(&priv->ctx_lock);
740 list_add_tail(&dev_ctx->list, &priv->ctx_list);
741 spin_unlock_irq(&priv->ctx_lock);
747 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
749 struct mlx5_device_context *dev_ctx;
750 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
752 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
753 if (dev_ctx->intf == intf) {
754 spin_lock_irq(&priv->ctx_lock);
755 list_del(&dev_ctx->list);
756 spin_unlock_irq(&priv->ctx_lock);
758 intf->remove(dev, dev_ctx->context);
764 static int mlx5_register_device(struct mlx5_core_dev *dev)
766 struct mlx5_priv *priv = &dev->priv;
767 struct mlx5_interface *intf;
769 mutex_lock(&intf_mutex);
770 list_add_tail(&priv->dev_list, &dev_list);
771 list_for_each_entry(intf, &intf_list, list)
772 mlx5_add_device(intf, priv);
773 mutex_unlock(&intf_mutex);
778 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
780 struct mlx5_priv *priv = &dev->priv;
781 struct mlx5_interface *intf;
783 mutex_lock(&intf_mutex);
784 list_for_each_entry(intf, &intf_list, list)
785 mlx5_remove_device(intf, priv);
786 list_del(&priv->dev_list);
787 mutex_unlock(&intf_mutex);
790 int mlx5_register_interface(struct mlx5_interface *intf)
792 struct mlx5_priv *priv;
794 if (!intf->add || !intf->remove)
797 mutex_lock(&intf_mutex);
798 list_add_tail(&intf->list, &intf_list);
799 list_for_each_entry(priv, &dev_list, dev_list)
800 mlx5_add_device(intf, priv);
801 mutex_unlock(&intf_mutex);
805 EXPORT_SYMBOL(mlx5_register_interface);
807 void mlx5_unregister_interface(struct mlx5_interface *intf)
809 struct mlx5_priv *priv;
811 mutex_lock(&intf_mutex);
812 list_for_each_entry(priv, &dev_list, dev_list)
813 mlx5_remove_device(intf, priv);
814 list_del(&intf->list);
815 mutex_unlock(&intf_mutex);
817 EXPORT_SYMBOL(mlx5_unregister_interface);
819 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
821 struct mlx5_priv *priv = &mdev->priv;
822 struct mlx5_device_context *dev_ctx;
826 spin_lock_irqsave(&priv->ctx_lock, flags);
828 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
829 if ((dev_ctx->intf->protocol == protocol) &&
830 dev_ctx->intf->get_dev) {
831 result = dev_ctx->intf->get_dev(dev_ctx->context);
835 spin_unlock_irqrestore(&priv->ctx_lock, flags);
839 EXPORT_SYMBOL(mlx5_get_protocol_dev);
841 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
843 struct pci_dev *pdev = dev->pdev;
846 pci_set_drvdata(dev->pdev, dev);
847 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
848 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
850 mutex_init(&priv->pgdir_mutex);
851 INIT_LIST_HEAD(&priv->pgdir_list);
852 spin_lock_init(&priv->mkey_lock);
854 mutex_init(&priv->alloc_mutex);
856 priv->numa_node = dev_to_node(&dev->pdev->dev);
858 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
862 err = mlx5_pci_enable_device(dev);
864 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
868 err = request_bar(pdev);
870 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
874 pci_set_master(pdev);
876 err = set_dma_caps(pdev);
878 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
882 dev->iseg_base = pci_resource_start(dev->pdev, 0);
883 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
886 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
893 pci_clear_master(dev->pdev);
894 release_bar(dev->pdev);
896 mlx5_pci_disable_device(dev);
899 debugfs_remove(priv->dbg_root);
903 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
906 pci_clear_master(dev->pdev);
907 release_bar(dev->pdev);
908 mlx5_pci_disable_device(dev);
909 debugfs_remove(priv->dbg_root);
912 #define MLX5_IB_MOD "mlx5_ib"
913 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
915 struct pci_dev *pdev = dev->pdev;
918 mutex_lock(&dev->intf_state_mutex);
919 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
920 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
925 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
926 fw_rev_min(dev), fw_rev_sub(dev));
928 /* on load removing any previous indication of internal error, device is
931 dev->state = MLX5_DEVICE_STATE_UP;
933 err = mlx5_cmd_init(dev);
935 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
939 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
941 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
942 FW_INIT_TIMEOUT_MILI);
946 mlx5_pagealloc_init(dev);
948 err = mlx5_core_enable_hca(dev, 0);
950 dev_err(&pdev->dev, "enable hca failed\n");
951 goto err_pagealloc_cleanup;
954 #ifdef CONFIG_MLX5_CORE_EN
955 err = mlx5_core_set_issi(dev);
957 dev_err(&pdev->dev, "failed to set issi\n");
958 goto err_disable_hca;
962 err = mlx5_satisfy_startup_pages(dev, 1);
964 dev_err(&pdev->dev, "failed to allocate boot pages\n");
965 goto err_disable_hca;
968 err = set_hca_ctrl(dev);
970 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
971 goto reclaim_boot_pages;
974 err = handle_hca_cap(dev);
976 dev_err(&pdev->dev, "handle_hca_cap failed\n");
977 goto reclaim_boot_pages;
980 err = mlx5_satisfy_startup_pages(dev, 0);
982 dev_err(&pdev->dev, "failed to allocate init pages\n");
983 goto reclaim_boot_pages;
986 err = mlx5_pagealloc_start(dev);
988 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
989 goto reclaim_boot_pages;
992 err = mlx5_cmd_init_hca(dev);
994 dev_err(&pdev->dev, "init hca failed\n");
995 goto err_pagealloc_stop;
998 mlx5_start_health_poll(dev);
1000 err = mlx5_query_hca_caps(dev);
1002 dev_err(&pdev->dev, "query hca failed\n");
1006 err = mlx5_query_board_id(dev);
1008 dev_err(&pdev->dev, "query board id failed\n");
1012 err = mlx5_enable_msix(dev);
1014 dev_err(&pdev->dev, "enable msix failed\n");
1018 err = mlx5_eq_init(dev);
1020 dev_err(&pdev->dev, "failed to initialize eq\n");
1024 err = mlx5_alloc_uuars(dev, &priv->uuari);
1026 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1027 goto err_eq_cleanup;
1030 err = mlx5_start_eqs(dev);
1032 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1036 err = alloc_comp_eqs(dev);
1038 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1042 if (map_bf_area(dev))
1043 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1045 err = mlx5_irq_set_affinity_hints(dev);
1047 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1048 goto err_unmap_bf_area;
1051 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1053 mlx5_init_cq_table(dev);
1054 mlx5_init_qp_table(dev);
1055 mlx5_init_srq_table(dev);
1056 mlx5_init_mr_table(dev);
1058 #ifdef CONFIG_MLX5_CORE_EN
1059 err = mlx5_eswitch_init(dev);
1061 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1066 err = mlx5_sriov_init(dev);
1068 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1072 err = mlx5_register_device(dev);
1074 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1078 err = request_module_nowait(MLX5_IB_MOD);
1080 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1082 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1084 mutex_unlock(&dev->intf_state_mutex);
1089 if (mlx5_sriov_cleanup(dev))
1090 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1092 #ifdef CONFIG_MLX5_CORE_EN
1093 mlx5_eswitch_cleanup(dev->priv.eswitch);
1096 mlx5_cleanup_mr_table(dev);
1097 mlx5_cleanup_srq_table(dev);
1098 mlx5_cleanup_qp_table(dev);
1099 mlx5_cleanup_cq_table(dev);
1100 mlx5_irq_clear_affinity_hints(dev);
1111 mlx5_free_uuars(dev, &priv->uuari);
1114 mlx5_eq_cleanup(dev);
1117 mlx5_disable_msix(dev);
1120 mlx5_stop_health_poll(dev);
1121 if (mlx5_cmd_teardown_hca(dev)) {
1122 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1127 mlx5_pagealloc_stop(dev);
1130 mlx5_reclaim_startup_pages(dev);
1133 mlx5_core_disable_hca(dev, 0);
1135 err_pagealloc_cleanup:
1136 mlx5_pagealloc_cleanup(dev);
1137 mlx5_cmd_cleanup(dev);
1140 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1141 mutex_unlock(&dev->intf_state_mutex);
1146 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1150 err = mlx5_sriov_cleanup(dev);
1152 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1157 mutex_lock(&dev->intf_state_mutex);
1158 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1159 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1163 mlx5_unregister_device(dev);
1164 #ifdef CONFIG_MLX5_CORE_EN
1165 mlx5_eswitch_cleanup(dev->priv.eswitch);
1168 mlx5_cleanup_mr_table(dev);
1169 mlx5_cleanup_srq_table(dev);
1170 mlx5_cleanup_qp_table(dev);
1171 mlx5_cleanup_cq_table(dev);
1172 mlx5_irq_clear_affinity_hints(dev);
1176 mlx5_free_uuars(dev, &priv->uuari);
1177 mlx5_eq_cleanup(dev);
1178 mlx5_disable_msix(dev);
1179 mlx5_stop_health_poll(dev);
1180 err = mlx5_cmd_teardown_hca(dev);
1182 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1185 mlx5_pagealloc_stop(dev);
1186 mlx5_reclaim_startup_pages(dev);
1187 mlx5_core_disable_hca(dev, 0);
1188 mlx5_pagealloc_cleanup(dev);
1189 mlx5_cmd_cleanup(dev);
1192 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1193 mutex_unlock(&dev->intf_state_mutex);
1197 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1198 unsigned long param)
1200 struct mlx5_priv *priv = &dev->priv;
1201 struct mlx5_device_context *dev_ctx;
1202 unsigned long flags;
1204 spin_lock_irqsave(&priv->ctx_lock, flags);
1206 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1207 if (dev_ctx->intf->event)
1208 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1210 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1213 struct mlx5_core_event_handler {
1214 void (*event)(struct mlx5_core_dev *dev,
1215 enum mlx5_dev_event event,
1220 static int init_one(struct pci_dev *pdev,
1221 const struct pci_device_id *id)
1223 struct mlx5_core_dev *dev;
1224 struct mlx5_priv *priv;
1227 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1229 dev_err(&pdev->dev, "kzalloc failed\n");
1233 priv->pci_dev_data = id->driver_data;
1235 pci_set_drvdata(pdev, dev);
1237 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1238 pr_warn("selected profile out of range, selecting default (%d)\n",
1240 prof_sel = MLX5_DEFAULT_PROF;
1242 dev->profile = &profile[prof_sel];
1244 dev->event = mlx5_core_event;
1246 INIT_LIST_HEAD(&priv->ctx_list);
1247 spin_lock_init(&priv->ctx_lock);
1248 mutex_init(&dev->pci_status_mutex);
1249 mutex_init(&dev->intf_state_mutex);
1250 err = mlx5_pci_init(dev, priv);
1252 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1256 err = mlx5_health_init(dev);
1258 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1262 err = mlx5_load_one(dev, priv);
1264 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1271 mlx5_health_cleanup(dev);
1273 mlx5_pci_close(dev, priv);
1275 pci_set_drvdata(pdev, NULL);
1281 static void remove_one(struct pci_dev *pdev)
1283 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1284 struct mlx5_priv *priv = &dev->priv;
1286 if (mlx5_unload_one(dev, priv)) {
1287 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1288 mlx5_health_cleanup(dev);
1291 mlx5_health_cleanup(dev);
1292 mlx5_pci_close(dev, priv);
1293 pci_set_drvdata(pdev, NULL);
1297 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1298 pci_channel_state_t state)
1300 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1301 struct mlx5_priv *priv = &dev->priv;
1303 dev_info(&pdev->dev, "%s was called\n", __func__);
1304 mlx5_enter_error_state(dev);
1305 mlx5_unload_one(dev, priv);
1306 mlx5_pci_disable_device(dev);
1307 return state == pci_channel_io_perm_failure ?
1308 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1311 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1313 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1316 dev_info(&pdev->dev, "%s was called\n", __func__);
1318 err = mlx5_pci_enable_device(dev);
1320 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1322 return PCI_ERS_RESULT_DISCONNECT;
1324 pci_set_master(pdev);
1325 pci_set_power_state(pdev, PCI_D0);
1326 pci_restore_state(pdev);
1328 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1331 void mlx5_disable_device(struct mlx5_core_dev *dev)
1333 mlx5_pci_err_detected(dev->pdev, 0);
1336 /* wait for the device to show vital signs. For now we check
1337 * that we can read the device ID and that the health buffer
1338 * shows a non zero value which is different than 0xffffffff
1340 static void wait_vital(struct pci_dev *pdev)
1342 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1343 struct mlx5_core_health *health = &dev->priv.health;
1344 const int niter = 100;
1349 /* Wait for firmware to be ready after reset */
1351 for (i = 0; i < niter; i++) {
1352 if (pci_read_config_word(pdev, 2, &did)) {
1353 dev_warn(&pdev->dev, "failed reading config word\n");
1356 if (did == pdev->device) {
1357 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1363 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1365 for (i = 0; i < niter; i++) {
1366 count = ioread32be(health->health_counter);
1367 if (count && count != 0xffffffff) {
1368 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1375 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1378 static void mlx5_pci_resume(struct pci_dev *pdev)
1380 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1381 struct mlx5_priv *priv = &dev->priv;
1384 dev_info(&pdev->dev, "%s was called\n", __func__);
1386 pci_save_state(pdev);
1389 err = mlx5_load_one(dev, priv);
1391 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1394 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1397 static const struct pci_error_handlers mlx5_err_handler = {
1398 .error_detected = mlx5_pci_err_detected,
1399 .slot_reset = mlx5_pci_slot_reset,
1400 .resume = mlx5_pci_resume
1403 static const struct pci_device_id mlx5_core_pci_table[] = {
1404 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1405 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1406 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1407 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1408 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1409 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1413 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1415 static struct pci_driver mlx5_core_driver = {
1416 .name = DRIVER_NAME,
1417 .id_table = mlx5_core_pci_table,
1419 .remove = remove_one,
1420 .err_handler = &mlx5_err_handler,
1421 .sriov_configure = mlx5_core_sriov_configure,
1424 static int __init init(void)
1428 mlx5_register_debugfs();
1430 err = pci_register_driver(&mlx5_core_driver);
1434 #ifdef CONFIG_MLX5_CORE_EN
1441 mlx5_unregister_debugfs();
1445 static void __exit cleanup(void)
1447 #ifdef CONFIG_MLX5_CORE_EN
1450 pci_unregister_driver(&mlx5_core_driver);
1451 mlx5_unregister_debugfs();
1455 module_exit(cleanup);