2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/qp.h>
44 #include <linux/mlx5/srq.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include "mlx5_core.h"
50 #define DRIVER_NAME "mlx5_core"
51 #define DRIVER_VERSION "2.2-1"
52 #define DRIVER_RELDATE "Feb 2014"
54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55 MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
56 MODULE_LICENSE("Dual BSD/GPL");
57 MODULE_VERSION(DRIVER_VERSION);
59 int mlx5_core_debug_mask;
60 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
61 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
63 #define MLX5_DEFAULT_PROF 2
64 static int prof_sel = MLX5_DEFAULT_PROF;
65 module_param_named(prof_sel, prof_sel, int, 0444);
66 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
68 struct workqueue_struct *mlx5_core_wq;
69 static LIST_HEAD(intf_list);
70 static LIST_HEAD(dev_list);
71 static DEFINE_MUTEX(intf_mutex);
73 struct mlx5_device_context {
74 struct list_head list;
75 struct mlx5_interface *intf;
79 static struct mlx5_profile profile[] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
158 static int set_dma_caps(struct pci_dev *pdev)
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
164 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
165 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
167 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
175 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
176 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
179 "Can't set consistent PCI DMA mask, aborting\n");
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
188 static int request_bar(struct pci_dev *pdev)
192 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
193 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
197 err = pci_request_regions(pdev, DRIVER_NAME);
199 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
204 static void release_bar(struct pci_dev *pdev)
206 pci_release_regions(pdev);
209 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
211 struct mlx5_eq_table *table = &dev->priv.eq_table;
212 int num_eqs = 1 << dev->caps.gen.log_max_eq;
216 nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
217 nvec = min_t(int, nvec, num_eqs);
218 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
221 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
222 if (!table->msix_arr)
225 for (i = 0; i < nvec; i++)
226 table->msix_arr[i].entry = i;
228 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
229 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
233 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
238 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
240 struct mlx5_eq_table *table = &dev->priv.eq_table;
242 pci_disable_msix(dev->pdev);
243 kfree(table->msix_arr);
246 struct mlx5_reg_host_endianess {
252 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
255 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
256 MLX5_DEV_CAP_FLAG_DCT,
259 static u16 to_fw_pkey_sz(u32 size)
275 pr_warn("invalid pkey table size %d\n", size);
280 /* selectively copy writable fields clearing any reserved area
282 static void copy_rw_fields(void *to, struct mlx5_caps *from)
284 __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
287 MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
288 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
289 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
290 MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
291 MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
292 MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
293 v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
294 *flags_off = cpu_to_be64(v64);
297 static u16 get_pkey_table_size(int pkey)
299 if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
302 return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
305 static void fw2drv_caps(struct mlx5_caps *caps, void *out)
307 struct mlx5_general_caps *gen = &caps->gen;
309 gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
310 gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
311 gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
312 gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
313 gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
314 gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
315 gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
316 gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
317 gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
318 gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
319 gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
320 gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
321 gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
322 gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
323 gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
324 gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
325 gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
326 gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
327 gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
328 gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
329 gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
330 gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
331 gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
332 gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
333 gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
334 pr_debug("flags = 0x%llx\n", gen->flags);
335 gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
336 gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
337 gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
338 gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
339 gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
340 gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
341 gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
342 gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
343 gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
344 gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
345 gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
348 static const char *caps_opmod_str(u16 opmod)
351 case HCA_CAP_OPMOD_GET_MAX:
353 case HCA_CAP_OPMOD_GET_CUR:
360 int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
363 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
364 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
368 memset(in, 0, sizeof(in));
369 out = kzalloc(out_sz, GFP_KERNEL);
372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
374 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
378 err = mlx5_cmd_status_to_err_v2(out);
380 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
383 mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
384 fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
391 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
393 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
396 memset(out, 0, sizeof(out));
398 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
399 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
403 err = mlx5_cmd_status_to_err_v2(out);
408 static int handle_hca_cap(struct mlx5_core_dev *dev)
410 void *set_ctx = NULL;
411 struct mlx5_profile *prof = dev->profile;
412 struct mlx5_caps *cur_caps = NULL;
413 struct mlx5_caps *max_caps = NULL;
415 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
417 set_ctx = kzalloc(set_sz, GFP_KERNEL);
421 max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
425 cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
429 err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
433 err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
437 /* we limit the size of the pkey table to 128 entries for now */
438 cur_caps->gen.pkey_table_size = 128;
440 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
441 cur_caps->gen.log_max_qp = prof->log_max_qp;
443 /* disable checksum */
444 cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
446 copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
448 err = set_caps(dev, set_ctx, set_sz);
458 static int set_hca_ctrl(struct mlx5_core_dev *dev)
460 struct mlx5_reg_host_endianess he_in;
461 struct mlx5_reg_host_endianess he_out;
464 memset(&he_in, 0, sizeof(he_in));
465 he_in.he = MLX5_SET_HOST_ENDIANNESS;
466 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
467 &he_out, sizeof(he_out),
468 MLX5_REG_HOST_ENDIANNESS, 0, 1);
472 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
475 struct mlx5_enable_hca_mbox_in in;
476 struct mlx5_enable_hca_mbox_out out;
478 memset(&in, 0, sizeof(in));
479 memset(&out, 0, sizeof(out));
480 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
481 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
486 return mlx5_cmd_status_to_err(&out.hdr);
491 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
494 struct mlx5_disable_hca_mbox_in in;
495 struct mlx5_disable_hca_mbox_out out;
497 memset(&in, 0, sizeof(in));
498 memset(&out, 0, sizeof(out));
499 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
500 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
505 return mlx5_cmd_status_to_err(&out.hdr);
510 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
512 struct mlx5_priv *priv = &dev->priv;
516 pci_set_drvdata(dev->pdev, dev);
517 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
518 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
520 mutex_init(&priv->pgdir_mutex);
521 INIT_LIST_HEAD(&priv->pgdir_list);
522 spin_lock_init(&priv->mkey_lock);
524 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
528 err = pci_enable_device(pdev);
530 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
534 err = request_bar(pdev);
536 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
540 pci_set_master(pdev);
542 err = set_dma_caps(pdev);
544 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
548 dev->iseg_base = pci_resource_start(dev->pdev, 0);
549 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
552 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
555 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
556 fw_rev_min(dev), fw_rev_sub(dev));
558 err = mlx5_cmd_init(dev);
560 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
564 mlx5_pagealloc_init(dev);
566 err = mlx5_core_enable_hca(dev);
568 dev_err(&pdev->dev, "enable hca failed\n");
569 goto err_pagealloc_cleanup;
572 err = mlx5_satisfy_startup_pages(dev, 1);
574 dev_err(&pdev->dev, "failed to allocate boot pages\n");
575 goto err_disable_hca;
578 err = set_hca_ctrl(dev);
580 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
581 goto reclaim_boot_pages;
584 err = handle_hca_cap(dev);
586 dev_err(&pdev->dev, "handle_hca_cap failed\n");
587 goto reclaim_boot_pages;
590 err = mlx5_satisfy_startup_pages(dev, 0);
592 dev_err(&pdev->dev, "failed to allocate init pages\n");
593 goto reclaim_boot_pages;
596 err = mlx5_pagealloc_start(dev);
598 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
599 goto reclaim_boot_pages;
602 err = mlx5_cmd_init_hca(dev);
604 dev_err(&pdev->dev, "init hca failed\n");
605 goto err_pagealloc_stop;
608 mlx5_start_health_poll(dev);
610 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
612 dev_err(&pdev->dev, "query hca failed\n");
616 err = mlx5_cmd_query_adapter(dev);
618 dev_err(&pdev->dev, "query adapter failed\n");
622 err = mlx5_enable_msix(dev);
624 dev_err(&pdev->dev, "enable msix failed\n");
628 err = mlx5_eq_init(dev);
630 dev_err(&pdev->dev, "failed to initialize eq\n");
634 err = mlx5_alloc_uuars(dev, &priv->uuari);
636 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
640 err = mlx5_start_eqs(dev);
642 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
646 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
648 mlx5_init_cq_table(dev);
649 mlx5_init_qp_table(dev);
650 mlx5_init_srq_table(dev);
651 mlx5_init_mr_table(dev);
656 mlx5_free_uuars(dev, &priv->uuari);
659 mlx5_eq_cleanup(dev);
662 mlx5_disable_msix(dev);
665 mlx5_stop_health_poll(dev);
666 if (mlx5_cmd_teardown_hca(dev)) {
667 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
672 mlx5_pagealloc_stop(dev);
675 mlx5_reclaim_startup_pages(dev);
678 mlx5_core_disable_hca(dev);
680 err_pagealloc_cleanup:
681 mlx5_pagealloc_cleanup(dev);
682 mlx5_cmd_cleanup(dev);
688 pci_clear_master(dev->pdev);
689 release_bar(dev->pdev);
692 pci_disable_device(dev->pdev);
695 debugfs_remove(priv->dbg_root);
699 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
701 struct mlx5_priv *priv = &dev->priv;
703 mlx5_cleanup_srq_table(dev);
704 mlx5_cleanup_qp_table(dev);
705 mlx5_cleanup_cq_table(dev);
707 mlx5_free_uuars(dev, &priv->uuari);
708 mlx5_eq_cleanup(dev);
709 mlx5_disable_msix(dev);
710 mlx5_stop_health_poll(dev);
711 if (mlx5_cmd_teardown_hca(dev)) {
712 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
715 mlx5_pagealloc_stop(dev);
716 mlx5_reclaim_startup_pages(dev);
717 mlx5_core_disable_hca(dev);
718 mlx5_pagealloc_cleanup(dev);
719 mlx5_cmd_cleanup(dev);
721 pci_clear_master(dev->pdev);
722 release_bar(dev->pdev);
723 pci_disable_device(dev->pdev);
724 debugfs_remove(priv->dbg_root);
727 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
729 struct mlx5_device_context *dev_ctx;
730 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
732 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
734 pr_warn("mlx5_add_device: alloc context failed\n");
738 dev_ctx->intf = intf;
739 dev_ctx->context = intf->add(dev);
741 if (dev_ctx->context) {
742 spin_lock_irq(&priv->ctx_lock);
743 list_add_tail(&dev_ctx->list, &priv->ctx_list);
744 spin_unlock_irq(&priv->ctx_lock);
750 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
752 struct mlx5_device_context *dev_ctx;
753 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
755 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
756 if (dev_ctx->intf == intf) {
757 spin_lock_irq(&priv->ctx_lock);
758 list_del(&dev_ctx->list);
759 spin_unlock_irq(&priv->ctx_lock);
761 intf->remove(dev, dev_ctx->context);
766 static int mlx5_register_device(struct mlx5_core_dev *dev)
768 struct mlx5_priv *priv = &dev->priv;
769 struct mlx5_interface *intf;
771 mutex_lock(&intf_mutex);
772 list_add_tail(&priv->dev_list, &dev_list);
773 list_for_each_entry(intf, &intf_list, list)
774 mlx5_add_device(intf, priv);
775 mutex_unlock(&intf_mutex);
779 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
781 struct mlx5_priv *priv = &dev->priv;
782 struct mlx5_interface *intf;
784 mutex_lock(&intf_mutex);
785 list_for_each_entry(intf, &intf_list, list)
786 mlx5_remove_device(intf, priv);
787 list_del(&priv->dev_list);
788 mutex_unlock(&intf_mutex);
791 int mlx5_register_interface(struct mlx5_interface *intf)
793 struct mlx5_priv *priv;
795 if (!intf->add || !intf->remove)
798 mutex_lock(&intf_mutex);
799 list_add_tail(&intf->list, &intf_list);
800 list_for_each_entry(priv, &dev_list, dev_list)
801 mlx5_add_device(intf, priv);
802 mutex_unlock(&intf_mutex);
806 EXPORT_SYMBOL(mlx5_register_interface);
808 void mlx5_unregister_interface(struct mlx5_interface *intf)
810 struct mlx5_priv *priv;
812 mutex_lock(&intf_mutex);
813 list_for_each_entry(priv, &dev_list, dev_list)
814 mlx5_remove_device(intf, priv);
815 list_del(&intf->list);
816 mutex_unlock(&intf_mutex);
818 EXPORT_SYMBOL(mlx5_unregister_interface);
820 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
823 struct mlx5_priv *priv = &dev->priv;
824 struct mlx5_device_context *dev_ctx;
827 spin_lock_irqsave(&priv->ctx_lock, flags);
829 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
830 if (dev_ctx->intf->event)
831 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
833 spin_unlock_irqrestore(&priv->ctx_lock, flags);
836 struct mlx5_core_event_handler {
837 void (*event)(struct mlx5_core_dev *dev,
838 enum mlx5_dev_event event,
842 #define MLX5_IB_MOD "mlx5_ib"
844 static int init_one(struct pci_dev *pdev,
845 const struct pci_device_id *id)
847 struct mlx5_core_dev *dev;
848 struct mlx5_priv *priv;
851 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
853 dev_err(&pdev->dev, "kzalloc failed\n");
858 pci_set_drvdata(pdev, dev);
860 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
861 pr_warn("selected profile out of range, selecting default (%d)\n",
863 prof_sel = MLX5_DEFAULT_PROF;
865 dev->profile = &profile[prof_sel];
866 dev->event = mlx5_core_event;
868 INIT_LIST_HEAD(&priv->ctx_list);
869 spin_lock_init(&priv->ctx_lock);
870 err = mlx5_dev_init(dev, pdev);
872 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
876 err = mlx5_register_device(dev);
878 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
882 err = request_module_nowait(MLX5_IB_MOD);
884 pr_info("failed request module on %s\n", MLX5_IB_MOD);
889 mlx5_dev_cleanup(dev);
894 static void remove_one(struct pci_dev *pdev)
896 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
898 mlx5_unregister_device(dev);
899 mlx5_dev_cleanup(dev);
903 static const struct pci_device_id mlx5_core_pci_table[] = {
904 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
905 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
906 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
907 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
908 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
909 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
913 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
915 static struct pci_driver mlx5_core_driver = {
917 .id_table = mlx5_core_pci_table,
922 static int __init init(void)
926 mlx5_register_debugfs();
927 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
934 err = pci_register_driver(&mlx5_core_driver);
941 mlx5_health_cleanup();
942 destroy_workqueue(mlx5_core_wq);
944 mlx5_unregister_debugfs();
948 static void __exit cleanup(void)
950 pci_unregister_driver(&mlx5_core_driver);
951 mlx5_health_cleanup();
952 destroy_workqueue(mlx5_core_wq);
953 mlx5_unregister_debugfs();
957 module_exit(cleanup);