1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 // Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
4 #include <linux/mlx5/device.h>
5 #include <linux/mlx5/transobj.h>
11 /* data path - accessed per cqe */
14 /* data path - accessed per napi poll */
15 struct mlx5_core_cq mcq;
18 struct mlx5_core_dev *mdev;
19 struct mlx5_wq_ctrl wq_ctrl;
20 } ____cacheline_aligned_in_smp;
27 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
28 struct mlx5_aso_cq cq;
31 struct mlx5_wq_cyc wq;
32 void __iomem *uar_map;
36 struct mlx5_wq_ctrl wq_ctrl;
38 } ____cacheline_aligned_in_smp;
40 static void mlx5_aso_free_cq(struct mlx5_aso_cq *cq)
42 mlx5_wq_destroy(&cq->wq_ctrl);
45 static int mlx5_aso_alloc_cq(struct mlx5_core_dev *mdev, int numa_node,
46 void *cqc_data, struct mlx5_aso_cq *cq)
48 struct mlx5_core_cq *mcq = &cq->mcq;
49 struct mlx5_wq_param param;
53 param.buf_numa_node = numa_node;
54 param.db_numa_node = numa_node;
56 err = mlx5_cqwq_create(mdev, ¶m, cqc_data, &cq->wq, &cq->wq_ctrl);
61 mcq->set_ci_db = cq->wq_ctrl.db.db;
62 mcq->arm_db = cq->wq_ctrl.db.db + 1;
64 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
65 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
75 static int create_aso_cq(struct mlx5_aso_cq *cq, void *cqc_data)
77 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
78 struct mlx5_core_dev *mdev = cq->mdev;
79 struct mlx5_core_cq *mcq = &cq->mcq;
84 err = mlx5_comp_eqn_get(mdev, 0, &eqn);
88 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
89 sizeof(u64) * cq->wq_ctrl.buf.npages;
90 in = kvzalloc(inlen, GFP_KERNEL);
94 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
96 memcpy(cqc, cqc_data, MLX5_ST_SZ_BYTES(cqc));
98 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
99 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
101 MLX5_SET(cqc, cqc, cq_period_mode, DIM_CQ_PERIOD_MODE_START_FROM_EQE);
102 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
103 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
104 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
105 MLX5_ADAPTER_PAGE_SHIFT);
106 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
108 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
115 static void mlx5_aso_destroy_cq(struct mlx5_aso_cq *cq)
117 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
118 mlx5_wq_destroy(&cq->wq_ctrl);
121 static int mlx5_aso_create_cq(struct mlx5_core_dev *mdev, int numa_node,
122 struct mlx5_aso_cq *cq)
127 cqc_data = kvzalloc(MLX5_ST_SZ_BYTES(cqc), GFP_KERNEL);
131 MLX5_SET(cqc, cqc_data, log_cq_size, 1);
132 MLX5_SET(cqc, cqc_data, uar_page, mdev->priv.uar->index);
133 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128)
134 MLX5_SET(cqc, cqc_data, cqe_sz, CQE_STRIDE_128_PAD);
136 err = mlx5_aso_alloc_cq(mdev, numa_node, cqc_data, cq);
138 mlx5_core_err(mdev, "Failed to alloc aso wq cq, err=%d\n", err);
142 err = create_aso_cq(cq, cqc_data);
144 mlx5_core_err(mdev, "Failed to create aso wq cq, err=%d\n", err);
152 mlx5_aso_free_cq(cq);
158 static int mlx5_aso_alloc_sq(struct mlx5_core_dev *mdev, int numa_node,
159 void *sqc_data, struct mlx5_aso *sq)
161 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc_data, wq);
162 struct mlx5_wq_cyc *wq = &sq->wq;
163 struct mlx5_wq_param param;
166 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
168 param.db_numa_node = numa_node;
169 param.buf_numa_node = numa_node;
170 err = mlx5_wq_cyc_create(mdev, ¶m, sqc_wq, wq, &sq->wq_ctrl);
173 wq->db = &wq->db[MLX5_SND_DBR];
178 static int create_aso_sq(struct mlx5_core_dev *mdev, int pdn,
179 void *sqc_data, struct mlx5_aso *sq)
185 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
186 sizeof(u64) * sq->wq_ctrl.buf.npages;
187 in = kvzalloc(inlen, GFP_KERNEL);
191 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
192 wq = MLX5_ADDR_OF(sqc, sqc, wq);
194 memcpy(sqc, sqc_data, MLX5_ST_SZ_BYTES(sqc));
195 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
197 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
198 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
200 ts_format = mlx5_is_real_time_sq(mdev) ?
201 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
202 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
203 MLX5_SET(sqc, sqc, ts_format, ts_format);
205 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
206 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
207 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
208 MLX5_ADAPTER_PAGE_SHIFT);
209 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
211 mlx5_fill_page_frag_array(&sq->wq_ctrl.buf,
212 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
214 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
221 static int mlx5_aso_set_sq_rdy(struct mlx5_core_dev *mdev, u32 sqn)
226 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
227 in = kvzalloc(inlen, GFP_KERNEL);
231 MLX5_SET(modify_sq_in, in, sq_state, MLX5_SQC_STATE_RST);
232 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
233 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RDY);
235 err = mlx5_core_modify_sq(mdev, sqn, in);
242 static int mlx5_aso_create_sq_rdy(struct mlx5_core_dev *mdev, u32 pdn,
243 void *sqc_data, struct mlx5_aso *sq)
247 err = create_aso_sq(mdev, pdn, sqc_data, sq);
251 err = mlx5_aso_set_sq_rdy(mdev, sq->sqn);
253 mlx5_core_destroy_sq(mdev, sq->sqn);
258 static void mlx5_aso_free_sq(struct mlx5_aso *sq)
260 mlx5_wq_destroy(&sq->wq_ctrl);
263 static void mlx5_aso_destroy_sq(struct mlx5_aso *sq)
265 mlx5_core_destroy_sq(sq->cq.mdev, sq->sqn);
266 mlx5_aso_free_sq(sq);
269 static int mlx5_aso_create_sq(struct mlx5_core_dev *mdev, int numa_node,
270 u32 pdn, struct mlx5_aso *sq)
275 sqc_data = kvzalloc(MLX5_ST_SZ_BYTES(sqc), GFP_KERNEL);
279 wq = MLX5_ADDR_OF(sqc, sqc_data, wq);
280 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
281 MLX5_SET(wq, wq, pd, pdn);
282 MLX5_SET(wq, wq, log_wq_sz, 1);
284 err = mlx5_aso_alloc_sq(mdev, numa_node, sqc_data, sq);
286 mlx5_core_err(mdev, "Failed to alloc aso wq sq, err=%d\n", err);
290 err = mlx5_aso_create_sq_rdy(mdev, pdn, sqc_data, sq);
292 mlx5_core_err(mdev, "Failed to open aso wq sq, err=%d\n", err);
296 mlx5_core_dbg(mdev, "aso sq->sqn = 0x%x\n", sq->sqn);
302 mlx5_aso_free_sq(sq);
308 struct mlx5_aso *mlx5_aso_create(struct mlx5_core_dev *mdev, u32 pdn)
310 int numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
311 struct mlx5_aso *aso;
314 aso = kzalloc(sizeof(*aso), GFP_KERNEL);
316 return ERR_PTR(-ENOMEM);
318 err = mlx5_aso_create_cq(mdev, numa_node, &aso->cq);
322 err = mlx5_aso_create_sq(mdev, numa_node, pdn, aso);
329 mlx5_aso_destroy_cq(&aso->cq);
335 void mlx5_aso_destroy(struct mlx5_aso *aso)
337 mlx5_aso_destroy_sq(aso);
338 mlx5_aso_destroy_cq(&aso->cq);
342 void mlx5_aso_build_wqe(struct mlx5_aso *aso, u8 ds_cnt,
343 struct mlx5_aso_wqe *aso_wqe,
344 u32 obj_id, u32 opc_mode)
346 struct mlx5_wqe_ctrl_seg *cseg = &aso_wqe->ctrl;
348 cseg->opmod_idx_opcode = cpu_to_be32((opc_mode << MLX5_WQE_CTRL_WQE_OPC_MOD_SHIFT) |
349 (aso->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
350 MLX5_OPCODE_ACCESS_ASO);
351 cseg->qpn_ds = cpu_to_be32((aso->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | ds_cnt);
352 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
353 cseg->general_id = cpu_to_be32(obj_id);
356 struct mlx5_aso_wqe *mlx5_aso_get_wqe(struct mlx5_aso *aso)
358 struct mlx5_aso_wqe *wqe;
361 pi = mlx5_wq_cyc_ctr2ix(&aso->wq, aso->pc);
362 wqe = mlx5_wq_cyc_get_wqe(&aso->wq, pi);
363 memset(wqe, 0, sizeof(*wqe));
367 void mlx5_aso_post_wqe(struct mlx5_aso *aso, bool with_data,
368 struct mlx5_wqe_ctrl_seg *doorbell_cseg)
370 doorbell_cseg->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE;
371 /* ensure wqe is visible to device before updating doorbell record */
375 aso->pc += MLX5_ASO_WQEBBS_DATA;
377 aso->pc += MLX5_ASO_WQEBBS;
378 *aso->wq.db = cpu_to_be32(aso->pc);
380 /* ensure doorbell record is visible to device before ringing the
385 mlx5_write64((__be32 *)doorbell_cseg, aso->uar_map);
387 /* Ensure doorbell is written on uar_page before poll_cq */
388 WRITE_ONCE(doorbell_cseg, NULL);
391 int mlx5_aso_poll_cq(struct mlx5_aso *aso, bool with_data)
393 struct mlx5_aso_cq *cq = &aso->cq;
394 struct mlx5_cqe64 *cqe;
396 cqe = mlx5_cqwq_get_cqe(&cq->wq);
400 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
401 * otherwise a cq overrun may occur
403 mlx5_cqwq_pop(&cq->wq);
405 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
406 struct mlx5_err_cqe *err_cqe;
408 mlx5_core_err(cq->mdev, "Bad OP in ASOSQ CQE: 0x%x\n",
409 get_cqe_opcode(cqe));
411 err_cqe = (struct mlx5_err_cqe *)cqe;
412 mlx5_core_err(cq->mdev, "vendor_err_synd=%x\n",
413 err_cqe->vendor_err_synd);
414 mlx5_core_err(cq->mdev, "syndrome=%x\n",
416 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
418 sizeof(*err_cqe), false);
421 mlx5_cqwq_update_db_record(&cq->wq);
423 /* ensure cq space is freed before enabling more cqes */
427 aso->cc += MLX5_ASO_WQEBBS_DATA;
429 aso->cc += MLX5_ASO_WQEBBS;