2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <net/devlink.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/mlx5/eswitch.h>
41 #include <linux/mlx5/vport.h>
42 #include <linux/mlx5/fs.h>
45 #ifdef CONFIG_MLX5_ESWITCH
47 #define MLX5_MAX_UC_PER_VPORT(dev) \
48 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
50 #define MLX5_MAX_MC_PER_VPORT(dev) \
51 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
53 #define MLX5_MIN_BW_SHARE 1
55 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
56 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
58 #define mlx5_esw_has_fwd_fdb(dev) \
59 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
61 #define FDB_MAX_CHAIN 3
62 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
63 #define FDB_MAX_PRIO 16
65 struct vport_ingress {
66 struct mlx5_flow_table *acl;
67 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
68 struct mlx5_flow_group *allow_spoofchk_only_grp;
69 struct mlx5_flow_group *allow_untagged_only_grp;
70 struct mlx5_flow_group *drop_grp;
71 int modify_metadata_id;
72 struct mlx5_flow_handle *modify_metadata_rule;
73 struct mlx5_flow_handle *allow_rule;
74 struct mlx5_flow_handle *drop_rule;
75 struct mlx5_fc *drop_counter;
79 struct mlx5_flow_table *acl;
80 struct mlx5_flow_group *allowed_vlans_grp;
81 struct mlx5_flow_group *drop_grp;
82 struct mlx5_flow_handle *allowed_vlan;
83 struct mlx5_flow_handle *drop_rule;
84 struct mlx5_fc *drop_counter;
87 struct mlx5_vport_drop_stats {
92 struct mlx5_vport_info {
104 /* Vport context events */
105 enum mlx5_eswitch_vport_event {
106 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
107 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
108 MLX5_VPORT_PROMISC_CHANGE = BIT(3),
112 struct mlx5_core_dev *dev;
114 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
115 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
116 struct mlx5_flow_handle *promisc_rule;
117 struct mlx5_flow_handle *allmulti_rule;
118 struct work_struct vport_change_handler;
120 struct vport_ingress ingress;
121 struct vport_egress egress;
123 struct mlx5_vport_info info;
132 enum mlx5_eswitch_vport_event enabled_events;
135 enum offloads_fdb_flags {
136 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
139 extern const unsigned int ESW_POOLS[4];
141 #define PRIO_LEVELS 2
142 struct mlx5_eswitch_fdb {
145 struct mlx5_flow_table *fdb;
146 struct mlx5_flow_group *addr_grp;
147 struct mlx5_flow_group *allmulti_grp;
148 struct mlx5_flow_group *promisc_grp;
149 struct mlx5_flow_table *vepa_fdb;
150 struct mlx5_flow_handle *vepa_uplink_rule;
151 struct mlx5_flow_handle *vepa_star_rule;
154 struct offloads_fdb {
155 struct mlx5_flow_table *slow_fdb;
156 struct mlx5_flow_group *send_to_vport_grp;
157 struct mlx5_flow_group *peer_miss_grp;
158 struct mlx5_flow_handle **peer_miss_rules;
159 struct mlx5_flow_group *miss_grp;
160 struct mlx5_flow_handle *miss_rule_uni;
161 struct mlx5_flow_handle *miss_rule_multi;
162 int vlan_push_pop_refcount;
165 struct mlx5_flow_table *fdb;
167 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
168 /* Protects fdb_prio table */
169 struct mutex fdb_prio_lock;
171 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
177 struct mlx5_esw_offload {
178 struct mlx5_flow_table *ft_offloads;
179 struct mlx5_flow_group *vport_rx_group;
180 struct mlx5_eswitch_rep *vport_reps;
181 struct list_head peer_flows;
182 struct mutex peer_mutex;
183 DECLARE_HASHTABLE(encap_tbl, 8);
184 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
185 DECLARE_HASHTABLE(termtbl_tbl, 8);
186 struct mutex termtbl_mutex; /* protects termtbl hash */
187 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
190 enum devlink_eswitch_encap_mode encap;
193 /* E-Switch MC FDB table hash node */
194 struct esw_mc_addr { /* SRIOV only */
195 struct l2addr_node node;
196 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
200 struct mlx5_host_work {
201 struct work_struct work;
202 struct mlx5_eswitch *esw;
205 struct mlx5_esw_functions {
211 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
214 struct mlx5_eswitch {
215 struct mlx5_core_dev *dev;
217 /* legacy data structures */
218 struct mlx5_eswitch_fdb fdb_table;
219 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
220 struct esw_mc_addr mc_promisc;
222 struct workqueue_struct *work_queue;
223 struct mlx5_vport *vports;
227 /* Synchronize between vport change events
228 * and async SRIOV admin state changes
230 struct mutex state_lock;
237 struct mlx5_esw_offload offloads;
241 u16 first_host_vport;
242 struct mlx5_esw_functions esw_funcs;
245 void esw_offloads_disable(struct mlx5_eswitch *esw);
246 int esw_offloads_enable(struct mlx5_eswitch *esw);
247 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
248 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
249 void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
250 struct mlx5_vport *vport);
251 int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
252 struct mlx5_vport *vport);
253 void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
254 struct mlx5_vport *vport);
255 int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
256 struct mlx5_vport *vport);
257 void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
258 struct mlx5_vport *vport);
259 void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
260 struct mlx5_vport *vport);
261 void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
262 struct mlx5_vport *vport);
265 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
266 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
267 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode);
268 void mlx5_eswitch_disable(struct mlx5_eswitch *esw);
269 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
270 u16 vport, u8 mac[ETH_ALEN]);
271 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
272 u16 vport, int link_state);
273 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
274 u16 vport, u16 vlan, u8 qos);
275 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
276 u16 vport, bool spoofchk);
277 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
278 u16 vport_num, bool setting);
279 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
280 u32 max_rate, u32 min_rate);
281 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
282 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
283 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
284 u16 vport, struct ifla_vf_info *ivi);
285 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
287 struct ifla_vf_stats *vf_stats);
288 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
290 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
291 void *in, int inlen);
292 int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
293 void *out, int outlen);
295 struct mlx5_flow_spec;
296 struct mlx5_esw_flow_attr;
297 struct mlx5_termtbl_handle;
300 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
301 struct mlx5_flow_act *flow_act,
302 struct mlx5_flow_spec *spec);
304 struct mlx5_flow_handle *
305 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
306 struct mlx5_flow_table *ft,
307 struct mlx5_flow_spec *spec,
308 struct mlx5_esw_flow_attr *attr,
309 struct mlx5_flow_act *flow_act,
310 struct mlx5_flow_destination *dest,
314 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
315 struct mlx5_termtbl_handle *tt);
317 struct mlx5_flow_handle *
318 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
319 struct mlx5_flow_spec *spec,
320 struct mlx5_esw_flow_attr *attr);
321 struct mlx5_flow_handle *
322 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
323 struct mlx5_flow_spec *spec,
324 struct mlx5_esw_flow_attr *attr);
326 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
327 struct mlx5_flow_handle *rule,
328 struct mlx5_esw_flow_attr *attr);
330 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
331 struct mlx5_flow_handle *rule,
332 struct mlx5_esw_flow_attr *attr);
335 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
338 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
341 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
343 struct mlx5_flow_handle *
344 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
345 struct mlx5_flow_destination *dest);
348 SET_VLAN_STRIP = BIT(0),
349 SET_VLAN_INSERT = BIT(1)
352 enum mlx5_flow_match_level {
353 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
354 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
355 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
356 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
359 /* current maximum for flow based vport multicasting */
360 #define MLX5_MAX_FLOW_FWD_VPORTS 2
363 MLX5_ESW_DEST_ENCAP = BIT(0),
364 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
367 struct mlx5_esw_flow_attr {
368 struct mlx5_eswitch_rep *in_rep;
369 struct mlx5_core_dev *in_mdev;
370 struct mlx5_core_dev *counter_dev;
376 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
377 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
378 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
383 struct mlx5_eswitch_rep *rep;
384 struct mlx5_core_dev *mdev;
386 struct mlx5_termtbl_handle *termtbl;
387 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
389 u8 inner_match_level;
390 u8 outer_match_level;
391 struct mlx5_fc *counter;
395 struct mlx5e_tc_flow_parse_attr *parse_attr;
398 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
399 struct netlink_ext_ack *extack);
400 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
401 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
402 struct netlink_ext_ack *extack);
403 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
404 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode);
405 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
406 enum devlink_eswitch_encap_mode encap,
407 struct netlink_ext_ack *extack);
408 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
409 enum devlink_eswitch_encap_mode *encap);
410 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
412 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
413 struct mlx5_esw_flow_attr *attr);
414 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
415 struct mlx5_esw_flow_attr *attr);
416 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
417 u16 vport, u16 vlan, u8 qos, u8 set_flags);
419 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
422 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
423 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
428 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
429 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
432 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
433 struct mlx5_core_dev *dev1);
434 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
435 struct mlx5_core_dev *dev1);
437 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
439 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
441 #define esw_info(__dev, format, ...) \
442 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
444 #define esw_warn(__dev, format, ...) \
445 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
447 #define esw_debug(dev, format, ...) \
448 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
450 /* The returned number is valid only when the dev is eswitch manager. */
451 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
453 return mlx5_core_is_ecpf_esw_manager(dev) ?
454 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
457 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
459 return mlx5_core_is_ecpf_esw_manager(dev) ?
460 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
463 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev)
465 /* Ideally device should have the functions changed supported
466 * capability regardless of it being ECPF or PF wherever such
467 * event should be processed such as on eswitch manager device.
468 * However, some ECPF based device might not have this capability
469 * set. Hence OR for ECPF check to cover such device.
471 return MLX5_CAP_ESW(dev, esw_functions_changed) ||
472 mlx5_core_is_ecpf_esw_manager(dev);
475 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
477 /* Uplink always locate at the last element of the array.*/
478 return esw->total_vports - 1;
481 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
483 return esw->total_vports - 2;
486 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
489 if (vport_num == MLX5_VPORT_ECPF) {
490 if (!mlx5_ecpf_vport_exists(esw->dev))
491 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
492 return mlx5_eswitch_ecpf_idx(esw);
495 if (vport_num == MLX5_VPORT_UPLINK)
496 return mlx5_eswitch_uplink_idx(esw);
501 static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
504 if (index == mlx5_eswitch_ecpf_idx(esw) &&
505 mlx5_ecpf_vport_exists(esw->dev))
506 return MLX5_VPORT_ECPF;
508 if (index == mlx5_eswitch_uplink_idx(esw))
509 return MLX5_VPORT_UPLINK;
514 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
515 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
517 /* The vport getter/iterator are only valid after esw->total_vports
518 * and vport->vport are initialized in mlx5_eswitch_init.
520 #define mlx5_esw_for_all_vports(esw, i, vport) \
521 for ((i) = MLX5_VPORT_PF; \
522 (vport) = &(esw)->vports[i], \
523 (i) < (esw)->total_vports; (i)++)
525 #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \
526 for ((i) = (esw)->total_vports - 1; \
527 (vport) = &(esw)->vports[i], \
528 (i) >= MLX5_VPORT_PF; (i)--)
530 #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
531 for ((i) = MLX5_VPORT_FIRST_VF; \
532 (vport) = &(esw)->vports[(i)], \
533 (i) <= (nvfs); (i)++)
535 #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
537 (vport) = &(esw)->vports[(i)], \
538 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
540 /* The rep getter/iterator are only valid after esw->total_vports
541 * and vport->vport are initialized in mlx5_eswitch_init.
543 #define mlx5_esw_for_all_reps(esw, i, rep) \
544 for ((i) = MLX5_VPORT_PF; \
545 (rep) = &(esw)->offloads.vport_reps[i], \
546 (i) < (esw)->total_vports; (i)++)
548 #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
549 for ((i) = MLX5_VPORT_FIRST_VF; \
550 (rep) = &(esw)->offloads.vport_reps[i], \
551 (i) <= (nvfs); (i)++)
553 #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
555 (rep) = &(esw)->offloads.vport_reps[i], \
556 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
558 #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
559 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
561 #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
562 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
564 /* Includes host PF (vport 0) if it's not esw manager. */
565 #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \
566 for ((i) = (esw)->first_host_vport; \
567 (rep) = &(esw)->offloads.vport_reps[i], \
568 (i) <= (nvfs); (i)++)
570 #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \
572 (rep) = &(esw)->offloads.vport_reps[i], \
573 (i) >= (esw)->first_host_vport; (i)--)
575 #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \
576 for ((vport) = (esw)->first_host_vport; \
577 (vport) <= (nvfs); (vport)++)
579 #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \
580 for ((vport) = (nvfs); \
581 (vport) >= (esw)->first_host_vport; (vport)--)
583 struct mlx5_vport *__must_check
584 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
586 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num);
588 void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs);
589 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
592 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
593 enum mlx5_eswitch_vport_event enabled_events);
594 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
596 #else /* CONFIG_MLX5_ESWITCH */
597 /* eswitch API stubs */
598 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
599 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
600 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; }
601 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
602 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
603 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
604 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
606 return ERR_PTR(-EOPNOTSUPP);
609 static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {}
611 #define FDB_MAX_CHAIN 1
612 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
613 #define FDB_MAX_PRIO 1
615 #endif /* CONFIG_MLX5_ESWITCH */
617 #endif /* __MLX5_ESWITCH_H__ */