2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
40 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
41 MLX5_EQE_OWNER_INIT_VAL = 0x1,
45 MLX5_EQ_STATE_ARMED = 0x9,
46 MLX5_EQ_STATE_FIRED = 0xa,
47 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
51 MLX5_NUM_SPARE_EQE = 0x80,
52 MLX5_NUM_ASYNC_EQE = 0x100,
53 MLX5_NUM_CMD_EQE = 32,
57 MLX5_EQ_DOORBEL_OFFSET = 0x40,
60 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
61 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
62 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
63 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
64 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
65 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
66 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
67 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
68 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
69 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
70 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
71 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
84 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
86 struct mlx5_destroy_eq_mbox_in in;
87 struct mlx5_destroy_eq_mbox_out out;
90 memset(&in, 0, sizeof(in));
91 memset(&out, 0, sizeof(out));
92 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_EQ);
94 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
99 err = mlx5_cmd_status_to_err(&out.hdr);
105 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
107 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
110 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
112 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
114 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
117 static const char *eqe_type_str(u8 type)
120 case MLX5_EVENT_TYPE_COMP:
121 return "MLX5_EVENT_TYPE_COMP";
122 case MLX5_EVENT_TYPE_PATH_MIG:
123 return "MLX5_EVENT_TYPE_PATH_MIG";
124 case MLX5_EVENT_TYPE_COMM_EST:
125 return "MLX5_EVENT_TYPE_COMM_EST";
126 case MLX5_EVENT_TYPE_SQ_DRAINED:
127 return "MLX5_EVENT_TYPE_SQ_DRAINED";
128 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
129 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
130 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
131 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
132 case MLX5_EVENT_TYPE_CQ_ERROR:
133 return "MLX5_EVENT_TYPE_CQ_ERROR";
134 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
135 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
136 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
137 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
138 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
139 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
140 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
141 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
142 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
143 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
144 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
145 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
146 case MLX5_EVENT_TYPE_PORT_CHANGE:
147 return "MLX5_EVENT_TYPE_PORT_CHANGE";
148 case MLX5_EVENT_TYPE_GPIO_EVENT:
149 return "MLX5_EVENT_TYPE_GPIO_EVENT";
150 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
151 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
152 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
153 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
154 case MLX5_EVENT_TYPE_STALL_EVENT:
155 return "MLX5_EVENT_TYPE_STALL_EVENT";
156 case MLX5_EVENT_TYPE_CMD:
157 return "MLX5_EVENT_TYPE_CMD";
158 case MLX5_EVENT_TYPE_PAGE_REQUEST:
159 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
161 return "Unrecognized event";
165 static enum mlx5_dev_event port_subtype_event(u8 subtype)
168 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
169 return MLX5_DEV_EVENT_PORT_DOWN;
170 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
171 return MLX5_DEV_EVENT_PORT_UP;
172 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
173 return MLX5_DEV_EVENT_PORT_INITIALIZED;
174 case MLX5_PORT_CHANGE_SUBTYPE_LID:
175 return MLX5_DEV_EVENT_LID_CHANGE;
176 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
177 return MLX5_DEV_EVENT_PKEY_CHANGE;
178 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
179 return MLX5_DEV_EVENT_GUID_CHANGE;
180 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
181 return MLX5_DEV_EVENT_CLIENT_REREG;
186 static void eq_update_ci(struct mlx5_eq *eq, int arm)
188 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
189 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
190 __raw_writel((__force u32) cpu_to_be32(val), addr);
191 /* We still want ordering, just not swabbing, so add a barrier */
195 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
197 struct mlx5_eqe *eqe;
204 while ((eqe = next_eqe_sw(eq))) {
206 * Make sure we read EQ entry contents after we've
207 * checked the ownership bit.
211 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
212 eq->eqn, eqe_type_str(eqe->type));
214 case MLX5_EVENT_TYPE_COMP:
215 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
216 mlx5_cq_completion(dev, cqn);
219 case MLX5_EVENT_TYPE_PATH_MIG:
220 case MLX5_EVENT_TYPE_COMM_EST:
221 case MLX5_EVENT_TYPE_SQ_DRAINED:
222 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
227 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
228 mlx5_core_dbg(dev, "event %s(%d) arrived\n",
229 eqe_type_str(eqe->type), eqe->type);
230 mlx5_rsc_event(dev, rsn, eqe->type);
233 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
234 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
235 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
236 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
237 eqe_type_str(eqe->type), eqe->type, rsn);
238 mlx5_srq_event(dev, rsn, eqe->type);
241 case MLX5_EVENT_TYPE_CMD:
242 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
245 case MLX5_EVENT_TYPE_PORT_CHANGE:
246 port = (eqe->data.port.port >> 4) & 0xf;
247 switch (eqe->sub_type) {
248 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
249 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
250 case MLX5_PORT_CHANGE_SUBTYPE_LID:
251 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
252 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
253 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
254 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
256 dev->event(dev, port_subtype_event(eqe->sub_type),
257 (unsigned long)port);
260 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
261 port, eqe->sub_type);
264 case MLX5_EVENT_TYPE_CQ_ERROR:
265 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
266 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
267 cqn, eqe->data.cq_err.syndrome);
268 mlx5_cq_event(dev, cqn, eqe->type);
271 case MLX5_EVENT_TYPE_PAGE_REQUEST:
273 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
274 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
276 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
278 mlx5_core_req_pages_handler(dev, func_id, npages);
284 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
293 /* The HCA will think the queue has overflowed if we
294 * don't tell it we've been processing events. We
295 * create our EQs with MLX5_NUM_SPARE_EQE extra
296 * entries, so we must update our consumer index at
299 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
310 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
312 struct mlx5_eq *eq = eq_ptr;
313 struct mlx5_core_dev *dev = eq->dev;
315 mlx5_eq_int(dev, eq);
317 /* MSI-X vectors always belong to us */
321 static void init_eq_buf(struct mlx5_eq *eq)
323 struct mlx5_eqe *eqe;
326 for (i = 0; i < eq->nent; i++) {
327 eqe = get_eqe(eq, i);
328 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
332 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
333 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
335 struct mlx5_eq_table *table = &dev->priv.eq_table;
336 struct mlx5_create_eq_mbox_in *in;
337 struct mlx5_create_eq_mbox_out out;
341 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
342 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
349 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
350 in = mlx5_vzalloc(inlen);
355 memset(&out, 0, sizeof(out));
357 mlx5_fill_page_array(&eq->buf, in->pas);
359 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
360 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
361 in->ctx.intr = vecidx;
362 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
363 in->events_mask = cpu_to_be64(mask);
365 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
369 if (out.hdr.status) {
370 err = mlx5_cmd_status_to_err(&out.hdr);
374 snprintf(eq->name, MLX5_MAX_EQ_NAME, "%s@pci:%s",
375 name, pci_name(dev->pdev));
376 eq->eqn = out.eq_number;
377 err = request_irq(table->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
384 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
386 err = mlx5_debug_eq_add(dev, eq);
390 /* EQs are created in ARMED state
398 free_irq(table->msix_arr[vecidx].vector, eq);
401 mlx5_cmd_destroy_eq(dev, eq->eqn);
407 mlx5_buf_free(dev, &eq->buf);
410 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
412 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
414 struct mlx5_eq_table *table = &dev->priv.eq_table;
417 mlx5_debug_eq_remove(dev, eq);
418 free_irq(table->msix_arr[eq->irqn].vector, eq);
419 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
421 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
423 mlx5_buf_free(dev, &eq->buf);
427 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
429 int mlx5_eq_init(struct mlx5_core_dev *dev)
433 spin_lock_init(&dev->priv.eq_table.lock);
435 err = mlx5_eq_debugfs_init(dev);
441 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
443 mlx5_eq_debugfs_cleanup(dev);
446 int mlx5_start_eqs(struct mlx5_core_dev *dev)
448 struct mlx5_eq_table *table = &dev->priv.eq_table;
451 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
452 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
453 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
455 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
459 mlx5_cmd_use_events(dev);
461 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
462 MLX5_NUM_ASYNC_EQE, MLX5_ASYNC_EVENT_MASK,
463 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
465 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
469 err = mlx5_create_map_eq(dev, &table->pages_eq,
471 dev->caps.gen.max_vf + 1,
472 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
473 &dev->priv.uuari.uars[0]);
475 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
482 mlx5_destroy_unmap_eq(dev, &table->async_eq);
485 mlx5_cmd_use_polling(dev);
486 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
490 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
492 struct mlx5_eq_table *table = &dev->priv.eq_table;
495 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
499 mlx5_destroy_unmap_eq(dev, &table->async_eq);
500 mlx5_cmd_use_polling(dev);
502 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
504 mlx5_cmd_use_events(dev);
509 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
510 struct mlx5_query_eq_mbox_out *out, int outlen)
512 struct mlx5_query_eq_mbox_in in;
515 memset(&in, 0, sizeof(in));
516 memset(out, 0, outlen);
517 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
519 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
524 err = mlx5_cmd_status_to_err(&out->hdr);
528 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);