2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/interrupt.h>
34 #include <linux/notifier.h>
35 #include <linux/module.h>
36 #include <linux/mlx5/driver.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/eq.h>
39 #ifdef CONFIG_RFS_ACCEL
40 #include <linux/cpu_rmap.h>
42 #include "mlx5_core.h"
44 #include "fpga/core.h"
46 #include "lib/clock.h"
47 #include "diag/fw_tracer.h"
50 MLX5_EQE_OWNER_INIT_VAL = 0x1,
54 MLX5_EQ_STATE_ARMED = 0x9,
55 MLX5_EQ_STATE_FIRED = 0xa,
56 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_EQ_DOORBEL_OFFSET = 0x40,
63 /* budget must be smaller than MLX5_NUM_SPARE_EQE to guarantee that we update
64 * the ci before we polled all the entries in the EQ. MLX5_NUM_SPARE_EQE is
65 * used to set the EQ size, budget must be smaller than the EQ size.
68 MLX5_EQ_POLLING_BUDGET = 128,
71 static_assert(MLX5_EQ_POLLING_BUDGET <= MLX5_NUM_SPARE_EQE);
73 struct mlx5_eq_table {
74 struct list_head comp_eqs_list;
75 struct mlx5_eq_async pages_eq;
76 struct mlx5_eq_async cmd_eq;
77 struct mlx5_eq_async async_eq;
79 struct atomic_notifier_head nh[MLX5_EVENT_TYPE_MAX];
81 /* Since CQ DB is stored in async_eq */
82 struct mlx5_nb cq_err_nb;
84 struct mutex lock; /* sync async eqs creations */
86 struct mlx5_irq_table *irq_table;
89 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
90 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
91 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
92 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
93 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
94 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
95 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
96 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
97 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
98 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
99 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
100 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
102 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
104 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {};
106 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
107 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
108 return mlx5_cmd_exec_in(dev, destroy_eq, in);
111 /* caller must eventually call mlx5_cq_put on the returned cq */
112 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn)
114 struct mlx5_cq_table *table = &eq->cq_table;
115 struct mlx5_core_cq *cq = NULL;
118 cq = radix_tree_lookup(&table->tree, cqn);
126 static int mlx5_eq_comp_int(struct notifier_block *nb,
127 __always_unused unsigned long action,
128 __always_unused void *data)
130 struct mlx5_eq_comp *eq_comp =
131 container_of(nb, struct mlx5_eq_comp, irq_nb);
132 struct mlx5_eq *eq = &eq_comp->core;
133 struct mlx5_eqe *eqe;
137 eqe = next_eqe_sw(eq);
142 struct mlx5_core_cq *cq;
144 /* Make sure we read EQ entry contents after we've
145 * checked the ownership bit.
148 /* Assume (eqe->type) is always MLX5_EVENT_TYPE_COMP */
149 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
151 cq = mlx5_eq_cq_get(eq, cqn);
157 dev_dbg_ratelimited(eq->dev->device,
158 "Completion event for bogus CQ 0x%x\n", cqn);
163 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
169 tasklet_schedule(&eq_comp->tasklet_ctx.task);
174 /* Some architectures don't latch interrupts when they are disabled, so using
175 * mlx5_eq_poll_irq_disabled could end up losing interrupts while trying to
176 * avoid losing them. It is not recommended to use it, unless this is the last
179 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq_comp *eq)
183 disable_irq(eq->core.irqn);
184 count_eqe = eq->core.cons_index;
185 mlx5_eq_comp_int(&eq->irq_nb, 0, NULL);
186 count_eqe = eq->core.cons_index - count_eqe;
187 enable_irq(eq->core.irqn);
192 static int mlx5_eq_async_int(struct notifier_block *nb,
193 unsigned long action, void *data)
195 struct mlx5_eq_async *eq_async =
196 container_of(nb, struct mlx5_eq_async, irq_nb);
197 struct mlx5_eq *eq = &eq_async->core;
198 struct mlx5_eq_table *eqt;
199 struct mlx5_core_dev *dev;
200 struct mlx5_eqe *eqe;
204 eqt = dev->priv.eq_table;
206 eqe = next_eqe_sw(eq);
212 * Make sure we read EQ entry contents after we've
213 * checked the ownership bit.
217 atomic_notifier_call_chain(&eqt->nh[eqe->type], eqe->type, eqe);
218 atomic_notifier_call_chain(&eqt->nh[MLX5_EVENT_TYPE_NOTIFY_ANY], eqe->type, eqe);
222 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
230 static void init_eq_buf(struct mlx5_eq *eq)
232 struct mlx5_eqe *eqe;
235 for (i = 0; i < eq->nent; i++) {
236 eqe = get_eqe(eq, i);
237 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
242 create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
243 struct mlx5_eq_param *param)
245 struct mlx5_cq_table *cq_table = &eq->cq_table;
246 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
247 struct mlx5_priv *priv = &dev->priv;
248 u8 vecidx = param->irq_index;
257 memset(cq_table, 0, sizeof(*cq_table));
258 spin_lock_init(&cq_table->lock);
259 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
261 eq->nent = roundup_pow_of_two(param->nent + MLX5_NUM_SPARE_EQE);
263 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
269 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
270 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
272 in = kvzalloc(inlen, GFP_KERNEL);
278 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
279 mlx5_fill_page_array(&eq->buf, pas);
281 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
282 if (!param->mask[0] && MLX5_CAP_GEN(dev, log_max_uctx))
283 MLX5_SET(create_eq_in, in, uid, MLX5_SHARED_RESOURCE_UID);
285 for (i = 0; i < 4; i++)
286 MLX5_ARRAY_SET64(create_eq_in, in, event_bitmask, i,
289 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
290 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
291 MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
292 MLX5_SET(eqc, eqc, intr, vecidx);
293 MLX5_SET(eqc, eqc, log_page_size,
294 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
296 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
301 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
302 eq->irqn = pci_irq_vector(dev->pdev, vecidx);
304 eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
306 err = mlx5_debug_eq_add(dev, eq);
314 mlx5_cmd_destroy_eq(dev, eq->eqn);
320 mlx5_buf_free(dev, &eq->buf);
325 * mlx5_eq_enable - Enable EQ for receiving EQEs
326 * @dev : Device which owns the eq
328 * @nb : Notifier call block
330 * Must be called after EQ is created in device.
332 * @return: 0 if no error
334 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
335 struct notifier_block *nb)
337 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
340 err = mlx5_irq_attach_nb(eq_table->irq_table, eq->vecidx, nb);
346 EXPORT_SYMBOL(mlx5_eq_enable);
349 * mlx5_eq_disable - Disable EQ for receiving EQEs
350 * @dev : Device which owns the eq
351 * @eq : EQ to disable
352 * @nb : Notifier call block
354 * Must be called before EQ is destroyed.
356 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
357 struct notifier_block *nb)
359 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
361 mlx5_irq_detach_nb(eq_table->irq_table, eq->vecidx, nb);
363 EXPORT_SYMBOL(mlx5_eq_disable);
365 static int destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
369 mlx5_debug_eq_remove(dev, eq);
371 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
373 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
375 synchronize_irq(eq->irqn);
377 mlx5_buf_free(dev, &eq->buf);
382 int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq)
384 struct mlx5_cq_table *table = &eq->cq_table;
387 spin_lock(&table->lock);
388 err = radix_tree_insert(&table->tree, cq->cqn, cq);
389 spin_unlock(&table->lock);
394 void mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq)
396 struct mlx5_cq_table *table = &eq->cq_table;
397 struct mlx5_core_cq *tmp;
399 spin_lock(&table->lock);
400 tmp = radix_tree_delete(&table->tree, cq->cqn);
401 spin_unlock(&table->lock);
404 mlx5_core_dbg(eq->dev, "cq 0x%x not found in eq 0x%x tree\n",
410 mlx5_core_dbg(eq->dev, "corruption on cqn 0x%x in eq 0x%x\n",
414 int mlx5_eq_table_init(struct mlx5_core_dev *dev)
416 struct mlx5_eq_table *eq_table;
419 eq_table = kvzalloc(sizeof(*eq_table), GFP_KERNEL);
423 dev->priv.eq_table = eq_table;
425 mlx5_eq_debugfs_init(dev);
427 mutex_init(&eq_table->lock);
428 for (i = 0; i < MLX5_EVENT_TYPE_MAX; i++)
429 ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
431 eq_table->irq_table = dev->priv.irq_table;
435 void mlx5_eq_table_cleanup(struct mlx5_core_dev *dev)
437 mlx5_eq_debugfs_cleanup(dev);
438 kvfree(dev->priv.eq_table);
443 static int create_async_eq(struct mlx5_core_dev *dev,
444 struct mlx5_eq *eq, struct mlx5_eq_param *param)
446 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
449 mutex_lock(&eq_table->lock);
450 /* Async EQs must share irq index 0 */
451 if (param->irq_index != 0) {
456 err = create_map_eq(dev, eq, param);
458 mutex_unlock(&eq_table->lock);
462 static int destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
464 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
467 mutex_lock(&eq_table->lock);
468 err = destroy_unmap_eq(dev, eq);
469 mutex_unlock(&eq_table->lock);
473 static int cq_err_event_notifier(struct notifier_block *nb,
474 unsigned long type, void *data)
476 struct mlx5_eq_table *eqt;
477 struct mlx5_core_cq *cq;
478 struct mlx5_eqe *eqe;
482 /* type == MLX5_EVENT_TYPE_CQ_ERROR */
484 eqt = mlx5_nb_cof(nb, struct mlx5_eq_table, cq_err_nb);
485 eq = &eqt->async_eq.core;
488 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
489 mlx5_core_warn(eq->dev, "CQ error on CQN 0x%x, syndrome 0x%x\n",
490 cqn, eqe->data.cq_err.syndrome);
492 cq = mlx5_eq_cq_get(eq, cqn);
494 mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn);
506 static void gather_user_async_events(struct mlx5_core_dev *dev, u64 mask[4])
508 __be64 *user_unaffiliated_events;
509 __be64 *user_affiliated_events;
512 user_affiliated_events =
513 MLX5_CAP_DEV_EVENT(dev, user_affiliated_events);
514 user_unaffiliated_events =
515 MLX5_CAP_DEV_EVENT(dev, user_unaffiliated_events);
517 for (i = 0; i < 4; i++)
518 mask[i] |= be64_to_cpu(user_affiliated_events[i] |
519 user_unaffiliated_events[i]);
522 static void gather_async_events_mask(struct mlx5_core_dev *dev, u64 mask[4])
524 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
526 if (MLX5_VPORT_MANAGER(dev))
527 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
529 if (MLX5_CAP_GEN(dev, general_notification_event))
530 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
532 if (MLX5_CAP_GEN(dev, port_module_event))
533 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
535 mlx5_core_dbg(dev, "port_module_event is not set\n");
537 if (MLX5_PPS_CAP(dev))
538 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
540 if (MLX5_CAP_GEN(dev, fpga))
541 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
542 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
543 if (MLX5_CAP_GEN_MAX(dev, dct))
544 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);
546 if (MLX5_CAP_GEN(dev, temp_warn_event))
547 async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
549 if (MLX5_CAP_MCAM_REG(dev, tracer_registers))
550 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DEVICE_TRACER);
552 if (MLX5_CAP_GEN(dev, max_num_of_monitor_counters))
553 async_event_mask |= (1ull << MLX5_EVENT_TYPE_MONITOR_COUNTER);
555 if (mlx5_eswitch_is_funcs_handler(dev))
557 (1ull << MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED);
559 mask[0] = async_event_mask;
561 if (MLX5_CAP_GEN(dev, event_cap))
562 gather_user_async_events(dev, mask);
566 setup_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq_async *eq,
567 struct mlx5_eq_param *param, const char *name)
571 eq->irq_nb.notifier_call = mlx5_eq_async_int;
573 err = create_async_eq(dev, &eq->core, param);
575 mlx5_core_warn(dev, "failed to create %s EQ %d\n", name, err);
578 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb);
580 mlx5_core_warn(dev, "failed to enable %s EQ %d\n", name, err);
581 destroy_async_eq(dev, &eq->core);
586 static void cleanup_async_eq(struct mlx5_core_dev *dev,
587 struct mlx5_eq_async *eq, const char *name)
591 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb);
592 err = destroy_async_eq(dev, &eq->core);
594 mlx5_core_err(dev, "failed to destroy %s eq, err(%d)\n",
598 static int create_async_eqs(struct mlx5_core_dev *dev)
600 struct mlx5_eq_table *table = dev->priv.eq_table;
601 struct mlx5_eq_param param = {};
604 MLX5_NB_INIT(&table->cq_err_nb, cq_err_event_notifier, CQ_ERROR);
605 mlx5_eq_notifier_register(dev, &table->cq_err_nb);
607 param = (struct mlx5_eq_param) {
609 .nent = MLX5_NUM_CMD_EQE,
610 .mask[0] = 1ull << MLX5_EVENT_TYPE_CMD,
612 mlx5_cmd_allowed_opcode(dev, MLX5_CMD_OP_CREATE_EQ);
613 err = setup_async_eq(dev, &table->cmd_eq, ¶m, "cmd");
617 mlx5_cmd_use_events(dev);
618 mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL);
620 param = (struct mlx5_eq_param) {
622 .nent = MLX5_NUM_ASYNC_EQE,
625 gather_async_events_mask(dev, param.mask);
626 err = setup_async_eq(dev, &table->async_eq, ¶m, "async");
630 param = (struct mlx5_eq_param) {
632 .nent = /* TODO: sriov max_vf + */ 1,
633 .mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_REQUEST,
636 err = setup_async_eq(dev, &table->pages_eq, ¶m, "pages");
643 cleanup_async_eq(dev, &table->async_eq, "async");
645 mlx5_cmd_use_polling(dev);
646 cleanup_async_eq(dev, &table->cmd_eq, "cmd");
648 mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL);
649 mlx5_eq_notifier_unregister(dev, &table->cq_err_nb);
653 static void destroy_async_eqs(struct mlx5_core_dev *dev)
655 struct mlx5_eq_table *table = dev->priv.eq_table;
657 cleanup_async_eq(dev, &table->pages_eq, "pages");
658 cleanup_async_eq(dev, &table->async_eq, "async");
659 mlx5_cmd_use_polling(dev);
660 cleanup_async_eq(dev, &table->cmd_eq, "cmd");
661 mlx5_eq_notifier_unregister(dev, &table->cq_err_nb);
664 struct mlx5_eq *mlx5_get_async_eq(struct mlx5_core_dev *dev)
666 return &dev->priv.eq_table->async_eq.core;
669 void mlx5_eq_synchronize_async_irq(struct mlx5_core_dev *dev)
671 synchronize_irq(dev->priv.eq_table->async_eq.core.irqn);
674 void mlx5_eq_synchronize_cmd_irq(struct mlx5_core_dev *dev)
676 synchronize_irq(dev->priv.eq_table->cmd_eq.core.irqn);
679 /* Generic EQ API for mlx5_core consumers
680 * Needed For RDMA ODP EQ for now
683 mlx5_eq_create_generic(struct mlx5_core_dev *dev,
684 struct mlx5_eq_param *param)
686 struct mlx5_eq *eq = kvzalloc(sizeof(*eq), GFP_KERNEL);
690 return ERR_PTR(-ENOMEM);
692 err = create_async_eq(dev, eq, param);
700 EXPORT_SYMBOL(mlx5_eq_create_generic);
702 int mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
709 err = destroy_async_eq(dev, eq);
717 EXPORT_SYMBOL(mlx5_eq_destroy_generic);
719 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc)
721 u32 ci = eq->cons_index + cc;
722 struct mlx5_eqe *eqe;
724 eqe = get_eqe(eq, ci & (eq->nent - 1));
725 eqe = ((eqe->owner & 1) ^ !!(ci & eq->nent)) ? NULL : eqe;
726 /* Make sure we read EQ entry contents after we've
727 * checked the ownership bit.
734 EXPORT_SYMBOL(mlx5_eq_get_eqe);
736 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
738 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
741 eq->cons_index += cc;
742 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
744 __raw_writel((__force u32)cpu_to_be32(val), addr);
745 /* We still want ordering, just not swabbing, so add a barrier */
748 EXPORT_SYMBOL(mlx5_eq_update_ci);
750 static void destroy_comp_eqs(struct mlx5_core_dev *dev)
752 struct mlx5_eq_table *table = dev->priv.eq_table;
753 struct mlx5_eq_comp *eq, *n;
755 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
757 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb);
758 if (destroy_unmap_eq(dev, &eq->core))
759 mlx5_core_warn(dev, "failed to destroy comp EQ 0x%x\n",
761 tasklet_disable(&eq->tasklet_ctx.task);
766 static int create_comp_eqs(struct mlx5_core_dev *dev)
768 struct mlx5_eq_table *table = dev->priv.eq_table;
769 struct mlx5_eq_comp *eq;
775 INIT_LIST_HEAD(&table->comp_eqs_list);
776 ncomp_eqs = table->num_comp_eqs;
777 nent = MLX5_COMP_EQ_SIZE;
778 for (i = 0; i < ncomp_eqs; i++) {
779 int vecidx = i + MLX5_IRQ_VEC_COMP_BASE;
780 struct mlx5_eq_param param = {};
782 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
788 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
789 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
790 spin_lock_init(&eq->tasklet_ctx.lock);
791 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
792 (unsigned long)&eq->tasklet_ctx);
794 eq->irq_nb.notifier_call = mlx5_eq_comp_int;
795 param = (struct mlx5_eq_param) {
799 err = create_map_eq(dev, &eq->core, ¶m);
804 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb);
806 destroy_unmap_eq(dev, &eq->core);
811 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->core.eqn);
812 /* add tail, to keep the list ordered, for mlx5_vector2eqn to work */
813 list_add_tail(&eq->list, &table->comp_eqs_list);
819 destroy_comp_eqs(dev);
823 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
826 struct mlx5_eq_table *table = dev->priv.eq_table;
827 struct mlx5_eq_comp *eq, *n;
831 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
834 *irqn = eq->core.irqn;
842 EXPORT_SYMBOL(mlx5_vector2eqn);
844 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev)
846 return dev->priv.eq_table->num_comp_eqs;
848 EXPORT_SYMBOL(mlx5_comp_vectors_count);
851 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector)
853 int vecidx = vector + MLX5_IRQ_VEC_COMP_BASE;
855 return mlx5_irq_get_affinity_mask(dev->priv.eq_table->irq_table,
858 EXPORT_SYMBOL(mlx5_comp_irq_get_affinity_mask);
860 #ifdef CONFIG_RFS_ACCEL
861 struct cpu_rmap *mlx5_eq_table_get_rmap(struct mlx5_core_dev *dev)
863 return mlx5_irq_get_rmap(dev->priv.eq_table->irq_table);
867 struct mlx5_eq_comp *mlx5_eqn2comp_eq(struct mlx5_core_dev *dev, int eqn)
869 struct mlx5_eq_table *table = dev->priv.eq_table;
870 struct mlx5_eq_comp *eq;
872 list_for_each_entry(eq, &table->comp_eqs_list, list) {
873 if (eq->core.eqn == eqn)
877 return ERR_PTR(-ENOENT);
880 /* This function should only be called after mlx5_cmd_force_teardown_hca */
881 void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
883 struct mlx5_eq_table *table = dev->priv.eq_table;
885 mutex_lock(&table->lock); /* sync with create/destroy_async_eq */
886 mlx5_irq_table_destroy(dev);
887 mutex_unlock(&table->lock);
890 int mlx5_eq_table_create(struct mlx5_core_dev *dev)
892 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
895 eq_table->num_comp_eqs =
896 mlx5_irq_get_num_comp(eq_table->irq_table);
898 err = create_async_eqs(dev);
900 mlx5_core_err(dev, "Failed to create async EQs\n");
904 err = create_comp_eqs(dev);
906 mlx5_core_err(dev, "Failed to create completion EQs\n");
912 destroy_async_eqs(dev);
917 void mlx5_eq_table_destroy(struct mlx5_core_dev *dev)
919 destroy_comp_eqs(dev);
920 destroy_async_eqs(dev);
923 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb)
925 struct mlx5_eq_table *eqt = dev->priv.eq_table;
927 return atomic_notifier_chain_register(&eqt->nh[nb->event_type], &nb->nb);
929 EXPORT_SYMBOL(mlx5_eq_notifier_register);
931 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb)
933 struct mlx5_eq_table *eqt = dev->priv.eq_table;
935 return atomic_notifier_chain_unregister(&eqt->nh[nb->event_type], &nb->nb);
937 EXPORT_SYMBOL(mlx5_eq_notifier_unregister);