2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/dsfield.h>
37 #include "ipoib/ipoib.h"
38 #include "en_accel/en_accel.h"
39 #include "lib/clock.h"
41 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
43 #ifndef CONFIG_MLX5_EN_TLS
44 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
47 /* TLS offload requires MLX5E_SQ_STOP_ROOM to have
48 * enough room for a resync SKB, a normal SKB and a NOP
50 #define MLX5E_SQ_STOP_ROOM (2 * MLX5_SEND_WQE_MAX_WQEBBS +\
54 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
55 struct mlx5e_sq_dma *dma)
58 case MLX5E_DMA_MAP_SINGLE:
59 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
61 case MLX5E_DMA_MAP_PAGE:
62 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
65 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
69 static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq,
72 enum mlx5e_dma_map_type map_type)
74 u32 i = sq->dma_fifo_pc & sq->dma_fifo_mask;
76 sq->db.dma_fifo[i].addr = addr;
77 sq->db.dma_fifo[i].size = size;
78 sq->db.dma_fifo[i].type = map_type;
82 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
84 return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
87 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
91 for (i = 0; i < num_dma; i++) {
92 struct mlx5e_sq_dma *last_pushed_dma =
93 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
95 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
99 #ifdef CONFIG_MLX5_CORE_EN_DCB
100 static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb)
104 if (skb->protocol == htons(ETH_P_IP))
105 dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
106 else if (skb->protocol == htons(ETH_P_IPV6))
107 dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
109 return priv->dcbx_dp.dscp2prio[dscp_cp];
113 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
114 void *accel_priv, select_queue_fallback_t fallback)
116 struct mlx5e_priv *priv = netdev_priv(dev);
117 int channel_ix = fallback(dev, skb);
121 if (!netdev_get_num_tc(dev))
124 #ifdef CONFIG_MLX5_CORE_EN_DCB
125 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
126 up = mlx5e_get_dscp_up(priv, skb);
129 if (skb_vlan_tag_present(skb))
130 up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
132 /* channel_ix can be larger than num_channels since
133 * dev->num_real_tx_queues = num_channels * num_tc
135 num_channels = priv->channels.params.num_channels;
136 if (channel_ix >= num_channels)
137 channel_ix = reciprocal_scale(channel_ix, num_channels);
139 return priv->channel_tc2txq[channel_ix][up];
142 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
144 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
146 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
149 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
151 struct flow_keys keys;
153 if (skb_transport_header_was_set(skb))
154 return skb_transport_offset(skb);
155 else if (skb_flow_dissect_flow_keys(skb, &keys, 0))
156 return keys.control.thoff;
158 return mlx5e_skb_l2_header_offset(skb);
161 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
167 case MLX5_INLINE_MODE_NONE:
169 case MLX5_INLINE_MODE_TCP_UDP:
170 hlen = eth_get_headlen(skb->data, skb_headlen(skb));
171 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
174 case MLX5_INLINE_MODE_IP:
175 /* When transport header is set to zero, it means no transport
176 * header. When transport header is set to 0xff's, it means
177 * transport header wasn't set.
179 if (skb_transport_offset(skb)) {
180 hlen = mlx5e_skb_l3_header_offset(skb);
184 case MLX5_INLINE_MODE_L2:
186 hlen = mlx5e_skb_l2_header_offset(skb);
188 return min_t(u16, hlen, skb_headlen(skb));
191 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
192 unsigned int *skb_len,
199 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
200 unsigned char **skb_data,
201 unsigned int *skb_len)
203 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
204 int cpy1_sz = 2 * ETH_ALEN;
205 int cpy2_sz = ihs - cpy1_sz;
207 memcpy(vhdr, *skb_data, cpy1_sz);
208 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
209 vhdr->h_vlan_proto = skb->vlan_proto;
210 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
211 memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
212 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
216 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
218 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
219 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
220 if (skb->encapsulation) {
221 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
222 MLX5_ETH_WQE_L4_INNER_CSUM;
223 sq->stats.csum_partial_inner++;
225 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
226 sq->stats.csum_partial++;
229 sq->stats.csum_none++;
233 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb)
237 if (skb->encapsulation) {
238 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
239 sq->stats.tso_inner_packets++;
240 sq->stats.tso_inner_bytes += skb->len - ihs;
242 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
243 sq->stats.tso_packets++;
244 sq->stats.tso_bytes += skb->len - ihs;
251 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
252 unsigned char *skb_data, u16 headlen,
253 struct mlx5_wqe_data_seg *dseg)
255 dma_addr_t dma_addr = 0;
260 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
262 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
263 goto dma_unmap_wqe_err;
265 dseg->addr = cpu_to_be64(dma_addr);
266 dseg->lkey = sq->mkey_be;
267 dseg->byte_count = cpu_to_be32(headlen);
269 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
274 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
275 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
276 int fsz = skb_frag_size(frag);
278 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
280 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
281 goto dma_unmap_wqe_err;
283 dseg->addr = cpu_to_be64(dma_addr);
284 dseg->lkey = sq->mkey_be;
285 dseg->byte_count = cpu_to_be32(fsz);
287 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
295 mlx5e_dma_unmap_wqe_err(sq, num_dma);
299 static inline void mlx5e_fill_sq_frag_edge(struct mlx5e_txqsq *sq,
300 struct mlx5_wq_cyc *wq,
303 struct mlx5e_tx_wqe_info *edge_wi, *wi = &sq->db.wqe_info[pi];
304 u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
306 edge_wi = wi + nnops;
308 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
309 for (; wi < edge_wi; wi++) {
312 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
314 sq->stats.nop += nnops;
318 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
319 u8 opcode, u16 ds_cnt, u8 num_wqebbs, u32 num_bytes, u8 num_dma,
320 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg)
322 struct mlx5_wq_cyc *wq = &sq->wq;
324 wi->num_bytes = num_bytes;
325 wi->num_dma = num_dma;
326 wi->num_wqebbs = num_wqebbs;
329 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
330 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
332 netdev_tx_sent_queue(sq->txq, num_bytes);
334 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
335 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
337 sq->pc += wi->num_wqebbs;
338 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM))) {
339 netif_tx_stop_queue(sq->txq);
343 if (!skb->xmit_more || netif_xmit_stopped(sq->txq))
344 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
347 #define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
349 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
350 struct mlx5e_tx_wqe *wqe, u16 pi)
352 struct mlx5_wq_cyc *wq = &sq->wq;
353 struct mlx5_wqe_ctrl_seg *cseg;
354 struct mlx5_wqe_eth_seg *eseg;
355 struct mlx5_wqe_data_seg *dseg;
356 struct mlx5e_tx_wqe_info *wi;
358 unsigned char *skb_data = skb->data;
359 unsigned int skb_len = skb->len;
360 u16 ds_cnt, ds_cnt_inl = 0;
361 u16 headlen, ihs, frag_pi;
362 u8 num_wqebbs, opcode;
367 /* Calc ihs and ds cnt, no writes to wqe yet */
368 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
369 if (skb_is_gso(skb)) {
370 opcode = MLX5_OPCODE_LSO;
371 mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
372 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
373 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
374 sq->stats.packets += skb_shinfo(skb)->gso_segs;
376 opcode = MLX5_OPCODE_SEND;
378 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
379 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
383 sq->stats.bytes += num_bytes;
384 sq->stats.xmit_more += skb->xmit_more;
386 headlen = skb_len - ihs - skb->data_len;
388 ds_cnt += skb_shinfo(skb)->nr_frags;
391 ihs += !!skb_vlan_tag_present(skb) * VLAN_HLEN;
393 ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
394 ds_cnt += ds_cnt_inl;
397 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
398 frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
399 if (unlikely(frag_pi + num_wqebbs > mlx5_wq_cyc_get_frag_size(wq))) {
400 mlx5e_fill_sq_frag_edge(sq, wq, pi, frag_pi);
401 mlx5e_sq_fetch_wqe(sq, &wqe, &pi);
405 wi = &sq->db.wqe_info[pi];
410 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
415 if (skb_vlan_tag_present(skb)) {
416 mlx5e_insert_vlan(eseg->inline_hdr.start, skb,
417 ihs - VLAN_HLEN, &skb_data, &skb_len);
418 sq->stats.added_vlan_packets++;
420 memcpy(eseg->inline_hdr.start, skb_data, ihs);
421 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
423 eseg->inline_hdr.sz = cpu_to_be16(ihs);
425 } else if (skb_vlan_tag_present(skb)) {
426 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
427 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
428 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
429 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
430 sq->stats.added_vlan_packets++;
433 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen, dseg);
434 if (unlikely(num_dma < 0))
437 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes,
444 dev_kfree_skb_any(skb);
449 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
451 struct mlx5e_priv *priv = netdev_priv(dev);
452 struct mlx5e_tx_wqe *wqe;
453 struct mlx5e_txqsq *sq;
456 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
457 mlx5e_sq_fetch_wqe(sq, &wqe, &pi);
459 #ifdef CONFIG_MLX5_ACCEL
460 /* might send skbs and update wqe and pi */
461 skb = mlx5e_accel_handle_tx(skb, sq, dev, &wqe, &pi);
465 return mlx5e_sq_xmit(sq, skb, wqe, pi);
468 static void mlx5e_dump_error_cqe(struct mlx5e_txqsq *sq,
469 struct mlx5_err_cqe *err_cqe)
471 u32 ci = mlx5_cqwq_get_ci(&sq->cq.wq);
473 netdev_err(sq->channel->netdev,
474 "Error cqe on cqn 0x%x, ci 0x%x, sqn 0x%x, syndrome 0x%x, vendor syndrome 0x%x\n",
475 sq->cq.mcq.cqn, ci, sq->sqn, err_cqe->syndrome,
476 err_cqe->vendor_err_synd);
477 mlx5_dump_err_cqe(sq->cq.mdev, err_cqe);
480 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
482 struct mlx5e_txqsq *sq;
483 struct mlx5_cqe64 *cqe;
490 sq = container_of(cq, struct mlx5e_txqsq, cq);
492 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
495 cqe = mlx5_cqwq_get_cqe(&cq->wq);
502 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
503 * otherwise a cq overrun may occur
507 /* avoid dirtying sq cache line every cqe */
508 dma_fifo_cc = sq->dma_fifo_cc;
515 mlx5_cqwq_pop(&cq->wq);
517 wqe_counter = be16_to_cpu(cqe->wqe_counter);
519 if (unlikely(cqe->op_own >> 4 == MLX5_CQE_REQ_ERR)) {
520 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
522 mlx5e_dump_error_cqe(sq,
523 (struct mlx5_err_cqe *)cqe);
524 queue_work(cq->channel->priv->wq,
525 &sq->recover.recover_work);
531 struct mlx5e_tx_wqe_info *wi;
536 last_wqe = (sqcc == wqe_counter);
538 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
539 wi = &sq->db.wqe_info[ci];
542 if (unlikely(!skb)) { /* nop */
547 if (unlikely(skb_shinfo(skb)->tx_flags &
549 struct skb_shared_hwtstamps hwts = {};
552 mlx5_timecounter_cyc2time(sq->clock,
554 skb_tstamp_tx(skb, &hwts);
557 for (j = 0; j < wi->num_dma; j++) {
558 struct mlx5e_sq_dma *dma =
559 mlx5e_dma_get(sq, dma_fifo_cc++);
561 mlx5e_tx_dma_unmap(sq->pdev, dma);
565 nbytes += wi->num_bytes;
566 sqcc += wi->num_wqebbs;
567 napi_consume_skb(skb, napi_budget);
570 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
572 mlx5_cqwq_update_db_record(&cq->wq);
574 /* ensure cq space is freed before enabling more cqes */
577 sq->dma_fifo_cc = dma_fifo_cc;
580 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
582 if (netif_tx_queue_stopped(sq->txq) &&
583 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
584 MLX5E_SQ_STOP_ROOM) &&
585 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
586 netif_tx_wake_queue(sq->txq);
590 return (i == MLX5E_TX_CQ_POLL_BUDGET);
593 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
595 struct mlx5e_tx_wqe_info *wi;
600 while (sq->cc != sq->pc) {
601 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
602 wi = &sq->db.wqe_info[ci];
605 if (!skb) { /* nop */
610 for (i = 0; i < wi->num_dma; i++) {
611 struct mlx5e_sq_dma *dma =
612 mlx5e_dma_get(sq, sq->dma_fifo_cc++);
614 mlx5e_tx_dma_unmap(sq->pdev, dma);
617 dev_kfree_skb_any(skb);
618 sq->cc += wi->num_wqebbs;
622 #ifdef CONFIG_MLX5_CORE_IPOIB
624 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
625 struct mlx5_wqe_datagram_seg *dseg)
627 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
628 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
629 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
632 netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
633 struct mlx5_av *av, u32 dqpn, u32 dqkey)
635 struct mlx5_wq_cyc *wq = &sq->wq;
636 struct mlx5i_tx_wqe *wqe;
638 struct mlx5_wqe_datagram_seg *datagram;
639 struct mlx5_wqe_ctrl_seg *cseg;
640 struct mlx5_wqe_eth_seg *eseg;
641 struct mlx5_wqe_data_seg *dseg;
642 struct mlx5e_tx_wqe_info *wi;
644 unsigned char *skb_data = skb->data;
645 unsigned int skb_len = skb->len;
646 u16 headlen, ihs, pi, frag_pi;
647 u16 ds_cnt, ds_cnt_inl = 0;
648 u8 num_wqebbs, opcode;
653 mlx5i_sq_fetch_wqe(sq, &wqe, &pi);
655 /* Calc ihs and ds cnt, no writes to wqe yet */
656 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
657 if (skb_is_gso(skb)) {
658 opcode = MLX5_OPCODE_LSO;
659 mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
660 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
661 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
662 sq->stats.packets += skb_shinfo(skb)->gso_segs;
664 opcode = MLX5_OPCODE_SEND;
666 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
667 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
671 sq->stats.bytes += num_bytes;
672 sq->stats.xmit_more += skb->xmit_more;
674 headlen = skb_len - ihs - skb->data_len;
676 ds_cnt += skb_shinfo(skb)->nr_frags;
679 ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
680 ds_cnt += ds_cnt_inl;
683 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
684 frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
685 if (unlikely(frag_pi + num_wqebbs > mlx5_wq_cyc_get_frag_size(wq))) {
686 mlx5e_fill_sq_frag_edge(sq, wq, pi, frag_pi);
687 mlx5i_sq_fetch_wqe(sq, &wqe, &pi);
691 wi = &sq->db.wqe_info[pi];
693 datagram = &wqe->datagram;
697 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
699 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
704 memcpy(eseg->inline_hdr.start, skb_data, ihs);
705 eseg->inline_hdr.sz = cpu_to_be16(ihs);
709 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen, dseg);
710 if (unlikely(num_dma < 0))
713 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes,
720 dev_kfree_skb_any(skb);