2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
36 #include "ipoib/ipoib.h"
37 #include "en_accel/ipsec_rxtx.h"
38 #include "lib/clock.h"
40 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
41 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
44 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
45 struct mlx5e_sq_dma *dma)
48 case MLX5E_DMA_MAP_SINGLE:
49 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
51 case MLX5E_DMA_MAP_PAGE:
52 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
55 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
59 static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq,
62 enum mlx5e_dma_map_type map_type)
64 u32 i = sq->dma_fifo_pc & sq->dma_fifo_mask;
66 sq->db.dma_fifo[i].addr = addr;
67 sq->db.dma_fifo[i].size = size;
68 sq->db.dma_fifo[i].type = map_type;
72 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
74 return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
77 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
81 for (i = 0; i < num_dma; i++) {
82 struct mlx5e_sq_dma *last_pushed_dma =
83 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
85 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
89 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
90 void *accel_priv, select_queue_fallback_t fallback)
92 struct mlx5e_priv *priv = netdev_priv(dev);
93 int channel_ix = fallback(dev, skb);
97 if (!netdev_get_num_tc(dev))
100 if (skb_vlan_tag_present(skb))
101 up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
103 /* channel_ix can be larger than num_channels since
104 * dev->num_real_tx_queues = num_channels * num_tc
106 num_channels = priv->channels.params.num_channels;
107 if (channel_ix >= num_channels)
108 channel_ix = reciprocal_scale(channel_ix, num_channels);
110 return priv->channel_tc2txq[channel_ix][up];
113 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
115 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
117 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
120 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
122 struct flow_keys keys;
124 if (skb_transport_header_was_set(skb))
125 return skb_transport_offset(skb);
126 else if (skb_flow_dissect_flow_keys(skb, &keys, 0))
127 return keys.control.thoff;
129 return mlx5e_skb_l2_header_offset(skb);
132 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
138 case MLX5_INLINE_MODE_NONE:
140 case MLX5_INLINE_MODE_TCP_UDP:
141 hlen = eth_get_headlen(skb->data, skb_headlen(skb));
142 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
145 case MLX5_INLINE_MODE_IP:
146 /* When transport header is set to zero, it means no transport
147 * header. When transport header is set to 0xff's, it means
148 * transport header wasn't set.
150 if (skb_transport_offset(skb)) {
151 hlen = mlx5e_skb_l3_header_offset(skb);
155 case MLX5_INLINE_MODE_L2:
157 hlen = mlx5e_skb_l2_header_offset(skb);
159 return min_t(u16, hlen, skb->len);
162 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
163 unsigned int *skb_len,
170 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
171 unsigned char **skb_data,
172 unsigned int *skb_len)
174 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
175 int cpy1_sz = 2 * ETH_ALEN;
176 int cpy2_sz = ihs - cpy1_sz;
178 memcpy(vhdr, *skb_data, cpy1_sz);
179 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
180 vhdr->h_vlan_proto = skb->vlan_proto;
181 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
182 memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
183 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
187 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
189 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
190 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
191 if (skb->encapsulation) {
192 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
193 MLX5_ETH_WQE_L4_INNER_CSUM;
194 sq->stats.csum_partial_inner++;
196 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
197 sq->stats.csum_partial++;
200 sq->stats.csum_none++;
204 mlx5e_txwqe_build_eseg_gso(struct mlx5e_txqsq *sq, struct sk_buff *skb,
205 struct mlx5_wqe_eth_seg *eseg, unsigned int *num_bytes)
209 eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
211 if (skb->encapsulation) {
212 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
213 sq->stats.tso_inner_packets++;
214 sq->stats.tso_inner_bytes += skb->len - ihs;
216 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
217 sq->stats.tso_packets++;
218 sq->stats.tso_bytes += skb->len - ihs;
221 *num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
226 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
227 unsigned char *skb_data, u16 headlen,
228 struct mlx5_wqe_data_seg *dseg)
230 dma_addr_t dma_addr = 0;
235 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
237 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
240 dseg->addr = cpu_to_be64(dma_addr);
241 dseg->lkey = sq->mkey_be;
242 dseg->byte_count = cpu_to_be32(headlen);
244 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
249 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
250 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
251 int fsz = skb_frag_size(frag);
253 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
255 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
258 dseg->addr = cpu_to_be64(dma_addr);
259 dseg->lkey = sq->mkey_be;
260 dseg->byte_count = cpu_to_be32(fsz);
262 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
271 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
272 u8 opcode, u16 ds_cnt, u32 num_bytes, u8 num_dma,
273 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg)
275 struct mlx5_wq_cyc *wq = &sq->wq;
278 wi->num_bytes = num_bytes;
279 wi->num_dma = num_dma;
280 wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
283 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
284 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
286 netdev_tx_sent_queue(sq->txq, num_bytes);
288 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
289 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
291 sq->pc += wi->num_wqebbs;
292 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM))) {
293 netif_tx_stop_queue(sq->txq);
297 if (!skb->xmit_more || netif_xmit_stopped(sq->txq))
298 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
300 /* fill sq edge with nops to avoid wqe wrap around */
301 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
302 sq->db.wqe_info[pi].skb = NULL;
303 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
308 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
309 struct mlx5e_tx_wqe *wqe, u16 pi)
311 struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
313 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
314 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
316 unsigned char *skb_data = skb->data;
317 unsigned int skb_len = skb->len;
318 u8 opcode = MLX5_OPCODE_SEND;
319 unsigned int num_bytes;
325 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
327 if (skb_is_gso(skb)) {
328 opcode = MLX5_OPCODE_LSO;
329 ihs = mlx5e_txwqe_build_eseg_gso(sq, skb, eseg, &num_bytes);
330 sq->stats.packets += skb_shinfo(skb)->gso_segs;
332 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
333 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
336 sq->stats.bytes += num_bytes;
337 sq->stats.xmit_more += skb->xmit_more;
339 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
341 if (skb_vlan_tag_present(skb)) {
342 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, ihs, &skb_data, &skb_len);
345 memcpy(eseg->inline_hdr.start, skb_data, ihs);
346 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
348 eseg->inline_hdr.sz = cpu_to_be16(ihs);
349 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr.start), MLX5_SEND_WQE_DS);
350 } else if (skb_vlan_tag_present(skb)) {
351 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
352 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
355 headlen = skb_len - skb->data_len;
356 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen,
357 (struct mlx5_wqe_data_seg *)cseg + ds_cnt);
358 if (unlikely(num_dma < 0))
359 goto dma_unmap_wqe_err;
361 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt + num_dma,
362 num_bytes, num_dma, wi, cseg);
368 mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
370 dev_kfree_skb_any(skb);
375 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
377 struct mlx5e_priv *priv = netdev_priv(dev);
378 struct mlx5e_txqsq *sq = priv->txq2sq[skb_get_queue_mapping(skb)];
379 struct mlx5_wq_cyc *wq = &sq->wq;
380 u16 pi = sq->pc & wq->sz_m1;
381 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
383 memset(wqe, 0, sizeof(*wqe));
385 #ifdef CONFIG_MLX5_EN_IPSEC
386 if (sq->state & BIT(MLX5E_SQ_STATE_IPSEC)) {
387 skb = mlx5e_ipsec_handle_tx_skb(dev, wqe, skb);
393 return mlx5e_sq_xmit(sq, skb, wqe, pi);
396 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
398 struct mlx5e_txqsq *sq;
399 struct mlx5_cqe64 *cqe;
406 sq = container_of(cq, struct mlx5e_txqsq, cq);
408 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
411 cqe = mlx5_cqwq_get_cqe(&cq->wq);
418 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
419 * otherwise a cq overrun may occur
423 /* avoid dirtying sq cache line every cqe */
424 dma_fifo_cc = sq->dma_fifo_cc;
431 mlx5_cqwq_pop(&cq->wq);
433 wqe_counter = be16_to_cpu(cqe->wqe_counter);
436 struct mlx5e_tx_wqe_info *wi;
441 last_wqe = (sqcc == wqe_counter);
443 ci = sqcc & sq->wq.sz_m1;
444 wi = &sq->db.wqe_info[ci];
447 if (unlikely(!skb)) { /* nop */
452 if (unlikely(skb_shinfo(skb)->tx_flags &
454 struct skb_shared_hwtstamps hwts = {};
457 mlx5_timecounter_cyc2time(sq->clock,
459 skb_tstamp_tx(skb, &hwts);
462 for (j = 0; j < wi->num_dma; j++) {
463 struct mlx5e_sq_dma *dma =
464 mlx5e_dma_get(sq, dma_fifo_cc++);
466 mlx5e_tx_dma_unmap(sq->pdev, dma);
470 nbytes += wi->num_bytes;
471 sqcc += wi->num_wqebbs;
472 napi_consume_skb(skb, napi_budget);
475 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
477 mlx5_cqwq_update_db_record(&cq->wq);
479 /* ensure cq space is freed before enabling more cqes */
482 sq->dma_fifo_cc = dma_fifo_cc;
485 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
487 if (netif_tx_queue_stopped(sq->txq) &&
488 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM)) {
489 netif_tx_wake_queue(sq->txq);
493 return (i == MLX5E_TX_CQ_POLL_BUDGET);
496 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
498 struct mlx5e_tx_wqe_info *wi;
503 while (sq->cc != sq->pc) {
504 ci = sq->cc & sq->wq.sz_m1;
505 wi = &sq->db.wqe_info[ci];
508 if (!skb) { /* nop */
513 for (i = 0; i < wi->num_dma; i++) {
514 struct mlx5e_sq_dma *dma =
515 mlx5e_dma_get(sq, sq->dma_fifo_cc++);
517 mlx5e_tx_dma_unmap(sq->pdev, dma);
520 dev_kfree_skb_any(skb);
521 sq->cc += wi->num_wqebbs;
525 #ifdef CONFIG_MLX5_CORE_IPOIB
527 struct mlx5_wqe_eth_pad {
531 struct mlx5i_tx_wqe {
532 struct mlx5_wqe_ctrl_seg ctrl;
533 struct mlx5_wqe_datagram_seg datagram;
534 struct mlx5_wqe_eth_pad pad;
535 struct mlx5_wqe_eth_seg eth;
539 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
540 struct mlx5_wqe_datagram_seg *dseg)
542 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
543 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
544 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
547 netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
548 struct mlx5_av *av, u32 dqpn, u32 dqkey)
550 struct mlx5_wq_cyc *wq = &sq->wq;
551 u16 pi = sq->pc & wq->sz_m1;
552 struct mlx5i_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
553 struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
555 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
556 struct mlx5_wqe_datagram_seg *datagram = &wqe->datagram;
557 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
559 unsigned char *skb_data = skb->data;
560 unsigned int skb_len = skb->len;
561 u8 opcode = MLX5_OPCODE_SEND;
562 unsigned int num_bytes;
568 memset(wqe, 0, sizeof(*wqe));
570 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
572 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
574 if (skb_is_gso(skb)) {
575 opcode = MLX5_OPCODE_LSO;
576 ihs = mlx5e_txwqe_build_eseg_gso(sq, skb, eseg, &num_bytes);
577 sq->stats.packets += skb_shinfo(skb)->gso_segs;
579 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
580 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
584 sq->stats.bytes += num_bytes;
585 sq->stats.xmit_more += skb->xmit_more;
587 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
589 memcpy(eseg->inline_hdr.start, skb_data, ihs);
590 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
591 eseg->inline_hdr.sz = cpu_to_be16(ihs);
592 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr.start), MLX5_SEND_WQE_DS);
595 headlen = skb_len - skb->data_len;
596 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen,
597 (struct mlx5_wqe_data_seg *)cseg + ds_cnt);
598 if (unlikely(num_dma < 0))
599 goto dma_unmap_wqe_err;
601 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt + num_dma,
602 num_bytes, num_dma, wi, cseg);
608 mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
610 dev_kfree_skb_any(skb);