2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/geneve.h>
36 #include <net/dsfield.h>
39 #include "ipoib/ipoib.h"
40 #include "en_accel/en_accel.h"
41 #include "en_accel/ktls.h"
42 #include "lib/clock.h"
44 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
48 for (i = 0; i < num_dma; i++) {
49 struct mlx5e_sq_dma *last_pushed_dma =
50 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
52 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
56 #ifdef CONFIG_MLX5_CORE_EN_DCB
57 static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb)
61 if (skb->protocol == htons(ETH_P_IP))
62 dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
63 else if (skb->protocol == htons(ETH_P_IPV6))
64 dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
66 return priv->dcbx_dp.dscp2prio[dscp_cp];
70 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
71 struct net_device *sb_dev)
73 int txq_ix = netdev_pick_tx(dev, skb, NULL);
74 struct mlx5e_priv *priv = netdev_priv(dev);
78 if (!netdev_get_num_tc(dev))
81 #ifdef CONFIG_MLX5_CORE_EN_DCB
82 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
83 up = mlx5e_get_dscp_up(priv, skb);
86 if (skb_vlan_tag_present(skb))
87 up = skb_vlan_tag_get_prio(skb);
89 /* Normalize any picked txq_ix to [0, num_channels),
90 * So we can return a txq_ix that matches the channel and
93 ch_ix = priv->txq2sq[txq_ix]->ch_ix;
95 return priv->channel_tc2realtxq[ch_ix][up];
98 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
100 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
102 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
105 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
107 if (skb_transport_header_was_set(skb))
108 return skb_transport_offset(skb);
110 return mlx5e_skb_l2_header_offset(skb);
113 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
119 case MLX5_INLINE_MODE_NONE:
121 case MLX5_INLINE_MODE_TCP_UDP:
122 hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
123 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
126 case MLX5_INLINE_MODE_IP:
127 hlen = mlx5e_skb_l3_header_offset(skb);
129 case MLX5_INLINE_MODE_L2:
131 hlen = mlx5e_skb_l2_header_offset(skb);
133 return min_t(u16, hlen, skb_headlen(skb));
136 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
138 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
139 int cpy1_sz = 2 * ETH_ALEN;
140 int cpy2_sz = ihs - cpy1_sz;
142 memcpy(vhdr, skb->data, cpy1_sz);
143 vhdr->h_vlan_proto = skb->vlan_proto;
144 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
145 memcpy(&vhdr->h_vlan_encapsulated_proto, skb->data + cpy1_sz, cpy2_sz);
149 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
151 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
152 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
153 if (skb->encapsulation) {
154 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
155 MLX5_ETH_WQE_L4_INNER_CSUM;
156 sq->stats->csum_partial_inner++;
158 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
159 sq->stats->csum_partial++;
162 sq->stats->csum_none++;
166 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb)
168 struct mlx5e_sq_stats *stats = sq->stats;
171 if (skb->encapsulation) {
172 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
173 stats->tso_inner_packets++;
174 stats->tso_inner_bytes += skb->len - ihs;
176 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
177 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
179 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
180 stats->tso_packets++;
181 stats->tso_bytes += skb->len - ihs;
188 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
189 unsigned char *skb_data, u16 headlen,
190 struct mlx5_wqe_data_seg *dseg)
192 dma_addr_t dma_addr = 0;
197 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
199 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
200 goto dma_unmap_wqe_err;
202 dseg->addr = cpu_to_be64(dma_addr);
203 dseg->lkey = sq->mkey_be;
204 dseg->byte_count = cpu_to_be32(headlen);
206 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
211 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
212 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
213 int fsz = skb_frag_size(frag);
215 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
217 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
218 goto dma_unmap_wqe_err;
220 dseg->addr = cpu_to_be64(dma_addr);
221 dseg->lkey = sq->mkey_be;
222 dseg->byte_count = cpu_to_be32(fsz);
224 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
232 mlx5e_dma_unmap_wqe_err(sq, num_dma);
237 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
238 u8 opcode, u16 ds_cnt, u8 num_wqebbs, u32 num_bytes, u8 num_dma,
239 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg,
242 struct mlx5_wq_cyc *wq = &sq->wq;
245 wi->num_bytes = num_bytes;
246 wi->num_dma = num_dma;
247 wi->num_wqebbs = num_wqebbs;
250 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
251 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
253 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
254 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
256 sq->pc += wi->num_wqebbs;
257 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, sq->stop_room))) {
258 netif_tx_stop_queue(sq->txq);
259 sq->stats->stopped++;
262 send_doorbell = __netdev_tx_sent_queue(sq->txq, num_bytes,
265 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
268 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
269 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
271 struct mlx5_wq_cyc *wq = &sq->wq;
272 struct mlx5_wqe_ctrl_seg *cseg;
273 struct mlx5_wqe_eth_seg *eseg;
274 struct mlx5_wqe_data_seg *dseg;
275 struct mlx5e_tx_wqe_info *wi;
277 struct mlx5e_sq_stats *stats = sq->stats;
278 u16 headlen, ihs, contig_wqebbs_room;
279 u16 ds_cnt, ds_cnt_inl = 0;
280 u8 num_wqebbs, opcode;
285 /* Calc ihs and ds cnt, no writes to wqe yet */
286 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
287 if (skb_is_gso(skb)) {
288 opcode = MLX5_OPCODE_LSO;
289 mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
290 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
291 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
292 stats->packets += skb_shinfo(skb)->gso_segs;
294 u8 mode = mlx5e_tx_wqe_inline_mode(sq, &wqe->ctrl, skb);
296 opcode = MLX5_OPCODE_SEND;
298 ihs = mlx5e_calc_min_inline(mode, skb);
299 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
303 stats->bytes += num_bytes;
304 stats->xmit_more += xmit_more;
306 headlen = skb->len - ihs - skb->data_len;
308 ds_cnt += skb_shinfo(skb)->nr_frags;
311 ihs += !!skb_vlan_tag_present(skb) * VLAN_HLEN;
313 ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
314 ds_cnt += ds_cnt_inl;
317 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
318 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
319 if (unlikely(contig_wqebbs_room < num_wqebbs)) {
320 #ifdef CONFIG_MLX5_EN_IPSEC
321 struct mlx5_wqe_eth_seg cur_eth = wqe->eth;
323 #ifdef CONFIG_MLX5_EN_TLS
324 struct mlx5_wqe_ctrl_seg cur_ctrl = wqe->ctrl;
326 mlx5e_fill_sq_frag_edge(sq, wq, pi, contig_wqebbs_room);
327 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
328 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
329 #ifdef CONFIG_MLX5_EN_IPSEC
332 #ifdef CONFIG_MLX5_EN_TLS
333 wqe->ctrl = cur_ctrl;
338 wi = &sq->db.wqe_info[pi];
343 #if IS_ENABLED(CONFIG_GENEVE)
344 if (skb->encapsulation)
345 mlx5e_tx_tunnel_accel(skb, eseg);
347 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
352 eseg->inline_hdr.sz = cpu_to_be16(ihs);
353 if (skb_vlan_tag_present(skb)) {
355 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, ihs);
356 stats->added_vlan_packets++;
358 memcpy(eseg->inline_hdr.start, skb->data, ihs);
361 } else if (skb_vlan_tag_present(skb)) {
362 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
363 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
364 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
365 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
366 stats->added_vlan_packets++;
369 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + ihs, headlen, dseg);
370 if (unlikely(num_dma < 0))
373 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes,
374 num_dma, wi, cseg, xmit_more);
380 dev_kfree_skb_any(skb);
385 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
387 struct mlx5e_priv *priv = netdev_priv(dev);
388 struct mlx5e_tx_wqe *wqe;
389 struct mlx5e_txqsq *sq;
392 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
393 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
394 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
396 /* might send skbs and update wqe and pi */
397 if (unlikely(!mlx5e_accel_handle_tx(skb, sq, dev, &wqe, &pi)))
400 return mlx5e_sq_xmit(sq, skb, wqe, pi, netdev_xmit_more());
403 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
405 struct mlx5e_sq_stats *stats;
406 struct mlx5e_txqsq *sq;
407 struct mlx5_cqe64 *cqe;
414 sq = container_of(cq, struct mlx5e_txqsq, cq);
416 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
419 cqe = mlx5_cqwq_get_cqe(&cq->wq);
428 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
429 * otherwise a cq overrun may occur
433 /* avoid dirtying sq cache line every cqe */
434 dma_fifo_cc = sq->dma_fifo_cc;
438 struct mlx5e_tx_wqe_info *wi;
443 mlx5_cqwq_pop(&cq->wq);
445 wqe_counter = be16_to_cpu(cqe->wqe_counter);
451 last_wqe = (sqcc == wqe_counter);
453 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
454 wi = &sq->db.wqe_info[ci];
457 if (unlikely(!skb)) {
458 mlx5e_ktls_tx_handle_resync_dump_comp(sq, wi, &dma_fifo_cc);
459 sqcc += wi->num_wqebbs;
463 if (unlikely(skb_shinfo(skb)->tx_flags &
465 struct skb_shared_hwtstamps hwts = {};
468 mlx5_timecounter_cyc2time(sq->clock,
470 skb_tstamp_tx(skb, &hwts);
473 for (j = 0; j < wi->num_dma; j++) {
474 struct mlx5e_sq_dma *dma =
475 mlx5e_dma_get(sq, dma_fifo_cc++);
477 mlx5e_tx_dma_unmap(sq->pdev, dma);
481 nbytes += wi->num_bytes;
482 sqcc += wi->num_wqebbs;
483 napi_consume_skb(skb, napi_budget);
486 if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) {
487 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
489 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
490 (struct mlx5_err_cqe *)cqe);
491 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
492 queue_work(cq->channel->priv->wq,
498 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
502 mlx5_cqwq_update_db_record(&cq->wq);
504 /* ensure cq space is freed before enabling more cqes */
507 sq->dma_fifo_cc = dma_fifo_cc;
510 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
512 if (netif_tx_queue_stopped(sq->txq) &&
513 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) &&
514 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
515 netif_tx_wake_queue(sq->txq);
519 return (i == MLX5E_TX_CQ_POLL_BUDGET);
522 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
524 struct mlx5e_tx_wqe_info *wi;
532 dma_fifo_cc = sq->dma_fifo_cc;
534 while (sqcc != sq->pc) {
535 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
536 wi = &sq->db.wqe_info[ci];
540 mlx5e_ktls_tx_handle_resync_dump_comp(sq, wi, &dma_fifo_cc);
541 sqcc += wi->num_wqebbs;
545 for (i = 0; i < wi->num_dma; i++) {
546 struct mlx5e_sq_dma *dma =
547 mlx5e_dma_get(sq, dma_fifo_cc++);
549 mlx5e_tx_dma_unmap(sq->pdev, dma);
552 dev_kfree_skb_any(skb);
553 sqcc += wi->num_wqebbs;
556 sq->dma_fifo_cc = dma_fifo_cc;
560 #ifdef CONFIG_MLX5_CORE_IPOIB
562 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
563 struct mlx5_wqe_datagram_seg *dseg)
565 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
566 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
567 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
570 netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
571 struct mlx5_av *av, u32 dqpn, u32 dqkey,
574 struct mlx5i_tx_wqe *wqe;
576 struct mlx5_wqe_datagram_seg *datagram;
577 struct mlx5_wqe_ctrl_seg *cseg;
578 struct mlx5_wqe_eth_seg *eseg;
579 struct mlx5_wqe_data_seg *dseg;
580 struct mlx5e_tx_wqe_info *wi;
582 struct mlx5e_sq_stats *stats = sq->stats;
583 u16 ds_cnt, ds_cnt_inl = 0;
584 u8 num_wqebbs, opcode;
585 u16 headlen, ihs, pi;
590 /* Calc ihs and ds cnt, no writes to wqe yet */
591 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
592 if (skb_is_gso(skb)) {
593 opcode = MLX5_OPCODE_LSO;
594 mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
595 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
596 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
597 stats->packets += skb_shinfo(skb)->gso_segs;
599 u8 mode = mlx5e_tx_wqe_inline_mode(sq, NULL, skb);
601 opcode = MLX5_OPCODE_SEND;
603 ihs = mlx5e_calc_min_inline(mode, skb);
604 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
608 stats->bytes += num_bytes;
609 stats->xmit_more += xmit_more;
611 headlen = skb->len - ihs - skb->data_len;
613 ds_cnt += skb_shinfo(skb)->nr_frags;
616 ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
617 ds_cnt += ds_cnt_inl;
620 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
621 pi = mlx5e_txqsq_get_next_pi(sq, num_wqebbs);
622 wqe = MLX5I_SQ_FETCH_WQE(sq, pi);
625 wi = &sq->db.wqe_info[pi];
627 datagram = &wqe->datagram;
631 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
633 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
638 memcpy(eseg->inline_hdr.start, skb->data, ihs);
639 eseg->inline_hdr.sz = cpu_to_be16(ihs);
643 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + ihs, headlen, dseg);
644 if (unlikely(num_dma < 0))
647 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes,
648 num_dma, wi, cseg, xmit_more);
654 dev_kfree_skb_any(skb);