drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/sch_generic.h>
  35 #include <net/pkt_cls.h>
  36 #include <net/tc_act/tc_gact.h>
  37 #include <net/tc_act/tc_skbedit.h>
  38 #include <linux/mlx5/fs.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/rhashtable.h>
  41 #include <linux/refcount.h>
  42 #include <linux/completion.h>
  43 #include <net/tc_act/tc_mirred.h>
  44 #include <net/tc_act/tc_vlan.h>
  45 #include <net/tc_act/tc_tunnel_key.h>
  46 #include <net/tc_act/tc_pedit.h>
  47 #include <net/tc_act/tc_csum.h>
  48 #include <net/arp.h>
  49 #include <net/ipv6_stubs.h>
  50 #include "en.h"
  51 #include "en_rep.h"
  52 #include "en_tc.h"
  53 #include "eswitch.h"
  54 #include "eswitch_offloads_chains.h"
  55 #include "fs_core.h"
  56 #include "en/port.h"
  57 #include "en/tc_tun.h"
  58 #include "lib/devcom.h"
  59 #include "lib/geneve.h"
  60 #include "diag/en_tc_tracepoint.h"
  61
  62 struct mlx5_nic_flow_attr {
  63         u32 action;
  64         u32 flow_tag;
  65         struct mlx5_modify_hdr *modify_hdr;
  66         u32 hairpin_tirn;
  67         u8 match_level;
  68         struct mlx5_flow_table  *hairpin_ft;
  69         struct mlx5_fc          *counter;
  70 };
  71
  72 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
  73
  74 enum {
  75         MLX5E_TC_FLOW_FLAG_INGRESS      = MLX5E_TC_FLAG_INGRESS_BIT,
  76         MLX5E_TC_FLOW_FLAG_EGRESS       = MLX5E_TC_FLAG_EGRESS_BIT,
  77         MLX5E_TC_FLOW_FLAG_ESWITCH      = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
  78         MLX5E_TC_FLOW_FLAG_FT           = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
  79         MLX5E_TC_FLOW_FLAG_NIC          = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
  80         MLX5E_TC_FLOW_FLAG_OFFLOADED    = MLX5E_TC_FLOW_BASE,
  81         MLX5E_TC_FLOW_FLAG_HAIRPIN      = MLX5E_TC_FLOW_BASE + 1,
  82         MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS  = MLX5E_TC_FLOW_BASE + 2,
  83         MLX5E_TC_FLOW_FLAG_SLOW         = MLX5E_TC_FLOW_BASE + 3,
  84         MLX5E_TC_FLOW_FLAG_DUP          = MLX5E_TC_FLOW_BASE + 4,
  85         MLX5E_TC_FLOW_FLAG_NOT_READY    = MLX5E_TC_FLOW_BASE + 5,
  86         MLX5E_TC_FLOW_FLAG_DELETED      = MLX5E_TC_FLOW_BASE + 6,
  87 };
  88
  89 #define MLX5E_TC_MAX_SPLITS 1
  90
  91 /* Helper struct for accessing a struct containing list_head array.
  92  * Containing struct
  93  *   |- Helper array
  94  *      [0] Helper item 0
  95  *          |- list_head item 0
  96  *          |- index (0)
  97  *      [1] Helper item 1
  98  *          |- list_head item 1
  99  *          |- index (1)
 100  * To access the containing struct from one of the list_head items:
 101  * 1. Get the helper item from the list_head item using
 102  *    helper item =
 103  *        container_of(list_head item, helper struct type, list_head field)
 104  * 2. Get the contining struct from the helper item and its index in the array:
 105  *    containing struct =
 106  *        container_of(helper item, containing struct type, helper field[index])
 107  */
 108 struct encap_flow_item {
 109         struct mlx5e_encap_entry *e; /* attached encap instance */
 110         struct list_head list;
 111         int index;
 112 };
 113
 114 struct mlx5e_tc_flow {
 115         struct rhash_head       node;
 116         struct mlx5e_priv       *priv;
 117         u64                     cookie;
 118         unsigned long           flags;
 119         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
 120         /* Flow can be associated with multiple encap IDs.
 121          * The number of encaps is bounded by the number of supported
 122          * destinations.
 123          */
 124         struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
 125         struct mlx5e_tc_flow    *peer_flow;
 126         struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
 127         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
 128         struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
 129         struct list_head        hairpin; /* flows sharing the same hairpin */
 130         struct list_head        peer;    /* flows with peer flow */
 131         struct list_head        unready; /* flows not ready to be offloaded (e.g due to missing route) */
 132         int                     tmp_efi_index;
 133         struct list_head        tmp_list; /* temporary flow list used by neigh update */
 134         refcount_t              refcnt;
 135         struct rcu_head         rcu_head;
 136         struct completion       init_done;
 137         union {
 138                 struct mlx5_esw_flow_attr esw_attr[0];
 139                 struct mlx5_nic_flow_attr nic_attr[0];
 140         };
 141 };
 142
 143 struct mlx5e_tc_flow_parse_attr {
 144         const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
 145         struct net_device *filter_dev;
 146         struct mlx5_flow_spec spec;
 147         int num_mod_hdr_actions;
 148         int max_mod_hdr_actions;
 149         void *mod_hdr_actions;
 150         int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
 151 };
 152
 153 #define MLX5E_TC_TABLE_NUM_GROUPS 4
 154 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
 155
 156 struct mlx5e_hairpin {
 157         struct mlx5_hairpin *pair;
 158
 159         struct mlx5_core_dev *func_mdev;
 160         struct mlx5e_priv *func_priv;
 161         u32 tdn;
 162         u32 tirn;
 163
 164         int num_channels;
 165         struct mlx5e_rqt indir_rqt;
 166         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
 167         struct mlx5e_ttc_table ttc;
 168 };
 169
 170 struct mlx5e_hairpin_entry {
 171         /* a node of a hash table which keeps all the  hairpin entries */
 172         struct hlist_node hairpin_hlist;
 173
 174         /* protects flows list */
 175         spinlock_t flows_lock;
 176         /* flows sharing the same hairpin */
 177         struct list_head flows;
 178         /* hpe's that were not fully initialized when dead peer update event
 179          * function traversed them.
 180          */
 181         struct list_head dead_peer_wait_list;
 182
 183         u16 peer_vhca_id;
 184         u8 prio;
 185         struct mlx5e_hairpin *hp;
 186         refcount_t refcnt;
 187         struct completion res_ready;
 188 };
 189
 190 struct mod_hdr_key {
 191         int num_actions;
 192         void *actions;
 193 };
 194
 195 struct mlx5e_mod_hdr_entry {
 196         /* a node of a hash table which keeps all the mod_hdr entries */
 197         struct hlist_node mod_hdr_hlist;
 198
 199         /* protects flows list */
 200         spinlock_t flows_lock;
 201         /* flows sharing the same mod_hdr entry */
 202         struct list_head flows;
 203
 204         struct mod_hdr_key key;
 205
 206         struct mlx5_modify_hdr *modify_hdr;
 207
 208         refcount_t refcnt;
 209         struct completion res_ready;
 210         int compl_result;
 211 };
 212
 213 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
 214
 215 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 216                               struct mlx5e_tc_flow *flow);
 217
 218 static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 219 {
 220         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 221                 return ERR_PTR(-EINVAL);
 222         return flow;
 223 }
 224
 225 static void mlx5e_flow_put(struct mlx5e_priv *priv,
 226                            struct mlx5e_tc_flow *flow)
 227 {
 228         if (refcount_dec_and_test(&flow->refcnt)) {
 229                 mlx5e_tc_del_flow(priv, flow);
 230                 kfree_rcu(flow, rcu_head);
 231         }
 232 }
 233
 234 static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
 235 {
 236         /* Complete all memory stores before setting bit. */
 237         smp_mb__before_atomic();
 238         set_bit(flag, &flow->flags);
 239 }
 240
 241 #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
 242
 243 static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
 244                                      unsigned long flag)
 245 {
 246         /* test_and_set_bit() provides all necessary barriers */
 247         return test_and_set_bit(flag, &flow->flags);
 248 }
 249
 250 #define flow_flag_test_and_set(flow, flag)                      \
 251         __flow_flag_test_and_set(flow,                          \
 252                                  MLX5E_TC_FLOW_FLAG_##flag)
 253
 254 static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
 255 {
 256         /* Complete all memory stores before clearing bit. */
 257         smp_mb__before_atomic();
 258         clear_bit(flag, &flow->flags);
 259 }
 260
 261 #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
 262                                                       MLX5E_TC_FLOW_FLAG_##flag)
 263
 264 static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
 265 {
 266         bool ret = test_bit(flag, &flow->flags);
 267
 268         /* Read fields of flow structure only after checking flags. */
 269         smp_mb__after_atomic();
 270         return ret;
 271 }
 272
 273 #define flow_flag_test(flow, flag) __flow_flag_test(flow, \
 274                                                     MLX5E_TC_FLOW_FLAG_##flag)
 275
 276 static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 277 {
 278         return flow_flag_test(flow, ESWITCH);
 279 }
 280
 281 static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 282 {
 283         return flow_flag_test(flow, FT);
 284 }
 285
 286 static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 287 {
 288         return flow_flag_test(flow, OFFLOADED);
 289 }
 290
 291 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
 292 {
 293         return jhash(key->actions,
 294                      key->num_actions * MLX5_MH_ACT_SZ, 0);
 295 }
 296
 297 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
 298                                    struct mod_hdr_key *b)
 299 {
 300         if (a->num_actions != b->num_actions)
 301                 return 1;
 302
 303         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
 304 }
 305
 306 static struct mod_hdr_tbl *
 307 get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
 308 {
 309         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 310
 311         return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
 312                 &priv->fs.tc.mod_hdr;
 313 }
 314
 315 static struct mlx5e_mod_hdr_entry *
 316 mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
 317 {
 318         struct mlx5e_mod_hdr_entry *mh, *found = NULL;
 319
 320         hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
 321                 if (!cmp_mod_hdr_info(&mh->key, key)) {
 322                         refcount_inc(&mh->refcnt);
 323                         found = mh;
 324                         break;
 325                 }
 326         }
 327
 328         return found;
 329 }
 330
 331 static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
 332                               struct mlx5e_mod_hdr_entry *mh,
 333                               int namespace)
 334 {
 335         struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
 336
 337         if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
 338                 return;
 339         hash_del(&mh->mod_hdr_hlist);
 340         mutex_unlock(&tbl->lock);
 341
 342         WARN_ON(!list_empty(&mh->flows));
 343         if (mh->compl_result > 0)
 344                 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
 345
 346         kfree(mh);
 347 }
 348
 349 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
 350 {
 351         return mlx5e_is_eswitch_flow(flow) ?
 352                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 353 }
 354 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 355                                 struct mlx5e_tc_flow *flow,
 356                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 357 {
 358         int num_actions, actions_size, namespace, err;
 359         struct mlx5e_mod_hdr_entry *mh;
 360         struct mod_hdr_tbl *tbl;
 361         struct mod_hdr_key key;
 362         u32 hash_key;
 363
 364         num_actions  = parse_attr->num_mod_hdr_actions;
 365         actions_size = MLX5_MH_ACT_SZ * num_actions;
 366
 367         key.actions = parse_attr->mod_hdr_actions;
 368         key.num_actions = num_actions;
 369
 370         hash_key = hash_mod_hdr_info(&key);
 371
 372         namespace = get_flow_name_space(flow);
 373         tbl = get_mod_hdr_table(priv, namespace);
 374
 375         mutex_lock(&tbl->lock);
 376         mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
 377         if (mh) {
 378                 mutex_unlock(&tbl->lock);
 379                 wait_for_completion(&mh->res_ready);
 380
 381                 if (mh->compl_result < 0) {
 382                         err = -EREMOTEIO;
 383                         goto attach_header_err;
 384                 }
 385                 goto attach_flow;
 386         }
 387
 388         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
 389         if (!mh) {
 390                 mutex_unlock(&tbl->lock);
 391                 return -ENOMEM;
 392         }
 393
 394         mh->key.actions = (void *)mh + sizeof(*mh);
 395         memcpy(mh->key.actions, key.actions, actions_size);
 396         mh->key.num_actions = num_actions;
 397         spin_lock_init(&mh->flows_lock);
 398         INIT_LIST_HEAD(&mh->flows);
 399         refcount_set(&mh->refcnt, 1);
 400         init_completion(&mh->res_ready);
 401
 402         hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
 403         mutex_unlock(&tbl->lock);
 404
 405         mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
 406                                                   mh->key.num_actions,
 407                                                   mh->key.actions);
 408         if (IS_ERR(mh->modify_hdr)) {
 409                 err = PTR_ERR(mh->modify_hdr);
 410                 mh->compl_result = err;
 411                 goto alloc_header_err;
 412         }
 413         mh->compl_result = 1;
 414         complete_all(&mh->res_ready);
 415
 416 attach_flow:
 417         flow->mh = mh;
 418         spin_lock(&mh->flows_lock);
 419         list_add(&flow->mod_hdr, &mh->flows);
 420         spin_unlock(&mh->flows_lock);
 421         if (mlx5e_is_eswitch_flow(flow))
 422                 flow->esw_attr->modify_hdr = mh->modify_hdr;
 423         else
 424                 flow->nic_attr->modify_hdr = mh->modify_hdr;
 425
 426         return 0;
 427
 428 alloc_header_err:
 429         complete_all(&mh->res_ready);
 430 attach_header_err:
 431         mlx5e_mod_hdr_put(priv, mh, namespace);
 432         return err;
 433 }
 434
 435 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 436                                  struct mlx5e_tc_flow *flow)
 437 {
 438         /* flow wasn't fully initialized */
 439         if (!flow->mh)
 440                 return;
 441
 442         spin_lock(&flow->mh->flows_lock);
 443         list_del(&flow->mod_hdr);
 444         spin_unlock(&flow->mh->flows_lock);
 445
 446         mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
 447         flow->mh = NULL;
 448 }
 449
 450 static
 451 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 452 {
 453         struct net_device *netdev;
 454         struct mlx5e_priv *priv;
 455
 456         netdev = __dev_get_by_index(net, ifindex);
 457         priv = netdev_priv(netdev);
 458         return priv->mdev;
 459 }
 460
 461 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 462 {
 463         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 464         void *tirc;
 465         int err;
 466
 467         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 468         if (err)
 469                 goto alloc_tdn_err;
 470
 471         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 472
 473         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
 474         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
 475         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 476
 477         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
 478         if (err)
 479                 goto create_tir_err;
 480
 481         return 0;
 482
 483 create_tir_err:
 484         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 485 alloc_tdn_err:
 486         return err;
 487 }
 488
 489 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 490 {
 491         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
 492         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 493 }
 494
 495 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
 496 {
 497         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
 498         struct mlx5e_priv *priv = hp->func_priv;
 499         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
 500
 501         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
 502                                       hp->num_channels);
 503
 504         for (i = 0; i < sz; i++) {
 505                 ix = i;
 506                 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
 507                         ix = mlx5e_bits_invert(i, ilog2(sz));
 508                 ix = indirection_rqt[ix];
 509                 rqn = hp->pair->rqn[ix];
 510                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
 511         }
 512 }
 513
 514 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 515 {
 516         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
 517         struct mlx5e_priv *priv = hp->func_priv;
 518         struct mlx5_core_dev *mdev = priv->mdev;
 519         void *rqtc;
 520         u32 *in;
 521
 522         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
 523         in = kvzalloc(inlen, GFP_KERNEL);
 524         if (!in)
 525                 return -ENOMEM;
 526
 527         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 528
 529         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
 530         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
 531
 532         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
 533
 534         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
 535         if (!err)
 536                 hp->indir_rqt.enabled = true;
 537
 538         kvfree(in);
 539         return err;
 540 }
 541
 542 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 543 {
 544         struct mlx5e_priv *priv = hp->func_priv;
 545         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
 546         int tt, i, err;
 547         void *tirc;
 548
 549         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 550                 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
 551
 552                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
 553                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 554
 555                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 556                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 557                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
 558                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
 559
 560                 err = mlx5_core_create_tir(hp->func_mdev, in,
 561                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
 562                 if (err) {
 563                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 564                         goto err_destroy_tirs;
 565                 }
 566         }
 567         return 0;
 568
 569 err_destroy_tirs:
 570         for (i = 0; i < tt; i++)
 571                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
 572         return err;
 573 }
 574
 575 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 576 {
 577         int tt;
 578
 579         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 580                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
 581 }
 582
 583 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 584                                          struct ttc_params *ttc_params)
 585 {
 586         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 587         int tt;
 588
 589         memset(ttc_params, 0, sizeof(*ttc_params));
 590
 591         ttc_params->any_tt_tirn = hp->tirn;
 592
 593         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 594                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
 595
 596         ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
 597         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 598         ft_attr->prio = MLX5E_TC_PRIO;
 599 }
 600
 601 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 602 {
 603         struct mlx5e_priv *priv = hp->func_priv;
 604         struct ttc_params ttc_params;
 605         int err;
 606
 607         err = mlx5e_hairpin_create_indirect_rqt(hp);
 608         if (err)
 609                 return err;
 610
 611         err = mlx5e_hairpin_create_indirect_tirs(hp);
 612         if (err)
 613                 goto err_create_indirect_tirs;
 614
 615         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 616         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
 617         if (err)
 618                 goto err_create_ttc_table;
 619
 620         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 621                    hp->num_channels, hp->ttc.ft.t->id);
 622
 623         return 0;
 624
 625 err_create_ttc_table:
 626         mlx5e_hairpin_destroy_indirect_tirs(hp);
 627 err_create_indirect_tirs:
 628         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 629
 630         return err;
 631 }
 632
 633 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 634 {
 635         struct mlx5e_priv *priv = hp->func_priv;
 636
 637         mlx5e_destroy_ttc_table(priv, &hp->ttc);
 638         mlx5e_hairpin_destroy_indirect_tirs(hp);
 639         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 640 }
 641
 642 static struct mlx5e_hairpin *
 643 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 644                      int peer_ifindex)
 645 {
 646         struct mlx5_core_dev *func_mdev, *peer_mdev;
 647         struct mlx5e_hairpin *hp;
 648         struct mlx5_hairpin *pair;
 649         int err;
 650
 651         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 652         if (!hp)
 653                 return ERR_PTR(-ENOMEM);
 654
 655         func_mdev = priv->mdev;
 656         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 657
 658         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 659         if (IS_ERR(pair)) {
 660                 err = PTR_ERR(pair);
 661                 goto create_pair_err;
 662         }
 663         hp->pair = pair;
 664         hp->func_mdev = func_mdev;
 665         hp->func_priv = priv;
 666         hp->num_channels = params->num_channels;
 667
 668         err = mlx5e_hairpin_create_transport(hp);
 669         if (err)
 670                 goto create_transport_err;
 671
 672         if (hp->num_channels > 1) {
 673                 err = mlx5e_hairpin_rss_init(hp);
 674                 if (err)
 675                         goto rss_init_err;
 676         }
 677
 678         return hp;
 679
 680 rss_init_err:
 681         mlx5e_hairpin_destroy_transport(hp);
 682 create_transport_err:
 683         mlx5_core_hairpin_destroy(hp->pair);
 684 create_pair_err:
 685         kfree(hp);
 686         return ERR_PTR(err);
 687 }
 688
 689 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 690 {
 691         if (hp->num_channels > 1)
 692                 mlx5e_hairpin_rss_cleanup(hp);
 693         mlx5e_hairpin_destroy_transport(hp);
 694         mlx5_core_hairpin_destroy(hp->pair);
 695         kvfree(hp);
 696 }
 697
 698 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 699 {
 700         return (peer_vhca_id << 16 | prio);
 701 }
 702
 703 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 704                                                      u16 peer_vhca_id, u8 prio)
 705 {
 706         struct mlx5e_hairpin_entry *hpe;
 707         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 708
 709         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
 710                                hairpin_hlist, hash_key) {
 711                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 712                         refcount_inc(&hpe->refcnt);
 713                         return hpe;
 714                 }
 715         }
 716
 717         return NULL;
 718 }
 719
 720 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 721                               struct mlx5e_hairpin_entry *hpe)
 722 {
 723         /* no more hairpin flows for us, release the hairpin pair */
 724         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
 725                 return;
 726         hash_del(&hpe->hairpin_hlist);
 727         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 728
 729         if (!IS_ERR_OR_NULL(hpe->hp)) {
 730                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 731                            dev_name(hpe->hp->pair->peer_mdev->device));
 732
 733                 mlx5e_hairpin_destroy(hpe->hp);
 734         }
 735
 736         WARN_ON(!list_empty(&hpe->flows));
 737         kfree(hpe);
 738 }
 739
 740 #define UNKNOWN_MATCH_PRIO 8
 741
 742 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 743                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 744                                   struct netlink_ext_ack *extack)
 745 {
 746         void *headers_c, *headers_v;
 747         u8 prio_val, prio_mask = 0;
 748         bool vlan_present;
 749
 750 #ifdef CONFIG_MLX5_CORE_EN_DCB
 751         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
 752                 NL_SET_ERR_MSG_MOD(extack,
 753                                    "only PCP trust state supported for hairpin");
 754                 return -EOPNOTSUPP;
 755         }
 756 #endif
 757         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
 758         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
 759
 760         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
 761         if (vlan_present) {
 762                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
 763                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
 764         }
 765
 766         if (!vlan_present || !prio_mask) {
 767                 prio_val = UNKNOWN_MATCH_PRIO;
 768         } else if (prio_mask != 0x7) {
 769                 NL_SET_ERR_MSG_MOD(extack,
 770                                    "masked priority match not supported for hairpin");
 771                 return -EOPNOTSUPP;
 772         }
 773
 774         *match_prio = prio_val;
 775         return 0;
 776 }
 777
 778 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
 779                                   struct mlx5e_tc_flow *flow,
 780                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
 781                                   struct netlink_ext_ack *extack)
 782 {
 783         int peer_ifindex = parse_attr->mirred_ifindex[0];
 784         struct mlx5_hairpin_params params;
 785         struct mlx5_core_dev *peer_mdev;
 786         struct mlx5e_hairpin_entry *hpe;
 787         struct mlx5e_hairpin *hp;
 788         u64 link_speed64;
 789         u32 link_speed;
 790         u8 match_prio;
 791         u16 peer_id;
 792         int err;
 793
 794         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 795         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
 796                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
 797                 return -EOPNOTSUPP;
 798         }
 799
 800         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
 801         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
 802                                      extack);
 803         if (err)
 804                 return err;
 805
 806         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
 807         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
 808         if (hpe) {
 809                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 810                 wait_for_completion(&hpe->res_ready);
 811
 812                 if (IS_ERR(hpe->hp)) {
 813                         err = -EREMOTEIO;
 814                         goto out_err;
 815                 }
 816                 goto attach_flow;
 817         }
 818
 819         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
 820         if (!hpe) {
 821                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 822                 return -ENOMEM;
 823         }
 824
 825         spin_lock_init(&hpe->flows_lock);
 826         INIT_LIST_HEAD(&hpe->flows);
 827         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
 828         hpe->peer_vhca_id = peer_id;
 829         hpe->prio = match_prio;
 830         refcount_set(&hpe->refcnt, 1);
 831         init_completion(&hpe->res_ready);
 832
 833         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
 834                  hash_hairpin_info(peer_id, match_prio));
 835         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 836
 837         params.log_data_size = 15;
 838         params.log_data_size = min_t(u8, params.log_data_size,
 839                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
 840         params.log_data_size = max_t(u8, params.log_data_size,
 841                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
 842
 843         params.log_num_packets = params.log_data_size -
 844                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
 845         params.log_num_packets = min_t(u8, params.log_num_packets,
 846                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
 847
 848         params.q_counter = priv->q_counter;
 849         /* set hairpin pair per each 50Gbs share of the link */
 850         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
 851         link_speed = max_t(u32, link_speed, 50000);
 852         link_speed64 = link_speed;
 853         do_div(link_speed64, 50000);
 854         params.num_channels = link_speed64;
 855
 856         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
 857         hpe->hp = hp;
 858         complete_all(&hpe->res_ready);
 859         if (IS_ERR(hp)) {
 860                 err = PTR_ERR(hp);
 861                 goto out_err;
 862         }
 863
 864         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
 865                    hp->tirn, hp->pair->rqn[0],
 866                    dev_name(hp->pair->peer_mdev->device),
 867                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
 868
 869 attach_flow:
 870         if (hpe->hp->num_channels > 1) {
 871                 flow_flag_set(flow, HAIRPIN_RSS);
 872                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
 873         } else {
 874                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
 875         }
 876
 877         flow->hpe = hpe;
 878         spin_lock(&hpe->flows_lock);
 879         list_add(&flow->hairpin, &hpe->flows);
 880         spin_unlock(&hpe->flows_lock);
 881
 882         return 0;
 883
 884 out_err:
 885         mlx5e_hairpin_put(priv, hpe);
 886         return err;
 887 }
 888
 889 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
 890                                    struct mlx5e_tc_flow *flow)
 891 {
 892         /* flow wasn't fully initialized */
 893         if (!flow->hpe)
 894                 return;
 895
 896         spin_lock(&flow->hpe->flows_lock);
 897         list_del(&flow->hairpin);
 898         spin_unlock(&flow->hpe->flows_lock);
 899
 900         mlx5e_hairpin_put(priv, flow->hpe);
 901         flow->hpe = NULL;
 902 }
 903
 904 static int
 905 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
 906                       struct mlx5e_tc_flow_parse_attr *parse_attr,
 907                       struct mlx5e_tc_flow *flow,
 908                       struct netlink_ext_ack *extack)
 909 {
 910         struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
 911         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 912         struct mlx5_core_dev *dev = priv->mdev;
 913         struct mlx5_flow_destination dest[2] = {};
 914         struct mlx5_flow_act flow_act = {
 915                 .action = attr->action,
 916                 .flags    = FLOW_ACT_NO_APPEND,
 917         };
 918         struct mlx5_fc *counter = NULL;
 919         int err, dest_ix = 0;
 920
 921         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
 922         flow_context->flow_tag = attr->flow_tag;
 923
 924         if (flow_flag_test(flow, HAIRPIN)) {
 925                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
 926                 if (err)
 927                         return err;
 928
 929                 if (flow_flag_test(flow, HAIRPIN_RSS)) {
 930                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 931                         dest[dest_ix].ft = attr->hairpin_ft;
 932                 } else {
 933                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 934                         dest[dest_ix].tir_num = attr->hairpin_tirn;
 935                 }
 936                 dest_ix++;
 937         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
 938                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 939                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
 940                 dest_ix++;
 941         }
 942
 943         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
 944                 counter = mlx5_fc_create(dev, true);
 945                 if (IS_ERR(counter))
 946                         return PTR_ERR(counter);
 947
 948                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
 949                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
 950                 dest_ix++;
 951                 attr->counter = counter;
 952         }
 953
 954         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
 955                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
 956                 flow_act.modify_hdr = attr->modify_hdr;
 957                 kfree(parse_attr->mod_hdr_actions);
 958                 if (err)
 959                         return err;
 960         }
 961
 962         mutex_lock(&priv->fs.tc.t_lock);
 963         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
 964                 struct mlx5_flow_table_attr ft_attr = {};
 965                 int tc_grp_size, tc_tbl_size, tc_num_grps;
 966                 u32 max_flow_counter;
 967
 968                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
 969                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
 970
 971                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
 972
 973                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
 974                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
 975                 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
 976
 977                 ft_attr.prio = MLX5E_TC_PRIO;
 978                 ft_attr.max_fte = tc_tbl_size;
 979                 ft_attr.level = MLX5E_TC_FT_LEVEL;
 980                 ft_attr.autogroup.max_num_groups = tc_num_grps;
 981                 priv->fs.tc.t =
 982                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
 983                                                             &ft_attr);
 984                 if (IS_ERR(priv->fs.tc.t)) {
 985                         mutex_unlock(&priv->fs.tc.t_lock);
 986                         NL_SET_ERR_MSG_MOD(extack,
 987                                            "Failed to create tc offload table\n");
 988                         netdev_err(priv->netdev,
 989                                    "Failed to create tc offload table\n");
 990                         return PTR_ERR(priv->fs.tc.t);
 991                 }
 992         }
 993
 994         if (attr->match_level != MLX5_MATCH_NONE)
 995                 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
 996
 997         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
 998                                             &flow_act, dest, dest_ix);
 999         mutex_unlock(&priv->fs.tc.t_lock);
1000
1001         return PTR_ERR_OR_ZERO(flow->rule[0]);
1002 }
1003
1004 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1005                                   struct mlx5e_tc_flow *flow)
1006 {
1007         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1008         struct mlx5_fc *counter = NULL;
1009
1010         counter = attr->counter;
1011         if (!IS_ERR_OR_NULL(flow->rule[0]))
1012                 mlx5_del_flow_rules(flow->rule[0]);
1013         mlx5_fc_destroy(priv->mdev, counter);
1014
1015         mutex_lock(&priv->fs.tc.t_lock);
1016         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1017                 mlx5_destroy_flow_table(priv->fs.tc.t);
1018                 priv->fs.tc.t = NULL;
1019         }
1020         mutex_unlock(&priv->fs.tc.t_lock);
1021
1022         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1023                 mlx5e_detach_mod_hdr(priv, flow);
1024
1025         if (flow_flag_test(flow, HAIRPIN))
1026                 mlx5e_hairpin_flow_del(priv, flow);
1027 }
1028
1029 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1030                                struct mlx5e_tc_flow *flow, int out_index);
1031
1032 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1033                               struct mlx5e_tc_flow *flow,
1034                               struct net_device *mirred_dev,
1035                               int out_index,
1036                               struct netlink_ext_ack *extack,
1037                               struct net_device **encap_dev,
1038                               bool *encap_valid);
1039
1040 static struct mlx5_flow_handle *
1041 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1042                            struct mlx5e_tc_flow *flow,
1043                            struct mlx5_flow_spec *spec,
1044                            struct mlx5_esw_flow_attr *attr)
1045 {
1046         struct mlx5_flow_handle *rule;
1047
1048         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1049         if (IS_ERR(rule))
1050                 return rule;
1051
1052         if (attr->split_count) {
1053                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1054                 if (IS_ERR(flow->rule[1])) {
1055                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1056                         return flow->rule[1];
1057                 }
1058         }
1059
1060         return rule;
1061 }
1062
1063 static void
1064 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1065                              struct mlx5e_tc_flow *flow,
1066                            struct mlx5_esw_flow_attr *attr)
1067 {
1068         flow_flag_clear(flow, OFFLOADED);
1069
1070         if (attr->split_count)
1071                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1072
1073         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1074 }
1075
1076 static struct mlx5_flow_handle *
1077 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1078                               struct mlx5e_tc_flow *flow,
1079                               struct mlx5_flow_spec *spec)
1080 {
1081         struct mlx5_esw_flow_attr slow_attr;
1082         struct mlx5_flow_handle *rule;
1083
1084         memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1085         slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1086         slow_attr.split_count = 0;
1087         slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1088
1089         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
1090         if (!IS_ERR(rule))
1091                 flow_flag_set(flow, SLOW);
1092
1093         return rule;
1094 }
1095
1096 static void
1097 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1098                                   struct mlx5e_tc_flow *flow)
1099 {
1100         struct mlx5_esw_flow_attr slow_attr;
1101
1102         memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1103         slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1104         slow_attr.split_count = 0;
1105         slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1106         mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
1107         flow_flag_clear(flow, SLOW);
1108 }
1109
1110 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1111  * function.
1112  */
1113 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1114                              struct list_head *unready_flows)
1115 {
1116         flow_flag_set(flow, NOT_READY);
1117         list_add_tail(&flow->unready, unready_flows);
1118 }
1119
1120 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1121  * function.
1122  */
1123 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1124 {
1125         list_del(&flow->unready);
1126         flow_flag_clear(flow, NOT_READY);
1127 }
1128
1129 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1130 {
1131         struct mlx5_rep_uplink_priv *uplink_priv;
1132         struct mlx5e_rep_priv *rpriv;
1133         struct mlx5_eswitch *esw;
1134
1135         esw = flow->priv->mdev->priv.eswitch;
1136         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1137         uplink_priv = &rpriv->uplink_priv;
1138
1139         mutex_lock(&uplink_priv->unready_flows_lock);
1140         unready_flow_add(flow, &uplink_priv->unready_flows);
1141         mutex_unlock(&uplink_priv->unready_flows_lock);
1142 }
1143
1144 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1145 {
1146         struct mlx5_rep_uplink_priv *uplink_priv;
1147         struct mlx5e_rep_priv *rpriv;
1148         struct mlx5_eswitch *esw;
1149
1150         esw = flow->priv->mdev->priv.eswitch;
1151         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1152         uplink_priv = &rpriv->uplink_priv;
1153
1154         mutex_lock(&uplink_priv->unready_flows_lock);
1155         unready_flow_del(flow);
1156         mutex_unlock(&uplink_priv->unready_flows_lock);
1157 }
1158
1159 static int
1160 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1161                       struct mlx5e_tc_flow *flow,
1162                       struct netlink_ext_ack *extack)
1163 {
1164         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1165         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1166         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1167         struct net_device *out_dev, *encap_dev = NULL;
1168         struct mlx5_fc *counter = NULL;
1169         struct mlx5e_rep_priv *rpriv;
1170         struct mlx5e_priv *out_priv;
1171         bool encap_valid = true;
1172         u32 max_prio, max_chain;
1173         int err = 0;
1174         int out_index;
1175
1176         if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
1177                 NL_SET_ERR_MSG_MOD(extack,
1178                                    "E-switch priorities unsupported, upgrade FW");
1179                 return -EOPNOTSUPP;
1180         }
1181
1182         /* We check chain range only for tc flows.
1183          * For ft flows, we checked attr->chain was originally 0 and set it to
1184          * FDB_FT_CHAIN which is outside tc range.
1185          * See mlx5e_rep_setup_ft_cb().
1186          */
1187         max_chain = mlx5_esw_chains_get_chain_range(esw);
1188         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1189                 NL_SET_ERR_MSG_MOD(extack,
1190                                    "Requested chain is out of supported range");
1191                 return -EOPNOTSUPP;
1192         }
1193
1194         max_prio = mlx5_esw_chains_get_prio_range(esw);
1195         if (attr->prio > max_prio) {
1196                 NL_SET_ERR_MSG_MOD(extack,
1197                                    "Requested priority is out of supported range");
1198                 return -EOPNOTSUPP;
1199         }
1200
1201         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1202                 int mirred_ifindex;
1203
1204                 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1205                         continue;
1206
1207                 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1208                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1209                                              mirred_ifindex);
1210                 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1211                                          extack, &encap_dev, &encap_valid);
1212                 if (err)
1213                         return err;
1214
1215                 out_priv = netdev_priv(encap_dev);
1216                 rpriv = out_priv->ppriv;
1217                 attr->dests[out_index].rep = rpriv->rep;
1218                 attr->dests[out_index].mdev = out_priv->mdev;
1219         }
1220
1221         err = mlx5_eswitch_add_vlan_action(esw, attr);
1222         if (err)
1223                 return err;
1224
1225         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1226                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1227                 kfree(parse_attr->mod_hdr_actions);
1228                 if (err)
1229                         return err;
1230         }
1231
1232         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1233                 counter = mlx5_fc_create(attr->counter_dev, true);
1234                 if (IS_ERR(counter))
1235                         return PTR_ERR(counter);
1236
1237                 attr->counter = counter;
1238         }
1239
1240         /* we get here if one of the following takes place:
1241          * (1) there's no error
1242          * (2) there's an encap action and we don't have valid neigh
1243          */
1244         if (!encap_valid)
1245                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1246         else
1247                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1248
1249         if (IS_ERR(flow->rule[0]))
1250                 return PTR_ERR(flow->rule[0]);
1251         else
1252                 flow_flag_set(flow, OFFLOADED);
1253
1254         return 0;
1255 }
1256
1257 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1258 {
1259         struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1260         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1261                                        spec->match_value,
1262                                        misc_parameters_3);
1263         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1264                                              headers_v,
1265                                              geneve_tlv_option_0_data);
1266
1267         return !!geneve_tlv_opt_0_data;
1268 }
1269
1270 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1271                                   struct mlx5e_tc_flow *flow)
1272 {
1273         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1274         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1275         int out_index;
1276
1277         if (flow_flag_test(flow, NOT_READY)) {
1278                 remove_unready_flow(flow);
1279                 kvfree(attr->parse_attr);
1280                 return;
1281         }
1282
1283         if (mlx5e_is_offloaded_flow(flow)) {
1284                 if (flow_flag_test(flow, SLOW))
1285                         mlx5e_tc_unoffload_from_slow_path(esw, flow);
1286                 else
1287                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1288         }
1289
1290         if (mlx5_flow_has_geneve_opt(flow))
1291                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1292
1293         mlx5_eswitch_del_vlan_action(esw, attr);
1294
1295         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1296                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1297                         mlx5e_detach_encap(priv, flow, out_index);
1298                         kfree(attr->parse_attr->tun_info[out_index]);
1299                 }
1300         kvfree(attr->parse_attr);
1301
1302         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1303                 mlx5e_detach_mod_hdr(priv, flow);
1304
1305         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1306                 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1307 }
1308
1309 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1310                               struct mlx5e_encap_entry *e,
1311                               struct list_head *flow_list)
1312 {
1313         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1314         struct mlx5_esw_flow_attr *esw_attr;
1315         struct mlx5_flow_handle *rule;
1316         struct mlx5_flow_spec *spec;
1317         struct mlx5e_tc_flow *flow;
1318         int err;
1319
1320         e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1321                                                      e->reformat_type,
1322                                                      e->encap_size, e->encap_header,
1323                                                      MLX5_FLOW_NAMESPACE_FDB);
1324         if (IS_ERR(e->pkt_reformat)) {
1325                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1326                                PTR_ERR(e->pkt_reformat));
1327                 return;
1328         }
1329         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1330         mlx5e_rep_queue_neigh_stats_work(priv);
1331
1332         list_for_each_entry(flow, flow_list, tmp_list) {
1333                 bool all_flow_encaps_valid = true;
1334                 int i;
1335
1336                 if (!mlx5e_is_offloaded_flow(flow))
1337                         continue;
1338                 esw_attr = flow->esw_attr;
1339                 spec = &esw_attr->parse_attr->spec;
1340
1341                 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
1342                 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1343                 /* Flow can be associated with multiple encap entries.
1344                  * Before offloading the flow verify that all of them have
1345                  * a valid neighbour.
1346                  */
1347                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1348                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1349                                 continue;
1350                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1351                                 all_flow_encaps_valid = false;
1352                                 break;
1353                         }
1354                 }
1355                 /* Do not offload flows with unresolved neighbors */
1356                 if (!all_flow_encaps_valid)
1357                         continue;
1358                 /* update from slow path rule to encap rule */
1359                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1360                 if (IS_ERR(rule)) {
1361                         err = PTR_ERR(rule);
1362                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1363                                        err);
1364                         continue;
1365                 }
1366
1367                 mlx5e_tc_unoffload_from_slow_path(esw, flow);
1368                 flow->rule[0] = rule;
1369                 /* was unset when slow path rule removed */
1370                 flow_flag_set(flow, OFFLOADED);
1371         }
1372 }
1373
1374 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1375                               struct mlx5e_encap_entry *e,
1376                               struct list_head *flow_list)
1377 {
1378         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1379         struct mlx5_flow_handle *rule;
1380         struct mlx5_flow_spec *spec;
1381         struct mlx5e_tc_flow *flow;
1382         int err;
1383
1384         list_for_each_entry(flow, flow_list, tmp_list) {
1385                 if (!mlx5e_is_offloaded_flow(flow))
1386                         continue;
1387                 spec = &flow->esw_attr->parse_attr->spec;
1388
1389                 /* update from encap rule to slow path rule */
1390                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
1391                 /* mark the flow's encap dest as non-valid */
1392                 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1393
1394                 if (IS_ERR(rule)) {
1395                         err = PTR_ERR(rule);
1396                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1397                                        err);
1398                         continue;
1399                 }
1400
1401                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1402                 flow->rule[0] = rule;
1403                 /* was unset when fast path rule removed */
1404                 flow_flag_set(flow, OFFLOADED);
1405         }
1406
1407         /* we know that the encap is valid */
1408         e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1409         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1410 }
1411
1412 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1413 {
1414         if (mlx5e_is_eswitch_flow(flow))
1415                 return flow->esw_attr->counter;
1416         else
1417                 return flow->nic_attr->counter;
1418 }
1419
1420 /* Takes reference to all flows attached to encap and adds the flows to
1421  * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1422  */
1423 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1424 {
1425         struct encap_flow_item *efi;
1426         struct mlx5e_tc_flow *flow;
1427
1428         list_for_each_entry(efi, &e->flows, list) {
1429                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1430                 if (IS_ERR(mlx5e_flow_get(flow)))
1431                         continue;
1432                 wait_for_completion(&flow->init_done);
1433
1434                 flow->tmp_efi_index = efi->index;
1435                 list_add(&flow->tmp_list, flow_list);
1436         }
1437 }
1438
1439 /* Iterate over tmp_list of flows attached to flow_list head. */
1440 void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1441 {
1442         struct mlx5e_tc_flow *flow, *tmp;
1443
1444         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1445                 mlx5e_flow_put(priv, flow);
1446 }
1447
1448 static struct mlx5e_encap_entry *
1449 mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1450                            struct mlx5e_encap_entry *e)
1451 {
1452         struct mlx5e_encap_entry *next = NULL;
1453
1454 retry:
1455         rcu_read_lock();
1456
1457         /* find encap with non-zero reference counter value */
1458         for (next = e ?
1459                      list_next_or_null_rcu(&nhe->encap_list,
1460                                            &e->encap_list,
1461                                            struct mlx5e_encap_entry,
1462                                            encap_list) :
1463                      list_first_or_null_rcu(&nhe->encap_list,
1464                                             struct mlx5e_encap_entry,
1465                                             encap_list);
1466              next;
1467              next = list_next_or_null_rcu(&nhe->encap_list,
1468                                           &next->encap_list,
1469                                           struct mlx5e_encap_entry,
1470                                           encap_list))
1471                 if (mlx5e_encap_take(next))
1472                         break;
1473
1474         rcu_read_unlock();
1475
1476         /* release starting encap */
1477         if (e)
1478                 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1479         if (!next)
1480                 return next;
1481
1482         /* wait for encap to be fully initialized */
1483         wait_for_completion(&next->res_ready);
1484         /* continue searching if encap entry is not in valid state after completion */
1485         if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1486                 e = next;
1487                 goto retry;
1488         }
1489
1490         return next;
1491 }
1492
1493 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1494 {
1495         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1496         struct mlx5e_encap_entry *e = NULL;
1497         struct mlx5e_tc_flow *flow;
1498         struct mlx5_fc *counter;
1499         struct neigh_table *tbl;
1500         bool neigh_used = false;
1501         struct neighbour *n;
1502         u64 lastuse;
1503
1504         if (m_neigh->family == AF_INET)
1505                 tbl = &arp_tbl;
1506 #if IS_ENABLED(CONFIG_IPV6)
1507         else if (m_neigh->family == AF_INET6)
1508                 tbl = ipv6_stub->nd_tbl;
1509 #endif
1510         else
1511                 return;
1512
1513         /* mlx5e_get_next_valid_encap() releases previous encap before returning
1514          * next one.
1515          */
1516         while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
1517                 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
1518                 struct encap_flow_item *efi, *tmp;
1519                 struct mlx5_eswitch *esw;
1520                 LIST_HEAD(flow_list);
1521
1522                 esw = priv->mdev->priv.eswitch;
1523                 mutex_lock(&esw->offloads.encap_tbl_lock);
1524                 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1525                         flow = container_of(efi, struct mlx5e_tc_flow,
1526                                             encaps[efi->index]);
1527                         if (IS_ERR(mlx5e_flow_get(flow)))
1528                                 continue;
1529                         list_add(&flow->tmp_list, &flow_list);
1530
1531                         if (mlx5e_is_offloaded_flow(flow)) {
1532                                 counter = mlx5e_tc_get_counter(flow);
1533                                 lastuse = mlx5_fc_query_lastuse(counter);
1534                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1535                                         neigh_used = true;
1536                                         break;
1537                                 }
1538                         }
1539                 }
1540                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1541
1542                 mlx5e_put_encap_flow_list(priv, &flow_list);
1543                 if (neigh_used) {
1544                         /* release current encap before breaking the loop */
1545                         mlx5e_encap_put(priv, e);
1546                         break;
1547                 }
1548         }
1549
1550         trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1551
1552         if (neigh_used) {
1553                 nhe->reported_lastuse = jiffies;
1554
1555                 /* find the relevant neigh according to the cached device and
1556                  * dst ip pair
1557                  */
1558                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1559                 if (!n)
1560                         return;
1561
1562                 neigh_event_send(n, NULL);
1563                 neigh_release(n);
1564         }
1565 }
1566
1567 static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1568 {
1569         WARN_ON(!list_empty(&e->flows));
1570
1571         if (e->compl_result > 0) {
1572                 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1573
1574                 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1575                         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1576         }
1577
1578         kfree(e->tun_info);
1579         kfree(e->encap_header);
1580         kfree_rcu(e, rcu);
1581 }
1582
1583 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1584 {
1585         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1586
1587         if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1588                 return;
1589         hash_del_rcu(&e->encap_hlist);
1590         mutex_unlock(&esw->offloads.encap_tbl_lock);
1591
1592         mlx5e_encap_dealloc(priv, e);
1593 }
1594
1595 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1596                                struct mlx5e_tc_flow *flow, int out_index)
1597 {
1598         struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1599         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1600
1601         /* flow wasn't fully initialized */
1602         if (!e)
1603                 return;
1604
1605         mutex_lock(&esw->offloads.encap_tbl_lock);
1606         list_del(&flow->encaps[out_index].list);
1607         flow->encaps[out_index].e = NULL;
1608         if (!refcount_dec_and_test(&e->refcnt)) {
1609                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1610                 return;
1611         }
1612         hash_del_rcu(&e->encap_hlist);
1613         mutex_unlock(&esw->offloads.encap_tbl_lock);
1614
1615         mlx5e_encap_dealloc(priv, e);
1616 }
1617
1618 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1619 {
1620         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1621
1622         if (!flow_flag_test(flow, ESWITCH) ||
1623             !flow_flag_test(flow, DUP))
1624                 return;
1625
1626         mutex_lock(&esw->offloads.peer_mutex);
1627         list_del(&flow->peer);
1628         mutex_unlock(&esw->offloads.peer_mutex);
1629
1630         flow_flag_clear(flow, DUP);
1631
1632         if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1633                 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1634                 kfree(flow->peer_flow);
1635         }
1636
1637         flow->peer_flow = NULL;
1638 }
1639
1640 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1641 {
1642         struct mlx5_core_dev *dev = flow->priv->mdev;
1643         struct mlx5_devcom *devcom = dev->priv.devcom;
1644         struct mlx5_eswitch *peer_esw;
1645
1646         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1647         if (!peer_esw)
1648                 return;
1649
1650         __mlx5e_tc_del_fdb_peer_flow(flow);
1651         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1652 }
1653
1654 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1655                               struct mlx5e_tc_flow *flow)
1656 {
1657         if (mlx5e_is_eswitch_flow(flow)) {
1658                 mlx5e_tc_del_fdb_peer_flow(flow);
1659                 mlx5e_tc_del_fdb_flow(priv, flow);
1660         } else {
1661                 mlx5e_tc_del_nic_flow(priv, flow);
1662         }
1663 }
1664
1665
1666 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1667                              struct mlx5_flow_spec *spec,
1668                              struct flow_cls_offload *f,
1669                              struct net_device *filter_dev, u8 *match_level)
1670 {
1671         struct netlink_ext_ack *extack = f->common.extack;
1672         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1673                                        outer_headers);
1674         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1675                                        outer_headers);
1676         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1677         int err;
1678
1679         err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1680                                  headers_c, headers_v, match_level);
1681         if (err) {
1682                 NL_SET_ERR_MSG_MOD(extack,
1683                                    "failed to parse tunnel attributes");
1684                 return err;
1685         }
1686
1687         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1688                 struct flow_match_control match;
1689                 u16 addr_type;
1690
1691                 flow_rule_match_enc_control(rule, &match);
1692                 addr_type = match.key->addr_type;
1693
1694                 /* For tunnel addr_type used same key id`s as for non-tunnel */
1695                 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1696                         struct flow_match_ipv4_addrs match;
1697
1698                         flow_rule_match_enc_ipv4_addrs(rule, &match);
1699                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1700                                  src_ipv4_src_ipv6.ipv4_layout.ipv4,
1701                                  ntohl(match.mask->src));
1702                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1703                                  src_ipv4_src_ipv6.ipv4_layout.ipv4,
1704                                  ntohl(match.key->src));
1705
1706                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1707                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1708                                  ntohl(match.mask->dst));
1709                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1710                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1711                                  ntohl(match.key->dst));
1712
1713                         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1714                                          ethertype);
1715                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1716                                  ETH_P_IP);
1717                 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1718                         struct flow_match_ipv6_addrs match;
1719
1720                         flow_rule_match_enc_ipv6_addrs(rule, &match);
1721                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1722                                             src_ipv4_src_ipv6.ipv6_layout.ipv6),
1723                                &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1724                                                                    ipv6));
1725                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1726                                             src_ipv4_src_ipv6.ipv6_layout.ipv6),
1727                                &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1728                                                                   ipv6));
1729
1730                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1731                                             dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1732                                &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1733                                                                    ipv6));
1734                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1735                                             dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1736                                &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1737                                                                   ipv6));
1738
1739                         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1740                                          ethertype);
1741                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1742                                  ETH_P_IPV6);
1743                 }
1744         }
1745
1746         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1747                 struct flow_match_ip match;
1748
1749                 flow_rule_match_enc_ip(rule, &match);
1750                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1751                          match.mask->tos & 0x3);
1752                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1753                          match.key->tos & 0x3);
1754
1755                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1756                          match.mask->tos >> 2);
1757                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1758                          match.key->tos  >> 2);
1759
1760                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1761                          match.mask->ttl);
1762                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1763                          match.key->ttl);
1764
1765                 if (match.mask->ttl &&
1766                     !MLX5_CAP_ESW_FLOWTABLE_FDB
1767                         (priv->mdev,
1768                          ft_field_support.outer_ipv4_ttl)) {
1769                         NL_SET_ERR_MSG_MOD(extack,
1770                                            "Matching on TTL is not supported");
1771                         return -EOPNOTSUPP;
1772                 }
1773
1774         }
1775
1776         /* Enforce DMAC when offloading incoming tunneled flows.
1777          * Flow counters require a match on the DMAC.
1778          */
1779         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1780         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1781         ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1782                                      dmac_47_16), priv->netdev->dev_addr);
1783
1784         /* let software handle IP fragments */
1785         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1786         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1787
1788         return 0;
1789 }
1790
1791 static void *get_match_headers_criteria(u32 flags,
1792                                         struct mlx5_flow_spec *spec)
1793 {
1794         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1795                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1796                              inner_headers) :
1797                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1798                              outer_headers);
1799 }
1800
1801 static void *get_match_headers_value(u32 flags,
1802                                      struct mlx5_flow_spec *spec)
1803 {
1804         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1805                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1806                              inner_headers) :
1807                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1808                              outer_headers);
1809 }
1810
1811 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1812                                    struct flow_cls_offload *f)
1813 {
1814         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1815         struct netlink_ext_ack *extack = f->common.extack;
1816         struct net_device *ingress_dev;
1817         struct flow_match_meta match;
1818
1819         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1820                 return 0;
1821
1822         flow_rule_match_meta(rule, &match);
1823         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1824                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
1825                 return -EINVAL;
1826         }
1827
1828         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1829                                          match.key->ingress_ifindex);
1830         if (!ingress_dev) {
1831                 NL_SET_ERR_MSG_MOD(extack,
1832                                    "Can't find the ingress port to match on");
1833                 return -EINVAL;
1834         }
1835
1836         if (ingress_dev != filter_dev) {
1837                 NL_SET_ERR_MSG_MOD(extack,
1838                                    "Can't match on the ingress filter port");
1839                 return -EINVAL;
1840         }
1841
1842         return 0;
1843 }
1844
1845 static int __parse_cls_flower(struct mlx5e_priv *priv,
1846                               struct mlx5_flow_spec *spec,
1847                               struct flow_cls_offload *f,
1848                               struct net_device *filter_dev,
1849                               u8 *inner_match_level, u8 *outer_match_level)
1850 {
1851         struct netlink_ext_ack *extack = f->common.extack;
1852         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1853                                        outer_headers);
1854         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1855                                        outer_headers);
1856         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1857                                     misc_parameters);
1858         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1859                                     misc_parameters);
1860         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1861         struct flow_dissector *dissector = rule->match.dissector;
1862         u16 addr_type = 0;
1863         u8 ip_proto = 0;
1864         u8 *match_level;
1865         int err;
1866
1867         match_level = outer_match_level;
1868
1869         if (dissector->used_keys &
1870             ~(BIT(FLOW_DISSECTOR_KEY_META) |
1871               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1872               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1873               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1874               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1875               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1876               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1877               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1878               BIT(FLOW_DISSECTOR_KEY_PORTS) |
1879               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1880               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1881               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1882               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1883               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1884               BIT(FLOW_DISSECTOR_KEY_TCP) |
1885               BIT(FLOW_DISSECTOR_KEY_IP)  |
1886               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1887               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
1888                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1889                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1890                             dissector->used_keys);
1891                 return -EOPNOTSUPP;
1892         }
1893
1894         if (mlx5e_get_tc_tun(filter_dev)) {
1895                 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1896                                       outer_match_level))
1897                         return -EOPNOTSUPP;
1898
1899                 /* At this point, header pointers should point to the inner
1900                  * headers, outer header were already set by parse_tunnel_attr
1901                  */
1902                 match_level = inner_match_level;
1903                 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1904                                                        spec);
1905                 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1906                                                     spec);
1907         }
1908
1909         err = mlx5e_flower_parse_meta(filter_dev, f);
1910         if (err)
1911                 return err;
1912
1913         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1914                 struct flow_match_basic match;
1915
1916                 flow_rule_match_basic(rule, &match);
1917                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1918                          ntohs(match.mask->n_proto));
1919                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1920                          ntohs(match.key->n_proto));
1921
1922                 if (match.mask->n_proto)
1923                         *match_level = MLX5_MATCH_L2;
1924         }
1925         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1926             is_vlan_dev(filter_dev)) {
1927                 struct flow_dissector_key_vlan filter_dev_mask;
1928                 struct flow_dissector_key_vlan filter_dev_key;
1929                 struct flow_match_vlan match;
1930
1931                 if (is_vlan_dev(filter_dev)) {
1932                         match.key = &filter_dev_key;
1933                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1934                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1935                         match.key->vlan_priority = 0;
1936                         match.mask = &filter_dev_mask;
1937                         memset(match.mask, 0xff, sizeof(*match.mask));
1938                         match.mask->vlan_priority = 0;
1939                 } else {
1940                         flow_rule_match_vlan(rule, &match);
1941                 }
1942                 if (match.mask->vlan_id ||
1943                     match.mask->vlan_priority ||
1944                     match.mask->vlan_tpid) {
1945                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1946                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1947                                          svlan_tag, 1);
1948                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1949                                          svlan_tag, 1);
1950                         } else {
1951                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1952                                          cvlan_tag, 1);
1953                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1954                                          cvlan_tag, 1);
1955                         }
1956
1957                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1958                                  match.mask->vlan_id);
1959                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1960                                  match.key->vlan_id);
1961
1962                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1963                                  match.mask->vlan_priority);
1964                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1965                                  match.key->vlan_priority);
1966
1967                         *match_level = MLX5_MATCH_L2;
1968                 }
1969         } else if (*match_level != MLX5_MATCH_NONE) {
1970                 /* cvlan_tag enabled in match criteria and
1971                  * disabled in match value means both S & C tags
1972                  * don't exist (untagged of both)
1973                  */
1974                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1975                 *match_level = MLX5_MATCH_L2;
1976         }
1977
1978         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1979                 struct flow_match_vlan match;
1980
1981                 flow_rule_match_cvlan(rule, &match);
1982                 if (match.mask->vlan_id ||
1983                     match.mask->vlan_priority ||
1984                     match.mask->vlan_tpid) {
1985                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1986                                 MLX5_SET(fte_match_set_misc, misc_c,
1987                                          outer_second_svlan_tag, 1);
1988                                 MLX5_SET(fte_match_set_misc, misc_v,
1989                                          outer_second_svlan_tag, 1);
1990                         } else {
1991                                 MLX5_SET(fte_match_set_misc, misc_c,
1992                                          outer_second_cvlan_tag, 1);
1993                                 MLX5_SET(fte_match_set_misc, misc_v,
1994                                          outer_second_cvlan_tag, 1);
1995                         }
1996
1997                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1998                                  match.mask->vlan_id);
1999                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2000                                  match.key->vlan_id);
2001                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2002                                  match.mask->vlan_priority);
2003                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2004                                  match.key->vlan_priority);
2005
2006                         *match_level = MLX5_MATCH_L2;
2007                 }
2008         }
2009
2010         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2011                 struct flow_match_eth_addrs match;
2012
2013                 flow_rule_match_eth_addrs(rule, &match);
2014                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2015                                              dmac_47_16),
2016                                 match.mask->dst);
2017                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2018                                              dmac_47_16),
2019                                 match.key->dst);
2020
2021                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2022                                              smac_47_16),
2023                                 match.mask->src);
2024                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2025                                              smac_47_16),
2026                                 match.key->src);
2027
2028                 if (!is_zero_ether_addr(match.mask->src) ||
2029                     !is_zero_ether_addr(match.mask->dst))
2030                         *match_level = MLX5_MATCH_L2;
2031         }
2032
2033         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2034                 struct flow_match_control match;
2035
2036                 flow_rule_match_control(rule, &match);
2037                 addr_type = match.key->addr_type;
2038
2039                 /* the HW doesn't support frag first/later */
2040                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
2041                         return -EOPNOTSUPP;
2042
2043                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2044                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2045                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2046                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2047
2048                         /* the HW doesn't need L3 inline to match on frag=no */
2049                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2050                                 *match_level = MLX5_MATCH_L2;
2051         /* ***  L2 attributes parsing up to here *** */
2052                         else
2053                                 *match_level = MLX5_MATCH_L3;
2054                 }
2055         }
2056
2057         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2058                 struct flow_match_basic match;
2059
2060                 flow_rule_match_basic(rule, &match);
2061                 ip_proto = match.key->ip_proto;
2062
2063                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2064                          match.mask->ip_proto);
2065                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2066                          match.key->ip_proto);
2067
2068                 if (match.mask->ip_proto)
2069                         *match_level = MLX5_MATCH_L3;
2070         }
2071
2072         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2073                 struct flow_match_ipv4_addrs match;
2074
2075                 flow_rule_match_ipv4_addrs(rule, &match);
2076                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2077                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2078                        &match.mask->src, sizeof(match.mask->src));
2079                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2080                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2081                        &match.key->src, sizeof(match.key->src));
2082                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2083                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2084                        &match.mask->dst, sizeof(match.mask->dst));
2085                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2086                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2087                        &match.key->dst, sizeof(match.key->dst));
2088
2089                 if (match.mask->src || match.mask->dst)
2090                         *match_level = MLX5_MATCH_L3;
2091         }
2092
2093         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2094                 struct flow_match_ipv6_addrs match;
2095
2096                 flow_rule_match_ipv6_addrs(rule, &match);
2097                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2098                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2099                        &match.mask->src, sizeof(match.mask->src));
2100                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2101                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2102                        &match.key->src, sizeof(match.key->src));
2103
2104                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2105                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2106                        &match.mask->dst, sizeof(match.mask->dst));
2107                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2108                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2109                        &match.key->dst, sizeof(match.key->dst));
2110
2111                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2112                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2113                         *match_level = MLX5_MATCH_L3;
2114         }
2115
2116         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2117                 struct flow_match_ip match;
2118
2119                 flow_rule_match_ip(rule, &match);
2120                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2121                          match.mask->tos & 0x3);
2122                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2123                          match.key->tos & 0x3);
2124
2125                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2126                          match.mask->tos >> 2);
2127                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2128                          match.key->tos  >> 2);
2129
2130                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2131                          match.mask->ttl);
2132                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2133                          match.key->ttl);
2134
2135                 if (match.mask->ttl &&
2136                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2137                                                 ft_field_support.outer_ipv4_ttl)) {
2138                         NL_SET_ERR_MSG_MOD(extack,
2139                                            "Matching on TTL is not supported");
2140                         return -EOPNOTSUPP;
2141                 }
2142
2143                 if (match.mask->tos || match.mask->ttl)
2144                         *match_level = MLX5_MATCH_L3;
2145         }
2146
2147         /* ***  L3 attributes parsing up to here *** */
2148
2149         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2150                 struct flow_match_ports match;
2151
2152                 flow_rule_match_ports(rule, &match);
2153                 switch (ip_proto) {
2154                 case IPPROTO_TCP:
2155                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2156                                  tcp_sport, ntohs(match.mask->src));
2157                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2158                                  tcp_sport, ntohs(match.key->src));
2159
2160                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2161                                  tcp_dport, ntohs(match.mask->dst));
2162                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2163                                  tcp_dport, ntohs(match.key->dst));
2164                         break;
2165
2166                 case IPPROTO_UDP:
2167                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2168                                  udp_sport, ntohs(match.mask->src));
2169                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2170                                  udp_sport, ntohs(match.key->src));
2171
2172                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2173                                  udp_dport, ntohs(match.mask->dst));
2174                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2175                                  udp_dport, ntohs(match.key->dst));
2176                         break;
2177                 default:
2178                         NL_SET_ERR_MSG_MOD(extack,
2179                                            "Only UDP and TCP transports are supported for L4 matching");
2180                         netdev_err(priv->netdev,
2181                                    "Only UDP and TCP transport are supported\n");
2182                         return -EINVAL;
2183                 }
2184
2185                 if (match.mask->src || match.mask->dst)
2186                         *match_level = MLX5_MATCH_L4;
2187         }
2188
2189         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2190                 struct flow_match_tcp match;
2191
2192                 flow_rule_match_tcp(rule, &match);
2193                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2194                          ntohs(match.mask->flags));
2195                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2196                          ntohs(match.key->flags));
2197
2198                 if (match.mask->flags)
2199                         *match_level = MLX5_MATCH_L4;
2200         }
2201
2202         return 0;
2203 }
2204
2205 static int parse_cls_flower(struct mlx5e_priv *priv,
2206                             struct mlx5e_tc_flow *flow,
2207                             struct mlx5_flow_spec *spec,
2208                             struct flow_cls_offload *f,
2209                             struct net_device *filter_dev)
2210 {
2211         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2212         struct netlink_ext_ack *extack = f->common.extack;
2213         struct mlx5_core_dev *dev = priv->mdev;
2214         struct mlx5_eswitch *esw = dev->priv.eswitch;
2215         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2216         struct mlx5_eswitch_rep *rep;
2217         bool is_eswitch_flow;
2218         int err;
2219
2220         inner_match_level = MLX5_MATCH_NONE;
2221         outer_match_level = MLX5_MATCH_NONE;
2222
2223         err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2224                                  &outer_match_level);
2225         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2226                                  outer_match_level : inner_match_level;
2227
2228         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2229         if (!err && is_eswitch_flow) {
2230                 rep = rpriv->rep;
2231                 if (rep->vport != MLX5_VPORT_UPLINK &&
2232                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2233                     esw->offloads.inline_mode < non_tunnel_match_level)) {
2234                         NL_SET_ERR_MSG_MOD(extack,
2235                                            "Flow is not offloaded due to min inline setting");
2236                         netdev_warn(priv->netdev,
2237                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2238                                     non_tunnel_match_level, esw->offloads.inline_mode);
2239                         return -EOPNOTSUPP;
2240                 }
2241         }
2242
2243         if (is_eswitch_flow) {
2244                 flow->esw_attr->inner_match_level = inner_match_level;
2245                 flow->esw_attr->outer_match_level = outer_match_level;
2246         } else {
2247                 flow->nic_attr->match_level = non_tunnel_match_level;
2248         }
2249
2250         return err;
2251 }
2252
2253 struct pedit_headers {
2254         struct ethhdr  eth;
2255         struct vlan_hdr vlan;
2256         struct iphdr   ip4;
2257         struct ipv6hdr ip6;
2258         struct tcphdr  tcp;
2259         struct udphdr  udp;
2260 };
2261
2262 struct pedit_headers_action {
2263         struct pedit_headers    vals;
2264         struct pedit_headers    masks;
2265         u32                     pedits;
2266 };
2267
2268 static int pedit_header_offsets[] = {
2269         [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2270         [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2271         [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2272         [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2273         [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2274 };
2275
2276 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2277
2278 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2279                          struct pedit_headers_action *hdrs)
2280 {
2281         u32 *curr_pmask, *curr_pval;
2282
2283         curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2284         curr_pval  = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2285
2286         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
2287                 goto out_err;
2288
2289         *curr_pmask |= mask;
2290         *curr_pval  |= (val & mask);
2291
2292         return 0;
2293
2294 out_err:
2295         return -EOPNOTSUPP;
2296 }
2297
2298 struct mlx5_fields {
2299         u8  field;
2300         u8  field_bsize;
2301         u32 field_mask;
2302         u32 offset;
2303         u32 match_offset;
2304 };
2305
2306 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2307                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
2308                  offsetof(struct pedit_headers, field) + (off), \
2309                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2310
2311 /* masked values are the same and there are no rewrites that do not have a
2312  * match.
2313  */
2314 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2315         type matchmaskx = *(type *)(matchmaskp); \
2316         type matchvalx = *(type *)(matchvalp); \
2317         type maskx = *(type *)(maskp); \
2318         type valx = *(type *)(valp); \
2319         \
2320         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2321                                                                  matchmaskx)); \
2322 })
2323
2324 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2325                          void *matchmaskp, u8 bsize)
2326 {
2327         bool same = false;
2328
2329         switch (bsize) {
2330         case 8:
2331                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2332                 break;
2333         case 16:
2334                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2335                 break;
2336         case 32:
2337                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2338                 break;
2339         }
2340
2341         return same;
2342 }
2343
2344 static struct mlx5_fields fields[] = {
2345         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2346         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2347         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2348         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2349         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
2350         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2351
2352         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
2353         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
2354         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2355         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2356
2357         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
2358                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2359         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
2360                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2361         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
2362                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2363         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
2364                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2365         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
2366                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2367         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
2368                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2369         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
2370                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2371         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
2372                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2373         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
2374
2375         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
2376         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
2377         /* in linux iphdr tcp_flags is 8 bits long */
2378         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
2379
2380         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2381         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
2382 };
2383
2384 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2385  * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2386  * says how many HW actions were actually parsed.
2387  */
2388 static int offload_pedit_fields(struct pedit_headers_action *hdrs,
2389                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2390                                 u32 *action_flags,
2391                                 struct netlink_ext_ack *extack)
2392 {
2393         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2394         int i, action_size, nactions, max_actions, first, last, next_z;
2395         void *headers_c, *headers_v, *action, *vals_p;
2396         u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
2397         struct mlx5_fields *f;
2398         unsigned long mask;
2399         __be32 mask_be32;
2400         __be16 mask_be16;
2401         u8 cmd;
2402
2403         headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2404         headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
2405
2406         set_masks = &hdrs[0].masks;
2407         add_masks = &hdrs[1].masks;
2408         set_vals = &hdrs[0].vals;
2409         add_vals = &hdrs[1].vals;
2410
2411         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2412         action = parse_attr->mod_hdr_actions +
2413                  parse_attr->num_mod_hdr_actions * action_size;
2414
2415         max_actions = parse_attr->max_mod_hdr_actions;
2416         nactions = parse_attr->num_mod_hdr_actions;
2417
2418         for (i = 0; i < ARRAY_SIZE(fields); i++) {
2419                 bool skip;
2420
2421                 f = &fields[i];
2422                 /* avoid seeing bits set from previous iterations */
2423                 s_mask = 0;
2424                 a_mask = 0;
2425
2426                 s_masks_p = (void *)set_masks + f->offset;
2427                 a_masks_p = (void *)add_masks + f->offset;
2428
2429                 s_mask = *s_masks_p & f->field_mask;
2430                 a_mask = *a_masks_p & f->field_mask;
2431
2432                 if (!s_mask && !a_mask) /* nothing to offload here */
2433                         continue;
2434
2435                 if (s_mask && a_mask) {
2436                         NL_SET_ERR_MSG_MOD(extack,
2437                                            "can't set and add to the same HW field");
2438                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2439                         return -EOPNOTSUPP;
2440                 }
2441
2442                 if (nactions == max_actions) {
2443                         NL_SET_ERR_MSG_MOD(extack,
2444                                            "too many pedit actions, can't offload");
2445                         printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2446                         return -EOPNOTSUPP;
2447                 }
2448
2449                 skip = false;
2450                 if (s_mask) {
2451                         void *match_mask = headers_c + f->match_offset;
2452                         void *match_val = headers_v + f->match_offset;
2453
2454                         cmd  = MLX5_ACTION_TYPE_SET;
2455                         mask = s_mask;
2456                         vals_p = (void *)set_vals + f->offset;
2457                         /* don't rewrite if we have a match on the same value */
2458                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
2459                                          match_mask, f->field_bsize))
2460                                 skip = true;
2461                         /* clear to denote we consumed this field */
2462                         *s_masks_p &= ~f->field_mask;
2463                 } else {
2464                         cmd  = MLX5_ACTION_TYPE_ADD;
2465                         mask = a_mask;
2466                         vals_p = (void *)add_vals + f->offset;
2467                         /* add 0 is no change */
2468                         if ((*(u32 *)vals_p & f->field_mask) == 0)
2469                                 skip = true;
2470                         /* clear to denote we consumed this field */
2471                         *a_masks_p &= ~f->field_mask;
2472                 }
2473                 if (skip)
2474                         continue;
2475
2476                 if (f->field_bsize == 32) {
2477                         mask_be32 = *(__be32 *)&mask;
2478                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2479                 } else if (f->field_bsize == 16) {
2480                         mask_be16 = *(__be16 *)&mask;
2481                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2482                 }
2483
2484                 first = find_first_bit(&mask, f->field_bsize);
2485                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2486                 last  = find_last_bit(&mask, f->field_bsize);
2487                 if (first < next_z && next_z < last) {
2488                         NL_SET_ERR_MSG_MOD(extack,
2489                                            "rewrite of few sub-fields isn't supported");
2490                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2491                                mask);
2492                         return -EOPNOTSUPP;
2493                 }
2494
2495                 MLX5_SET(set_action_in, action, action_type, cmd);
2496                 MLX5_SET(set_action_in, action, field, f->field);
2497
2498                 if (cmd == MLX5_ACTION_TYPE_SET) {
2499                         int start;
2500
2501                         /* if field is bit sized it can start not from first bit */
2502                         start = find_first_bit((unsigned long *)&f->field_mask,
2503                                                f->field_bsize);
2504
2505                         MLX5_SET(set_action_in, action, offset, first - start);
2506                         /* length is num of bits to be written, zero means length of 32 */
2507                         MLX5_SET(set_action_in, action, length, (last - first + 1));
2508                 }
2509
2510                 if (f->field_bsize == 32)
2511                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2512                 else if (f->field_bsize == 16)
2513                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2514                 else if (f->field_bsize == 8)
2515                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2516
2517                 action += action_size;
2518                 nactions++;
2519         }
2520
2521         parse_attr->num_mod_hdr_actions = nactions;
2522         return 0;
2523 }
2524
2525 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2526                                                   int namespace)
2527 {
2528         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2529                 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2530         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2531                 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2532 }
2533
2534 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2535                                  struct pedit_headers_action *hdrs,
2536                                  int namespace,
2537                                  struct mlx5e_tc_flow_parse_attr *parse_attr)
2538 {
2539         int nkeys, action_size, max_actions;
2540
2541         nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2542                 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
2543         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2544
2545         max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
2546         /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2547         max_actions = min(max_actions, nkeys * 16);
2548
2549         parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2550         if (!parse_attr->mod_hdr_actions)
2551                 return -ENOMEM;
2552
2553         parse_attr->max_mod_hdr_actions = max_actions;
2554         return 0;
2555 }
2556
2557 static const struct pedit_headers zero_masks = {};
2558
2559 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2560                                  const struct flow_action_entry *act, int namespace,
2561                                  struct pedit_headers_action *hdrs,
2562                                  struct netlink_ext_ack *extack)
2563 {
2564         u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2565         int err = -EOPNOTSUPP;
2566         u32 mask, val, offset;
2567         u8 htype;
2568
2569         htype = act->mangle.htype;
2570         err = -EOPNOTSUPP; /* can't be all optimistic */
2571
2572         if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2573                 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2574                 goto out_err;
2575         }
2576
2577         if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2578                 NL_SET_ERR_MSG_MOD(extack,
2579                                    "The pedit offload action is not supported");
2580                 goto out_err;
2581         }
2582
2583         mask = act->mangle.mask;
2584         val = act->mangle.val;
2585         offset = act->mangle.offset;
2586
2587         err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2588         if (err)
2589                 goto out_err;
2590
2591         hdrs[cmd].pedits++;
2592
2593         return 0;
2594 out_err:
2595         return err;
2596 }
2597
2598 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2599                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2600                                  struct pedit_headers_action *hdrs,
2601                                  u32 *action_flags,
2602                                  struct netlink_ext_ack *extack)
2603 {
2604         struct pedit_headers *cmd_masks;
2605         int err;
2606         u8 cmd;
2607
2608         if (!parse_attr->mod_hdr_actions) {
2609                 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
2610                 if (err)
2611                         goto out_err;
2612         }
2613
2614         err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
2615         if (err < 0)
2616                 goto out_dealloc_parsed_actions;
2617
2618         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2619                 cmd_masks = &hdrs[cmd].masks;
2620                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2621                         NL_SET_ERR_MSG_MOD(extack,
2622                                            "attempt to offload an unsupported field");
2623                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2624                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2625                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2626                         err = -EOPNOTSUPP;
2627                         goto out_dealloc_parsed_actions;
2628                 }
2629         }
2630
2631         return 0;
2632
2633 out_dealloc_parsed_actions:
2634         kfree(parse_attr->mod_hdr_actions);
2635 out_err:
2636         return err;
2637 }
2638
2639 static bool csum_offload_supported(struct mlx5e_priv *priv,
2640                                    u32 action,
2641                                    u32 update_flags,
2642                                    struct netlink_ext_ack *extack)
2643 {
2644         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2645                          TCA_CSUM_UPDATE_FLAG_UDP;
2646
2647         /*  The HW recalcs checksums only if re-writing headers */
2648         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2649                 NL_SET_ERR_MSG_MOD(extack,
2650                                    "TC csum action is only offloaded with pedit");
2651                 netdev_warn(priv->netdev,
2652                             "TC csum action is only offloaded with pedit\n");
2653                 return false;
2654         }
2655
2656         if (update_flags & ~prot_flags) {
2657                 NL_SET_ERR_MSG_MOD(extack,
2658                                    "can't offload TC csum action for some header/s");
2659                 netdev_warn(priv->netdev,
2660                             "can't offload TC csum action for some header/s - flags %#x\n",
2661                             update_flags);
2662                 return false;
2663         }
2664
2665         return true;
2666 }
2667
2668 struct ip_ttl_word {
2669         __u8    ttl;
2670         __u8    protocol;
2671         __sum16 check;
2672 };
2673
2674 struct ipv6_hoplimit_word {
2675         __be16  payload_len;
2676         __u8    nexthdr;
2677         __u8    hop_limit;
2678 };
2679
2680 static bool is_action_keys_supported(const struct flow_action_entry *act)
2681 {
2682         u32 mask, offset;
2683         u8 htype;
2684
2685         htype = act->mangle.htype;
2686         offset = act->mangle.offset;
2687         mask = ~act->mangle.mask;
2688         /* For IPv4 & IPv6 header check 4 byte word,
2689          * to determine that modified fields
2690          * are NOT ttl & hop_limit only.
2691          */
2692         if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2693                 struct ip_ttl_word *ttl_word =
2694                         (struct ip_ttl_word *)&mask;
2695
2696                 if (offset != offsetof(struct iphdr, ttl) ||
2697                     ttl_word->protocol ||
2698                     ttl_word->check) {
2699                         return true;
2700                 }
2701         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2702                 struct ipv6_hoplimit_word *hoplimit_word =
2703                         (struct ipv6_hoplimit_word *)&mask;
2704
2705                 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2706                     hoplimit_word->payload_len ||
2707                     hoplimit_word->nexthdr) {
2708                         return true;
2709                 }
2710         }
2711         return false;
2712 }
2713
2714 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2715                                           struct flow_action *flow_action,
2716                                           u32 actions,
2717                                           struct netlink_ext_ack *extack)
2718 {
2719         const struct flow_action_entry *act;
2720         bool modify_ip_header;
2721         void *headers_v;
2722         u16 ethertype;
2723         u8 ip_proto;
2724         int i;
2725
2726         headers_v = get_match_headers_value(actions, spec);
2727         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2728
2729         /* for non-IP we only re-write MACs, so we're okay */
2730         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2731                 goto out_ok;
2732
2733         modify_ip_header = false;
2734         flow_action_for_each(i, act, flow_action) {
2735                 if (act->id != FLOW_ACTION_MANGLE &&
2736                     act->id != FLOW_ACTION_ADD)
2737                         continue;
2738
2739                 if (is_action_keys_supported(act)) {
2740                         modify_ip_header = true;
2741                         break;
2742                 }
2743         }
2744
2745         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2746         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2747             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2748                 NL_SET_ERR_MSG_MOD(extack,
2749                                    "can't offload re-write of non TCP/UDP");
2750                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2751                 return false;
2752         }
2753
2754 out_ok:
2755         return true;
2756 }
2757
2758 static bool actions_match_supported(struct mlx5e_priv *priv,
2759                                     struct flow_action *flow_action,
2760                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
2761                                     struct mlx5e_tc_flow *flow,
2762                                     struct netlink_ext_ack *extack)
2763 {
2764         u32 actions;
2765
2766         if (mlx5e_is_eswitch_flow(flow))
2767                 actions = flow->esw_attr->action;
2768         else
2769                 actions = flow->nic_attr->action;
2770
2771         if (flow_flag_test(flow, EGRESS) &&
2772             !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2773               (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2774               (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
2775                 return false;
2776
2777         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2778                 return modify_header_match_supported(&parse_attr->spec,
2779                                                      flow_action, actions,
2780                                                      extack);
2781
2782         return true;
2783 }
2784
2785 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2786 {
2787         struct mlx5_core_dev *fmdev, *pmdev;
2788         u64 fsystem_guid, psystem_guid;
2789
2790         fmdev = priv->mdev;
2791         pmdev = peer_priv->mdev;
2792
2793         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2794         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2795
2796         return (fsystem_guid == psystem_guid);
2797 }
2798
2799 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2800                                    const struct flow_action_entry *act,
2801                                    struct mlx5e_tc_flow_parse_attr *parse_attr,
2802                                    struct pedit_headers_action *hdrs,
2803                                    u32 *action, struct netlink_ext_ack *extack)
2804 {
2805         u16 mask16 = VLAN_VID_MASK;
2806         u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2807         const struct flow_action_entry pedit_act = {
2808                 .id = FLOW_ACTION_MANGLE,
2809                 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2810                 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2811                 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2812                 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2813         };
2814         u8 match_prio_mask, match_prio_val;
2815         void *headers_c, *headers_v;
2816         int err;
2817
2818         headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2819         headers_v = get_match_headers_value(*action, &parse_attr->spec);
2820
2821         if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2822               MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2823                 NL_SET_ERR_MSG_MOD(extack,
2824                                    "VLAN rewrite action must have VLAN protocol match");
2825                 return -EOPNOTSUPP;
2826         }
2827
2828         match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2829         match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2830         if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2831                 NL_SET_ERR_MSG_MOD(extack,
2832                                    "Changing VLAN prio is not supported");
2833                 return -EOPNOTSUPP;
2834         }
2835
2836         err = parse_tc_pedit_action(priv, &pedit_act, namespace, hdrs, NULL);
2837         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2838
2839         return err;
2840 }
2841
2842 static int
2843 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2844                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2845                                  struct pedit_headers_action *hdrs,
2846                                  u32 *action, struct netlink_ext_ack *extack)
2847 {
2848         const struct flow_action_entry prio_tag_act = {
2849                 .vlan.vid = 0,
2850                 .vlan.prio =
2851                         MLX5_GET(fte_match_set_lyr_2_4,
2852                                  get_match_headers_value(*action,
2853                                                          &parse_attr->spec),
2854                                  first_prio) &
2855                         MLX5_GET(fte_match_set_lyr_2_4,
2856                                  get_match_headers_criteria(*action,
2857                                                             &parse_attr->spec),
2858                                  first_prio),
2859         };
2860
2861         return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2862                                        &prio_tag_act, parse_attr, hdrs, action,
2863                                        extack);
2864 }
2865
2866 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2867                                 struct flow_action *flow_action,
2868                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2869                                 struct mlx5e_tc_flow *flow,
2870                                 struct netlink_ext_ack *extack)
2871 {
2872         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2873         struct pedit_headers_action hdrs[2] = {};
2874         const struct flow_action_entry *act;
2875         u32 action = 0;
2876         int err, i;
2877
2878         if (!flow_action_has_entries(flow_action))
2879                 return -EINVAL;
2880
2881         if (!flow_action_hw_stats_types_check(flow_action, extack,
2882                                               FLOW_ACTION_HW_STATS_TYPE_DELAYED))
2883                 return -EOPNOTSUPP;
2884
2885         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2886
2887         flow_action_for_each(i, act, flow_action) {
2888                 switch (act->id) {
2889                 case FLOW_ACTION_ACCEPT:
2890                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2891                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
2892                         break;
2893                 case FLOW_ACTION_DROP:
2894                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2895                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
2896                                                flow_table_properties_nic_receive.flow_counter))
2897                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2898                         break;
2899                 case FLOW_ACTION_MANGLE:
2900                 case FLOW_ACTION_ADD:
2901                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
2902                                                     hdrs, extack);
2903                         if (err)
2904                                 return err;
2905
2906                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2907                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2908                         break;
2909                 case FLOW_ACTION_VLAN_MANGLE:
2910                         err = add_vlan_rewrite_action(priv,
2911                                                       MLX5_FLOW_NAMESPACE_KERNEL,
2912                                                       act, parse_attr, hdrs,
2913                                                       &action, extack);
2914                         if (err)
2915                                 return err;
2916
2917                         break;
2918                 case FLOW_ACTION_CSUM:
2919                         if (csum_offload_supported(priv, action,
2920                                                    act->csum_flags,
2921                                                    extack))
2922                                 break;
2923
2924                         return -EOPNOTSUPP;
2925                 case FLOW_ACTION_REDIRECT: {
2926                         struct net_device *peer_dev = act->dev;
2927
2928                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2929                             same_hw_devs(priv, netdev_priv(peer_dev))) {
2930                                 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
2931                                 flow_flag_set(flow, HAIRPIN);
2932                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2933                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
2934                         } else {
2935                                 NL_SET_ERR_MSG_MOD(extack,
2936                                                    "device is not on same HW, can't offload");
2937                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2938                                             peer_dev->name);
2939                                 return -EINVAL;
2940                         }
2941                         }
2942                         break;
2943                 case FLOW_ACTION_MARK: {
2944                         u32 mark = act->mark;
2945
2946                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2947                                 NL_SET_ERR_MSG_MOD(extack,
2948                                                    "Bad flow mark - only 16 bit is supported");
2949                                 return -EINVAL;
2950                         }
2951
2952                         attr->flow_tag = mark;
2953                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2954                         }
2955                         break;
2956                 default:
2957                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2958                         return -EOPNOTSUPP;
2959                 }
2960         }
2961
2962         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2963             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2964                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2965                                             parse_attr, hdrs, &action, extack);
2966                 if (err)
2967                         return err;
2968                 /* in case all pedit actions are skipped, remove the MOD_HDR
2969                  * flag.
2970                  */
2971                 if (parse_attr->num_mod_hdr_actions == 0) {
2972                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2973                         kfree(parse_attr->mod_hdr_actions);
2974                 }
2975         }
2976
2977         attr->action = action;
2978         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2979                 return -EOPNOTSUPP;
2980
2981         return 0;
2982 }
2983
2984 struct encap_key {
2985         const struct ip_tunnel_key *ip_tun_key;
2986         struct mlx5e_tc_tunnel *tc_tunnel;
2987 };
2988
2989 static inline int cmp_encap_info(struct encap_key *a,
2990                                  struct encap_key *b)
2991 {
2992         return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
2993                a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
2994 }
2995
2996 static inline int hash_encap_info(struct encap_key *key)
2997 {
2998         return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
2999                      key->tc_tunnel->tunnel_type);
3000 }
3001
3002
3003 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3004                                   struct net_device *peer_netdev)
3005 {
3006         struct mlx5e_priv *peer_priv;
3007
3008         peer_priv = netdev_priv(peer_netdev);
3009
3010         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
3011                 mlx5e_eswitch_rep(priv->netdev) &&
3012                 mlx5e_eswitch_rep(peer_netdev) &&
3013                 same_hw_devs(priv, peer_priv));
3014 }
3015
3016
3017
3018 bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3019 {
3020         return refcount_inc_not_zero(&e->refcnt);
3021 }
3022
3023 static struct mlx5e_encap_entry *
3024 mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3025                 uintptr_t hash_key)
3026 {
3027         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3028         struct mlx5e_encap_entry *e;
3029         struct encap_key e_key;
3030
3031         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3032                                    encap_hlist, hash_key) {
3033                 e_key.ip_tun_key = &e->tun_info->key;
3034                 e_key.tc_tunnel = e->tunnel;
3035                 if (!cmp_encap_info(&e_key, key) &&
3036                     mlx5e_encap_take(e))
3037                         return e;
3038         }
3039
3040         return NULL;
3041 }
3042
3043 static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3044 {
3045         size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3046
3047         return kmemdup(tun_info, tun_size, GFP_KERNEL);
3048 }
3049
3050 static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3051                                       struct mlx5e_tc_flow *flow,
3052                                       int out_index,
3053                                       struct mlx5e_encap_entry *e,
3054                                       struct netlink_ext_ack *extack)
3055 {
3056         int i;
3057
3058         for (i = 0; i < out_index; i++) {
3059                 if (flow->encaps[i].e != e)
3060                         continue;
3061                 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3062                 netdev_err(priv->netdev, "can't duplicate encap action\n");
3063                 return true;
3064         }
3065
3066         return false;
3067 }
3068
3069 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
3070                               struct mlx5e_tc_flow *flow,
3071                               struct net_device *mirred_dev,
3072                               int out_index,
3073                               struct netlink_ext_ack *extack,
3074                               struct net_device **encap_dev,
3075                               bool *encap_valid)
3076 {
3077         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3078         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3079         struct mlx5e_tc_flow_parse_attr *parse_attr;
3080         const struct ip_tunnel_info *tun_info;
3081         struct encap_key key;
3082         struct mlx5e_encap_entry *e;
3083         unsigned short family;
3084         uintptr_t hash_key;
3085         int err = 0;
3086
3087         parse_attr = attr->parse_attr;
3088         tun_info = parse_attr->tun_info[out_index];
3089         family = ip_tunnel_info_af(tun_info);
3090         key.ip_tun_key = &tun_info->key;
3091         key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
3092         if (!key.tc_tunnel) {
3093                 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3094                 return -EOPNOTSUPP;
3095         }
3096
3097         hash_key = hash_encap_info(&key);
3098
3099         mutex_lock(&esw->offloads.encap_tbl_lock);
3100         e = mlx5e_encap_get(priv, &key, hash_key);
3101
3102         /* must verify if encap is valid or not */
3103         if (e) {
3104                 /* Check that entry was not already attached to this flow */
3105                 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3106                         err = -EOPNOTSUPP;
3107                         goto out_err;
3108                 }
3109
3110                 mutex_unlock(&esw->offloads.encap_tbl_lock);
3111                 wait_for_completion(&e->res_ready);
3112
3113                 /* Protect against concurrent neigh update. */
3114                 mutex_lock(&esw->offloads.encap_tbl_lock);
3115                 if (e->compl_result < 0) {
3116                         err = -EREMOTEIO;
3117                         goto out_err;
3118                 }
3119                 goto attach_flow;
3120         }
3121
3122         e = kzalloc(sizeof(*e), GFP_KERNEL);
3123         if (!e) {
3124                 err = -ENOMEM;
3125                 goto out_err;
3126         }
3127
3128         refcount_set(&e->refcnt, 1);
3129         init_completion(&e->res_ready);
3130
3131         tun_info = dup_tun_info(tun_info);
3132         if (!tun_info) {
3133                 err = -ENOMEM;
3134                 goto out_err_init;
3135         }
3136         e->tun_info = tun_info;
3137         err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
3138         if (err)
3139                 goto out_err_init;
3140
3141         INIT_LIST_HEAD(&e->flows);
3142         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3143         mutex_unlock(&esw->offloads.encap_tbl_lock);
3144
3145         if (family == AF_INET)
3146                 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
3147         else if (family == AF_INET6)
3148                 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
3149
3150         /* Protect against concurrent neigh update. */
3151         mutex_lock(&esw->offloads.encap_tbl_lock);
3152         complete_all(&e->res_ready);
3153         if (err) {
3154                 e->compl_result = err;
3155                 goto out_err;
3156         }
3157         e->compl_result = 1;
3158
3159 attach_flow:
3160         flow->encaps[out_index].e = e;
3161         list_add(&flow->encaps[out_index].list, &e->flows);
3162         flow->encaps[out_index].index = out_index;
3163         *encap_dev = e->out_dev;
3164         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
3165                 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3166                 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
3167                 *encap_valid = true;
3168         } else {
3169                 *encap_valid = false;
3170         }
3171         mutex_unlock(&esw->offloads.encap_tbl_lock);
3172
3173         return err;
3174
3175 out_err:
3176         mutex_unlock(&esw->offloads.encap_tbl_lock);
3177         if (e)
3178                 mlx5e_encap_put(priv, e);
3179         return err;
3180
3181 out_err_init:
3182         mutex_unlock(&esw->offloads.encap_tbl_lock);
3183         kfree(tun_info);
3184         kfree(e);
3185         return err;
3186 }
3187
3188 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3189                                 const struct flow_action_entry *act,
3190                                 struct mlx5_esw_flow_attr *attr,
3191                                 u32 *action)
3192 {
3193         u8 vlan_idx = attr->total_vlan;
3194
3195         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3196                 return -EOPNOTSUPP;
3197
3198         switch (act->id) {
3199         case FLOW_ACTION_VLAN_POP:
3200                 if (vlan_idx) {
3201                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3202                                                                  MLX5_FS_VLAN_DEPTH))
3203                                 return -EOPNOTSUPP;
3204
3205                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3206                 } else {
3207                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3208                 }
3209                 break;
3210         case FLOW_ACTION_VLAN_PUSH:
3211                 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3212                 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3213                 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3214                 if (!attr->vlan_proto[vlan_idx])
3215                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3216
3217                 if (vlan_idx) {
3218                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3219                                                                  MLX5_FS_VLAN_DEPTH))
3220                                 return -EOPNOTSUPP;
3221
3222                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3223                 } else {
3224                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3225                             (act->vlan.proto != htons(ETH_P_8021Q) ||
3226                              act->vlan.prio))
3227                                 return -EOPNOTSUPP;
3228
3229                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3230                 }
3231                 break;
3232         default:
3233                 return -EINVAL;
3234         }
3235
3236         attr->total_vlan = vlan_idx + 1;
3237
3238         return 0;
3239 }
3240
3241 static int add_vlan_push_action(struct mlx5e_priv *priv,
3242                                 struct mlx5_esw_flow_attr *attr,
3243                                 struct net_device **out_dev,
3244                                 u32 *action)
3245 {
3246         struct net_device *vlan_dev = *out_dev;
3247         struct flow_action_entry vlan_act = {
3248                 .id = FLOW_ACTION_VLAN_PUSH,
3249                 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3250                 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3251                 .vlan.prio = 0,
3252         };
3253         int err;
3254
3255         err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3256         if (err)
3257                 return err;
3258
3259         *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3260                                         dev_get_iflink(vlan_dev));
3261         if (is_vlan_dev(*out_dev))
3262                 err = add_vlan_push_action(priv, attr, out_dev, action);
3263
3264         return err;
3265 }
3266
3267 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3268                                struct mlx5_esw_flow_attr *attr,
3269                                u32 *action)
3270 {
3271         int nest_level = attr->parse_attr->filter_dev->lower_level;
3272         struct flow_action_entry vlan_act = {
3273                 .id = FLOW_ACTION_VLAN_POP,
3274         };
3275         int err = 0;
3276
3277         while (nest_level--) {
3278                 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3279                 if (err)
3280                         return err;
3281         }
3282
3283         return err;
3284 }
3285
3286 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3287                                     struct net_device *out_dev)
3288 {
3289         if (is_merged_eswitch_dev(priv, out_dev))
3290                 return true;
3291
3292         return mlx5e_eswitch_rep(out_dev) &&
3293                same_hw_devs(priv, netdev_priv(out_dev));
3294 }
3295
3296 static bool is_duplicated_output_device(struct net_device *dev,
3297                                         struct net_device *out_dev,
3298                                         int *ifindexes, int if_count,
3299                                         struct netlink_ext_ack *extack)
3300 {
3301         int i;
3302
3303         for (i = 0; i < if_count; i++) {
3304                 if (ifindexes[i] == out_dev->ifindex) {
3305                         NL_SET_ERR_MSG_MOD(extack,
3306                                            "can't duplicate output to same device");
3307                         netdev_err(dev, "can't duplicate output to same device: %s\n",
3308                                    out_dev->name);
3309                         return true;
3310                 }
3311         }
3312
3313         return false;
3314 }
3315
3316 static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3317                                     struct mlx5e_tc_flow *flow,
3318                                     const struct flow_action_entry *act,
3319                                     u32 actions,
3320                                     struct netlink_ext_ack *extack)
3321 {
3322         u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3323         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3324         bool ft_flow = mlx5e_is_ft_flow(flow);
3325         u32 dest_chain = act->chain_index;
3326
3327         if (ft_flow) {
3328                 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3329                 return -EOPNOTSUPP;
3330         }
3331
3332         if (!mlx5_esw_chains_backwards_supported(esw) &&
3333             dest_chain <= attr->chain) {
3334                 NL_SET_ERR_MSG_MOD(extack,
3335                                    "Goto lower numbered chain isn't supported");
3336                 return -EOPNOTSUPP;
3337         }
3338         if (dest_chain > max_chain) {
3339                 NL_SET_ERR_MSG_MOD(extack,
3340                                    "Requested destination chain is out of supported range");
3341                 return -EOPNOTSUPP;
3342         }
3343
3344         if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3345                        MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3346             !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3347                 NL_SET_ERR_MSG_MOD(extack,
3348                                    "Goto chain is not allowed if action has reformat or decap");
3349                 return -EOPNOTSUPP;
3350         }
3351
3352         return 0;
3353 }
3354
3355 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3356                                 struct flow_action *flow_action,
3357                                 struct mlx5e_tc_flow *flow,
3358                                 struct netlink_ext_ack *extack)
3359 {
3360         struct pedit_headers_action hdrs[2] = {};
3361         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3362         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3363         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3364         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3365         const struct ip_tunnel_info *info = NULL;
3366         int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
3367         bool ft_flow = mlx5e_is_ft_flow(flow);
3368         const struct flow_action_entry *act;
3369         int err, i, if_count = 0;
3370         bool encap = false;
3371         u32 action = 0;
3372
3373         if (!flow_action_has_entries(flow_action))
3374                 return -EINVAL;
3375
3376         if (!flow_action_hw_stats_types_check(flow_action, extack,
3377                                               FLOW_ACTION_HW_STATS_TYPE_DELAYED))
3378                 return -EOPNOTSUPP;
3379
3380         flow_action_for_each(i, act, flow_action) {
3381                 switch (act->id) {
3382                 case FLOW_ACTION_DROP:
3383                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3384                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3385                         break;
3386                 case FLOW_ACTION_MANGLE:
3387                 case FLOW_ACTION_ADD:
3388                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3389                                                     hdrs, extack);
3390                         if (err)
3391                                 return err;
3392
3393                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3394                         attr->split_count = attr->out_count;
3395                         break;
3396                 case FLOW_ACTION_CSUM:
3397                         if (csum_offload_supported(priv, action,
3398                                                    act->csum_flags, extack))
3399                                 break;
3400
3401                         return -EOPNOTSUPP;
3402                 case FLOW_ACTION_REDIRECT:
3403                 case FLOW_ACTION_MIRRED: {
3404                         struct mlx5e_priv *out_priv;
3405                         struct net_device *out_dev;
3406
3407                         out_dev = act->dev;
3408                         if (!out_dev) {
3409                                 /* out_dev is NULL when filters with
3410                                  * non-existing mirred device are replayed to
3411                                  * the driver.
3412                                  */
3413                                 return -EINVAL;
3414                         }
3415
3416                         if (ft_flow && out_dev == priv->netdev) {
3417                                 /* Ignore forward to self rules generated
3418                                  * by adding both mlx5 devs to the flow table
3419                                  * block on a normal nft offload setup.
3420                                  */
3421                                 return -EOPNOTSUPP;
3422                         }
3423
3424                         if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3425                                 NL_SET_ERR_MSG_MOD(extack,
3426                                                    "can't support more output ports, can't offload forwarding");
3427                                 netdev_warn(priv->netdev,
3428                                             "can't support more than %d output ports, can't offload forwarding\n",
3429                                             attr->out_count);
3430                                 return -EOPNOTSUPP;
3431                         }
3432
3433                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3434                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3435                         if (encap) {
3436                                 parse_attr->mirred_ifindex[attr->out_count] =
3437                                         out_dev->ifindex;
3438                                 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3439                                 if (!parse_attr->tun_info[attr->out_count])
3440                                         return -ENOMEM;
3441                                 encap = false;
3442                                 attr->dests[attr->out_count].flags |=
3443                                         MLX5_ESW_DEST_ENCAP;
3444                                 attr->out_count++;
3445                                 /* attr->dests[].rep is resolved when we
3446                                  * handle encap
3447                                  */
3448                         } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3449                                 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3450                                 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3451                                 struct net_device *uplink_upper;
3452                                 struct mlx5e_rep_priv *rep_priv;
3453
3454                                 if (is_duplicated_output_device(priv->netdev,
3455                                                                 out_dev,
3456                                                                 ifindexes,
3457                                                                 if_count,
3458                                                                 extack))
3459                                         return -EOPNOTSUPP;
3460
3461                                 ifindexes[if_count] = out_dev->ifindex;
3462                                 if_count++;
3463
3464                                 rcu_read_lock();
3465                                 uplink_upper =
3466                                         netdev_master_upper_dev_get_rcu(uplink_dev);
3467                                 if (uplink_upper &&
3468                                     netif_is_lag_master(uplink_upper) &&
3469                                     uplink_upper == out_dev)
3470                                         out_dev = uplink_dev;
3471                                 rcu_read_unlock();
3472
3473                                 if (is_vlan_dev(out_dev)) {
3474                                         err = add_vlan_push_action(priv, attr,
3475                                                                    &out_dev,
3476                                                                    &action);
3477                                         if (err)
3478                                                 return err;
3479                                 }
3480
3481                                 if (is_vlan_dev(parse_attr->filter_dev)) {
3482                                         err = add_vlan_pop_action(priv, attr,
3483                                                                   &action);
3484                                         if (err)
3485                                                 return err;
3486                                 }
3487
3488                                 /* Don't allow forwarding between uplink.
3489                                  *
3490                                  * Input vport was stored esw_attr->in_rep.
3491                                  * In LAG case, *priv* is the private data of
3492                                  * uplink which may be not the input vport.
3493                                  */
3494                                 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3495                                 if (mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3496                                     mlx5e_eswitch_uplink_rep(out_dev)) {
3497                                         NL_SET_ERR_MSG_MOD(extack,
3498                                                            "devices are both uplink, can't offload forwarding");
3499                                         pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3500                                                priv->netdev->name, out_dev->name);
3501                                         return -EOPNOTSUPP;
3502                                 }
3503
3504                                 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3505                                         NL_SET_ERR_MSG_MOD(extack,
3506                                                            "devices are not on same switch HW, can't offload forwarding");
3507                                         netdev_warn(priv->netdev,
3508                                                     "devices %s %s not on same switch HW, can't offload forwarding\n",
3509                                                     priv->netdev->name,
3510                                                     out_dev->name);
3511                                         return -EOPNOTSUPP;
3512                                 }
3513
3514                                 out_priv = netdev_priv(out_dev);
3515                                 rpriv = out_priv->ppriv;
3516                                 attr->dests[attr->out_count].rep = rpriv->rep;
3517                                 attr->dests[attr->out_count].mdev = out_priv->mdev;
3518                                 attr->out_count++;
3519                         } else if (parse_attr->filter_dev != priv->netdev) {
3520                                 /* All mlx5 devices are called to configure
3521                                  * high level device filters. Therefore, the
3522                                  * *attempt* to  install a filter on invalid
3523                                  * eswitch should not trigger an explicit error
3524                                  */
3525                                 return -EINVAL;
3526                         } else {
3527                                 NL_SET_ERR_MSG_MOD(extack,
3528                                                    "devices are not on same switch HW, can't offload forwarding");
3529                                 netdev_warn(priv->netdev,
3530                                             "devices %s %s not on same switch HW, can't offload forwarding\n",
3531                                             priv->netdev->name,
3532                                             out_dev->name);
3533                                 return -EINVAL;
3534                         }
3535                         }
3536                         break;
3537                 case FLOW_ACTION_TUNNEL_ENCAP:
3538                         info = act->tunnel;
3539                         if (info)
3540                                 encap = true;
3541                         else
3542                                 return -EOPNOTSUPP;
3543
3544                         break;
3545                 case FLOW_ACTION_VLAN_PUSH:
3546                 case FLOW_ACTION_VLAN_POP:
3547                         if (act->id == FLOW_ACTION_VLAN_PUSH &&
3548                             (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3549                                 /* Replace vlan pop+push with vlan modify */
3550                                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3551                                 err = add_vlan_rewrite_action(priv,
3552                                                               MLX5_FLOW_NAMESPACE_FDB,
3553                                                               act, parse_attr, hdrs,
3554                                                               &action, extack);
3555                         } else {
3556                                 err = parse_tc_vlan_action(priv, act, attr, &action);
3557                         }
3558                         if (err)
3559                                 return err;
3560
3561                         attr->split_count = attr->out_count;
3562                         break;
3563                 case FLOW_ACTION_VLAN_MANGLE:
3564                         err = add_vlan_rewrite_action(priv,
3565                                                       MLX5_FLOW_NAMESPACE_FDB,
3566                                                       act, parse_attr, hdrs,
3567                                                       &action, extack);
3568                         if (err)
3569                                 return err;
3570
3571                         attr->split_count = attr->out_count;
3572                         break;
3573                 case FLOW_ACTION_TUNNEL_DECAP:
3574                         action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
3575                         break;
3576                 case FLOW_ACTION_GOTO:
3577                         err = mlx5_validate_goto_chain(esw, flow, act, action,
3578                                                        extack);
3579                         if (err)
3580                                 return err;
3581
3582                         action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3583                         attr->dest_chain = act->chain_index;
3584                         break;
3585                 default:
3586                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3587                         return -EOPNOTSUPP;
3588                 }
3589         }
3590
3591         if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3592             action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3593                 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3594                  * tag rewrite.
3595                  */
3596                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3597                 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3598                                                        &action, extack);
3599                 if (err)
3600                         return err;
3601         }
3602
3603         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3604             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3605                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3606                                             parse_attr, hdrs, &action, extack);
3607                 if (err)
3608                         return err;
3609                 /* in case all pedit actions are skipped, remove the MOD_HDR
3610                  * flag. we might have set split_count either by pedit or
3611                  * pop/push. if there is no pop/push either, reset it too.
3612                  */
3613                 if (parse_attr->num_mod_hdr_actions == 0) {
3614                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3615                         kfree(parse_attr->mod_hdr_actions);
3616                         if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3617                               (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3618                                 attr->split_count = 0;
3619                 }
3620         }
3621
3622         attr->action = action;
3623         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3624                 return -EOPNOTSUPP;
3625
3626         if (attr->dest_chain) {
3627                 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3628                         NL_SET_ERR_MSG_MOD(extack,
3629                                            "Mirroring goto chain rules isn't supported");
3630                         return -EOPNOTSUPP;
3631                 }
3632                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3633         }
3634
3635         if (!(attr->action &
3636               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3637                 NL_SET_ERR_MSG_MOD(extack,
3638                                    "Rule must have at least one forward/drop action");
3639                 return -EOPNOTSUPP;
3640         }
3641
3642         if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3643                 NL_SET_ERR_MSG_MOD(extack,
3644                                    "current firmware doesn't support split rule for port mirroring");
3645                 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3646                 return -EOPNOTSUPP;
3647         }
3648
3649         return 0;
3650 }
3651
3652 static void get_flags(int flags, unsigned long *flow_flags)
3653 {
3654         unsigned long __flow_flags = 0;
3655
3656         if (flags & MLX5_TC_FLAG(INGRESS))
3657                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3658         if (flags & MLX5_TC_FLAG(EGRESS))
3659                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3660
3661         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3662                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3663         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3664                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3665         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3666                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
3667
3668         *flow_flags = __flow_flags;
3669 }
3670
3671 static const struct rhashtable_params tc_ht_params = {
3672         .head_offset = offsetof(struct mlx5e_tc_flow, node),
3673         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3674         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3675         .automatic_shrinking = true,
3676 };
3677
3678 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3679                                     unsigned long flags)
3680 {
3681         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3682         struct mlx5e_rep_priv *uplink_rpriv;
3683
3684         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
3685                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3686                 return &uplink_rpriv->uplink_priv.tc_ht;
3687         } else /* NIC offload */
3688                 return &priv->fs.tc.ht;
3689 }
3690
3691 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3692 {
3693         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3694         bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
3695                 flow_flag_test(flow, INGRESS);
3696         bool act_is_encap = !!(attr->action &
3697                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3698         bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3699                                                 MLX5_DEVCOM_ESW_OFFLOADS);
3700
3701         if (!esw_paired)
3702                 return false;
3703
3704         if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3705              mlx5_lag_is_multipath(attr->in_mdev)) &&
3706             (is_rep_ingress || act_is_encap))
3707                 return true;
3708
3709         return false;
3710 }
3711
3712 static int
3713 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
3714                  struct flow_cls_offload *f, unsigned long flow_flags,
3715                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
3716                  struct mlx5e_tc_flow **__flow)
3717 {
3718         struct mlx5e_tc_flow_parse_attr *parse_attr;
3719         struct mlx5e_tc_flow *flow;
3720         int out_index, err;
3721
3722         flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
3723         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3724         if (!parse_attr || !flow) {
3725                 err = -ENOMEM;
3726                 goto err_free;
3727         }
3728
3729         flow->cookie = f->cookie;
3730         flow->flags = flow_flags;
3731         flow->priv = priv;
3732         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3733                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3734         INIT_LIST_HEAD(&flow->mod_hdr);
3735         INIT_LIST_HEAD(&flow->hairpin);
3736         refcount_set(&flow->refcnt, 1);
3737         init_completion(&flow->init_done);
3738
3739         *__flow = flow;
3740         *__parse_attr = parse_attr;
3741
3742         return 0;
3743
3744 err_free:
3745         kfree(flow);
3746         kvfree(parse_attr);
3747         return err;
3748 }
3749
3750 static void
3751 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3752                          struct mlx5e_priv *priv,
3753                          struct mlx5e_tc_flow_parse_attr *parse_attr,
3754                          struct flow_cls_offload *f,
3755                          struct mlx5_eswitch_rep *in_rep,
3756                          struct mlx5_core_dev *in_mdev)
3757 {
3758         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3759
3760         esw_attr->parse_attr = parse_attr;
3761         esw_attr->chain = f->common.chain_index;
3762         esw_attr->prio = f->common.prio;
3763
3764         esw_attr->in_rep = in_rep;
3765         esw_attr->in_mdev = in_mdev;
3766
3767         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3768             MLX5_COUNTER_SOURCE_ESWITCH)
3769                 esw_attr->counter_dev = in_mdev;
3770         else
3771                 esw_attr->counter_dev = priv->mdev;
3772 }
3773
3774 static struct mlx5e_tc_flow *
3775 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3776                      struct flow_cls_offload *f,
3777                      unsigned long flow_flags,
3778                      struct net_device *filter_dev,
3779                      struct mlx5_eswitch_rep *in_rep,
3780                      struct mlx5_core_dev *in_mdev)
3781 {
3782         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3783         struct netlink_ext_ack *extack = f->common.extack;
3784         struct mlx5e_tc_flow_parse_attr *parse_attr;
3785         struct mlx5e_tc_flow *flow;
3786         int attr_size, err;
3787
3788         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3789         attr_size  = sizeof(struct mlx5_esw_flow_attr);
3790         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3791                                &parse_attr, &flow);
3792         if (err)
3793                 goto out;
3794
3795         parse_attr->filter_dev = filter_dev;
3796         mlx5e_flow_esw_attr_init(flow->esw_attr,
3797                                  priv, parse_attr,
3798                                  f, in_rep, in_mdev);
3799
3800         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3801                                f, filter_dev);
3802         if (err)
3803                 goto err_free;
3804
3805         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
3806         if (err)
3807                 goto err_free;
3808
3809         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
3810         complete_all(&flow->init_done);
3811         if (err) {
3812                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3813                         goto err_free;
3814
3815                 add_unready_flow(flow);
3816         }
3817
3818         return flow;
3819
3820 err_free:
3821         mlx5e_flow_put(priv, flow);
3822 out:
3823         return ERR_PTR(err);
3824 }
3825
3826 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
3827                                       struct mlx5e_tc_flow *flow,
3828                                       unsigned long flow_flags)
3829 {
3830         struct mlx5e_priv *priv = flow->priv, *peer_priv;
3831         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3832         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3833         struct mlx5e_tc_flow_parse_attr *parse_attr;
3834         struct mlx5e_rep_priv *peer_urpriv;
3835         struct mlx5e_tc_flow *peer_flow;
3836         struct mlx5_core_dev *in_mdev;
3837         int err = 0;
3838
3839         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3840         if (!peer_esw)
3841                 return -ENODEV;
3842
3843         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3844         peer_priv = netdev_priv(peer_urpriv->netdev);
3845
3846         /* in_mdev is assigned of which the packet originated from.
3847          * So packets redirected to uplink use the same mdev of the
3848          * original flow and packets redirected from uplink use the
3849          * peer mdev.
3850          */
3851         if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
3852                 in_mdev = peer_priv->mdev;
3853         else
3854                 in_mdev = priv->mdev;
3855
3856         parse_attr = flow->esw_attr->parse_attr;
3857         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
3858                                          parse_attr->filter_dev,
3859                                          flow->esw_attr->in_rep, in_mdev);
3860         if (IS_ERR(peer_flow)) {
3861                 err = PTR_ERR(peer_flow);
3862                 goto out;
3863         }
3864
3865         flow->peer_flow = peer_flow;
3866         flow_flag_set(flow, DUP);
3867         mutex_lock(&esw->offloads.peer_mutex);
3868         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3869         mutex_unlock(&esw->offloads.peer_mutex);
3870
3871 out:
3872         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3873         return err;
3874 }
3875
3876 static int
3877 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3878                    struct flow_cls_offload *f,
3879                    unsigned long flow_flags,
3880                    struct net_device *filter_dev,
3881                    struct mlx5e_tc_flow **__flow)
3882 {
3883         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3884         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3885         struct mlx5_core_dev *in_mdev = priv->mdev;
3886         struct mlx5e_tc_flow *flow;
3887         int err;
3888
3889         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3890                                     in_mdev);
3891         if (IS_ERR(flow))
3892                 return PTR_ERR(flow);
3893
3894         if (is_peer_flow_needed(flow)) {
3895                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
3896                 if (err) {
3897                         mlx5e_tc_del_fdb_flow(priv, flow);
3898                         goto out;
3899                 }
3900         }
3901
3902         *__flow = flow;
3903
3904         return 0;
3905
3906 out:
3907         return err;
3908 }
3909
3910 static int
3911 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3912                    struct flow_cls_offload *f,
3913                    unsigned long flow_flags,
3914                    struct net_device *filter_dev,
3915                    struct mlx5e_tc_flow **__flow)
3916 {
3917         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3918         struct netlink_ext_ack *extack = f->common.extack;
3919         struct mlx5e_tc_flow_parse_attr *parse_attr;
3920         struct mlx5e_tc_flow *flow;
3921         int attr_size, err;
3922
3923         /* multi-chain not supported for NIC rules */
3924         if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3925                 return -EOPNOTSUPP;
3926
3927         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3928         attr_size  = sizeof(struct mlx5_nic_flow_attr);
3929         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3930                                &parse_attr, &flow);
3931         if (err)
3932                 goto out;
3933
3934         parse_attr->filter_dev = filter_dev;
3935         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3936                                f, filter_dev);
3937         if (err)
3938                 goto err_free;
3939
3940         err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
3941         if (err)
3942                 goto err_free;
3943
3944         err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3945         if (err)
3946                 goto err_free;
3947
3948         flow_flag_set(flow, OFFLOADED);
3949         kvfree(parse_attr);
3950         *__flow = flow;
3951
3952         return 0;
3953
3954 err_free:
3955         mlx5e_flow_put(priv, flow);
3956         kvfree(parse_attr);
3957 out:
3958         return err;
3959 }
3960
3961 static int
3962 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3963                   struct flow_cls_offload *f,
3964                   unsigned long flags,
3965                   struct net_device *filter_dev,
3966                   struct mlx5e_tc_flow **flow)
3967 {
3968         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3969         unsigned long flow_flags;
3970         int err;
3971
3972         get_flags(flags, &flow_flags);
3973
3974         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3975                 return -EOPNOTSUPP;
3976
3977         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
3978                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3979                                          filter_dev, flow);
3980         else
3981                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3982                                          filter_dev, flow);
3983
3984         return err;
3985 }
3986
3987 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
3988                            struct flow_cls_offload *f, unsigned long flags)
3989 {
3990         struct netlink_ext_ack *extack = f->common.extack;
3991         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3992         struct mlx5e_tc_flow *flow;
3993         int err = 0;
3994
3995         rcu_read_lock();
3996         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3997         rcu_read_unlock();
3998         if (flow) {
3999                 NL_SET_ERR_MSG_MOD(extack,
4000                                    "flow cookie already exists, ignoring");
4001                 netdev_warn_once(priv->netdev,
4002                                  "flow cookie %lx already exists, ignoring\n",
4003                                  f->cookie);
4004                 err = -EEXIST;
4005                 goto out;
4006         }
4007
4008         trace_mlx5e_configure_flower(f);
4009         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4010         if (err)
4011                 goto out;
4012
4013         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4014         if (err)
4015                 goto err_free;
4016
4017         return 0;
4018
4019 err_free:
4020         mlx5e_flow_put(priv, flow);
4021 out:
4022         return err;
4023 }
4024
4025 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4026 {
4027         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4028         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4029
4030         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4031                 flow_flag_test(flow, EGRESS) == dir_egress;
4032 }
4033
4034 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4035                         struct flow_cls_offload *f, unsigned long flags)
4036 {
4037         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4038         struct mlx5e_tc_flow *flow;
4039         int err;
4040
4041         rcu_read_lock();
4042         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4043         if (!flow || !same_flow_direction(flow, flags)) {
4044                 err = -EINVAL;
4045                 goto errout;
4046         }
4047
4048         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4049          * set.
4050          */
4051         if (flow_flag_test_and_set(flow, DELETED)) {
4052                 err = -EINVAL;
4053                 goto errout;
4054         }
4055         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4056         rcu_read_unlock();
4057
4058         trace_mlx5e_delete_flower(f);
4059         mlx5e_flow_put(priv, flow);
4060
4061         return 0;
4062
4063 errout:
4064         rcu_read_unlock();
4065         return err;
4066 }
4067
4068 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4069                        struct flow_cls_offload *f, unsigned long flags)
4070 {
4071         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4072         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4073         struct mlx5_eswitch *peer_esw;
4074         struct mlx5e_tc_flow *flow;
4075         struct mlx5_fc *counter;
4076         u64 lastuse = 0;
4077         u64 packets = 0;
4078         u64 bytes = 0;
4079         int err = 0;
4080
4081         rcu_read_lock();
4082         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4083                                                 tc_ht_params));
4084         rcu_read_unlock();
4085         if (IS_ERR(flow))
4086                 return PTR_ERR(flow);
4087
4088         if (!same_flow_direction(flow, flags)) {
4089                 err = -EINVAL;
4090                 goto errout;
4091         }
4092
4093         if (mlx5e_is_offloaded_flow(flow)) {
4094                 counter = mlx5e_tc_get_counter(flow);
4095                 if (!counter)
4096                         goto errout;
4097
4098                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4099         }
4100
4101         /* Under multipath it's possible for one rule to be currently
4102          * un-offloaded while the other rule is offloaded.
4103          */
4104         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4105         if (!peer_esw)
4106                 goto out;
4107
4108         if (flow_flag_test(flow, DUP) &&
4109             flow_flag_test(flow->peer_flow, OFFLOADED)) {
4110                 u64 bytes2;
4111                 u64 packets2;
4112                 u64 lastuse2;
4113
4114                 counter = mlx5e_tc_get_counter(flow->peer_flow);
4115                 if (!counter)
4116                         goto no_peer_counter;
4117                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4118
4119                 bytes += bytes2;
4120                 packets += packets2;
4121                 lastuse = max_t(u64, lastuse, lastuse2);
4122         }
4123
4124 no_peer_counter:
4125         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4126 out:
4127         flow_stats_update(&f->stats, bytes, packets, lastuse);
4128         trace_mlx5e_stats_flower(f);
4129 errout:
4130         mlx5e_flow_put(priv, flow);
4131         return err;
4132 }
4133
4134 static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4135                                struct netlink_ext_ack *extack)
4136 {
4137         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4138         struct mlx5_eswitch *esw;
4139         u16 vport_num;
4140         u32 rate_mbps;
4141         int err;
4142
4143         vport_num = rpriv->rep->vport;
4144         if (vport_num >= MLX5_VPORT_ECPF) {
4145                 NL_SET_ERR_MSG_MOD(extack,
4146                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4147                 return -EOPNOTSUPP;
4148         }
4149
4150         esw = priv->mdev->priv.eswitch;
4151         /* rate is given in bytes/sec.
4152          * First convert to bits/sec and then round to the nearest mbit/secs.
4153          * mbit means million bits.
4154          * Moreover, if rate is non zero we choose to configure to a minimum of
4155          * 1 mbit/sec.
4156          */
4157         rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
4158         err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4159         if (err)
4160                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4161
4162         return err;
4163 }
4164
4165 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4166                                         struct flow_action *flow_action,
4167                                         struct netlink_ext_ack *extack)
4168 {
4169         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4170         const struct flow_action_entry *act;
4171         int err;
4172         int i;
4173
4174         if (!flow_action_has_entries(flow_action)) {
4175                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4176                 return -EINVAL;
4177         }
4178
4179         if (!flow_offload_has_one_action(flow_action)) {
4180                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4181                 return -EOPNOTSUPP;
4182         }
4183
4184         if (!flow_action_basic_hw_stats_types_check(flow_action, extack))
4185                 return -EOPNOTSUPP;
4186
4187         flow_action_for_each(i, act, flow_action) {
4188                 switch (act->id) {
4189                 case FLOW_ACTION_POLICE:
4190                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4191                         if (err)
4192                                 return err;
4193
4194                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4195                         break;
4196                 default:
4197                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4198                         return -EOPNOTSUPP;
4199                 }
4200         }
4201
4202         return 0;
4203 }
4204
4205 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4206                                 struct tc_cls_matchall_offload *ma)
4207 {
4208         struct netlink_ext_ack *extack = ma->common.extack;
4209
4210         if (ma->common.prio != 1) {
4211                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4212                 return -EINVAL;
4213         }
4214
4215         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4216 }
4217
4218 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4219                              struct tc_cls_matchall_offload *ma)
4220 {
4221         struct netlink_ext_ack *extack = ma->common.extack;
4222
4223         return apply_police_params(priv, 0, extack);
4224 }
4225
4226 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4227                              struct tc_cls_matchall_offload *ma)
4228 {
4229         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4230         struct rtnl_link_stats64 cur_stats;
4231         u64 dbytes;
4232         u64 dpkts;
4233
4234         cur_stats = priv->stats.vf_vport;
4235         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4236         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4237         rpriv->prev_vf_vport_stats = cur_stats;
4238         flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4239 }
4240
4241 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4242                                               struct mlx5e_priv *peer_priv)
4243 {
4244         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4245         struct mlx5e_hairpin_entry *hpe, *tmp;
4246         LIST_HEAD(init_wait_list);
4247         u16 peer_vhca_id;
4248         int bkt;
4249
4250         if (!same_hw_devs(priv, peer_priv))
4251                 return;
4252
4253         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4254
4255         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
4256         hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4257                 if (refcount_inc_not_zero(&hpe->refcnt))
4258                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4259         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4260
4261         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4262                 wait_for_completion(&hpe->res_ready);
4263                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4264                         hpe->hp->pair->peer_gone = true;
4265
4266                 mlx5e_hairpin_put(priv, hpe);
4267         }
4268 }
4269
4270 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4271                                  unsigned long event, void *ptr)
4272 {
4273         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4274         struct mlx5e_flow_steering *fs;
4275         struct mlx5e_priv *peer_priv;
4276         struct mlx5e_tc_table *tc;
4277         struct mlx5e_priv *priv;
4278
4279         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4280             event != NETDEV_UNREGISTER ||
4281             ndev->reg_state == NETREG_REGISTERED)
4282                 return NOTIFY_DONE;
4283
4284         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4285         fs = container_of(tc, struct mlx5e_flow_steering, tc);
4286         priv = container_of(fs, struct mlx5e_priv, fs);
4287         peer_priv = netdev_priv(ndev);
4288         if (priv == peer_priv ||
4289             !(priv->netdev->features & NETIF_F_HW_TC))
4290                 return NOTIFY_DONE;
4291
4292         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4293
4294         return NOTIFY_DONE;
4295 }
4296
4297 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4298 {
4299         struct mlx5e_tc_table *tc = &priv->fs.tc;
4300         int err;
4301
4302         mutex_init(&tc->t_lock);
4303         mutex_init(&tc->mod_hdr.lock);
4304         hash_init(tc->mod_hdr.hlist);
4305         mutex_init(&tc->hairpin_tbl_lock);
4306         hash_init(tc->hairpin_tbl);
4307
4308         err = rhashtable_init(&tc->ht, &tc_ht_params);
4309         if (err)
4310                 return err;
4311
4312         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4313         err = register_netdevice_notifier_dev_net(priv->netdev,
4314                                                   &tc->netdevice_nb,
4315                                                   &tc->netdevice_nn);
4316         if (err) {
4317                 tc->netdevice_nb.notifier_call = NULL;
4318                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4319         }
4320
4321         return err;
4322 }
4323
4324 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4325 {
4326         struct mlx5e_tc_flow *flow = ptr;
4327         struct mlx5e_priv *priv = flow->priv;
4328
4329         mlx5e_tc_del_flow(priv, flow);
4330         kfree(flow);
4331 }
4332
4333 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4334 {
4335         struct mlx5e_tc_table *tc = &priv->fs.tc;
4336
4337         if (tc->netdevice_nb.notifier_call)
4338                 unregister_netdevice_notifier_dev_net(priv->netdev,
4339                                                       &tc->netdevice_nb,
4340                                                       &tc->netdevice_nn);
4341
4342         mutex_destroy(&tc->mod_hdr.lock);
4343         mutex_destroy(&tc->hairpin_tbl_lock);
4344
4345         rhashtable_destroy(&tc->ht);
4346
4347         if (!IS_ERR_OR_NULL(tc->t)) {
4348                 mlx5_destroy_flow_table(tc->t);
4349                 tc->t = NULL;
4350         }
4351         mutex_destroy(&tc->t_lock);
4352 }
4353
4354 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4355 {
4356         return rhashtable_init(tc_ht, &tc_ht_params);
4357 }
4358
4359 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4360 {
4361         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4362 }
4363
4364 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4365 {
4366         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4367
4368         return atomic_read(&tc_ht->nelems);
4369 }
4370
4371 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4372 {
4373         struct mlx5e_tc_flow *flow, *tmp;
4374
4375         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4376                 __mlx5e_tc_del_fdb_peer_flow(flow);
4377 }
4378
4379 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4380 {
4381         struct mlx5_rep_uplink_priv *rpriv =
4382                 container_of(work, struct mlx5_rep_uplink_priv,
4383                              reoffload_flows_work);
4384         struct mlx5e_tc_flow *flow, *tmp;
4385
4386         mutex_lock(&rpriv->unready_flows_lock);
4387         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4388                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4389                         unready_flow_del(flow);
4390         }
4391         mutex_unlock(&rpriv->unready_flows_lock);
4392 }