drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/sch_generic.h>
  35 #include <net/pkt_cls.h>
  36 #include <net/tc_act/tc_gact.h>
  37 #include <net/tc_act/tc_skbedit.h>
  38 #include <linux/mlx5/fs.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/rhashtable.h>
  41 #include <linux/refcount.h>
  42 #include <linux/completion.h>
  43 #include <net/tc_act/tc_mirred.h>
  44 #include <net/tc_act/tc_vlan.h>
  45 #include <net/tc_act/tc_tunnel_key.h>
  46 #include <net/tc_act/tc_pedit.h>
  47 #include <net/tc_act/tc_csum.h>
  48 #include <net/arp.h>
  49 #include <net/ipv6_stubs.h>
  50 #include "en.h"
  51 #include "en_rep.h"
  52 #include "en_tc.h"
  53 #include "eswitch.h"
  54 #include "eswitch_offloads_chains.h"
  55 #include "fs_core.h"
  56 #include "en/port.h"
  57 #include "en/tc_tun.h"
  58 #include "lib/devcom.h"
  59 #include "lib/geneve.h"
  60 #include "diag/en_tc_tracepoint.h"
  61
  62 struct mlx5_nic_flow_attr {
  63         u32 action;
  64         u32 flow_tag;
  65         struct mlx5_modify_hdr *modify_hdr;
  66         u32 hairpin_tirn;
  67         u8 match_level;
  68         struct mlx5_flow_table  *hairpin_ft;
  69         struct mlx5_fc          *counter;
  70 };
  71
  72 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
  73
  74 enum {
  75         MLX5E_TC_FLOW_FLAG_INGRESS      = MLX5E_TC_FLAG_INGRESS_BIT,
  76         MLX5E_TC_FLOW_FLAG_EGRESS       = MLX5E_TC_FLAG_EGRESS_BIT,
  77         MLX5E_TC_FLOW_FLAG_ESWITCH      = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
  78         MLX5E_TC_FLOW_FLAG_FT           = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
  79         MLX5E_TC_FLOW_FLAG_NIC          = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
  80         MLX5E_TC_FLOW_FLAG_OFFLOADED    = MLX5E_TC_FLOW_BASE,
  81         MLX5E_TC_FLOW_FLAG_HAIRPIN      = MLX5E_TC_FLOW_BASE + 1,
  82         MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS  = MLX5E_TC_FLOW_BASE + 2,
  83         MLX5E_TC_FLOW_FLAG_SLOW         = MLX5E_TC_FLOW_BASE + 3,
  84         MLX5E_TC_FLOW_FLAG_DUP          = MLX5E_TC_FLOW_BASE + 4,
  85         MLX5E_TC_FLOW_FLAG_NOT_READY    = MLX5E_TC_FLOW_BASE + 5,
  86         MLX5E_TC_FLOW_FLAG_DELETED      = MLX5E_TC_FLOW_BASE + 6,
  87 };
  88
  89 #define MLX5E_TC_MAX_SPLITS 1
  90
  91 /* Helper struct for accessing a struct containing list_head array.
  92  * Containing struct
  93  *   |- Helper array
  94  *      [0] Helper item 0
  95  *          |- list_head item 0
  96  *          |- index (0)
  97  *      [1] Helper item 1
  98  *          |- list_head item 1
  99  *          |- index (1)
 100  * To access the containing struct from one of the list_head items:
 101  * 1. Get the helper item from the list_head item using
 102  *    helper item =
 103  *        container_of(list_head item, helper struct type, list_head field)
 104  * 2. Get the contining struct from the helper item and its index in the array:
 105  *    containing struct =
 106  *        container_of(helper item, containing struct type, helper field[index])
 107  */
 108 struct encap_flow_item {
 109         struct mlx5e_encap_entry *e; /* attached encap instance */
 110         struct list_head list;
 111         int index;
 112 };
 113
 114 struct mlx5e_tc_flow {
 115         struct rhash_head       node;
 116         struct mlx5e_priv       *priv;
 117         u64                     cookie;
 118         unsigned long           flags;
 119         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
 120         /* Flow can be associated with multiple encap IDs.
 121          * The number of encaps is bounded by the number of supported
 122          * destinations.
 123          */
 124         struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
 125         struct mlx5e_tc_flow    *peer_flow;
 126         struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
 127         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
 128         struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
 129         struct list_head        hairpin; /* flows sharing the same hairpin */
 130         struct list_head        peer;    /* flows with peer flow */
 131         struct list_head        unready; /* flows not ready to be offloaded (e.g due to missing route) */
 132         int                     tmp_efi_index;
 133         struct list_head        tmp_list; /* temporary flow list used by neigh update */
 134         refcount_t              refcnt;
 135         struct rcu_head         rcu_head;
 136         struct completion       init_done;
 137         union {
 138                 struct mlx5_esw_flow_attr esw_attr[0];
 139                 struct mlx5_nic_flow_attr nic_attr[0];
 140         };
 141 };
 142
 143 struct mlx5e_tc_flow_parse_attr {
 144         const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
 145         struct net_device *filter_dev;
 146         struct mlx5_flow_spec spec;
 147         int num_mod_hdr_actions;
 148         int max_mod_hdr_actions;
 149         void *mod_hdr_actions;
 150         int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
 151 };
 152
 153 #define MLX5E_TC_TABLE_NUM_GROUPS 4
 154 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
 155
 156 struct mlx5e_hairpin {
 157         struct mlx5_hairpin *pair;
 158
 159         struct mlx5_core_dev *func_mdev;
 160         struct mlx5e_priv *func_priv;
 161         u32 tdn;
 162         u32 tirn;
 163
 164         int num_channels;
 165         struct mlx5e_rqt indir_rqt;
 166         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
 167         struct mlx5e_ttc_table ttc;
 168 };
 169
 170 struct mlx5e_hairpin_entry {
 171         /* a node of a hash table which keeps all the  hairpin entries */
 172         struct hlist_node hairpin_hlist;
 173
 174         /* protects flows list */
 175         spinlock_t flows_lock;
 176         /* flows sharing the same hairpin */
 177         struct list_head flows;
 178         /* hpe's that were not fully initialized when dead peer update event
 179          * function traversed them.
 180          */
 181         struct list_head dead_peer_wait_list;
 182
 183         u16 peer_vhca_id;
 184         u8 prio;
 185         struct mlx5e_hairpin *hp;
 186         refcount_t refcnt;
 187         struct completion res_ready;
 188 };
 189
 190 struct mod_hdr_key {
 191         int num_actions;
 192         void *actions;
 193 };
 194
 195 struct mlx5e_mod_hdr_entry {
 196         /* a node of a hash table which keeps all the mod_hdr entries */
 197         struct hlist_node mod_hdr_hlist;
 198
 199         /* protects flows list */
 200         spinlock_t flows_lock;
 201         /* flows sharing the same mod_hdr entry */
 202         struct list_head flows;
 203
 204         struct mod_hdr_key key;
 205
 206         struct mlx5_modify_hdr *modify_hdr;
 207
 208         refcount_t refcnt;
 209         struct completion res_ready;
 210         int compl_result;
 211 };
 212
 213 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
 214
 215 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 216                               struct mlx5e_tc_flow *flow);
 217
 218 static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 219 {
 220         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 221                 return ERR_PTR(-EINVAL);
 222         return flow;
 223 }
 224
 225 static void mlx5e_flow_put(struct mlx5e_priv *priv,
 226                            struct mlx5e_tc_flow *flow)
 227 {
 228         if (refcount_dec_and_test(&flow->refcnt)) {
 229                 mlx5e_tc_del_flow(priv, flow);
 230                 kfree_rcu(flow, rcu_head);
 231         }
 232 }
 233
 234 static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
 235 {
 236         /* Complete all memory stores before setting bit. */
 237         smp_mb__before_atomic();
 238         set_bit(flag, &flow->flags);
 239 }
 240
 241 #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
 242
 243 static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
 244                                      unsigned long flag)
 245 {
 246         /* test_and_set_bit() provides all necessary barriers */
 247         return test_and_set_bit(flag, &flow->flags);
 248 }
 249
 250 #define flow_flag_test_and_set(flow, flag)                      \
 251         __flow_flag_test_and_set(flow,                          \
 252                                  MLX5E_TC_FLOW_FLAG_##flag)
 253
 254 static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
 255 {
 256         /* Complete all memory stores before clearing bit. */
 257         smp_mb__before_atomic();
 258         clear_bit(flag, &flow->flags);
 259 }
 260
 261 #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
 262                                                       MLX5E_TC_FLOW_FLAG_##flag)
 263
 264 static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
 265 {
 266         bool ret = test_bit(flag, &flow->flags);
 267
 268         /* Read fields of flow structure only after checking flags. */
 269         smp_mb__after_atomic();
 270         return ret;
 271 }
 272
 273 #define flow_flag_test(flow, flag) __flow_flag_test(flow, \
 274                                                     MLX5E_TC_FLOW_FLAG_##flag)
 275
 276 static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 277 {
 278         return flow_flag_test(flow, ESWITCH);
 279 }
 280
 281 static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 282 {
 283         return flow_flag_test(flow, FT);
 284 }
 285
 286 static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 287 {
 288         return flow_flag_test(flow, OFFLOADED);
 289 }
 290
 291 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
 292 {
 293         return jhash(key->actions,
 294                      key->num_actions * MLX5_MH_ACT_SZ, 0);
 295 }
 296
 297 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
 298                                    struct mod_hdr_key *b)
 299 {
 300         if (a->num_actions != b->num_actions)
 301                 return 1;
 302
 303         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
 304 }
 305
 306 static struct mod_hdr_tbl *
 307 get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
 308 {
 309         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 310
 311         return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
 312                 &priv->fs.tc.mod_hdr;
 313 }
 314
 315 static struct mlx5e_mod_hdr_entry *
 316 mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
 317 {
 318         struct mlx5e_mod_hdr_entry *mh, *found = NULL;
 319
 320         hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
 321                 if (!cmp_mod_hdr_info(&mh->key, key)) {
 322                         refcount_inc(&mh->refcnt);
 323                         found = mh;
 324                         break;
 325                 }
 326         }
 327
 328         return found;
 329 }
 330
 331 static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
 332                               struct mlx5e_mod_hdr_entry *mh,
 333                               int namespace)
 334 {
 335         struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
 336
 337         if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
 338                 return;
 339         hash_del(&mh->mod_hdr_hlist);
 340         mutex_unlock(&tbl->lock);
 341
 342         WARN_ON(!list_empty(&mh->flows));
 343         if (mh->compl_result > 0)
 344                 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
 345
 346         kfree(mh);
 347 }
 348
 349 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
 350 {
 351         return mlx5e_is_eswitch_flow(flow) ?
 352                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 353 }
 354 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 355                                 struct mlx5e_tc_flow *flow,
 356                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 357 {
 358         int num_actions, actions_size, namespace, err;
 359         struct mlx5e_mod_hdr_entry *mh;
 360         struct mod_hdr_tbl *tbl;
 361         struct mod_hdr_key key;
 362         u32 hash_key;
 363
 364         num_actions  = parse_attr->num_mod_hdr_actions;
 365         actions_size = MLX5_MH_ACT_SZ * num_actions;
 366
 367         key.actions = parse_attr->mod_hdr_actions;
 368         key.num_actions = num_actions;
 369
 370         hash_key = hash_mod_hdr_info(&key);
 371
 372         namespace = get_flow_name_space(flow);
 373         tbl = get_mod_hdr_table(priv, namespace);
 374
 375         mutex_lock(&tbl->lock);
 376         mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
 377         if (mh) {
 378                 mutex_unlock(&tbl->lock);
 379                 wait_for_completion(&mh->res_ready);
 380
 381                 if (mh->compl_result < 0) {
 382                         err = -EREMOTEIO;
 383                         goto attach_header_err;
 384                 }
 385                 goto attach_flow;
 386         }
 387
 388         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
 389         if (!mh) {
 390                 mutex_unlock(&tbl->lock);
 391                 return -ENOMEM;
 392         }
 393
 394         mh->key.actions = (void *)mh + sizeof(*mh);
 395         memcpy(mh->key.actions, key.actions, actions_size);
 396         mh->key.num_actions = num_actions;
 397         spin_lock_init(&mh->flows_lock);
 398         INIT_LIST_HEAD(&mh->flows);
 399         refcount_set(&mh->refcnt, 1);
 400         init_completion(&mh->res_ready);
 401
 402         hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
 403         mutex_unlock(&tbl->lock);
 404
 405         mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
 406                                                   mh->key.num_actions,
 407                                                   mh->key.actions);
 408         if (IS_ERR(mh->modify_hdr)) {
 409                 err = PTR_ERR(mh->modify_hdr);
 410                 mh->compl_result = err;
 411                 goto alloc_header_err;
 412         }
 413         mh->compl_result = 1;
 414         complete_all(&mh->res_ready);
 415
 416 attach_flow:
 417         flow->mh = mh;
 418         spin_lock(&mh->flows_lock);
 419         list_add(&flow->mod_hdr, &mh->flows);
 420         spin_unlock(&mh->flows_lock);
 421         if (mlx5e_is_eswitch_flow(flow))
 422                 flow->esw_attr->modify_hdr = mh->modify_hdr;
 423         else
 424                 flow->nic_attr->modify_hdr = mh->modify_hdr;
 425
 426         return 0;
 427
 428 alloc_header_err:
 429         complete_all(&mh->res_ready);
 430 attach_header_err:
 431         mlx5e_mod_hdr_put(priv, mh, namespace);
 432         return err;
 433 }
 434
 435 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 436                                  struct mlx5e_tc_flow *flow)
 437 {
 438         /* flow wasn't fully initialized */
 439         if (!flow->mh)
 440                 return;
 441
 442         spin_lock(&flow->mh->flows_lock);
 443         list_del(&flow->mod_hdr);
 444         spin_unlock(&flow->mh->flows_lock);
 445
 446         mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
 447         flow->mh = NULL;
 448 }
 449
 450 static
 451 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 452 {
 453         struct net_device *netdev;
 454         struct mlx5e_priv *priv;
 455
 456         netdev = __dev_get_by_index(net, ifindex);
 457         priv = netdev_priv(netdev);
 458         return priv->mdev;
 459 }
 460
 461 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 462 {
 463         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 464         void *tirc;
 465         int err;
 466
 467         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 468         if (err)
 469                 goto alloc_tdn_err;
 470
 471         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 472
 473         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
 474         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
 475         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 476
 477         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
 478         if (err)
 479                 goto create_tir_err;
 480
 481         return 0;
 482
 483 create_tir_err:
 484         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 485 alloc_tdn_err:
 486         return err;
 487 }
 488
 489 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 490 {
 491         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
 492         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 493 }
 494
 495 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
 496 {
 497         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
 498         struct mlx5e_priv *priv = hp->func_priv;
 499         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
 500
 501         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
 502                                       hp->num_channels);
 503
 504         for (i = 0; i < sz; i++) {
 505                 ix = i;
 506                 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
 507                         ix = mlx5e_bits_invert(i, ilog2(sz));
 508                 ix = indirection_rqt[ix];
 509                 rqn = hp->pair->rqn[ix];
 510                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
 511         }
 512 }
 513
 514 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 515 {
 516         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
 517         struct mlx5e_priv *priv = hp->func_priv;
 518         struct mlx5_core_dev *mdev = priv->mdev;
 519         void *rqtc;
 520         u32 *in;
 521
 522         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
 523         in = kvzalloc(inlen, GFP_KERNEL);
 524         if (!in)
 525                 return -ENOMEM;
 526
 527         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 528
 529         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
 530         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
 531
 532         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
 533
 534         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
 535         if (!err)
 536                 hp->indir_rqt.enabled = true;
 537
 538         kvfree(in);
 539         return err;
 540 }
 541
 542 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 543 {
 544         struct mlx5e_priv *priv = hp->func_priv;
 545         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
 546         int tt, i, err;
 547         void *tirc;
 548
 549         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 550                 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
 551
 552                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
 553                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 554
 555                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 556                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 557                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
 558                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
 559
 560                 err = mlx5_core_create_tir(hp->func_mdev, in,
 561                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
 562                 if (err) {
 563                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 564                         goto err_destroy_tirs;
 565                 }
 566         }
 567         return 0;
 568
 569 err_destroy_tirs:
 570         for (i = 0; i < tt; i++)
 571                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
 572         return err;
 573 }
 574
 575 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 576 {
 577         int tt;
 578
 579         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 580                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
 581 }
 582
 583 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 584                                          struct ttc_params *ttc_params)
 585 {
 586         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 587         int tt;
 588
 589         memset(ttc_params, 0, sizeof(*ttc_params));
 590
 591         ttc_params->any_tt_tirn = hp->tirn;
 592
 593         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 594                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
 595
 596         ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
 597         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 598         ft_attr->prio = MLX5E_TC_PRIO;
 599 }
 600
 601 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 602 {
 603         struct mlx5e_priv *priv = hp->func_priv;
 604         struct ttc_params ttc_params;
 605         int err;
 606
 607         err = mlx5e_hairpin_create_indirect_rqt(hp);
 608         if (err)
 609                 return err;
 610
 611         err = mlx5e_hairpin_create_indirect_tirs(hp);
 612         if (err)
 613                 goto err_create_indirect_tirs;
 614
 615         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 616         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
 617         if (err)
 618                 goto err_create_ttc_table;
 619
 620         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 621                    hp->num_channels, hp->ttc.ft.t->id);
 622
 623         return 0;
 624
 625 err_create_ttc_table:
 626         mlx5e_hairpin_destroy_indirect_tirs(hp);
 627 err_create_indirect_tirs:
 628         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 629
 630         return err;
 631 }
 632
 633 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 634 {
 635         struct mlx5e_priv *priv = hp->func_priv;
 636
 637         mlx5e_destroy_ttc_table(priv, &hp->ttc);
 638         mlx5e_hairpin_destroy_indirect_tirs(hp);
 639         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 640 }
 641
 642 static struct mlx5e_hairpin *
 643 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 644                      int peer_ifindex)
 645 {
 646         struct mlx5_core_dev *func_mdev, *peer_mdev;
 647         struct mlx5e_hairpin *hp;
 648         struct mlx5_hairpin *pair;
 649         int err;
 650
 651         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 652         if (!hp)
 653                 return ERR_PTR(-ENOMEM);
 654
 655         func_mdev = priv->mdev;
 656         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 657
 658         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 659         if (IS_ERR(pair)) {
 660                 err = PTR_ERR(pair);
 661                 goto create_pair_err;
 662         }
 663         hp->pair = pair;
 664         hp->func_mdev = func_mdev;
 665         hp->func_priv = priv;
 666         hp->num_channels = params->num_channels;
 667
 668         err = mlx5e_hairpin_create_transport(hp);
 669         if (err)
 670                 goto create_transport_err;
 671
 672         if (hp->num_channels > 1) {
 673                 err = mlx5e_hairpin_rss_init(hp);
 674                 if (err)
 675                         goto rss_init_err;
 676         }
 677
 678         return hp;
 679
 680 rss_init_err:
 681         mlx5e_hairpin_destroy_transport(hp);
 682 create_transport_err:
 683         mlx5_core_hairpin_destroy(hp->pair);
 684 create_pair_err:
 685         kfree(hp);
 686         return ERR_PTR(err);
 687 }
 688
 689 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 690 {
 691         if (hp->num_channels > 1)
 692                 mlx5e_hairpin_rss_cleanup(hp);
 693         mlx5e_hairpin_destroy_transport(hp);
 694         mlx5_core_hairpin_destroy(hp->pair);
 695         kvfree(hp);
 696 }
 697
 698 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 699 {
 700         return (peer_vhca_id << 16 | prio);
 701 }
 702
 703 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 704                                                      u16 peer_vhca_id, u8 prio)
 705 {
 706         struct mlx5e_hairpin_entry *hpe;
 707         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 708
 709         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
 710                                hairpin_hlist, hash_key) {
 711                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 712                         refcount_inc(&hpe->refcnt);
 713                         return hpe;
 714                 }
 715         }
 716
 717         return NULL;
 718 }
 719
 720 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 721                               struct mlx5e_hairpin_entry *hpe)
 722 {
 723         /* no more hairpin flows for us, release the hairpin pair */
 724         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
 725                 return;
 726         hash_del(&hpe->hairpin_hlist);
 727         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 728
 729         if (!IS_ERR_OR_NULL(hpe->hp)) {
 730                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 731                            dev_name(hpe->hp->pair->peer_mdev->device));
 732
 733                 mlx5e_hairpin_destroy(hpe->hp);
 734         }
 735
 736         WARN_ON(!list_empty(&hpe->flows));
 737         kfree(hpe);
 738 }
 739
 740 #define UNKNOWN_MATCH_PRIO 8
 741
 742 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 743                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 744                                   struct netlink_ext_ack *extack)
 745 {
 746         void *headers_c, *headers_v;
 747         u8 prio_val, prio_mask = 0;
 748         bool vlan_present;
 749
 750 #ifdef CONFIG_MLX5_CORE_EN_DCB
 751         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
 752                 NL_SET_ERR_MSG_MOD(extack,
 753                                    "only PCP trust state supported for hairpin");
 754                 return -EOPNOTSUPP;
 755         }
 756 #endif
 757         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
 758         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
 759
 760         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
 761         if (vlan_present) {
 762                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
 763                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
 764         }
 765
 766         if (!vlan_present || !prio_mask) {
 767                 prio_val = UNKNOWN_MATCH_PRIO;
 768         } else if (prio_mask != 0x7) {
 769                 NL_SET_ERR_MSG_MOD(extack,
 770                                    "masked priority match not supported for hairpin");
 771                 return -EOPNOTSUPP;
 772         }
 773
 774         *match_prio = prio_val;
 775         return 0;
 776 }
 777
 778 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
 779                                   struct mlx5e_tc_flow *flow,
 780                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
 781                                   struct netlink_ext_ack *extack)
 782 {
 783         int peer_ifindex = parse_attr->mirred_ifindex[0];
 784         struct mlx5_hairpin_params params;
 785         struct mlx5_core_dev *peer_mdev;
 786         struct mlx5e_hairpin_entry *hpe;
 787         struct mlx5e_hairpin *hp;
 788         u64 link_speed64;
 789         u32 link_speed;
 790         u8 match_prio;
 791         u16 peer_id;
 792         int err;
 793
 794         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 795         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
 796                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
 797                 return -EOPNOTSUPP;
 798         }
 799
 800         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
 801         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
 802                                      extack);
 803         if (err)
 804                 return err;
 805
 806         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
 807         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
 808         if (hpe) {
 809                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 810                 wait_for_completion(&hpe->res_ready);
 811
 812                 if (IS_ERR(hpe->hp)) {
 813                         err = -EREMOTEIO;
 814                         goto out_err;
 815                 }
 816                 goto attach_flow;
 817         }
 818
 819         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
 820         if (!hpe) {
 821                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 822                 return -ENOMEM;
 823         }
 824
 825         spin_lock_init(&hpe->flows_lock);
 826         INIT_LIST_HEAD(&hpe->flows);
 827         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
 828         hpe->peer_vhca_id = peer_id;
 829         hpe->prio = match_prio;
 830         refcount_set(&hpe->refcnt, 1);
 831         init_completion(&hpe->res_ready);
 832
 833         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
 834                  hash_hairpin_info(peer_id, match_prio));
 835         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 836
 837         params.log_data_size = 15;
 838         params.log_data_size = min_t(u8, params.log_data_size,
 839                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
 840         params.log_data_size = max_t(u8, params.log_data_size,
 841                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
 842
 843         params.log_num_packets = params.log_data_size -
 844                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
 845         params.log_num_packets = min_t(u8, params.log_num_packets,
 846                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
 847
 848         params.q_counter = priv->q_counter;
 849         /* set hairpin pair per each 50Gbs share of the link */
 850         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
 851         link_speed = max_t(u32, link_speed, 50000);
 852         link_speed64 = link_speed;
 853         do_div(link_speed64, 50000);
 854         params.num_channels = link_speed64;
 855
 856         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
 857         hpe->hp = hp;
 858         complete_all(&hpe->res_ready);
 859         if (IS_ERR(hp)) {
 860                 err = PTR_ERR(hp);
 861                 goto out_err;
 862         }
 863
 864         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
 865                    hp->tirn, hp->pair->rqn[0],
 866                    dev_name(hp->pair->peer_mdev->device),
 867                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
 868
 869 attach_flow:
 870         if (hpe->hp->num_channels > 1) {
 871                 flow_flag_set(flow, HAIRPIN_RSS);
 872                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
 873         } else {
 874                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
 875         }
 876
 877         flow->hpe = hpe;
 878         spin_lock(&hpe->flows_lock);
 879         list_add(&flow->hairpin, &hpe->flows);
 880         spin_unlock(&hpe->flows_lock);
 881
 882         return 0;
 883
 884 out_err:
 885         mlx5e_hairpin_put(priv, hpe);
 886         return err;
 887 }
 888
 889 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
 890                                    struct mlx5e_tc_flow *flow)
 891 {
 892         /* flow wasn't fully initialized */
 893         if (!flow->hpe)
 894                 return;
 895
 896         spin_lock(&flow->hpe->flows_lock);
 897         list_del(&flow->hairpin);
 898         spin_unlock(&flow->hpe->flows_lock);
 899
 900         mlx5e_hairpin_put(priv, flow->hpe);
 901         flow->hpe = NULL;
 902 }
 903
 904 static int
 905 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
 906                       struct mlx5e_tc_flow_parse_attr *parse_attr,
 907                       struct mlx5e_tc_flow *flow,
 908                       struct netlink_ext_ack *extack)
 909 {
 910         struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
 911         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 912         struct mlx5_core_dev *dev = priv->mdev;
 913         struct mlx5_flow_destination dest[2] = {};
 914         struct mlx5_flow_act flow_act = {
 915                 .action = attr->action,
 916                 .flags    = FLOW_ACT_NO_APPEND,
 917         };
 918         struct mlx5_fc *counter = NULL;
 919         int err, dest_ix = 0;
 920
 921         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
 922         flow_context->flow_tag = attr->flow_tag;
 923
 924         if (flow_flag_test(flow, HAIRPIN)) {
 925                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
 926                 if (err)
 927                         return err;
 928
 929                 if (flow_flag_test(flow, HAIRPIN_RSS)) {
 930                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 931                         dest[dest_ix].ft = attr->hairpin_ft;
 932                 } else {
 933                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 934                         dest[dest_ix].tir_num = attr->hairpin_tirn;
 935                 }
 936                 dest_ix++;
 937         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
 938                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 939                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
 940                 dest_ix++;
 941         }
 942
 943         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
 944                 counter = mlx5_fc_create(dev, true);
 945                 if (IS_ERR(counter))
 946                         return PTR_ERR(counter);
 947
 948                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
 949                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
 950                 dest_ix++;
 951                 attr->counter = counter;
 952         }
 953
 954         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
 955                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
 956                 flow_act.modify_hdr = attr->modify_hdr;
 957                 kfree(parse_attr->mod_hdr_actions);
 958                 if (err)
 959                         return err;
 960         }
 961
 962         mutex_lock(&priv->fs.tc.t_lock);
 963         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
 964                 struct mlx5_flow_table_attr ft_attr = {};
 965                 int tc_grp_size, tc_tbl_size, tc_num_grps;
 966                 u32 max_flow_counter;
 967
 968                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
 969                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
 970
 971                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
 972
 973                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
 974                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
 975                 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
 976
 977                 ft_attr.prio = MLX5E_TC_PRIO;
 978                 ft_attr.max_fte = tc_tbl_size;
 979                 ft_attr.level = MLX5E_TC_FT_LEVEL;
 980                 ft_attr.autogroup.max_num_groups = tc_num_grps;
 981                 priv->fs.tc.t =
 982                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
 983                                                             &ft_attr);
 984                 if (IS_ERR(priv->fs.tc.t)) {
 985                         mutex_unlock(&priv->fs.tc.t_lock);
 986                         NL_SET_ERR_MSG_MOD(extack,
 987                                            "Failed to create tc offload table\n");
 988                         netdev_err(priv->netdev,
 989                                    "Failed to create tc offload table\n");
 990                         return PTR_ERR(priv->fs.tc.t);
 991                 }
 992         }
 993
 994         if (attr->match_level != MLX5_MATCH_NONE)
 995                 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
 996
 997         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
 998                                             &flow_act, dest, dest_ix);
 999         mutex_unlock(&priv->fs.tc.t_lock);
1000
1001         return PTR_ERR_OR_ZERO(flow->rule[0]);
1002 }
1003
1004 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1005                                   struct mlx5e_tc_flow *flow)
1006 {
1007         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1008         struct mlx5_fc *counter = NULL;
1009
1010         counter = attr->counter;
1011         if (!IS_ERR_OR_NULL(flow->rule[0]))
1012                 mlx5_del_flow_rules(flow->rule[0]);
1013         mlx5_fc_destroy(priv->mdev, counter);
1014
1015         mutex_lock(&priv->fs.tc.t_lock);
1016         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1017                 mlx5_destroy_flow_table(priv->fs.tc.t);
1018                 priv->fs.tc.t = NULL;
1019         }
1020         mutex_unlock(&priv->fs.tc.t_lock);
1021
1022         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1023                 mlx5e_detach_mod_hdr(priv, flow);
1024
1025         if (flow_flag_test(flow, HAIRPIN))
1026                 mlx5e_hairpin_flow_del(priv, flow);
1027 }
1028
1029 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1030                                struct mlx5e_tc_flow *flow, int out_index);
1031
1032 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1033                               struct mlx5e_tc_flow *flow,
1034                               struct net_device *mirred_dev,
1035                               int out_index,
1036                               struct netlink_ext_ack *extack,
1037                               struct net_device **encap_dev,
1038                               bool *encap_valid);
1039
1040 static struct mlx5_flow_handle *
1041 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1042                            struct mlx5e_tc_flow *flow,
1043                            struct mlx5_flow_spec *spec,
1044                            struct mlx5_esw_flow_attr *attr)
1045 {
1046         struct mlx5_flow_handle *rule;
1047
1048         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1049         if (IS_ERR(rule))
1050                 return rule;
1051
1052         if (attr->split_count) {
1053                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1054                 if (IS_ERR(flow->rule[1])) {
1055                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1056                         return flow->rule[1];
1057                 }
1058         }
1059
1060         return rule;
1061 }
1062
1063 static void
1064 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1065                              struct mlx5e_tc_flow *flow,
1066                            struct mlx5_esw_flow_attr *attr)
1067 {
1068         flow_flag_clear(flow, OFFLOADED);
1069
1070         if (attr->split_count)
1071                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1072
1073         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1074 }
1075
1076 static struct mlx5_flow_handle *
1077 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1078                               struct mlx5e_tc_flow *flow,
1079                               struct mlx5_flow_spec *spec,
1080                               struct mlx5_esw_flow_attr *slow_attr)
1081 {
1082         struct mlx5_flow_handle *rule;
1083
1084         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1085         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1086         slow_attr->split_count = 0;
1087         slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1088
1089         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1090         if (!IS_ERR(rule))
1091                 flow_flag_set(flow, SLOW);
1092
1093         return rule;
1094 }
1095
1096 static void
1097 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1098                                   struct mlx5e_tc_flow *flow,
1099                                   struct mlx5_esw_flow_attr *slow_attr)
1100 {
1101         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1102         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1103         slow_attr->split_count = 0;
1104         slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1105         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1106         flow_flag_clear(flow, SLOW);
1107 }
1108
1109 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1110  * function.
1111  */
1112 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1113                              struct list_head *unready_flows)
1114 {
1115         flow_flag_set(flow, NOT_READY);
1116         list_add_tail(&flow->unready, unready_flows);
1117 }
1118
1119 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1120  * function.
1121  */
1122 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1123 {
1124         list_del(&flow->unready);
1125         flow_flag_clear(flow, NOT_READY);
1126 }
1127
1128 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1129 {
1130         struct mlx5_rep_uplink_priv *uplink_priv;
1131         struct mlx5e_rep_priv *rpriv;
1132         struct mlx5_eswitch *esw;
1133
1134         esw = flow->priv->mdev->priv.eswitch;
1135         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1136         uplink_priv = &rpriv->uplink_priv;
1137
1138         mutex_lock(&uplink_priv->unready_flows_lock);
1139         unready_flow_add(flow, &uplink_priv->unready_flows);
1140         mutex_unlock(&uplink_priv->unready_flows_lock);
1141 }
1142
1143 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1144 {
1145         struct mlx5_rep_uplink_priv *uplink_priv;
1146         struct mlx5e_rep_priv *rpriv;
1147         struct mlx5_eswitch *esw;
1148
1149         esw = flow->priv->mdev->priv.eswitch;
1150         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1151         uplink_priv = &rpriv->uplink_priv;
1152
1153         mutex_lock(&uplink_priv->unready_flows_lock);
1154         unready_flow_del(flow);
1155         mutex_unlock(&uplink_priv->unready_flows_lock);
1156 }
1157
1158 static int
1159 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1160                       struct mlx5e_tc_flow *flow,
1161                       struct netlink_ext_ack *extack)
1162 {
1163         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1164         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1165         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1166         struct net_device *out_dev, *encap_dev = NULL;
1167         struct mlx5_fc *counter = NULL;
1168         struct mlx5e_rep_priv *rpriv;
1169         struct mlx5e_priv *out_priv;
1170         bool encap_valid = true;
1171         u32 max_prio, max_chain;
1172         int err = 0;
1173         int out_index;
1174
1175         if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
1176                 NL_SET_ERR_MSG_MOD(extack,
1177                                    "E-switch priorities unsupported, upgrade FW");
1178                 return -EOPNOTSUPP;
1179         }
1180
1181         /* We check chain range only for tc flows.
1182          * For ft flows, we checked attr->chain was originally 0 and set it to
1183          * FDB_FT_CHAIN which is outside tc range.
1184          * See mlx5e_rep_setup_ft_cb().
1185          */
1186         max_chain = mlx5_esw_chains_get_chain_range(esw);
1187         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1188                 NL_SET_ERR_MSG_MOD(extack,
1189                                    "Requested chain is out of supported range");
1190                 return -EOPNOTSUPP;
1191         }
1192
1193         max_prio = mlx5_esw_chains_get_prio_range(esw);
1194         if (attr->prio > max_prio) {
1195                 NL_SET_ERR_MSG_MOD(extack,
1196                                    "Requested priority is out of supported range");
1197                 return -EOPNOTSUPP;
1198         }
1199
1200         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1201                 int mirred_ifindex;
1202
1203                 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1204                         continue;
1205
1206                 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1207                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1208                                              mirred_ifindex);
1209                 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1210                                          extack, &encap_dev, &encap_valid);
1211                 if (err)
1212                         return err;
1213
1214                 out_priv = netdev_priv(encap_dev);
1215                 rpriv = out_priv->ppriv;
1216                 attr->dests[out_index].rep = rpriv->rep;
1217                 attr->dests[out_index].mdev = out_priv->mdev;
1218         }
1219
1220         err = mlx5_eswitch_add_vlan_action(esw, attr);
1221         if (err)
1222                 return err;
1223
1224         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1225                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1226                 kfree(parse_attr->mod_hdr_actions);
1227                 if (err)
1228                         return err;
1229         }
1230
1231         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1232                 counter = mlx5_fc_create(attr->counter_dev, true);
1233                 if (IS_ERR(counter))
1234                         return PTR_ERR(counter);
1235
1236                 attr->counter = counter;
1237         }
1238
1239         /* we get here if one of the following takes place:
1240          * (1) there's no error
1241          * (2) there's an encap action and we don't have valid neigh
1242          */
1243         if (!encap_valid) {
1244                 /* continue with goto slow path rule instead */
1245                 struct mlx5_esw_flow_attr slow_attr;
1246
1247                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1248         } else {
1249                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1250         }
1251
1252         if (IS_ERR(flow->rule[0]))
1253                 return PTR_ERR(flow->rule[0]);
1254         else
1255                 flow_flag_set(flow, OFFLOADED);
1256
1257         return 0;
1258 }
1259
1260 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1261 {
1262         struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1263         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1264                                        spec->match_value,
1265                                        misc_parameters_3);
1266         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1267                                              headers_v,
1268                                              geneve_tlv_option_0_data);
1269
1270         return !!geneve_tlv_opt_0_data;
1271 }
1272
1273 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1274                                   struct mlx5e_tc_flow *flow)
1275 {
1276         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1277         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1278         struct mlx5_esw_flow_attr slow_attr;
1279         int out_index;
1280
1281         if (flow_flag_test(flow, NOT_READY)) {
1282                 remove_unready_flow(flow);
1283                 kvfree(attr->parse_attr);
1284                 return;
1285         }
1286
1287         if (mlx5e_is_offloaded_flow(flow)) {
1288                 if (flow_flag_test(flow, SLOW))
1289                         mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1290                 else
1291                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1292         }
1293
1294         if (mlx5_flow_has_geneve_opt(flow))
1295                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1296
1297         mlx5_eswitch_del_vlan_action(esw, attr);
1298
1299         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1300                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1301                         mlx5e_detach_encap(priv, flow, out_index);
1302                         kfree(attr->parse_attr->tun_info[out_index]);
1303                 }
1304         kvfree(attr->parse_attr);
1305
1306         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1307                 mlx5e_detach_mod_hdr(priv, flow);
1308
1309         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1310                 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1311 }
1312
1313 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1314                               struct mlx5e_encap_entry *e,
1315                               struct list_head *flow_list)
1316 {
1317         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1318         struct mlx5_esw_flow_attr slow_attr, *esw_attr;
1319         struct mlx5_flow_handle *rule;
1320         struct mlx5_flow_spec *spec;
1321         struct mlx5e_tc_flow *flow;
1322         int err;
1323
1324         e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1325                                                      e->reformat_type,
1326                                                      e->encap_size, e->encap_header,
1327                                                      MLX5_FLOW_NAMESPACE_FDB);
1328         if (IS_ERR(e->pkt_reformat)) {
1329                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1330                                PTR_ERR(e->pkt_reformat));
1331                 return;
1332         }
1333         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1334         mlx5e_rep_queue_neigh_stats_work(priv);
1335
1336         list_for_each_entry(flow, flow_list, tmp_list) {
1337                 bool all_flow_encaps_valid = true;
1338                 int i;
1339
1340                 if (!mlx5e_is_offloaded_flow(flow))
1341                         continue;
1342                 esw_attr = flow->esw_attr;
1343                 spec = &esw_attr->parse_attr->spec;
1344
1345                 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
1346                 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1347                 /* Flow can be associated with multiple encap entries.
1348                  * Before offloading the flow verify that all of them have
1349                  * a valid neighbour.
1350                  */
1351                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1352                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1353                                 continue;
1354                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1355                                 all_flow_encaps_valid = false;
1356                                 break;
1357                         }
1358                 }
1359                 /* Do not offload flows with unresolved neighbors */
1360                 if (!all_flow_encaps_valid)
1361                         continue;
1362                 /* update from slow path rule to encap rule */
1363                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1364                 if (IS_ERR(rule)) {
1365                         err = PTR_ERR(rule);
1366                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1367                                        err);
1368                         continue;
1369                 }
1370
1371                 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1372                 flow->rule[0] = rule;
1373                 /* was unset when slow path rule removed */
1374                 flow_flag_set(flow, OFFLOADED);
1375         }
1376 }
1377
1378 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1379                               struct mlx5e_encap_entry *e,
1380                               struct list_head *flow_list)
1381 {
1382         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1383         struct mlx5_esw_flow_attr slow_attr;
1384         struct mlx5_flow_handle *rule;
1385         struct mlx5_flow_spec *spec;
1386         struct mlx5e_tc_flow *flow;
1387         int err;
1388
1389         list_for_each_entry(flow, flow_list, tmp_list) {
1390                 if (!mlx5e_is_offloaded_flow(flow))
1391                         continue;
1392                 spec = &flow->esw_attr->parse_attr->spec;
1393
1394                 /* update from encap rule to slow path rule */
1395                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1396                 /* mark the flow's encap dest as non-valid */
1397                 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1398
1399                 if (IS_ERR(rule)) {
1400                         err = PTR_ERR(rule);
1401                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1402                                        err);
1403                         continue;
1404                 }
1405
1406                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1407                 flow->rule[0] = rule;
1408                 /* was unset when fast path rule removed */
1409                 flow_flag_set(flow, OFFLOADED);
1410         }
1411
1412         /* we know that the encap is valid */
1413         e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1414         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1415 }
1416
1417 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1418 {
1419         if (mlx5e_is_eswitch_flow(flow))
1420                 return flow->esw_attr->counter;
1421         else
1422                 return flow->nic_attr->counter;
1423 }
1424
1425 /* Takes reference to all flows attached to encap and adds the flows to
1426  * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1427  */
1428 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1429 {
1430         struct encap_flow_item *efi;
1431         struct mlx5e_tc_flow *flow;
1432
1433         list_for_each_entry(efi, &e->flows, list) {
1434                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1435                 if (IS_ERR(mlx5e_flow_get(flow)))
1436                         continue;
1437                 wait_for_completion(&flow->init_done);
1438
1439                 flow->tmp_efi_index = efi->index;
1440                 list_add(&flow->tmp_list, flow_list);
1441         }
1442 }
1443
1444 /* Iterate over tmp_list of flows attached to flow_list head. */
1445 void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1446 {
1447         struct mlx5e_tc_flow *flow, *tmp;
1448
1449         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1450                 mlx5e_flow_put(priv, flow);
1451 }
1452
1453 static struct mlx5e_encap_entry *
1454 mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1455                            struct mlx5e_encap_entry *e)
1456 {
1457         struct mlx5e_encap_entry *next = NULL;
1458
1459 retry:
1460         rcu_read_lock();
1461
1462         /* find encap with non-zero reference counter value */
1463         for (next = e ?
1464                      list_next_or_null_rcu(&nhe->encap_list,
1465                                            &e->encap_list,
1466                                            struct mlx5e_encap_entry,
1467                                            encap_list) :
1468                      list_first_or_null_rcu(&nhe->encap_list,
1469                                             struct mlx5e_encap_entry,
1470                                             encap_list);
1471              next;
1472              next = list_next_or_null_rcu(&nhe->encap_list,
1473                                           &next->encap_list,
1474                                           struct mlx5e_encap_entry,
1475                                           encap_list))
1476                 if (mlx5e_encap_take(next))
1477                         break;
1478
1479         rcu_read_unlock();
1480
1481         /* release starting encap */
1482         if (e)
1483                 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1484         if (!next)
1485                 return next;
1486
1487         /* wait for encap to be fully initialized */
1488         wait_for_completion(&next->res_ready);
1489         /* continue searching if encap entry is not in valid state after completion */
1490         if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1491                 e = next;
1492                 goto retry;
1493         }
1494
1495         return next;
1496 }
1497
1498 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1499 {
1500         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1501         struct mlx5e_encap_entry *e = NULL;
1502         struct mlx5e_tc_flow *flow;
1503         struct mlx5_fc *counter;
1504         struct neigh_table *tbl;
1505         bool neigh_used = false;
1506         struct neighbour *n;
1507         u64 lastuse;
1508
1509         if (m_neigh->family == AF_INET)
1510                 tbl = &arp_tbl;
1511 #if IS_ENABLED(CONFIG_IPV6)
1512         else if (m_neigh->family == AF_INET6)
1513                 tbl = ipv6_stub->nd_tbl;
1514 #endif
1515         else
1516                 return;
1517
1518         /* mlx5e_get_next_valid_encap() releases previous encap before returning
1519          * next one.
1520          */
1521         while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
1522                 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
1523                 struct encap_flow_item *efi, *tmp;
1524                 struct mlx5_eswitch *esw;
1525                 LIST_HEAD(flow_list);
1526
1527                 esw = priv->mdev->priv.eswitch;
1528                 mutex_lock(&esw->offloads.encap_tbl_lock);
1529                 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1530                         flow = container_of(efi, struct mlx5e_tc_flow,
1531                                             encaps[efi->index]);
1532                         if (IS_ERR(mlx5e_flow_get(flow)))
1533                                 continue;
1534                         list_add(&flow->tmp_list, &flow_list);
1535
1536                         if (mlx5e_is_offloaded_flow(flow)) {
1537                                 counter = mlx5e_tc_get_counter(flow);
1538                                 lastuse = mlx5_fc_query_lastuse(counter);
1539                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1540                                         neigh_used = true;
1541                                         break;
1542                                 }
1543                         }
1544                 }
1545                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1546
1547                 mlx5e_put_encap_flow_list(priv, &flow_list);
1548                 if (neigh_used) {
1549                         /* release current encap before breaking the loop */
1550                         mlx5e_encap_put(priv, e);
1551                         break;
1552                 }
1553         }
1554
1555         trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1556
1557         if (neigh_used) {
1558                 nhe->reported_lastuse = jiffies;
1559
1560                 /* find the relevant neigh according to the cached device and
1561                  * dst ip pair
1562                  */
1563                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1564                 if (!n)
1565                         return;
1566
1567                 neigh_event_send(n, NULL);
1568                 neigh_release(n);
1569         }
1570 }
1571
1572 static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1573 {
1574         WARN_ON(!list_empty(&e->flows));
1575
1576         if (e->compl_result > 0) {
1577                 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1578
1579                 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1580                         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1581         }
1582
1583         kfree(e->tun_info);
1584         kfree(e->encap_header);
1585         kfree_rcu(e, rcu);
1586 }
1587
1588 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1589 {
1590         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1591
1592         if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1593                 return;
1594         hash_del_rcu(&e->encap_hlist);
1595         mutex_unlock(&esw->offloads.encap_tbl_lock);
1596
1597         mlx5e_encap_dealloc(priv, e);
1598 }
1599
1600 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1601                                struct mlx5e_tc_flow *flow, int out_index)
1602 {
1603         struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1604         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1605
1606         /* flow wasn't fully initialized */
1607         if (!e)
1608                 return;
1609
1610         mutex_lock(&esw->offloads.encap_tbl_lock);
1611         list_del(&flow->encaps[out_index].list);
1612         flow->encaps[out_index].e = NULL;
1613         if (!refcount_dec_and_test(&e->refcnt)) {
1614                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1615                 return;
1616         }
1617         hash_del_rcu(&e->encap_hlist);
1618         mutex_unlock(&esw->offloads.encap_tbl_lock);
1619
1620         mlx5e_encap_dealloc(priv, e);
1621 }
1622
1623 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1624 {
1625         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1626
1627         if (!flow_flag_test(flow, ESWITCH) ||
1628             !flow_flag_test(flow, DUP))
1629                 return;
1630
1631         mutex_lock(&esw->offloads.peer_mutex);
1632         list_del(&flow->peer);
1633         mutex_unlock(&esw->offloads.peer_mutex);
1634
1635         flow_flag_clear(flow, DUP);
1636
1637         if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1638                 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1639                 kfree(flow->peer_flow);
1640         }
1641
1642         flow->peer_flow = NULL;
1643 }
1644
1645 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1646 {
1647         struct mlx5_core_dev *dev = flow->priv->mdev;
1648         struct mlx5_devcom *devcom = dev->priv.devcom;
1649         struct mlx5_eswitch *peer_esw;
1650
1651         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1652         if (!peer_esw)
1653                 return;
1654
1655         __mlx5e_tc_del_fdb_peer_flow(flow);
1656         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1657 }
1658
1659 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1660                               struct mlx5e_tc_flow *flow)
1661 {
1662         if (mlx5e_is_eswitch_flow(flow)) {
1663                 mlx5e_tc_del_fdb_peer_flow(flow);
1664                 mlx5e_tc_del_fdb_flow(priv, flow);
1665         } else {
1666                 mlx5e_tc_del_nic_flow(priv, flow);
1667         }
1668 }
1669
1670
1671 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1672                              struct mlx5_flow_spec *spec,
1673                              struct flow_cls_offload *f,
1674                              struct net_device *filter_dev, u8 *match_level)
1675 {
1676         struct netlink_ext_ack *extack = f->common.extack;
1677         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1678                                        outer_headers);
1679         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1680                                        outer_headers);
1681         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1682         int err;
1683
1684         err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1685                                  headers_c, headers_v, match_level);
1686         if (err) {
1687                 NL_SET_ERR_MSG_MOD(extack,
1688                                    "failed to parse tunnel attributes");
1689                 return err;
1690         }
1691
1692         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1693                 struct flow_match_control match;
1694                 u16 addr_type;
1695
1696                 flow_rule_match_enc_control(rule, &match);
1697                 addr_type = match.key->addr_type;
1698
1699                 /* For tunnel addr_type used same key id`s as for non-tunnel */
1700                 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1701                         struct flow_match_ipv4_addrs match;
1702
1703                         flow_rule_match_enc_ipv4_addrs(rule, &match);
1704                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1705                                  src_ipv4_src_ipv6.ipv4_layout.ipv4,
1706                                  ntohl(match.mask->src));
1707                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1708                                  src_ipv4_src_ipv6.ipv4_layout.ipv4,
1709                                  ntohl(match.key->src));
1710
1711                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1712                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1713                                  ntohl(match.mask->dst));
1714                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1715                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1716                                  ntohl(match.key->dst));
1717
1718                         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1719                                          ethertype);
1720                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1721                                  ETH_P_IP);
1722                 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1723                         struct flow_match_ipv6_addrs match;
1724
1725                         flow_rule_match_enc_ipv6_addrs(rule, &match);
1726                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1727                                             src_ipv4_src_ipv6.ipv6_layout.ipv6),
1728                                &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1729                                                                    ipv6));
1730                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1731                                             src_ipv4_src_ipv6.ipv6_layout.ipv6),
1732                                &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1733                                                                   ipv6));
1734
1735                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1736                                             dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1737                                &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1738                                                                    ipv6));
1739                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1740                                             dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1741                                &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1742                                                                   ipv6));
1743
1744                         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1745                                          ethertype);
1746                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1747                                  ETH_P_IPV6);
1748                 }
1749         }
1750
1751         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1752                 struct flow_match_ip match;
1753
1754                 flow_rule_match_enc_ip(rule, &match);
1755                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1756                          match.mask->tos & 0x3);
1757                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1758                          match.key->tos & 0x3);
1759
1760                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1761                          match.mask->tos >> 2);
1762                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1763                          match.key->tos  >> 2);
1764
1765                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1766                          match.mask->ttl);
1767                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1768                          match.key->ttl);
1769
1770                 if (match.mask->ttl &&
1771                     !MLX5_CAP_ESW_FLOWTABLE_FDB
1772                         (priv->mdev,
1773                          ft_field_support.outer_ipv4_ttl)) {
1774                         NL_SET_ERR_MSG_MOD(extack,
1775                                            "Matching on TTL is not supported");
1776                         return -EOPNOTSUPP;
1777                 }
1778
1779         }
1780
1781         /* Enforce DMAC when offloading incoming tunneled flows.
1782          * Flow counters require a match on the DMAC.
1783          */
1784         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1785         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1786         ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1787                                      dmac_47_16), priv->netdev->dev_addr);
1788
1789         /* let software handle IP fragments */
1790         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1791         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1792
1793         return 0;
1794 }
1795
1796 static void *get_match_headers_criteria(u32 flags,
1797                                         struct mlx5_flow_spec *spec)
1798 {
1799         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1800                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1801                              inner_headers) :
1802                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1803                              outer_headers);
1804 }
1805
1806 static void *get_match_headers_value(u32 flags,
1807                                      struct mlx5_flow_spec *spec)
1808 {
1809         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1810                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1811                              inner_headers) :
1812                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1813                              outer_headers);
1814 }
1815
1816 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1817                                    struct flow_cls_offload *f)
1818 {
1819         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1820         struct netlink_ext_ack *extack = f->common.extack;
1821         struct net_device *ingress_dev;
1822         struct flow_match_meta match;
1823
1824         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1825                 return 0;
1826
1827         flow_rule_match_meta(rule, &match);
1828         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1829                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
1830                 return -EINVAL;
1831         }
1832
1833         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1834                                          match.key->ingress_ifindex);
1835         if (!ingress_dev) {
1836                 NL_SET_ERR_MSG_MOD(extack,
1837                                    "Can't find the ingress port to match on");
1838                 return -EINVAL;
1839         }
1840
1841         if (ingress_dev != filter_dev) {
1842                 NL_SET_ERR_MSG_MOD(extack,
1843                                    "Can't match on the ingress filter port");
1844                 return -EINVAL;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static int __parse_cls_flower(struct mlx5e_priv *priv,
1851                               struct mlx5_flow_spec *spec,
1852                               struct flow_cls_offload *f,
1853                               struct net_device *filter_dev,
1854                               u8 *inner_match_level, u8 *outer_match_level)
1855 {
1856         struct netlink_ext_ack *extack = f->common.extack;
1857         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1858                                        outer_headers);
1859         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1860                                        outer_headers);
1861         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1862                                     misc_parameters);
1863         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1864                                     misc_parameters);
1865         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1866         struct flow_dissector *dissector = rule->match.dissector;
1867         u16 addr_type = 0;
1868         u8 ip_proto = 0;
1869         u8 *match_level;
1870         int err;
1871
1872         match_level = outer_match_level;
1873
1874         if (dissector->used_keys &
1875             ~(BIT(FLOW_DISSECTOR_KEY_META) |
1876               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1877               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1878               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1879               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1880               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1881               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1882               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1883               BIT(FLOW_DISSECTOR_KEY_PORTS) |
1884               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1885               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1886               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1887               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1888               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1889               BIT(FLOW_DISSECTOR_KEY_TCP) |
1890               BIT(FLOW_DISSECTOR_KEY_IP)  |
1891               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1892               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
1893                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1894                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1895                             dissector->used_keys);
1896                 return -EOPNOTSUPP;
1897         }
1898
1899         if (mlx5e_get_tc_tun(filter_dev)) {
1900                 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1901                                       outer_match_level))
1902                         return -EOPNOTSUPP;
1903
1904                 /* At this point, header pointers should point to the inner
1905                  * headers, outer header were already set by parse_tunnel_attr
1906                  */
1907                 match_level = inner_match_level;
1908                 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1909                                                        spec);
1910                 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1911                                                     spec);
1912         }
1913
1914         err = mlx5e_flower_parse_meta(filter_dev, f);
1915         if (err)
1916                 return err;
1917
1918         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1919                 struct flow_match_basic match;
1920
1921                 flow_rule_match_basic(rule, &match);
1922                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1923                          ntohs(match.mask->n_proto));
1924                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1925                          ntohs(match.key->n_proto));
1926
1927                 if (match.mask->n_proto)
1928                         *match_level = MLX5_MATCH_L2;
1929         }
1930         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1931             is_vlan_dev(filter_dev)) {
1932                 struct flow_dissector_key_vlan filter_dev_mask;
1933                 struct flow_dissector_key_vlan filter_dev_key;
1934                 struct flow_match_vlan match;
1935
1936                 if (is_vlan_dev(filter_dev)) {
1937                         match.key = &filter_dev_key;
1938                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1939                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1940                         match.key->vlan_priority = 0;
1941                         match.mask = &filter_dev_mask;
1942                         memset(match.mask, 0xff, sizeof(*match.mask));
1943                         match.mask->vlan_priority = 0;
1944                 } else {
1945                         flow_rule_match_vlan(rule, &match);
1946                 }
1947                 if (match.mask->vlan_id ||
1948                     match.mask->vlan_priority ||
1949                     match.mask->vlan_tpid) {
1950                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1951                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1952                                          svlan_tag, 1);
1953                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1954                                          svlan_tag, 1);
1955                         } else {
1956                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1957                                          cvlan_tag, 1);
1958                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1959                                          cvlan_tag, 1);
1960                         }
1961
1962                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1963                                  match.mask->vlan_id);
1964                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1965                                  match.key->vlan_id);
1966
1967                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1968                                  match.mask->vlan_priority);
1969                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1970                                  match.key->vlan_priority);
1971
1972                         *match_level = MLX5_MATCH_L2;
1973                 }
1974         } else if (*match_level != MLX5_MATCH_NONE) {
1975                 /* cvlan_tag enabled in match criteria and
1976                  * disabled in match value means both S & C tags
1977                  * don't exist (untagged of both)
1978                  */
1979                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1980                 *match_level = MLX5_MATCH_L2;
1981         }
1982
1983         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1984                 struct flow_match_vlan match;
1985
1986                 flow_rule_match_cvlan(rule, &match);
1987                 if (match.mask->vlan_id ||
1988                     match.mask->vlan_priority ||
1989                     match.mask->vlan_tpid) {
1990                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1991                                 MLX5_SET(fte_match_set_misc, misc_c,
1992                                          outer_second_svlan_tag, 1);
1993                                 MLX5_SET(fte_match_set_misc, misc_v,
1994                                          outer_second_svlan_tag, 1);
1995                         } else {
1996                                 MLX5_SET(fte_match_set_misc, misc_c,
1997                                          outer_second_cvlan_tag, 1);
1998                                 MLX5_SET(fte_match_set_misc, misc_v,
1999                                          outer_second_cvlan_tag, 1);
2000                         }
2001
2002                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2003                                  match.mask->vlan_id);
2004                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2005                                  match.key->vlan_id);
2006                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2007                                  match.mask->vlan_priority);
2008                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2009                                  match.key->vlan_priority);
2010
2011                         *match_level = MLX5_MATCH_L2;
2012                 }
2013         }
2014
2015         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2016                 struct flow_match_eth_addrs match;
2017
2018                 flow_rule_match_eth_addrs(rule, &match);
2019                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2020                                              dmac_47_16),
2021                                 match.mask->dst);
2022                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2023                                              dmac_47_16),
2024                                 match.key->dst);
2025
2026                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2027                                              smac_47_16),
2028                                 match.mask->src);
2029                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2030                                              smac_47_16),
2031                                 match.key->src);
2032
2033                 if (!is_zero_ether_addr(match.mask->src) ||
2034                     !is_zero_ether_addr(match.mask->dst))
2035                         *match_level = MLX5_MATCH_L2;
2036         }
2037
2038         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2039                 struct flow_match_control match;
2040
2041                 flow_rule_match_control(rule, &match);
2042                 addr_type = match.key->addr_type;
2043
2044                 /* the HW doesn't support frag first/later */
2045                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
2046                         return -EOPNOTSUPP;
2047
2048                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2049                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2050                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2051                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2052
2053                         /* the HW doesn't need L3 inline to match on frag=no */
2054                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2055                                 *match_level = MLX5_MATCH_L2;
2056         /* ***  L2 attributes parsing up to here *** */
2057                         else
2058                                 *match_level = MLX5_MATCH_L3;
2059                 }
2060         }
2061
2062         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2063                 struct flow_match_basic match;
2064
2065                 flow_rule_match_basic(rule, &match);
2066                 ip_proto = match.key->ip_proto;
2067
2068                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2069                          match.mask->ip_proto);
2070                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2071                          match.key->ip_proto);
2072
2073                 if (match.mask->ip_proto)
2074                         *match_level = MLX5_MATCH_L3;
2075         }
2076
2077         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2078                 struct flow_match_ipv4_addrs match;
2079
2080                 flow_rule_match_ipv4_addrs(rule, &match);
2081                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2082                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2083                        &match.mask->src, sizeof(match.mask->src));
2084                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2085                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2086                        &match.key->src, sizeof(match.key->src));
2087                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2088                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2089                        &match.mask->dst, sizeof(match.mask->dst));
2090                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2091                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2092                        &match.key->dst, sizeof(match.key->dst));
2093
2094                 if (match.mask->src || match.mask->dst)
2095                         *match_level = MLX5_MATCH_L3;
2096         }
2097
2098         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2099                 struct flow_match_ipv6_addrs match;
2100
2101                 flow_rule_match_ipv6_addrs(rule, &match);
2102                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2103                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2104                        &match.mask->src, sizeof(match.mask->src));
2105                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2106                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2107                        &match.key->src, sizeof(match.key->src));
2108
2109                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2110                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2111                        &match.mask->dst, sizeof(match.mask->dst));
2112                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2113                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2114                        &match.key->dst, sizeof(match.key->dst));
2115
2116                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2117                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2118                         *match_level = MLX5_MATCH_L3;
2119         }
2120
2121         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2122                 struct flow_match_ip match;
2123
2124                 flow_rule_match_ip(rule, &match);
2125                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2126                          match.mask->tos & 0x3);
2127                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2128                          match.key->tos & 0x3);
2129
2130                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2131                          match.mask->tos >> 2);
2132                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2133                          match.key->tos  >> 2);
2134
2135                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2136                          match.mask->ttl);
2137                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2138                          match.key->ttl);
2139
2140                 if (match.mask->ttl &&
2141                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2142                                                 ft_field_support.outer_ipv4_ttl)) {
2143                         NL_SET_ERR_MSG_MOD(extack,
2144                                            "Matching on TTL is not supported");
2145                         return -EOPNOTSUPP;
2146                 }
2147
2148                 if (match.mask->tos || match.mask->ttl)
2149                         *match_level = MLX5_MATCH_L3;
2150         }
2151
2152         /* ***  L3 attributes parsing up to here *** */
2153
2154         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2155                 struct flow_match_ports match;
2156
2157                 flow_rule_match_ports(rule, &match);
2158                 switch (ip_proto) {
2159                 case IPPROTO_TCP:
2160                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2161                                  tcp_sport, ntohs(match.mask->src));
2162                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2163                                  tcp_sport, ntohs(match.key->src));
2164
2165                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2166                                  tcp_dport, ntohs(match.mask->dst));
2167                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2168                                  tcp_dport, ntohs(match.key->dst));
2169                         break;
2170
2171                 case IPPROTO_UDP:
2172                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2173                                  udp_sport, ntohs(match.mask->src));
2174                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2175                                  udp_sport, ntohs(match.key->src));
2176
2177                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2178                                  udp_dport, ntohs(match.mask->dst));
2179                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2180                                  udp_dport, ntohs(match.key->dst));
2181                         break;
2182                 default:
2183                         NL_SET_ERR_MSG_MOD(extack,
2184                                            "Only UDP and TCP transports are supported for L4 matching");
2185                         netdev_err(priv->netdev,
2186                                    "Only UDP and TCP transport are supported\n");
2187                         return -EINVAL;
2188                 }
2189
2190                 if (match.mask->src || match.mask->dst)
2191                         *match_level = MLX5_MATCH_L4;
2192         }
2193
2194         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2195                 struct flow_match_tcp match;
2196
2197                 flow_rule_match_tcp(rule, &match);
2198                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2199                          ntohs(match.mask->flags));
2200                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2201                          ntohs(match.key->flags));
2202
2203                 if (match.mask->flags)
2204                         *match_level = MLX5_MATCH_L4;
2205         }
2206
2207         return 0;
2208 }
2209
2210 static int parse_cls_flower(struct mlx5e_priv *priv,
2211                             struct mlx5e_tc_flow *flow,
2212                             struct mlx5_flow_spec *spec,
2213                             struct flow_cls_offload *f,
2214                             struct net_device *filter_dev)
2215 {
2216         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2217         struct netlink_ext_ack *extack = f->common.extack;
2218         struct mlx5_core_dev *dev = priv->mdev;
2219         struct mlx5_eswitch *esw = dev->priv.eswitch;
2220         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2221         struct mlx5_eswitch_rep *rep;
2222         bool is_eswitch_flow;
2223         int err;
2224
2225         inner_match_level = MLX5_MATCH_NONE;
2226         outer_match_level = MLX5_MATCH_NONE;
2227
2228         err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2229                                  &outer_match_level);
2230         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2231                                  outer_match_level : inner_match_level;
2232
2233         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2234         if (!err && is_eswitch_flow) {
2235                 rep = rpriv->rep;
2236                 if (rep->vport != MLX5_VPORT_UPLINK &&
2237                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2238                     esw->offloads.inline_mode < non_tunnel_match_level)) {
2239                         NL_SET_ERR_MSG_MOD(extack,
2240                                            "Flow is not offloaded due to min inline setting");
2241                         netdev_warn(priv->netdev,
2242                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2243                                     non_tunnel_match_level, esw->offloads.inline_mode);
2244                         return -EOPNOTSUPP;
2245                 }
2246         }
2247
2248         if (is_eswitch_flow) {
2249                 flow->esw_attr->inner_match_level = inner_match_level;
2250                 flow->esw_attr->outer_match_level = outer_match_level;
2251         } else {
2252                 flow->nic_attr->match_level = non_tunnel_match_level;
2253         }
2254
2255         return err;
2256 }
2257
2258 struct pedit_headers {
2259         struct ethhdr  eth;
2260         struct vlan_hdr vlan;
2261         struct iphdr   ip4;
2262         struct ipv6hdr ip6;
2263         struct tcphdr  tcp;
2264         struct udphdr  udp;
2265 };
2266
2267 struct pedit_headers_action {
2268         struct pedit_headers    vals;
2269         struct pedit_headers    masks;
2270         u32                     pedits;
2271 };
2272
2273 static int pedit_header_offsets[] = {
2274         [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2275         [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2276         [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2277         [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2278         [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2279 };
2280
2281 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2282
2283 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2284                          struct pedit_headers_action *hdrs)
2285 {
2286         u32 *curr_pmask, *curr_pval;
2287
2288         curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2289         curr_pval  = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2290
2291         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
2292                 goto out_err;
2293
2294         *curr_pmask |= mask;
2295         *curr_pval  |= (val & mask);
2296
2297         return 0;
2298
2299 out_err:
2300         return -EOPNOTSUPP;
2301 }
2302
2303 struct mlx5_fields {
2304         u8  field;
2305         u8  field_bsize;
2306         u32 field_mask;
2307         u32 offset;
2308         u32 match_offset;
2309 };
2310
2311 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2312                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
2313                  offsetof(struct pedit_headers, field) + (off), \
2314                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2315
2316 /* masked values are the same and there are no rewrites that do not have a
2317  * match.
2318  */
2319 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2320         type matchmaskx = *(type *)(matchmaskp); \
2321         type matchvalx = *(type *)(matchvalp); \
2322         type maskx = *(type *)(maskp); \
2323         type valx = *(type *)(valp); \
2324         \
2325         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2326                                                                  matchmaskx)); \
2327 })
2328
2329 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2330                          void *matchmaskp, u8 bsize)
2331 {
2332         bool same = false;
2333
2334         switch (bsize) {
2335         case 8:
2336                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2337                 break;
2338         case 16:
2339                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2340                 break;
2341         case 32:
2342                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2343                 break;
2344         }
2345
2346         return same;
2347 }
2348
2349 static struct mlx5_fields fields[] = {
2350         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2351         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2352         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2353         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2354         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
2355         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2356
2357         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
2358         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
2359         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2360         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2361
2362         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
2363                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2364         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
2365                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2366         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
2367                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2368         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
2369                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2370         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
2371                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2372         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
2373                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2374         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
2375                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2376         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
2377                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2378         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
2379
2380         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
2381         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
2382         /* in linux iphdr tcp_flags is 8 bits long */
2383         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
2384
2385         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2386         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
2387 };
2388
2389 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2390  * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2391  * says how many HW actions were actually parsed.
2392  */
2393 static int offload_pedit_fields(struct pedit_headers_action *hdrs,
2394                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2395                                 u32 *action_flags,
2396                                 struct netlink_ext_ack *extack)
2397 {
2398         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2399         int i, action_size, nactions, max_actions, first, last, next_z;
2400         void *headers_c, *headers_v, *action, *vals_p;
2401         u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
2402         struct mlx5_fields *f;
2403         unsigned long mask;
2404         __be32 mask_be32;
2405         __be16 mask_be16;
2406         u8 cmd;
2407
2408         headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2409         headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
2410
2411         set_masks = &hdrs[0].masks;
2412         add_masks = &hdrs[1].masks;
2413         set_vals = &hdrs[0].vals;
2414         add_vals = &hdrs[1].vals;
2415
2416         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2417         action = parse_attr->mod_hdr_actions +
2418                  parse_attr->num_mod_hdr_actions * action_size;
2419
2420         max_actions = parse_attr->max_mod_hdr_actions;
2421         nactions = parse_attr->num_mod_hdr_actions;
2422
2423         for (i = 0; i < ARRAY_SIZE(fields); i++) {
2424                 bool skip;
2425
2426                 f = &fields[i];
2427                 /* avoid seeing bits set from previous iterations */
2428                 s_mask = 0;
2429                 a_mask = 0;
2430
2431                 s_masks_p = (void *)set_masks + f->offset;
2432                 a_masks_p = (void *)add_masks + f->offset;
2433
2434                 s_mask = *s_masks_p & f->field_mask;
2435                 a_mask = *a_masks_p & f->field_mask;
2436
2437                 if (!s_mask && !a_mask) /* nothing to offload here */
2438                         continue;
2439
2440                 if (s_mask && a_mask) {
2441                         NL_SET_ERR_MSG_MOD(extack,
2442                                            "can't set and add to the same HW field");
2443                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2444                         return -EOPNOTSUPP;
2445                 }
2446
2447                 if (nactions == max_actions) {
2448                         NL_SET_ERR_MSG_MOD(extack,
2449                                            "too many pedit actions, can't offload");
2450                         printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2451                         return -EOPNOTSUPP;
2452                 }
2453
2454                 skip = false;
2455                 if (s_mask) {
2456                         void *match_mask = headers_c + f->match_offset;
2457                         void *match_val = headers_v + f->match_offset;
2458
2459                         cmd  = MLX5_ACTION_TYPE_SET;
2460                         mask = s_mask;
2461                         vals_p = (void *)set_vals + f->offset;
2462                         /* don't rewrite if we have a match on the same value */
2463                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
2464                                          match_mask, f->field_bsize))
2465                                 skip = true;
2466                         /* clear to denote we consumed this field */
2467                         *s_masks_p &= ~f->field_mask;
2468                 } else {
2469                         cmd  = MLX5_ACTION_TYPE_ADD;
2470                         mask = a_mask;
2471                         vals_p = (void *)add_vals + f->offset;
2472                         /* add 0 is no change */
2473                         if ((*(u32 *)vals_p & f->field_mask) == 0)
2474                                 skip = true;
2475                         /* clear to denote we consumed this field */
2476                         *a_masks_p &= ~f->field_mask;
2477                 }
2478                 if (skip)
2479                         continue;
2480
2481                 if (f->field_bsize == 32) {
2482                         mask_be32 = *(__be32 *)&mask;
2483                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2484                 } else if (f->field_bsize == 16) {
2485                         mask_be16 = *(__be16 *)&mask;
2486                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2487                 }
2488
2489                 first = find_first_bit(&mask, f->field_bsize);
2490                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2491                 last  = find_last_bit(&mask, f->field_bsize);
2492                 if (first < next_z && next_z < last) {
2493                         NL_SET_ERR_MSG_MOD(extack,
2494                                            "rewrite of few sub-fields isn't supported");
2495                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2496                                mask);
2497                         return -EOPNOTSUPP;
2498                 }
2499
2500                 MLX5_SET(set_action_in, action, action_type, cmd);
2501                 MLX5_SET(set_action_in, action, field, f->field);
2502
2503                 if (cmd == MLX5_ACTION_TYPE_SET) {
2504                         int start;
2505
2506                         /* if field is bit sized it can start not from first bit */
2507                         start = find_first_bit((unsigned long *)&f->field_mask,
2508                                                f->field_bsize);
2509
2510                         MLX5_SET(set_action_in, action, offset, first - start);
2511                         /* length is num of bits to be written, zero means length of 32 */
2512                         MLX5_SET(set_action_in, action, length, (last - first + 1));
2513                 }
2514
2515                 if (f->field_bsize == 32)
2516                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2517                 else if (f->field_bsize == 16)
2518                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2519                 else if (f->field_bsize == 8)
2520                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2521
2522                 action += action_size;
2523                 nactions++;
2524         }
2525
2526         parse_attr->num_mod_hdr_actions = nactions;
2527         return 0;
2528 }
2529
2530 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2531                                                   int namespace)
2532 {
2533         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2534                 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2535         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2536                 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2537 }
2538
2539 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2540                                  struct pedit_headers_action *hdrs,
2541                                  int namespace,
2542                                  struct mlx5e_tc_flow_parse_attr *parse_attr)
2543 {
2544         int nkeys, action_size, max_actions;
2545
2546         nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2547                 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
2548         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2549
2550         max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
2551         /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2552         max_actions = min(max_actions, nkeys * 16);
2553
2554         parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2555         if (!parse_attr->mod_hdr_actions)
2556                 return -ENOMEM;
2557
2558         parse_attr->max_mod_hdr_actions = max_actions;
2559         return 0;
2560 }
2561
2562 static const struct pedit_headers zero_masks = {};
2563
2564 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2565                                  const struct flow_action_entry *act, int namespace,
2566                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2567                                  struct pedit_headers_action *hdrs,
2568                                  struct netlink_ext_ack *extack)
2569 {
2570         u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2571         int err = -EOPNOTSUPP;
2572         u32 mask, val, offset;
2573         u8 htype;
2574
2575         htype = act->mangle.htype;
2576         err = -EOPNOTSUPP; /* can't be all optimistic */
2577
2578         if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2579                 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2580                 goto out_err;
2581         }
2582
2583         if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2584                 NL_SET_ERR_MSG_MOD(extack,
2585                                    "The pedit offload action is not supported");
2586                 goto out_err;
2587         }
2588
2589         mask = act->mangle.mask;
2590         val = act->mangle.val;
2591         offset = act->mangle.offset;
2592
2593         err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2594         if (err)
2595                 goto out_err;
2596
2597         hdrs[cmd].pedits++;
2598
2599         return 0;
2600 out_err:
2601         return err;
2602 }
2603
2604 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2605                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2606                                  struct pedit_headers_action *hdrs,
2607                                  u32 *action_flags,
2608                                  struct netlink_ext_ack *extack)
2609 {
2610         struct pedit_headers *cmd_masks;
2611         int err;
2612         u8 cmd;
2613
2614         if (!parse_attr->mod_hdr_actions) {
2615                 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
2616                 if (err)
2617                         goto out_err;
2618         }
2619
2620         err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
2621         if (err < 0)
2622                 goto out_dealloc_parsed_actions;
2623
2624         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2625                 cmd_masks = &hdrs[cmd].masks;
2626                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2627                         NL_SET_ERR_MSG_MOD(extack,
2628                                            "attempt to offload an unsupported field");
2629                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2630                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2631                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2632                         err = -EOPNOTSUPP;
2633                         goto out_dealloc_parsed_actions;
2634                 }
2635         }
2636
2637         return 0;
2638
2639 out_dealloc_parsed_actions:
2640         kfree(parse_attr->mod_hdr_actions);
2641 out_err:
2642         return err;
2643 }
2644
2645 static bool csum_offload_supported(struct mlx5e_priv *priv,
2646                                    u32 action,
2647                                    u32 update_flags,
2648                                    struct netlink_ext_ack *extack)
2649 {
2650         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2651                          TCA_CSUM_UPDATE_FLAG_UDP;
2652
2653         /*  The HW recalcs checksums only if re-writing headers */
2654         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2655                 NL_SET_ERR_MSG_MOD(extack,
2656                                    "TC csum action is only offloaded with pedit");
2657                 netdev_warn(priv->netdev,
2658                             "TC csum action is only offloaded with pedit\n");
2659                 return false;
2660         }
2661
2662         if (update_flags & ~prot_flags) {
2663                 NL_SET_ERR_MSG_MOD(extack,
2664                                    "can't offload TC csum action for some header/s");
2665                 netdev_warn(priv->netdev,
2666                             "can't offload TC csum action for some header/s - flags %#x\n",
2667                             update_flags);
2668                 return false;
2669         }
2670
2671         return true;
2672 }
2673
2674 struct ip_ttl_word {
2675         __u8    ttl;
2676         __u8    protocol;
2677         __sum16 check;
2678 };
2679
2680 struct ipv6_hoplimit_word {
2681         __be16  payload_len;
2682         __u8    nexthdr;
2683         __u8    hop_limit;
2684 };
2685
2686 static bool is_action_keys_supported(const struct flow_action_entry *act)
2687 {
2688         u32 mask, offset;
2689         u8 htype;
2690
2691         htype = act->mangle.htype;
2692         offset = act->mangle.offset;
2693         mask = ~act->mangle.mask;
2694         /* For IPv4 & IPv6 header check 4 byte word,
2695          * to determine that modified fields
2696          * are NOT ttl & hop_limit only.
2697          */
2698         if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2699                 struct ip_ttl_word *ttl_word =
2700                         (struct ip_ttl_word *)&mask;
2701
2702                 if (offset != offsetof(struct iphdr, ttl) ||
2703                     ttl_word->protocol ||
2704                     ttl_word->check) {
2705                         return true;
2706                 }
2707         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2708                 struct ipv6_hoplimit_word *hoplimit_word =
2709                         (struct ipv6_hoplimit_word *)&mask;
2710
2711                 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2712                     hoplimit_word->payload_len ||
2713                     hoplimit_word->nexthdr) {
2714                         return true;
2715                 }
2716         }
2717         return false;
2718 }
2719
2720 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2721                                           struct flow_action *flow_action,
2722                                           u32 actions,
2723                                           struct netlink_ext_ack *extack)
2724 {
2725         const struct flow_action_entry *act;
2726         bool modify_ip_header;
2727         void *headers_v;
2728         u16 ethertype;
2729         u8 ip_proto;
2730         int i;
2731
2732         headers_v = get_match_headers_value(actions, spec);
2733         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2734
2735         /* for non-IP we only re-write MACs, so we're okay */
2736         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2737                 goto out_ok;
2738
2739         modify_ip_header = false;
2740         flow_action_for_each(i, act, flow_action) {
2741                 if (act->id != FLOW_ACTION_MANGLE &&
2742                     act->id != FLOW_ACTION_ADD)
2743                         continue;
2744
2745                 if (is_action_keys_supported(act)) {
2746                         modify_ip_header = true;
2747                         break;
2748                 }
2749         }
2750
2751         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2752         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2753             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2754                 NL_SET_ERR_MSG_MOD(extack,
2755                                    "can't offload re-write of non TCP/UDP");
2756                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2757                 return false;
2758         }
2759
2760 out_ok:
2761         return true;
2762 }
2763
2764 static bool actions_match_supported(struct mlx5e_priv *priv,
2765                                     struct flow_action *flow_action,
2766                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
2767                                     struct mlx5e_tc_flow *flow,
2768                                     struct netlink_ext_ack *extack)
2769 {
2770         u32 actions;
2771
2772         if (mlx5e_is_eswitch_flow(flow))
2773                 actions = flow->esw_attr->action;
2774         else
2775                 actions = flow->nic_attr->action;
2776
2777         if (flow_flag_test(flow, EGRESS) &&
2778             !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2779               (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2780               (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
2781                 return false;
2782
2783         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2784                 return modify_header_match_supported(&parse_attr->spec,
2785                                                      flow_action, actions,
2786                                                      extack);
2787
2788         return true;
2789 }
2790
2791 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2792 {
2793         struct mlx5_core_dev *fmdev, *pmdev;
2794         u64 fsystem_guid, psystem_guid;
2795
2796         fmdev = priv->mdev;
2797         pmdev = peer_priv->mdev;
2798
2799         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2800         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2801
2802         return (fsystem_guid == psystem_guid);
2803 }
2804
2805 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2806                                    const struct flow_action_entry *act,
2807                                    struct mlx5e_tc_flow_parse_attr *parse_attr,
2808                                    struct pedit_headers_action *hdrs,
2809                                    u32 *action, struct netlink_ext_ack *extack)
2810 {
2811         u16 mask16 = VLAN_VID_MASK;
2812         u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2813         const struct flow_action_entry pedit_act = {
2814                 .id = FLOW_ACTION_MANGLE,
2815                 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2816                 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2817                 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2818                 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2819         };
2820         u8 match_prio_mask, match_prio_val;
2821         void *headers_c, *headers_v;
2822         int err;
2823
2824         headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2825         headers_v = get_match_headers_value(*action, &parse_attr->spec);
2826
2827         if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2828               MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2829                 NL_SET_ERR_MSG_MOD(extack,
2830                                    "VLAN rewrite action must have VLAN protocol match");
2831                 return -EOPNOTSUPP;
2832         }
2833
2834         match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2835         match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2836         if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2837                 NL_SET_ERR_MSG_MOD(extack,
2838                                    "Changing VLAN prio is not supported");
2839                 return -EOPNOTSUPP;
2840         }
2841
2842         err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2843                                     hdrs, NULL);
2844         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2845
2846         return err;
2847 }
2848
2849 static int
2850 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2851                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2852                                  struct pedit_headers_action *hdrs,
2853                                  u32 *action, struct netlink_ext_ack *extack)
2854 {
2855         const struct flow_action_entry prio_tag_act = {
2856                 .vlan.vid = 0,
2857                 .vlan.prio =
2858                         MLX5_GET(fte_match_set_lyr_2_4,
2859                                  get_match_headers_value(*action,
2860                                                          &parse_attr->spec),
2861                                  first_prio) &
2862                         MLX5_GET(fte_match_set_lyr_2_4,
2863                                  get_match_headers_criteria(*action,
2864                                                             &parse_attr->spec),
2865                                  first_prio),
2866         };
2867
2868         return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2869                                        &prio_tag_act, parse_attr, hdrs, action,
2870                                        extack);
2871 }
2872
2873 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2874                                 struct flow_action *flow_action,
2875                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2876                                 struct mlx5e_tc_flow *flow,
2877                                 struct netlink_ext_ack *extack)
2878 {
2879         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2880         struct pedit_headers_action hdrs[2] = {};
2881         const struct flow_action_entry *act;
2882         u32 action = 0;
2883         int err, i;
2884
2885         if (!flow_action_has_entries(flow_action))
2886                 return -EINVAL;
2887
2888         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2889
2890         flow_action_for_each(i, act, flow_action) {
2891                 switch (act->id) {
2892                 case FLOW_ACTION_ACCEPT:
2893                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2894                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
2895                         break;
2896                 case FLOW_ACTION_DROP:
2897                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2898                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
2899                                                flow_table_properties_nic_receive.flow_counter))
2900                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2901                         break;
2902                 case FLOW_ACTION_MANGLE:
2903                 case FLOW_ACTION_ADD:
2904                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
2905                                                     parse_attr, hdrs, extack);
2906                         if (err)
2907                                 return err;
2908
2909                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2910                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2911                         break;
2912                 case FLOW_ACTION_VLAN_MANGLE:
2913                         err = add_vlan_rewrite_action(priv,
2914                                                       MLX5_FLOW_NAMESPACE_KERNEL,
2915                                                       act, parse_attr, hdrs,
2916                                                       &action, extack);
2917                         if (err)
2918                                 return err;
2919
2920                         break;
2921                 case FLOW_ACTION_CSUM:
2922                         if (csum_offload_supported(priv, action,
2923                                                    act->csum_flags,
2924                                                    extack))
2925                                 break;
2926
2927                         return -EOPNOTSUPP;
2928                 case FLOW_ACTION_REDIRECT: {
2929                         struct net_device *peer_dev = act->dev;
2930
2931                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2932                             same_hw_devs(priv, netdev_priv(peer_dev))) {
2933                                 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
2934                                 flow_flag_set(flow, HAIRPIN);
2935                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2936                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
2937                         } else {
2938                                 NL_SET_ERR_MSG_MOD(extack,
2939                                                    "device is not on same HW, can't offload");
2940                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2941                                             peer_dev->name);
2942                                 return -EINVAL;
2943                         }
2944                         }
2945                         break;
2946                 case FLOW_ACTION_MARK: {
2947                         u32 mark = act->mark;
2948
2949                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2950                                 NL_SET_ERR_MSG_MOD(extack,
2951                                                    "Bad flow mark - only 16 bit is supported");
2952                                 return -EINVAL;
2953                         }
2954
2955                         attr->flow_tag = mark;
2956                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2957                         }
2958                         break;
2959                 default:
2960                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2961                         return -EOPNOTSUPP;
2962                 }
2963         }
2964
2965         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2966             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2967                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2968                                             parse_attr, hdrs, &action, extack);
2969                 if (err)
2970                         return err;
2971                 /* in case all pedit actions are skipped, remove the MOD_HDR
2972                  * flag.
2973                  */
2974                 if (parse_attr->num_mod_hdr_actions == 0) {
2975                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2976                         kfree(parse_attr->mod_hdr_actions);
2977                 }
2978         }
2979
2980         attr->action = action;
2981         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2982                 return -EOPNOTSUPP;
2983
2984         return 0;
2985 }
2986
2987 struct encap_key {
2988         const struct ip_tunnel_key *ip_tun_key;
2989         struct mlx5e_tc_tunnel *tc_tunnel;
2990 };
2991
2992 static inline int cmp_encap_info(struct encap_key *a,
2993                                  struct encap_key *b)
2994 {
2995         return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
2996                a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
2997 }
2998
2999 static inline int hash_encap_info(struct encap_key *key)
3000 {
3001         return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
3002                      key->tc_tunnel->tunnel_type);
3003 }
3004
3005
3006 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3007                                   struct net_device *peer_netdev)
3008 {
3009         struct mlx5e_priv *peer_priv;
3010
3011         peer_priv = netdev_priv(peer_netdev);
3012
3013         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
3014                 mlx5e_eswitch_rep(priv->netdev) &&
3015                 mlx5e_eswitch_rep(peer_netdev) &&
3016                 same_hw_devs(priv, peer_priv));
3017 }
3018
3019
3020
3021 bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3022 {
3023         return refcount_inc_not_zero(&e->refcnt);
3024 }
3025
3026 static struct mlx5e_encap_entry *
3027 mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3028                 uintptr_t hash_key)
3029 {
3030         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3031         struct mlx5e_encap_entry *e;
3032         struct encap_key e_key;
3033
3034         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3035                                    encap_hlist, hash_key) {
3036                 e_key.ip_tun_key = &e->tun_info->key;
3037                 e_key.tc_tunnel = e->tunnel;
3038                 if (!cmp_encap_info(&e_key, key) &&
3039                     mlx5e_encap_take(e))
3040                         return e;
3041         }
3042
3043         return NULL;
3044 }
3045
3046 static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3047 {
3048         size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3049
3050         return kmemdup(tun_info, tun_size, GFP_KERNEL);
3051 }
3052
3053 static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3054                                       struct mlx5e_tc_flow *flow,
3055                                       int out_index,
3056                                       struct mlx5e_encap_entry *e,
3057                                       struct netlink_ext_ack *extack)
3058 {
3059         int i;
3060
3061         for (i = 0; i < out_index; i++) {
3062                 if (flow->encaps[i].e != e)
3063                         continue;
3064                 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3065                 netdev_err(priv->netdev, "can't duplicate encap action\n");
3066                 return true;
3067         }
3068
3069         return false;
3070 }
3071
3072 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
3073                               struct mlx5e_tc_flow *flow,
3074                               struct net_device *mirred_dev,
3075                               int out_index,
3076                               struct netlink_ext_ack *extack,
3077                               struct net_device **encap_dev,
3078                               bool *encap_valid)
3079 {
3080         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3081         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3082         struct mlx5e_tc_flow_parse_attr *parse_attr;
3083         const struct ip_tunnel_info *tun_info;
3084         struct encap_key key;
3085         struct mlx5e_encap_entry *e;
3086         unsigned short family;
3087         uintptr_t hash_key;
3088         int err = 0;
3089
3090         parse_attr = attr->parse_attr;
3091         tun_info = parse_attr->tun_info[out_index];
3092         family = ip_tunnel_info_af(tun_info);
3093         key.ip_tun_key = &tun_info->key;
3094         key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
3095         if (!key.tc_tunnel) {
3096                 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3097                 return -EOPNOTSUPP;
3098         }
3099
3100         hash_key = hash_encap_info(&key);
3101
3102         mutex_lock(&esw->offloads.encap_tbl_lock);
3103         e = mlx5e_encap_get(priv, &key, hash_key);
3104
3105         /* must verify if encap is valid or not */
3106         if (e) {
3107                 /* Check that entry was not already attached to this flow */
3108                 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3109                         err = -EOPNOTSUPP;
3110                         goto out_err;
3111                 }
3112
3113                 mutex_unlock(&esw->offloads.encap_tbl_lock);
3114                 wait_for_completion(&e->res_ready);
3115
3116                 /* Protect against concurrent neigh update. */
3117                 mutex_lock(&esw->offloads.encap_tbl_lock);
3118                 if (e->compl_result < 0) {
3119                         err = -EREMOTEIO;
3120                         goto out_err;
3121                 }
3122                 goto attach_flow;
3123         }
3124
3125         e = kzalloc(sizeof(*e), GFP_KERNEL);
3126         if (!e) {
3127                 err = -ENOMEM;
3128                 goto out_err;
3129         }
3130
3131         refcount_set(&e->refcnt, 1);
3132         init_completion(&e->res_ready);
3133
3134         tun_info = dup_tun_info(tun_info);
3135         if (!tun_info) {
3136                 err = -ENOMEM;
3137                 goto out_err_init;
3138         }
3139         e->tun_info = tun_info;
3140         err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
3141         if (err)
3142                 goto out_err_init;
3143
3144         INIT_LIST_HEAD(&e->flows);
3145         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3146         mutex_unlock(&esw->offloads.encap_tbl_lock);
3147
3148         if (family == AF_INET)
3149                 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
3150         else if (family == AF_INET6)
3151                 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
3152
3153         /* Protect against concurrent neigh update. */
3154         mutex_lock(&esw->offloads.encap_tbl_lock);
3155         complete_all(&e->res_ready);
3156         if (err) {
3157                 e->compl_result = err;
3158                 goto out_err;
3159         }
3160         e->compl_result = 1;
3161
3162 attach_flow:
3163         flow->encaps[out_index].e = e;
3164         list_add(&flow->encaps[out_index].list, &e->flows);
3165         flow->encaps[out_index].index = out_index;
3166         *encap_dev = e->out_dev;
3167         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
3168                 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3169                 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
3170                 *encap_valid = true;
3171         } else {
3172                 *encap_valid = false;
3173         }
3174         mutex_unlock(&esw->offloads.encap_tbl_lock);
3175
3176         return err;
3177
3178 out_err:
3179         mutex_unlock(&esw->offloads.encap_tbl_lock);
3180         if (e)
3181                 mlx5e_encap_put(priv, e);
3182         return err;
3183
3184 out_err_init:
3185         mutex_unlock(&esw->offloads.encap_tbl_lock);
3186         kfree(tun_info);
3187         kfree(e);
3188         return err;
3189 }
3190
3191 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3192                                 const struct flow_action_entry *act,
3193                                 struct mlx5_esw_flow_attr *attr,
3194                                 u32 *action)
3195 {
3196         u8 vlan_idx = attr->total_vlan;
3197
3198         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3199                 return -EOPNOTSUPP;
3200
3201         switch (act->id) {
3202         case FLOW_ACTION_VLAN_POP:
3203                 if (vlan_idx) {
3204                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3205                                                                  MLX5_FS_VLAN_DEPTH))
3206                                 return -EOPNOTSUPP;
3207
3208                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3209                 } else {
3210                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3211                 }
3212                 break;
3213         case FLOW_ACTION_VLAN_PUSH:
3214                 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3215                 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3216                 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3217                 if (!attr->vlan_proto[vlan_idx])
3218                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3219
3220                 if (vlan_idx) {
3221                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3222                                                                  MLX5_FS_VLAN_DEPTH))
3223                                 return -EOPNOTSUPP;
3224
3225                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3226                 } else {
3227                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3228                             (act->vlan.proto != htons(ETH_P_8021Q) ||
3229                              act->vlan.prio))
3230                                 return -EOPNOTSUPP;
3231
3232                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3233                 }
3234                 break;
3235         default:
3236                 return -EINVAL;
3237         }
3238
3239         attr->total_vlan = vlan_idx + 1;
3240
3241         return 0;
3242 }
3243
3244 static int add_vlan_push_action(struct mlx5e_priv *priv,
3245                                 struct mlx5_esw_flow_attr *attr,
3246                                 struct net_device **out_dev,
3247                                 u32 *action)
3248 {
3249         struct net_device *vlan_dev = *out_dev;
3250         struct flow_action_entry vlan_act = {
3251                 .id = FLOW_ACTION_VLAN_PUSH,
3252                 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3253                 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3254                 .vlan.prio = 0,
3255         };
3256         int err;
3257
3258         err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3259         if (err)
3260                 return err;
3261
3262         *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3263                                         dev_get_iflink(vlan_dev));
3264         if (is_vlan_dev(*out_dev))
3265                 err = add_vlan_push_action(priv, attr, out_dev, action);
3266
3267         return err;
3268 }
3269
3270 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3271                                struct mlx5_esw_flow_attr *attr,
3272                                u32 *action)
3273 {
3274         int nest_level = attr->parse_attr->filter_dev->lower_level;
3275         struct flow_action_entry vlan_act = {
3276                 .id = FLOW_ACTION_VLAN_POP,
3277         };
3278         int err = 0;
3279
3280         while (nest_level--) {
3281                 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3282                 if (err)
3283                         return err;
3284         }
3285
3286         return err;
3287 }
3288
3289 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3290                                     struct net_device *out_dev)
3291 {
3292         if (is_merged_eswitch_dev(priv, out_dev))
3293                 return true;
3294
3295         return mlx5e_eswitch_rep(out_dev) &&
3296                same_hw_devs(priv, netdev_priv(out_dev));
3297 }
3298
3299 static bool is_duplicated_output_device(struct net_device *dev,
3300                                         struct net_device *out_dev,
3301                                         int *ifindexes, int if_count,
3302                                         struct netlink_ext_ack *extack)
3303 {
3304         int i;
3305
3306         for (i = 0; i < if_count; i++) {
3307                 if (ifindexes[i] == out_dev->ifindex) {
3308                         NL_SET_ERR_MSG_MOD(extack,
3309                                            "can't duplicate output to same device");
3310                         netdev_err(dev, "can't duplicate output to same device: %s\n",
3311                                    out_dev->name);
3312                         return true;
3313                 }
3314         }
3315
3316         return false;
3317 }
3318
3319 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3320                                 struct flow_action *flow_action,
3321                                 struct mlx5e_tc_flow *flow,
3322                                 struct netlink_ext_ack *extack)
3323 {
3324         struct pedit_headers_action hdrs[2] = {};
3325         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3326         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3327         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3328         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3329         const struct ip_tunnel_info *info = NULL;
3330         int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
3331         bool ft_flow = mlx5e_is_ft_flow(flow);
3332         const struct flow_action_entry *act;
3333         int err, i, if_count = 0;
3334         bool encap = false;
3335         u32 action = 0;
3336
3337         if (!flow_action_has_entries(flow_action))
3338                 return -EINVAL;
3339
3340         flow_action_for_each(i, act, flow_action) {
3341                 switch (act->id) {
3342                 case FLOW_ACTION_DROP:
3343                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3344                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3345                         break;
3346                 case FLOW_ACTION_MANGLE:
3347                 case FLOW_ACTION_ADD:
3348                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3349                                                     parse_attr, hdrs, extack);
3350                         if (err)
3351                                 return err;
3352
3353                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3354                         attr->split_count = attr->out_count;
3355                         break;
3356                 case FLOW_ACTION_CSUM:
3357                         if (csum_offload_supported(priv, action,
3358                                                    act->csum_flags, extack))
3359                                 break;
3360
3361                         return -EOPNOTSUPP;
3362                 case FLOW_ACTION_REDIRECT:
3363                 case FLOW_ACTION_MIRRED: {
3364                         struct mlx5e_priv *out_priv;
3365                         struct net_device *out_dev;
3366
3367                         out_dev = act->dev;
3368                         if (!out_dev) {
3369                                 /* out_dev is NULL when filters with
3370                                  * non-existing mirred device are replayed to
3371                                  * the driver.
3372                                  */
3373                                 return -EINVAL;
3374                         }
3375
3376                         if (ft_flow && out_dev == priv->netdev) {
3377                                 /* Ignore forward to self rules generated
3378                                  * by adding both mlx5 devs to the flow table
3379                                  * block on a normal nft offload setup.
3380                                  */
3381                                 return -EOPNOTSUPP;
3382                         }
3383
3384                         if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3385                                 NL_SET_ERR_MSG_MOD(extack,
3386                                                    "can't support more output ports, can't offload forwarding");
3387                                 netdev_warn(priv->netdev,
3388                                             "can't support more than %d output ports, can't offload forwarding\n",
3389                                             attr->out_count);
3390                                 return -EOPNOTSUPP;
3391                         }
3392
3393                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3394                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3395                         if (encap) {
3396                                 parse_attr->mirred_ifindex[attr->out_count] =
3397                                         out_dev->ifindex;
3398                                 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3399                                 if (!parse_attr->tun_info[attr->out_count])
3400                                         return -ENOMEM;
3401                                 encap = false;
3402                                 attr->dests[attr->out_count].flags |=
3403                                         MLX5_ESW_DEST_ENCAP;
3404                                 attr->out_count++;
3405                                 /* attr->dests[].rep is resolved when we
3406                                  * handle encap
3407                                  */
3408                         } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3409                                 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3410                                 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3411                                 struct net_device *uplink_upper;
3412                                 struct mlx5e_rep_priv *rep_priv;
3413
3414                                 if (is_duplicated_output_device(priv->netdev,
3415                                                                 out_dev,
3416                                                                 ifindexes,
3417                                                                 if_count,
3418                                                                 extack))
3419                                         return -EOPNOTSUPP;
3420
3421                                 ifindexes[if_count] = out_dev->ifindex;
3422                                 if_count++;
3423
3424                                 rcu_read_lock();
3425                                 uplink_upper =
3426                                         netdev_master_upper_dev_get_rcu(uplink_dev);
3427                                 if (uplink_upper &&
3428                                     netif_is_lag_master(uplink_upper) &&
3429                                     uplink_upper == out_dev)
3430                                         out_dev = uplink_dev;
3431                                 rcu_read_unlock();
3432
3433                                 if (is_vlan_dev(out_dev)) {
3434                                         err = add_vlan_push_action(priv, attr,
3435                                                                    &out_dev,
3436                                                                    &action);
3437                                         if (err)
3438                                                 return err;
3439                                 }
3440
3441                                 if (is_vlan_dev(parse_attr->filter_dev)) {
3442                                         err = add_vlan_pop_action(priv, attr,
3443                                                                   &action);
3444                                         if (err)
3445                                                 return err;
3446                                 }
3447
3448                                 /* Don't allow forwarding between uplink.
3449                                  *
3450                                  * Input vport was stored esw_attr->in_rep.
3451                                  * In LAG case, *priv* is the private data of
3452                                  * uplink which may be not the input vport.
3453                                  */
3454                                 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3455                                 if (mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3456                                     mlx5e_eswitch_uplink_rep(out_dev)) {
3457                                         NL_SET_ERR_MSG_MOD(extack,
3458                                                            "devices are both uplink, can't offload forwarding");
3459                                         pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3460                                                priv->netdev->name, out_dev->name);
3461                                         return -EOPNOTSUPP;
3462                                 }
3463
3464                                 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3465                                         NL_SET_ERR_MSG_MOD(extack,
3466                                                            "devices are not on same switch HW, can't offload forwarding");
3467                                         netdev_warn(priv->netdev,
3468                                                     "devices %s %s not on same switch HW, can't offload forwarding\n",
3469                                                     priv->netdev->name,
3470                                                     out_dev->name);
3471                                         return -EOPNOTSUPP;
3472                                 }
3473
3474                                 out_priv = netdev_priv(out_dev);
3475                                 rpriv = out_priv->ppriv;
3476                                 attr->dests[attr->out_count].rep = rpriv->rep;
3477                                 attr->dests[attr->out_count].mdev = out_priv->mdev;
3478                                 attr->out_count++;
3479                         } else if (parse_attr->filter_dev != priv->netdev) {
3480                                 /* All mlx5 devices are called to configure
3481                                  * high level device filters. Therefore, the
3482                                  * *attempt* to  install a filter on invalid
3483                                  * eswitch should not trigger an explicit error
3484                                  */
3485                                 return -EINVAL;
3486                         } else {
3487                                 NL_SET_ERR_MSG_MOD(extack,
3488                                                    "devices are not on same switch HW, can't offload forwarding");
3489                                 netdev_warn(priv->netdev,
3490                                             "devices %s %s not on same switch HW, can't offload forwarding\n",
3491                                             priv->netdev->name,
3492                                             out_dev->name);
3493                                 return -EINVAL;
3494                         }
3495                         }
3496                         break;
3497                 case FLOW_ACTION_TUNNEL_ENCAP:
3498                         info = act->tunnel;
3499                         if (info)
3500                                 encap = true;
3501                         else
3502                                 return -EOPNOTSUPP;
3503
3504                         break;
3505                 case FLOW_ACTION_VLAN_PUSH:
3506                 case FLOW_ACTION_VLAN_POP:
3507                         if (act->id == FLOW_ACTION_VLAN_PUSH &&
3508                             (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3509                                 /* Replace vlan pop+push with vlan modify */
3510                                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3511                                 err = add_vlan_rewrite_action(priv,
3512                                                               MLX5_FLOW_NAMESPACE_FDB,
3513                                                               act, parse_attr, hdrs,
3514                                                               &action, extack);
3515                         } else {
3516                                 err = parse_tc_vlan_action(priv, act, attr, &action);
3517                         }
3518                         if (err)
3519                                 return err;
3520
3521                         attr->split_count = attr->out_count;
3522                         break;
3523                 case FLOW_ACTION_VLAN_MANGLE:
3524                         err = add_vlan_rewrite_action(priv,
3525                                                       MLX5_FLOW_NAMESPACE_FDB,
3526                                                       act, parse_attr, hdrs,
3527                                                       &action, extack);
3528                         if (err)
3529                                 return err;
3530
3531                         attr->split_count = attr->out_count;
3532                         break;
3533                 case FLOW_ACTION_TUNNEL_DECAP:
3534                         action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
3535                         break;
3536                 case FLOW_ACTION_GOTO: {
3537                         u32 dest_chain = act->chain_index;
3538                         u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3539
3540                         if (ft_flow) {
3541                                 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3542                                 return -EOPNOTSUPP;
3543                         }
3544                         if (!mlx5_esw_chains_backwards_supported(esw) &&
3545                             dest_chain <= attr->chain) {
3546                                 NL_SET_ERR_MSG_MOD(extack,
3547                                                    "Goto earlier chain isn't supported");
3548                                 return -EOPNOTSUPP;
3549                         }
3550                         if (dest_chain > max_chain) {
3551                                 NL_SET_ERR_MSG_MOD(extack,
3552                                                    "Requested destination chain is out of supported range");
3553                                 return -EOPNOTSUPP;
3554                         }
3555                         action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3556                         attr->dest_chain = dest_chain;
3557                         break;
3558                         }
3559                 default:
3560                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3561                         return -EOPNOTSUPP;
3562                 }
3563         }
3564
3565         if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3566             action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3567                 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3568                  * tag rewrite.
3569                  */
3570                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3571                 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3572                                                        &action, extack);
3573                 if (err)
3574                         return err;
3575         }
3576
3577         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3578             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3579                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3580                                             parse_attr, hdrs, &action, extack);
3581                 if (err)
3582                         return err;
3583                 /* in case all pedit actions are skipped, remove the MOD_HDR
3584                  * flag. we might have set split_count either by pedit or
3585                  * pop/push. if there is no pop/push either, reset it too.
3586                  */
3587                 if (parse_attr->num_mod_hdr_actions == 0) {
3588                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3589                         kfree(parse_attr->mod_hdr_actions);
3590                         if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3591                               (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3592                                 attr->split_count = 0;
3593                 }
3594         }
3595
3596         attr->action = action;
3597         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3598                 return -EOPNOTSUPP;
3599
3600         if (attr->dest_chain) {
3601                 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3602                         NL_SET_ERR_MSG_MOD(extack,
3603                                            "Mirroring goto chain rules isn't supported");
3604                         return -EOPNOTSUPP;
3605                 }
3606                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3607         }
3608
3609         if (!(attr->action &
3610               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3611                 NL_SET_ERR_MSG_MOD(extack,
3612                                    "Rule must have at least one forward/drop action");
3613                 return -EOPNOTSUPP;
3614         }
3615
3616         if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3617                 NL_SET_ERR_MSG_MOD(extack,
3618                                    "current firmware doesn't support split rule for port mirroring");
3619                 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3620                 return -EOPNOTSUPP;
3621         }
3622
3623         return 0;
3624 }
3625
3626 static void get_flags(int flags, unsigned long *flow_flags)
3627 {
3628         unsigned long __flow_flags = 0;
3629
3630         if (flags & MLX5_TC_FLAG(INGRESS))
3631                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3632         if (flags & MLX5_TC_FLAG(EGRESS))
3633                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3634
3635         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3636                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3637         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3638                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3639         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3640                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
3641
3642         *flow_flags = __flow_flags;
3643 }
3644
3645 static const struct rhashtable_params tc_ht_params = {
3646         .head_offset = offsetof(struct mlx5e_tc_flow, node),
3647         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3648         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3649         .automatic_shrinking = true,
3650 };
3651
3652 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3653                                     unsigned long flags)
3654 {
3655         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3656         struct mlx5e_rep_priv *uplink_rpriv;
3657
3658         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
3659                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3660                 return &uplink_rpriv->uplink_priv.tc_ht;
3661         } else /* NIC offload */
3662                 return &priv->fs.tc.ht;
3663 }
3664
3665 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3666 {
3667         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3668         bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
3669                 flow_flag_test(flow, INGRESS);
3670         bool act_is_encap = !!(attr->action &
3671                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3672         bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3673                                                 MLX5_DEVCOM_ESW_OFFLOADS);
3674
3675         if (!esw_paired)
3676                 return false;
3677
3678         if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3679              mlx5_lag_is_multipath(attr->in_mdev)) &&
3680             (is_rep_ingress || act_is_encap))
3681                 return true;
3682
3683         return false;
3684 }
3685
3686 static int
3687 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
3688                  struct flow_cls_offload *f, unsigned long flow_flags,
3689                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
3690                  struct mlx5e_tc_flow **__flow)
3691 {
3692         struct mlx5e_tc_flow_parse_attr *parse_attr;
3693         struct mlx5e_tc_flow *flow;
3694         int out_index, err;
3695
3696         flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
3697         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3698         if (!parse_attr || !flow) {
3699                 err = -ENOMEM;
3700                 goto err_free;
3701         }
3702
3703         flow->cookie = f->cookie;
3704         flow->flags = flow_flags;
3705         flow->priv = priv;
3706         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3707                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3708         INIT_LIST_HEAD(&flow->mod_hdr);
3709         INIT_LIST_HEAD(&flow->hairpin);
3710         refcount_set(&flow->refcnt, 1);
3711         init_completion(&flow->init_done);
3712
3713         *__flow = flow;
3714         *__parse_attr = parse_attr;
3715
3716         return 0;
3717
3718 err_free:
3719         kfree(flow);
3720         kvfree(parse_attr);
3721         return err;
3722 }
3723
3724 static void
3725 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3726                          struct mlx5e_priv *priv,
3727                          struct mlx5e_tc_flow_parse_attr *parse_attr,
3728                          struct flow_cls_offload *f,
3729                          struct mlx5_eswitch_rep *in_rep,
3730                          struct mlx5_core_dev *in_mdev)
3731 {
3732         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3733
3734         esw_attr->parse_attr = parse_attr;
3735         esw_attr->chain = f->common.chain_index;
3736         esw_attr->prio = f->common.prio;
3737
3738         esw_attr->in_rep = in_rep;
3739         esw_attr->in_mdev = in_mdev;
3740
3741         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3742             MLX5_COUNTER_SOURCE_ESWITCH)
3743                 esw_attr->counter_dev = in_mdev;
3744         else
3745                 esw_attr->counter_dev = priv->mdev;
3746 }
3747
3748 static struct mlx5e_tc_flow *
3749 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3750                      struct flow_cls_offload *f,
3751                      unsigned long flow_flags,
3752                      struct net_device *filter_dev,
3753                      struct mlx5_eswitch_rep *in_rep,
3754                      struct mlx5_core_dev *in_mdev)
3755 {
3756         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3757         struct netlink_ext_ack *extack = f->common.extack;
3758         struct mlx5e_tc_flow_parse_attr *parse_attr;
3759         struct mlx5e_tc_flow *flow;
3760         int attr_size, err;
3761
3762         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3763         attr_size  = sizeof(struct mlx5_esw_flow_attr);
3764         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3765                                &parse_attr, &flow);
3766         if (err)
3767                 goto out;
3768
3769         parse_attr->filter_dev = filter_dev;
3770         mlx5e_flow_esw_attr_init(flow->esw_attr,
3771                                  priv, parse_attr,
3772                                  f, in_rep, in_mdev);
3773
3774         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3775                                f, filter_dev);
3776         if (err)
3777                 goto err_free;
3778
3779         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
3780         if (err)
3781                 goto err_free;
3782
3783         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
3784         complete_all(&flow->init_done);
3785         if (err) {
3786                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3787                         goto err_free;
3788
3789                 add_unready_flow(flow);
3790         }
3791
3792         return flow;
3793
3794 err_free:
3795         mlx5e_flow_put(priv, flow);
3796 out:
3797         return ERR_PTR(err);
3798 }
3799
3800 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
3801                                       struct mlx5e_tc_flow *flow,
3802                                       unsigned long flow_flags)
3803 {
3804         struct mlx5e_priv *priv = flow->priv, *peer_priv;
3805         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3806         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3807         struct mlx5e_tc_flow_parse_attr *parse_attr;
3808         struct mlx5e_rep_priv *peer_urpriv;
3809         struct mlx5e_tc_flow *peer_flow;
3810         struct mlx5_core_dev *in_mdev;
3811         int err = 0;
3812
3813         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3814         if (!peer_esw)
3815                 return -ENODEV;
3816
3817         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3818         peer_priv = netdev_priv(peer_urpriv->netdev);
3819
3820         /* in_mdev is assigned of which the packet originated from.
3821          * So packets redirected to uplink use the same mdev of the
3822          * original flow and packets redirected from uplink use the
3823          * peer mdev.
3824          */
3825         if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
3826                 in_mdev = peer_priv->mdev;
3827         else
3828                 in_mdev = priv->mdev;
3829
3830         parse_attr = flow->esw_attr->parse_attr;
3831         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
3832                                          parse_attr->filter_dev,
3833                                          flow->esw_attr->in_rep, in_mdev);
3834         if (IS_ERR(peer_flow)) {
3835                 err = PTR_ERR(peer_flow);
3836                 goto out;
3837         }
3838
3839         flow->peer_flow = peer_flow;
3840         flow_flag_set(flow, DUP);
3841         mutex_lock(&esw->offloads.peer_mutex);
3842         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3843         mutex_unlock(&esw->offloads.peer_mutex);
3844
3845 out:
3846         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3847         return err;
3848 }
3849
3850 static int
3851 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3852                    struct flow_cls_offload *f,
3853                    unsigned long flow_flags,
3854                    struct net_device *filter_dev,
3855                    struct mlx5e_tc_flow **__flow)
3856 {
3857         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3858         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3859         struct mlx5_core_dev *in_mdev = priv->mdev;
3860         struct mlx5e_tc_flow *flow;
3861         int err;
3862
3863         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3864                                     in_mdev);
3865         if (IS_ERR(flow))
3866                 return PTR_ERR(flow);
3867
3868         if (is_peer_flow_needed(flow)) {
3869                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
3870                 if (err) {
3871                         mlx5e_tc_del_fdb_flow(priv, flow);
3872                         goto out;
3873                 }
3874         }
3875
3876         *__flow = flow;
3877
3878         return 0;
3879
3880 out:
3881         return err;
3882 }
3883
3884 static int
3885 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3886                    struct flow_cls_offload *f,
3887                    unsigned long flow_flags,
3888                    struct net_device *filter_dev,
3889                    struct mlx5e_tc_flow **__flow)
3890 {
3891         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3892         struct netlink_ext_ack *extack = f->common.extack;
3893         struct mlx5e_tc_flow_parse_attr *parse_attr;
3894         struct mlx5e_tc_flow *flow;
3895         int attr_size, err;
3896
3897         /* multi-chain not supported for NIC rules */
3898         if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3899                 return -EOPNOTSUPP;
3900
3901         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3902         attr_size  = sizeof(struct mlx5_nic_flow_attr);
3903         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3904                                &parse_attr, &flow);
3905         if (err)
3906                 goto out;
3907
3908         parse_attr->filter_dev = filter_dev;
3909         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3910                                f, filter_dev);
3911         if (err)
3912                 goto err_free;
3913
3914         err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
3915         if (err)
3916                 goto err_free;
3917
3918         err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3919         if (err)
3920                 goto err_free;
3921
3922         flow_flag_set(flow, OFFLOADED);
3923         kvfree(parse_attr);
3924         *__flow = flow;
3925
3926         return 0;
3927
3928 err_free:
3929         mlx5e_flow_put(priv, flow);
3930         kvfree(parse_attr);
3931 out:
3932         return err;
3933 }
3934
3935 static int
3936 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3937                   struct flow_cls_offload *f,
3938                   unsigned long flags,
3939                   struct net_device *filter_dev,
3940                   struct mlx5e_tc_flow **flow)
3941 {
3942         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3943         unsigned long flow_flags;
3944         int err;
3945
3946         get_flags(flags, &flow_flags);
3947
3948         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3949                 return -EOPNOTSUPP;
3950
3951         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
3952                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3953                                          filter_dev, flow);
3954         else
3955                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3956                                          filter_dev, flow);
3957
3958         return err;
3959 }
3960
3961 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
3962                            struct flow_cls_offload *f, unsigned long flags)
3963 {
3964         struct netlink_ext_ack *extack = f->common.extack;
3965         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3966         struct mlx5e_tc_flow *flow;
3967         int err = 0;
3968
3969         rcu_read_lock();
3970         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3971         rcu_read_unlock();
3972         if (flow) {
3973                 NL_SET_ERR_MSG_MOD(extack,
3974                                    "flow cookie already exists, ignoring");
3975                 netdev_warn_once(priv->netdev,
3976                                  "flow cookie %lx already exists, ignoring\n",
3977                                  f->cookie);
3978                 err = -EEXIST;
3979                 goto out;
3980         }
3981
3982         trace_mlx5e_configure_flower(f);
3983         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
3984         if (err)
3985                 goto out;
3986
3987         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
3988         if (err)
3989                 goto err_free;
3990
3991         return 0;
3992
3993 err_free:
3994         mlx5e_flow_put(priv, flow);
3995 out:
3996         return err;
3997 }
3998
3999 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4000 {
4001         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4002         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4003
4004         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4005                 flow_flag_test(flow, EGRESS) == dir_egress;
4006 }
4007
4008 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4009                         struct flow_cls_offload *f, unsigned long flags)
4010 {
4011         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4012         struct mlx5e_tc_flow *flow;
4013         int err;
4014
4015         rcu_read_lock();
4016         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4017         if (!flow || !same_flow_direction(flow, flags)) {
4018                 err = -EINVAL;
4019                 goto errout;
4020         }
4021
4022         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4023          * set.
4024          */
4025         if (flow_flag_test_and_set(flow, DELETED)) {
4026                 err = -EINVAL;
4027                 goto errout;
4028         }
4029         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4030         rcu_read_unlock();
4031
4032         trace_mlx5e_delete_flower(f);
4033         mlx5e_flow_put(priv, flow);
4034
4035         return 0;
4036
4037 errout:
4038         rcu_read_unlock();
4039         return err;
4040 }
4041
4042 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4043                        struct flow_cls_offload *f, unsigned long flags)
4044 {
4045         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4046         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4047         struct mlx5_eswitch *peer_esw;
4048         struct mlx5e_tc_flow *flow;
4049         struct mlx5_fc *counter;
4050         u64 lastuse = 0;
4051         u64 packets = 0;
4052         u64 bytes = 0;
4053         int err = 0;
4054
4055         rcu_read_lock();
4056         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4057                                                 tc_ht_params));
4058         rcu_read_unlock();
4059         if (IS_ERR(flow))
4060                 return PTR_ERR(flow);
4061
4062         if (!same_flow_direction(flow, flags)) {
4063                 err = -EINVAL;
4064                 goto errout;
4065         }
4066
4067         if (mlx5e_is_offloaded_flow(flow)) {
4068                 counter = mlx5e_tc_get_counter(flow);
4069                 if (!counter)
4070                         goto errout;
4071
4072                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4073         }
4074
4075         /* Under multipath it's possible for one rule to be currently
4076          * un-offloaded while the other rule is offloaded.
4077          */
4078         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4079         if (!peer_esw)
4080                 goto out;
4081
4082         if (flow_flag_test(flow, DUP) &&
4083             flow_flag_test(flow->peer_flow, OFFLOADED)) {
4084                 u64 bytes2;
4085                 u64 packets2;
4086                 u64 lastuse2;
4087
4088                 counter = mlx5e_tc_get_counter(flow->peer_flow);
4089                 if (!counter)
4090                         goto no_peer_counter;
4091                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4092
4093                 bytes += bytes2;
4094                 packets += packets2;
4095                 lastuse = max_t(u64, lastuse, lastuse2);
4096         }
4097
4098 no_peer_counter:
4099         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4100 out:
4101         flow_stats_update(&f->stats, bytes, packets, lastuse);
4102         trace_mlx5e_stats_flower(f);
4103 errout:
4104         mlx5e_flow_put(priv, flow);
4105         return err;
4106 }
4107
4108 static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4109                                struct netlink_ext_ack *extack)
4110 {
4111         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4112         struct mlx5_eswitch *esw;
4113         u16 vport_num;
4114         u32 rate_mbps;
4115         int err;
4116
4117         vport_num = rpriv->rep->vport;
4118         if (vport_num >= MLX5_VPORT_ECPF) {
4119                 NL_SET_ERR_MSG_MOD(extack,
4120                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4121                 return -EOPNOTSUPP;
4122         }
4123
4124         esw = priv->mdev->priv.eswitch;
4125         /* rate is given in bytes/sec.
4126          * First convert to bits/sec and then round to the nearest mbit/secs.
4127          * mbit means million bits.
4128          * Moreover, if rate is non zero we choose to configure to a minimum of
4129          * 1 mbit/sec.
4130          */
4131         rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
4132         err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4133         if (err)
4134                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4135
4136         return err;
4137 }
4138
4139 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4140                                         struct flow_action *flow_action,
4141                                         struct netlink_ext_ack *extack)
4142 {
4143         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4144         const struct flow_action_entry *act;
4145         int err;
4146         int i;
4147
4148         if (!flow_action_has_entries(flow_action)) {
4149                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4150                 return -EINVAL;
4151         }
4152
4153         if (!flow_offload_has_one_action(flow_action)) {
4154                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4155                 return -EOPNOTSUPP;
4156         }
4157
4158         flow_action_for_each(i, act, flow_action) {
4159                 switch (act->id) {
4160                 case FLOW_ACTION_POLICE:
4161                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4162                         if (err)
4163                                 return err;
4164
4165                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4166                         break;
4167                 default:
4168                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4169                         return -EOPNOTSUPP;
4170                 }
4171         }
4172
4173         return 0;
4174 }
4175
4176 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4177                                 struct tc_cls_matchall_offload *ma)
4178 {
4179         struct netlink_ext_ack *extack = ma->common.extack;
4180
4181         if (ma->common.prio != 1) {
4182                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4183                 return -EINVAL;
4184         }
4185
4186         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4187 }
4188
4189 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4190                              struct tc_cls_matchall_offload *ma)
4191 {
4192         struct netlink_ext_ack *extack = ma->common.extack;
4193
4194         return apply_police_params(priv, 0, extack);
4195 }
4196
4197 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4198                              struct tc_cls_matchall_offload *ma)
4199 {
4200         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4201         struct rtnl_link_stats64 cur_stats;
4202         u64 dbytes;
4203         u64 dpkts;
4204
4205         cur_stats = priv->stats.vf_vport;
4206         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4207         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4208         rpriv->prev_vf_vport_stats = cur_stats;
4209         flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4210 }
4211
4212 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4213                                               struct mlx5e_priv *peer_priv)
4214 {
4215         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4216         struct mlx5e_hairpin_entry *hpe, *tmp;
4217         LIST_HEAD(init_wait_list);
4218         u16 peer_vhca_id;
4219         int bkt;
4220
4221         if (!same_hw_devs(priv, peer_priv))
4222                 return;
4223
4224         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4225
4226         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
4227         hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4228                 if (refcount_inc_not_zero(&hpe->refcnt))
4229                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4230         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4231
4232         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4233                 wait_for_completion(&hpe->res_ready);
4234                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4235                         hpe->hp->pair->peer_gone = true;
4236
4237                 mlx5e_hairpin_put(priv, hpe);
4238         }
4239 }
4240
4241 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4242                                  unsigned long event, void *ptr)
4243 {
4244         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4245         struct mlx5e_flow_steering *fs;
4246         struct mlx5e_priv *peer_priv;
4247         struct mlx5e_tc_table *tc;
4248         struct mlx5e_priv *priv;
4249
4250         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4251             event != NETDEV_UNREGISTER ||
4252             ndev->reg_state == NETREG_REGISTERED)
4253                 return NOTIFY_DONE;
4254
4255         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4256         fs = container_of(tc, struct mlx5e_flow_steering, tc);
4257         priv = container_of(fs, struct mlx5e_priv, fs);
4258         peer_priv = netdev_priv(ndev);
4259         if (priv == peer_priv ||
4260             !(priv->netdev->features & NETIF_F_HW_TC))
4261                 return NOTIFY_DONE;
4262
4263         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4264
4265         return NOTIFY_DONE;
4266 }
4267
4268 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4269 {
4270         struct mlx5e_tc_table *tc = &priv->fs.tc;
4271         int err;
4272
4273         mutex_init(&tc->t_lock);
4274         mutex_init(&tc->mod_hdr.lock);
4275         hash_init(tc->mod_hdr.hlist);
4276         mutex_init(&tc->hairpin_tbl_lock);
4277         hash_init(tc->hairpin_tbl);
4278
4279         err = rhashtable_init(&tc->ht, &tc_ht_params);
4280         if (err)
4281                 return err;
4282
4283         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4284         err = register_netdevice_notifier_dev_net(priv->netdev,
4285                                                   &tc->netdevice_nb,
4286                                                   &tc->netdevice_nn);
4287         if (err) {
4288                 tc->netdevice_nb.notifier_call = NULL;
4289                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4290         }
4291
4292         return err;
4293 }
4294
4295 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4296 {
4297         struct mlx5e_tc_flow *flow = ptr;
4298         struct mlx5e_priv *priv = flow->priv;
4299
4300         mlx5e_tc_del_flow(priv, flow);
4301         kfree(flow);
4302 }
4303
4304 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4305 {
4306         struct mlx5e_tc_table *tc = &priv->fs.tc;
4307
4308         if (tc->netdevice_nb.notifier_call)
4309                 unregister_netdevice_notifier_dev_net(priv->netdev,
4310                                                       &tc->netdevice_nb,
4311                                                       &tc->netdevice_nn);
4312
4313         mutex_destroy(&tc->mod_hdr.lock);
4314         mutex_destroy(&tc->hairpin_tbl_lock);
4315
4316         rhashtable_destroy(&tc->ht);
4317
4318         if (!IS_ERR_OR_NULL(tc->t)) {
4319                 mlx5_destroy_flow_table(tc->t);
4320                 tc->t = NULL;
4321         }
4322         mutex_destroy(&tc->t_lock);
4323 }
4324
4325 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4326 {
4327         return rhashtable_init(tc_ht, &tc_ht_params);
4328 }
4329
4330 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4331 {
4332         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4333 }
4334
4335 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4336 {
4337         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4338
4339         return atomic_read(&tc_ht->nelems);
4340 }
4341
4342 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4343 {
4344         struct mlx5e_tc_flow *flow, *tmp;
4345
4346         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4347                 __mlx5e_tc_del_fdb_peer_flow(flow);
4348 }
4349
4350 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4351 {
4352         struct mlx5_rep_uplink_priv *rpriv =
4353                 container_of(work, struct mlx5_rep_uplink_priv,
4354                              reoffload_flows_work);
4355         struct mlx5e_tc_flow *flow, *tmp;
4356
4357         mutex_lock(&rpriv->unready_flows_lock);
4358         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4359                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4360                         unready_flow_del(flow);
4361         }
4362         mutex_unlock(&rpriv->unready_flows_lock);
4363 }