2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
43 #include "ipoib/ipoib.h"
44 #include "en_accel/ipsec_rxtx.h"
46 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
51 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
54 u32 ci = cqcc & cq->wq.sz_m1;
56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
59 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
60 struct mlx5e_cq *cq, u32 cqcc)
62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
65 rq->stats.cqe_compress_blks++;
68 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
74 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
77 u32 wq_sz = 1 << cq->wq.log_sz;
78 u32 ci = cqcc & cq->wq.sz_m1;
79 u32 ci_top = min_t(u32, wq_sz, ci + n);
81 for (; ci < ci_top; ci++, n--) {
82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
87 if (unlikely(ci == wq_sz)) {
89 for (ci = 0; ci < n; ci++) {
90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
97 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
98 struct mlx5e_cq *cq, u32 cqcc)
100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
102 cq->title.op_own &= 0xf0;
103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
107 cq->decmprs_wqe_counter +=
108 mpwrq_get_cqe_consumed_strides(&cq->title);
110 cq->decmprs_wqe_counter =
111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
114 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
115 struct mlx5e_cq *cq, u32 cqcc)
117 mlx5e_decompress_cqe(rq, cq, cqcc);
118 cq->title.rss_hash_type = 0;
119 cq->title.rss_hash_result = 0;
122 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
124 int update_owner_only,
127 u32 cqcc = cq->wq.cc + update_owner_only;
131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
133 for (i = update_owner_only; i < cqe_count;
134 i++, cq->mini_arr_idx++, cqcc++) {
135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
136 mlx5e_read_mini_arr_slot(cq, cqcc);
138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
139 rq->handle_rx_cqe(rq, &cq->title);
141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
143 cq->decmprs_left -= cqe_count;
144 rq->stats.cqe_compress_pkts += cqe_count;
149 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
153 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
156 rq->handle_rx_cqe(rq, &cq->title);
159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
162 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
164 static inline bool mlx5e_page_is_reserved(struct page *page)
166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
169 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
170 struct mlx5e_dma_info *dma_info)
172 struct mlx5e_page_cache *cache = &rq->page_cache;
173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
175 if (tail_next == cache->head) {
176 rq->stats.cache_full++;
180 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
181 rq->stats.cache_waive++;
185 cache->page_cache[cache->tail] = *dma_info;
186 cache->tail = tail_next;
190 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
191 struct mlx5e_dma_info *dma_info)
193 struct mlx5e_page_cache *cache = &rq->page_cache;
195 if (unlikely(cache->head == cache->tail)) {
196 rq->stats.cache_empty++;
200 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
201 rq->stats.cache_busy++;
205 *dma_info = cache->page_cache[cache->head];
206 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
207 rq->stats.cache_reuse++;
209 dma_sync_single_for_device(rq->pdev, dma_info->addr,
215 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
216 struct mlx5e_dma_info *dma_info)
220 if (mlx5e_rx_cache_get(rq, dma_info))
223 page = dev_alloc_pages(rq->buff.page_order);
227 dma_info->addr = dma_map_page(rq->pdev, page, 0,
228 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
229 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
233 dma_info->page = page;
238 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
241 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
244 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
246 put_page(dma_info->page);
249 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
250 struct mlx5e_wqe_frag_info *wi)
252 return rq->wqe.page_reuse && wi->di.page &&
253 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
254 !mlx5e_page_is_reserved(wi->di.page);
257 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
259 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
261 /* check if page exists, hence can be reused */
263 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
268 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
272 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
273 struct mlx5e_wqe_frag_info *wi)
275 mlx5e_page_release(rq, &wi->di, true);
279 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
280 struct mlx5e_wqe_frag_info *wi)
282 if (mlx5e_page_reuse(rq, wi)) {
283 rq->stats.page_reuse++;
287 mlx5e_free_rx_wqe(rq, wi);
290 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
292 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
295 mlx5e_free_rx_wqe(rq, wi);
298 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
300 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
303 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
305 struct mlx5e_mpw_info *wi,
306 u32 page_idx, u32 frag_offset,
309 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
311 dma_sync_single_for_cpu(rq->pdev,
312 wi->umr.dma_info[page_idx].addr + frag_offset,
313 len, DMA_FROM_DEVICE);
314 wi->skbs_frags[page_idx]++;
315 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
316 wi->umr.dma_info[page_idx].page, frag_offset,
321 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
323 struct mlx5e_mpw_info *wi,
324 u32 page_idx, u32 offset,
327 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
328 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
331 /* Aligning len to sizeof(long) optimizes memcpy performance */
332 len = ALIGN(headlen_pg, sizeof(long));
333 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
335 skb_copy_to_linear_data_offset(skb, 0,
336 page_address(dma_info->page) + offset,
338 if (unlikely(offset + headlen > PAGE_SIZE)) {
341 len = ALIGN(headlen - headlen_pg, sizeof(long));
342 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
344 skb_copy_to_linear_data_offset(skb, headlen_pg,
345 page_address(dma_info->page),
350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
352 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
353 struct mlx5e_icosq *sq = &rq->channel->icosq;
354 struct mlx5_wq_cyc *wq = &sq->wq;
355 struct mlx5e_umr_wqe *wqe;
356 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
359 /* fill sq edge with nops to avoid wqe wrap around */
360 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
361 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
362 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
365 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
366 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
367 wqe->ctrl.opmod_idx_opcode =
368 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
371 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
372 sq->pc += num_wqebbs;
373 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
379 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
380 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
381 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
385 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
386 err = mlx5e_page_alloc_mapped(rq, dma_info);
389 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
390 page_ref_add(dma_info->page, pg_strides);
393 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
394 wi->consumed_strides = 0;
401 page_ref_sub(dma_info->page, pg_strides);
402 mlx5e_page_release(rq, dma_info, true);
408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
410 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
411 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
414 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
415 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
416 mlx5e_page_release(rq, dma_info, true);
420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
422 struct mlx5_wq_ll *wq = &rq->wq;
423 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
425 rq->mpwqe.umr_in_progress = false;
427 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
429 /* ensure wqes are visible to device before updating doorbell record */
432 mlx5_wq_ll_update_db_record(wq);
435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
439 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix);
441 rq->stats.buff_alloc_err++;
444 rq->mpwqe.umr_in_progress = true;
445 mlx5e_post_umr_wqe(rq, ix);
449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
453 mlx5e_free_rx_mpwqe(rq, wi);
456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
458 struct mlx5_wq_ll *wq = &rq->wq;
461 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
464 if (mlx5_wq_ll_is_full(wq))
468 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
470 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
472 rq->stats.buff_alloc_err++;
476 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
477 } while (!mlx5_wq_ll_is_full(wq));
479 /* ensure wqes are visible to device before updating doorbell record */
482 mlx5_wq_ll_update_db_record(wq);
487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
488 struct mlx5e_icosq *sq,
490 struct mlx5_cqe64 *cqe)
492 struct mlx5_wq_cyc *wq = &sq->wq;
493 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
494 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
496 mlx5_cqwq_pop(&cq->wq);
498 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
499 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
504 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
505 mlx5e_post_rx_mpwqe(rq);
509 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
511 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
515 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
517 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
518 struct mlx5_cqe64 *cqe;
520 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
523 cqe = mlx5_cqwq_get_cqe(&cq->wq);
527 /* by design, there's only a single cqe */
528 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
530 mlx5_cqwq_update_db_record(&cq->wq);
533 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
535 struct mlx5_wq_ll *wq = &rq->wq;
537 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
540 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
542 if (mlx5_wq_ll_is_full(wq))
545 if (!rq->mpwqe.umr_in_progress)
546 mlx5e_alloc_rx_mpwqe(rq, wq->head);
551 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
554 struct ethhdr *eth = (struct ethhdr *)(skb->data);
556 int network_depth = 0;
561 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
562 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
563 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
565 skb->mac_len = ETH_HLEN;
566 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
568 tot_len = cqe_bcnt - network_depth;
569 ip_p = skb->data + network_depth;
571 if (proto == htons(ETH_P_IP)) {
572 struct iphdr *ipv4 = ip_p;
574 tcp = ip_p + sizeof(struct iphdr);
575 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
577 ipv4->ttl = cqe->lro_min_ttl;
578 ipv4->tot_len = cpu_to_be16(tot_len);
580 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
583 struct ipv6hdr *ipv6 = ip_p;
585 tcp = ip_p + sizeof(struct ipv6hdr);
586 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
588 ipv6->hop_limit = cqe->lro_min_ttl;
589 ipv6->payload_len = cpu_to_be16(tot_len -
590 sizeof(struct ipv6hdr));
593 tcp->psh = get_cqe_lro_tcppsh(cqe);
597 tcp->ack_seq = cqe->lro_ack_seq_num;
598 tcp->window = cqe->lro_tcp_win;
602 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
605 u8 cht = cqe->rss_hash_type;
606 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
607 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
609 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
612 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
614 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
616 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
619 static inline void mlx5e_handle_csum(struct net_device *netdev,
620 struct mlx5_cqe64 *cqe,
625 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
629 skb->ip_summed = CHECKSUM_UNNECESSARY;
633 if (is_first_ethertype_ip(skb)) {
634 skb->ip_summed = CHECKSUM_COMPLETE;
635 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
636 rq->stats.csum_complete++;
640 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
641 (cqe->hds_ip_ext & CQE_L4_OK))) {
642 skb->ip_summed = CHECKSUM_UNNECESSARY;
643 if (cqe_is_tunneled(cqe)) {
645 skb->encapsulation = 1;
646 rq->stats.csum_unnecessary_inner++;
651 skb->ip_summed = CHECKSUM_NONE;
652 rq->stats.csum_none++;
655 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
660 struct net_device *netdev = rq->netdev;
661 struct mlx5e_tstamp *tstamp = rq->tstamp;
664 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
665 if (lro_num_seg > 1) {
666 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
667 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
668 /* Subtract one since we already counted this as one
669 * "regular" packet in mlx5e_complete_rx_cqe()
671 rq->stats.packets += lro_num_seg - 1;
672 rq->stats.lro_packets++;
673 rq->stats.lro_bytes += cqe_bcnt;
676 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
677 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
679 skb_record_rx_queue(skb, rq->ix);
681 if (likely(netdev->features & NETIF_F_RXHASH))
682 mlx5e_skb_set_hash(cqe, skb);
684 if (cqe_has_vlan(cqe))
685 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
686 be16_to_cpu(cqe->vlan_info));
688 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
690 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
691 skb->protocol = eth_type_trans(skb, netdev);
694 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
695 struct mlx5_cqe64 *cqe,
700 rq->stats.bytes += cqe_bcnt;
701 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
704 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
706 struct mlx5_wq_cyc *wq = &sq->wq;
707 struct mlx5e_tx_wqe *wqe;
708 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
710 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
712 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
715 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
716 struct mlx5e_dma_info *di,
717 const struct xdp_buff *xdp)
719 struct mlx5e_xdpsq *sq = &rq->xdpsq;
720 struct mlx5_wq_cyc *wq = &sq->wq;
721 u16 pi = sq->pc & wq->sz_m1;
722 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
724 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
725 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
726 struct mlx5_wqe_data_seg *dseg;
728 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
729 dma_addr_t dma_addr = di->addr + data_offset;
730 unsigned int dma_len = xdp->data_end - xdp->data;
734 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
735 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
736 rq->stats.xdp_drop++;
740 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
741 if (sq->db.doorbell) {
742 /* SQ is full, ring doorbell */
743 mlx5e_xmit_xdp_doorbell(sq);
744 sq->db.doorbell = false;
746 rq->stats.xdp_tx_full++;
750 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
754 dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
756 /* copy the inline part if required */
757 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
758 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
759 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
760 dma_len -= MLX5E_XDP_MIN_INLINE;
761 dma_addr += MLX5E_XDP_MIN_INLINE;
765 /* write the dma part */
766 dseg->addr = cpu_to_be64(dma_addr);
767 dseg->byte_count = cpu_to_be32(dma_len);
769 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
771 /* move page to reference to sq responsibility,
772 * and mark so it's not put back in page-cache.
774 rq->wqe.xdp_xmit = true;
778 sq->db.doorbell = true;
784 /* returns true if packet was consumed by xdp */
785 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
786 struct mlx5e_dma_info *di,
787 void *va, u16 *rx_headroom, u32 *len)
789 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
796 xdp.data = va + *rx_headroom;
797 xdp.data_end = xdp.data + *len;
798 xdp.data_hard_start = va;
800 act = bpf_prog_run_xdp(prog, &xdp);
803 *rx_headroom = xdp.data - xdp.data_hard_start;
804 *len = xdp.data_end - xdp.data;
807 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
808 trace_xdp_exception(rq->netdev, prog, act);
811 bpf_warn_invalid_xdp_action(act);
813 trace_xdp_exception(rq->netdev, prog, act);
815 rq->stats.xdp_drop++;
821 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
822 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
824 struct mlx5e_dma_info *di = &wi->di;
825 u16 rx_headroom = rq->buff.headroom;
831 va = page_address(di->page) + wi->offset;
832 data = va + rx_headroom;
833 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
835 dma_sync_single_range_for_cpu(rq->pdev,
836 di->addr + wi->offset,
840 wi->offset += frag_size;
842 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
848 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
851 return NULL; /* page/packet was consumed by XDP */
853 skb = build_skb(va, frag_size);
854 if (unlikely(!skb)) {
855 rq->stats.buff_alloc_err++;
859 /* queue up for recycling/reuse */
860 page_ref_inc(di->page);
862 skb_reserve(skb, rx_headroom);
863 skb_put(skb, cqe_bcnt);
868 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
870 struct mlx5e_wqe_frag_info *wi;
871 struct mlx5e_rx_wqe *wqe;
872 __be16 wqe_counter_be;
877 wqe_counter_be = cqe->wqe_counter;
878 wqe_counter = be16_to_cpu(wqe_counter_be);
879 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
880 wi = &rq->wqe.frag_info[wqe_counter];
881 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
883 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
885 /* probably for XDP */
886 if (rq->wqe.xdp_xmit) {
888 rq->wqe.xdp_xmit = false;
889 /* do not return page to cache, it will be returned on XDP_TX completion */
892 /* probably an XDP_DROP, save the page-reuse checks */
893 mlx5e_free_rx_wqe(rq, wi);
897 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
898 napi_gro_receive(rq->cq.napi, skb);
900 mlx5e_free_rx_wqe_reuse(rq, wi);
902 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
903 &wqe->next.next_wqe_index);
906 #ifdef CONFIG_MLX5_ESWITCH
907 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
909 struct net_device *netdev = rq->netdev;
910 struct mlx5e_priv *priv = netdev_priv(netdev);
911 struct mlx5e_rep_priv *rpriv = priv->ppriv;
912 struct mlx5_eswitch_rep *rep = rpriv->rep;
913 struct mlx5e_wqe_frag_info *wi;
914 struct mlx5e_rx_wqe *wqe;
916 __be16 wqe_counter_be;
920 wqe_counter_be = cqe->wqe_counter;
921 wqe_counter = be16_to_cpu(wqe_counter_be);
922 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
923 wi = &rq->wqe.frag_info[wqe_counter];
924 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
926 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
928 if (rq->wqe.xdp_xmit) {
930 rq->wqe.xdp_xmit = false;
931 /* do not return page to cache, it will be returned on XDP_TX completion */
934 /* probably an XDP_DROP, save the page-reuse checks */
935 mlx5e_free_rx_wqe(rq, wi);
939 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
941 if (rep->vlan && skb_vlan_tag_present(skb))
944 napi_gro_receive(rq->cq.napi, skb);
946 mlx5e_free_rx_wqe_reuse(rq, wi);
948 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
949 &wqe->next.next_wqe_index);
953 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
954 struct mlx5_cqe64 *cqe,
955 struct mlx5e_mpw_info *wi,
959 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
960 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
961 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
962 u32 page_idx = wqe_offset >> PAGE_SHIFT;
963 u32 head_page_idx = page_idx;
964 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
965 u32 frag_offset = head_offset + headlen;
966 u16 byte_cnt = cqe_bcnt - headlen;
968 if (unlikely(frag_offset >= PAGE_SIZE)) {
970 frag_offset -= PAGE_SIZE;
974 u32 pg_consumed_bytes =
975 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
977 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
979 byte_cnt -= pg_consumed_bytes;
984 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
985 head_offset, headlen);
986 /* skb linear part was allocated with headlen and aligned to long */
987 skb->tail += headlen;
991 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
993 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
994 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
995 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
996 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1000 wi->consumed_strides += cstrides;
1002 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1003 rq->stats.wqe_err++;
1007 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1008 rq->stats.mpwqe_filler++;
1012 skb = napi_alloc_skb(rq->cq.napi,
1013 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
1015 if (unlikely(!skb)) {
1016 rq->stats.buff_alloc_err++;
1020 prefetchw(skb->data);
1021 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1023 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
1024 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1025 napi_gro_receive(rq->cq.napi, skb);
1028 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1031 mlx5e_free_rx_mpwqe(rq, wi);
1032 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1035 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1037 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1038 struct mlx5e_xdpsq *xdpsq;
1039 struct mlx5_cqe64 *cqe;
1042 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1045 if (cq->decmprs_left)
1046 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1048 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1055 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1057 mlx5e_decompress_cqes_start(rq, cq,
1058 budget - work_done);
1062 mlx5_cqwq_pop(&cq->wq);
1064 rq->handle_rx_cqe(rq, cqe);
1065 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1067 if (xdpsq->db.doorbell) {
1068 mlx5e_xmit_xdp_doorbell(xdpsq);
1069 xdpsq->db.doorbell = false;
1072 mlx5_cqwq_update_db_record(&cq->wq);
1074 /* ensure cq space is freed before enabling more cqes */
1080 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1082 struct mlx5e_xdpsq *sq;
1083 struct mlx5_cqe64 *cqe;
1084 struct mlx5e_rq *rq;
1088 sq = container_of(cq, struct mlx5e_xdpsq, cq);
1090 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1093 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1097 rq = container_of(sq, struct mlx5e_rq, xdpsq);
1099 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1100 * otherwise a cq overrun may occur
1109 mlx5_cqwq_pop(&cq->wq);
1111 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1114 struct mlx5e_dma_info *di;
1117 last_wqe = (sqcc == wqe_counter);
1119 ci = sqcc & sq->wq.sz_m1;
1120 di = &sq->db.di[ci];
1123 /* Recycle RX page */
1124 mlx5e_page_release(rq, di, true);
1125 } while (!last_wqe);
1126 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1128 mlx5_cqwq_update_db_record(&cq->wq);
1130 /* ensure cq space is freed before enabling more cqes */
1134 return (i == MLX5E_TX_CQ_POLL_BUDGET);
1137 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1139 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1140 struct mlx5e_dma_info *di;
1143 while (sq->cc != sq->pc) {
1144 ci = sq->cc & sq->wq.sz_m1;
1145 di = &sq->db.di[ci];
1148 mlx5e_page_release(rq, di, false);
1152 #ifdef CONFIG_MLX5_CORE_IPOIB
1154 #define MLX5_IB_GRH_DGID_OFFSET 24
1155 #define MLX5_GID_SIZE 16
1157 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1158 struct mlx5_cqe64 *cqe,
1160 struct sk_buff *skb)
1162 struct net_device *netdev = rq->netdev;
1163 struct mlx5e_tstamp *tstamp = rq->tstamp;
1164 char *pseudo_header;
1168 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1169 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1170 if ((!g) || dgid[0] != 0xff)
1171 skb->pkt_type = PACKET_HOST;
1172 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1173 skb->pkt_type = PACKET_BROADCAST;
1175 skb->pkt_type = PACKET_MULTICAST;
1177 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1178 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1181 skb_pull(skb, MLX5_IB_GRH_BYTES);
1183 skb->protocol = *((__be16 *)(skb->data));
1185 skb->ip_summed = CHECKSUM_COMPLETE;
1186 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1188 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1189 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
1191 skb_record_rx_queue(skb, rq->ix);
1193 if (likely(netdev->features & NETIF_F_RXHASH))
1194 mlx5e_skb_set_hash(cqe, skb);
1196 /* 20 bytes of ipoib header and 4 for encap existing */
1197 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1198 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1199 skb_reset_mac_header(skb);
1200 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1204 rq->stats.csum_complete++;
1205 rq->stats.packets++;
1206 rq->stats.bytes += cqe_bcnt;
1209 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1211 struct mlx5e_wqe_frag_info *wi;
1212 struct mlx5e_rx_wqe *wqe;
1213 __be16 wqe_counter_be;
1214 struct sk_buff *skb;
1218 wqe_counter_be = cqe->wqe_counter;
1219 wqe_counter = be16_to_cpu(wqe_counter_be);
1220 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1221 wi = &rq->wqe.frag_info[wqe_counter];
1222 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1224 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1228 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1229 napi_gro_receive(rq->cq.napi, skb);
1232 mlx5e_free_rx_wqe_reuse(rq, wi);
1233 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1234 &wqe->next.next_wqe_index);
1237 #endif /* CONFIG_MLX5_CORE_IPOIB */
1239 #ifdef CONFIG_MLX5_EN_IPSEC
1241 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1243 struct mlx5e_wqe_frag_info *wi;
1244 struct mlx5e_rx_wqe *wqe;
1245 __be16 wqe_counter_be;
1246 struct sk_buff *skb;
1250 wqe_counter_be = cqe->wqe_counter;
1251 wqe_counter = be16_to_cpu(wqe_counter_be);
1252 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1253 wi = &rq->wqe.frag_info[wqe_counter];
1254 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1256 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1257 if (unlikely(!skb)) {
1258 /* a DROP, save the page-reuse checks */
1259 mlx5e_free_rx_wqe(rq, wi);
1262 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1263 if (unlikely(!skb)) {
1264 mlx5e_free_rx_wqe(rq, wi);
1268 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1269 napi_gro_receive(rq->cq.napi, skb);
1271 mlx5e_free_rx_wqe_reuse(rq, wi);
1273 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1274 &wqe->next.next_wqe_index);
1277 #endif /* CONFIG_MLX5_EN_IPSEC */