drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "eswitch.h"
  42 #include "en_rep.h"
  43 #include "ipoib/ipoib.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "lib/clock.h"
  46
  47 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  48 {
  49         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  50 }
  51
  52 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  53                                        void *data)
  54 {
  55         u32 ci = cqcc & cq->wq.sz_m1;
  56
  57         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  58 }
  59
  60 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  61                                          struct mlx5e_cq *cq, u32 cqcc)
  62 {
  63         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  64         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  65         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  66         rq->stats.cqe_compress_blks++;
  67 }
  68
  69 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  70 {
  71         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  72         cq->mini_arr_idx = 0;
  73 }
  74
  75 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  76 {
  77         u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
  78         u32 wq_sz = 1 << cq->wq.log_sz;
  79         u32 ci = cqcc & cq->wq.sz_m1;
  80         u32 ci_top = min_t(u32, wq_sz, ci + n);
  81
  82         for (; ci < ci_top; ci++, n--) {
  83                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  84
  85                 cqe->op_own = op_own;
  86         }
  87
  88         if (unlikely(ci == wq_sz)) {
  89                 op_own = !op_own;
  90                 for (ci = 0; ci < n; ci++) {
  91                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  92
  93                         cqe->op_own = op_own;
  94                 }
  95         }
  96 }
  97
  98 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
  99                                         struct mlx5e_cq *cq, u32 cqcc)
 100 {
 101         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 102         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 103         cq->title.op_own      &= 0xf0;
 104         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.log_sz);
 105         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 106
 107         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 108                 cq->decmprs_wqe_counter +=
 109                         mpwrq_get_cqe_consumed_strides(&cq->title);
 110         else
 111                 cq->decmprs_wqe_counter =
 112                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
 113 }
 114
 115 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 116                                                 struct mlx5e_cq *cq, u32 cqcc)
 117 {
 118         mlx5e_decompress_cqe(rq, cq, cqcc);
 119         cq->title.rss_hash_type   = 0;
 120         cq->title.rss_hash_result = 0;
 121 }
 122
 123 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 124                                              struct mlx5e_cq *cq,
 125                                              int update_owner_only,
 126                                              int budget_rem)
 127 {
 128         u32 cqcc = cq->wq.cc + update_owner_only;
 129         u32 cqe_count;
 130         u32 i;
 131
 132         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 133
 134         for (i = update_owner_only; i < cqe_count;
 135              i++, cq->mini_arr_idx++, cqcc++) {
 136                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 137                         mlx5e_read_mini_arr_slot(cq, cqcc);
 138
 139                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 140                 rq->handle_rx_cqe(rq, &cq->title);
 141         }
 142         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 143         cq->wq.cc = cqcc;
 144         cq->decmprs_left -= cqe_count;
 145         rq->stats.cqe_compress_pkts += cqe_count;
 146
 147         return cqe_count;
 148 }
 149
 150 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 151                                               struct mlx5e_cq *cq,
 152                                               int budget_rem)
 153 {
 154         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 155         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 156         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 157         rq->handle_rx_cqe(rq, &cq->title);
 158         cq->mini_arr_idx++;
 159
 160         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 161 }
 162
 163 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 164
 165 static inline bool mlx5e_page_is_reserved(struct page *page)
 166 {
 167         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 168 }
 169
 170 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 171                                       struct mlx5e_dma_info *dma_info)
 172 {
 173         struct mlx5e_page_cache *cache = &rq->page_cache;
 174         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 175
 176         if (tail_next == cache->head) {
 177                 rq->stats.cache_full++;
 178                 return false;
 179         }
 180
 181         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 182                 rq->stats.cache_waive++;
 183                 return false;
 184         }
 185
 186         cache->page_cache[cache->tail] = *dma_info;
 187         cache->tail = tail_next;
 188         return true;
 189 }
 190
 191 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 192                                       struct mlx5e_dma_info *dma_info)
 193 {
 194         struct mlx5e_page_cache *cache = &rq->page_cache;
 195
 196         if (unlikely(cache->head == cache->tail)) {
 197                 rq->stats.cache_empty++;
 198                 return false;
 199         }
 200
 201         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 202                 rq->stats.cache_busy++;
 203                 return false;
 204         }
 205
 206         *dma_info = cache->page_cache[cache->head];
 207         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 208         rq->stats.cache_reuse++;
 209
 210         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 211                                    RQ_PAGE_SIZE(rq),
 212                                    DMA_FROM_DEVICE);
 213         return true;
 214 }
 215
 216 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 217                                           struct mlx5e_dma_info *dma_info)
 218 {
 219         if (mlx5e_rx_cache_get(rq, dma_info))
 220                 return 0;
 221
 222         dma_info->page = dev_alloc_pages(rq->buff.page_order);
 223         if (unlikely(!dma_info->page))
 224                 return -ENOMEM;
 225
 226         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 227                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 228         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 229                 put_page(dma_info->page);
 230                 dma_info->page = NULL;
 231                 return -ENOMEM;
 232         }
 233
 234         return 0;
 235 }
 236
 237 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 238                         bool recycle)
 239 {
 240         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
 241                 return;
 242
 243         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 244                        rq->buff.map_dir);
 245         put_page(dma_info->page);
 246 }
 247
 248 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 249                                     struct mlx5e_wqe_frag_info *wi)
 250 {
 251         return rq->wqe.page_reuse && wi->di.page &&
 252                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 253                 !mlx5e_page_is_reserved(wi->di.page);
 254 }
 255
 256 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 257 {
 258         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 259
 260         /* check if page exists, hence can be reused */
 261         if (!wi->di.page) {
 262                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 263                         return -ENOMEM;
 264                 wi->offset = 0;
 265         }
 266
 267         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 268         return 0;
 269 }
 270
 271 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 272                                      struct mlx5e_wqe_frag_info *wi)
 273 {
 274         mlx5e_page_release(rq, &wi->di, true);
 275         wi->di.page = NULL;
 276 }
 277
 278 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 279                                            struct mlx5e_wqe_frag_info *wi)
 280 {
 281         if (mlx5e_page_reuse(rq, wi)) {
 282                 rq->stats.page_reuse++;
 283                 return;
 284         }
 285
 286         mlx5e_free_rx_wqe(rq, wi);
 287 }
 288
 289 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 290 {
 291         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 292
 293         if (wi->di.page)
 294                 mlx5e_free_rx_wqe(rq, wi);
 295 }
 296
 297 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
 298 {
 299         return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
 300 }
 301
 302 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 303                                             struct sk_buff *skb,
 304                                             struct mlx5e_mpw_info *wi,
 305                                             u32 page_idx, u32 frag_offset,
 306                                             u32 len)
 307 {
 308         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 309
 310         dma_sync_single_for_cpu(rq->pdev,
 311                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 312                                 len, DMA_FROM_DEVICE);
 313         wi->skbs_frags[page_idx]++;
 314         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 315                         wi->umr.dma_info[page_idx].page, frag_offset,
 316                         len, truesize);
 317 }
 318
 319 static inline void
 320 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 321                             struct sk_buff *skb,
 322                             struct mlx5e_mpw_info *wi,
 323                             u32 page_idx, u32 offset,
 324                             u32 headlen)
 325 {
 326         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 327         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 328         unsigned int len;
 329
 330          /* Aligning len to sizeof(long) optimizes memcpy performance */
 331         len = ALIGN(headlen_pg, sizeof(long));
 332         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 333                                 DMA_FROM_DEVICE);
 334         skb_copy_to_linear_data_offset(skb, 0,
 335                                        page_address(dma_info->page) + offset,
 336                                        len);
 337         if (unlikely(offset + headlen > PAGE_SIZE)) {
 338                 dma_info++;
 339                 headlen_pg = len;
 340                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 341                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 342                                         DMA_FROM_DEVICE);
 343                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 344                                                page_address(dma_info->page),
 345                                                len);
 346         }
 347 }
 348
 349 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
 350 {
 351         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 352         struct mlx5e_icosq *sq = &rq->channel->icosq;
 353         struct mlx5_wq_cyc *wq = &sq->wq;
 354         struct mlx5e_umr_wqe *wqe;
 355         u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
 356         u16 pi;
 357
 358         /* fill sq edge with nops to avoid wqe wrap around */
 359         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 360                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 361                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 362         }
 363
 364         wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 365         memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
 366         wqe->ctrl.opmod_idx_opcode =
 367                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 368                             MLX5_OPCODE_UMR);
 369
 370         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 371         sq->pc += num_wqebbs;
 372         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
 373 }
 374
 375 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
 376                                     u16 ix)
 377 {
 378         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 379         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 380         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 381         int err;
 382         int i;
 383
 384         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 385                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 386                 if (unlikely(err))
 387                         goto err_unmap;
 388                 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 389                 page_ref_add(dma_info->page, pg_strides);
 390         }
 391
 392         memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
 393         wi->consumed_strides = 0;
 394
 395         return 0;
 396
 397 err_unmap:
 398         while (--i >= 0) {
 399                 dma_info--;
 400                 page_ref_sub(dma_info->page, pg_strides);
 401                 mlx5e_page_release(rq, dma_info, true);
 402         }
 403
 404         return err;
 405 }
 406
 407 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 408 {
 409         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 410         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 411         int i;
 412
 413         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 414                 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
 415                 mlx5e_page_release(rq, dma_info, true);
 416         }
 417 }
 418
 419 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 420 {
 421         struct mlx5_wq_ll *wq = &rq->wq;
 422         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 423
 424         rq->mpwqe.umr_in_progress = false;
 425
 426         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 427
 428         /* ensure wqes are visible to device before updating doorbell record */
 429         dma_wmb();
 430
 431         mlx5_wq_ll_update_db_record(wq);
 432 }
 433
 434 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 435 {
 436         int err;
 437
 438         err = mlx5e_alloc_rx_umr_mpwqe(rq, ix);
 439         if (unlikely(err)) {
 440                 rq->stats.buff_alloc_err++;
 441                 return err;
 442         }
 443         rq->mpwqe.umr_in_progress = true;
 444         mlx5e_post_umr_wqe(rq, ix);
 445         return 0;
 446 }
 447
 448 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 449 {
 450         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 451
 452         mlx5e_free_rx_mpwqe(rq, wi);
 453 }
 454
 455 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 456 {
 457         struct mlx5_wq_ll *wq = &rq->wq;
 458         int err;
 459
 460         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 461                 return false;
 462
 463         if (mlx5_wq_ll_is_full(wq))
 464                 return false;
 465
 466         do {
 467                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 468
 469                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 470                 if (unlikely(err)) {
 471                         rq->stats.buff_alloc_err++;
 472                         break;
 473                 }
 474
 475                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 476         } while (!mlx5_wq_ll_is_full(wq));
 477
 478         /* ensure wqes are visible to device before updating doorbell record */
 479         dma_wmb();
 480
 481         mlx5_wq_ll_update_db_record(wq);
 482
 483         return !!err;
 484 }
 485
 486 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 487                                              struct mlx5e_icosq *sq,
 488                                              struct mlx5e_rq *rq,
 489                                              struct mlx5_cqe64 *cqe)
 490 {
 491         struct mlx5_wq_cyc *wq = &sq->wq;
 492         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
 493         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 494
 495         mlx5_cqwq_pop(&cq->wq);
 496
 497         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 498                 netdev_WARN_ONCE(cq->channel->netdev,
 499                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 500                 return;
 501         }
 502
 503         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 504                 mlx5e_post_rx_mpwqe(rq);
 505                 return;
 506         }
 507
 508         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 509                 netdev_WARN_ONCE(cq->channel->netdev,
 510                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 511 }
 512
 513 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 514 {
 515         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 516         struct mlx5_cqe64 *cqe;
 517
 518         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
 519                 return;
 520
 521         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 522         if (likely(!cqe))
 523                 return;
 524
 525         /* by design, there's only a single cqe */
 526         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 527
 528         mlx5_cqwq_update_db_record(&cq->wq);
 529 }
 530
 531 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 532 {
 533         struct mlx5_wq_ll *wq = &rq->wq;
 534
 535         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 536                 return false;
 537
 538         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 539
 540         if (mlx5_wq_ll_is_full(wq))
 541                 return false;
 542
 543         if (!rq->mpwqe.umr_in_progress)
 544                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 545
 546         return true;
 547 }
 548
 549 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 550                                  u32 cqe_bcnt)
 551 {
 552         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 553         struct tcphdr   *tcp;
 554         int network_depth = 0;
 555         __be16 proto;
 556         u16 tot_len;
 557         void *ip_p;
 558
 559         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 560         u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 561                 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 562
 563         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 564
 565         tot_len = cqe_bcnt - network_depth;
 566         ip_p = skb->data + network_depth;
 567
 568         if (proto == htons(ETH_P_IP)) {
 569                 struct iphdr *ipv4 = ip_p;
 570
 571                 tcp = ip_p + sizeof(struct iphdr);
 572                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 573
 574                 ipv4->ttl               = cqe->lro_min_ttl;
 575                 ipv4->tot_len           = cpu_to_be16(tot_len);
 576                 ipv4->check             = 0;
 577                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 578                                                        ipv4->ihl);
 579         } else {
 580                 struct ipv6hdr *ipv6 = ip_p;
 581
 582                 tcp = ip_p + sizeof(struct ipv6hdr);
 583                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 584
 585                 ipv6->hop_limit         = cqe->lro_min_ttl;
 586                 ipv6->payload_len       = cpu_to_be16(tot_len -
 587                                                       sizeof(struct ipv6hdr));
 588         }
 589
 590         tcp->psh = get_cqe_lro_tcppsh(cqe);
 591
 592         if (tcp_ack) {
 593                 tcp->ack                = 1;
 594                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 595                 tcp->window             = cqe->lro_tcp_win;
 596         }
 597 }
 598
 599 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 600                                       struct sk_buff *skb)
 601 {
 602         u8 cht = cqe->rss_hash_type;
 603         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 604                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 605                                             PKT_HASH_TYPE_NONE;
 606         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 607 }
 608
 609 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 610 {
 611         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 612
 613         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 614         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 615 }
 616
 617 static inline void mlx5e_handle_csum(struct net_device *netdev,
 618                                      struct mlx5_cqe64 *cqe,
 619                                      struct mlx5e_rq *rq,
 620                                      struct sk_buff *skb,
 621                                      bool   lro)
 622 {
 623         int network_depth = 0;
 624
 625         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 626                 goto csum_none;
 627
 628         if (lro) {
 629                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 630                 rq->stats.csum_unnecessary++;
 631                 return;
 632         }
 633
 634         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 635                 skb->ip_summed = CHECKSUM_COMPLETE;
 636                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 637                 if (network_depth > ETH_HLEN)
 638                         /* CQE csum is calculated from the IP header and does
 639                          * not cover VLAN headers (if present). This will add
 640                          * the checksum manually.
 641                          */
 642                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 643                                                  network_depth - ETH_HLEN,
 644                                                  skb->csum);
 645                 rq->stats.csum_complete++;
 646                 return;
 647         }
 648
 649         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 650                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 651                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 652                 if (cqe_is_tunneled(cqe)) {
 653                         skb->csum_level = 1;
 654                         skb->encapsulation = 1;
 655                         rq->stats.csum_unnecessary_inner++;
 656                         return;
 657                 }
 658                 rq->stats.csum_unnecessary++;
 659                 return;
 660         }
 661 csum_none:
 662         skb->ip_summed = CHECKSUM_NONE;
 663         rq->stats.csum_none++;
 664 }
 665
 666 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 667                                       u32 cqe_bcnt,
 668                                       struct mlx5e_rq *rq,
 669                                       struct sk_buff *skb)
 670 {
 671         struct net_device *netdev = rq->netdev;
 672         int lro_num_seg;
 673
 674         skb->mac_len = ETH_HLEN;
 675         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 676         if (lro_num_seg > 1) {
 677                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 678                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 679                 /* Subtract one since we already counted this as one
 680                  * "regular" packet in mlx5e_complete_rx_cqe()
 681                  */
 682                 rq->stats.packets += lro_num_seg - 1;
 683                 rq->stats.lro_packets++;
 684                 rq->stats.lro_bytes += cqe_bcnt;
 685         }
 686
 687         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 688                 skb_hwtstamps(skb)->hwtstamp =
 689                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 690
 691         skb_record_rx_queue(skb, rq->ix);
 692
 693         if (likely(netdev->features & NETIF_F_RXHASH))
 694                 mlx5e_skb_set_hash(cqe, skb);
 695
 696         if (cqe_has_vlan(cqe)) {
 697                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 698                                        be16_to_cpu(cqe->vlan_info));
 699                 rq->stats.removed_vlan_packets++;
 700         }
 701
 702         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 703
 704         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 705         skb->protocol = eth_type_trans(skb, netdev);
 706 }
 707
 708 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 709                                          struct mlx5_cqe64 *cqe,
 710                                          u32 cqe_bcnt,
 711                                          struct sk_buff *skb)
 712 {
 713         rq->stats.packets++;
 714         rq->stats.bytes += cqe_bcnt;
 715         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 716 }
 717
 718 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 719 {
 720         struct mlx5_wq_cyc *wq = &sq->wq;
 721         struct mlx5e_tx_wqe *wqe;
 722         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
 723
 724         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 725
 726         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 727 }
 728
 729 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 730                                         struct mlx5e_dma_info *di,
 731                                         const struct xdp_buff *xdp)
 732 {
 733         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 734         struct mlx5_wq_cyc       *wq   = &sq->wq;
 735         u16                       pi   = sq->pc & wq->sz_m1;
 736         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 737
 738         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 739         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 740         struct mlx5_wqe_data_seg *dseg;
 741
 742         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 743         dma_addr_t dma_addr  = di->addr + data_offset;
 744         unsigned int dma_len = xdp->data_end - xdp->data;
 745
 746         prefetchw(wqe);
 747
 748         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
 749                      MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
 750                 rq->stats.xdp_drop++;
 751                 return false;
 752         }
 753
 754         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 755                 if (sq->db.doorbell) {
 756                         /* SQ is full, ring doorbell */
 757                         mlx5e_xmit_xdp_doorbell(sq);
 758                         sq->db.doorbell = false;
 759                 }
 760                 rq->stats.xdp_tx_full++;
 761                 return false;
 762         }
 763
 764         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 765
 766         cseg->fm_ce_se = 0;
 767
 768         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 769
 770         /* copy the inline part if required */
 771         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 772                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 773                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 774                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 775                 dma_addr += MLX5E_XDP_MIN_INLINE;
 776                 dseg++;
 777         }
 778
 779         /* write the dma part */
 780         dseg->addr       = cpu_to_be64(dma_addr);
 781         dseg->byte_count = cpu_to_be32(dma_len);
 782
 783         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 784
 785         /* move page to reference to sq responsibility,
 786          * and mark so it's not put back in page-cache.
 787          */
 788         rq->wqe.xdp_xmit = true;
 789         sq->db.di[pi] = *di;
 790         sq->pc++;
 791
 792         sq->db.doorbell = true;
 793
 794         rq->stats.xdp_tx++;
 795         return true;
 796 }
 797
 798 /* returns true if packet was consumed by xdp */
 799 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 800                                    struct mlx5e_dma_info *di,
 801                                    void *va, u16 *rx_headroom, u32 *len)
 802 {
 803         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 804         struct xdp_buff xdp;
 805         u32 act;
 806
 807         if (!prog)
 808                 return false;
 809
 810         xdp.data = va + *rx_headroom;
 811         xdp_set_data_meta_invalid(&xdp);
 812         xdp.data_end = xdp.data + *len;
 813         xdp.data_hard_start = va;
 814         xdp.rxq = &rq->xdp_rxq;
 815
 816         act = bpf_prog_run_xdp(prog, &xdp);
 817         switch (act) {
 818         case XDP_PASS:
 819                 *rx_headroom = xdp.data - xdp.data_hard_start;
 820                 *len = xdp.data_end - xdp.data;
 821                 return false;
 822         case XDP_TX:
 823                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 824                         trace_xdp_exception(rq->netdev, prog, act);
 825                 return true;
 826         default:
 827                 bpf_warn_invalid_xdp_action(act);
 828         case XDP_ABORTED:
 829                 trace_xdp_exception(rq->netdev, prog, act);
 830         case XDP_DROP:
 831                 rq->stats.xdp_drop++;
 832                 return true;
 833         }
 834 }
 835
 836 static inline
 837 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 838                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 839 {
 840         struct mlx5e_dma_info *di = &wi->di;
 841         u16 rx_headroom = rq->buff.headroom;
 842         struct sk_buff *skb;
 843         void *va, *data;
 844         bool consumed;
 845         u32 frag_size;
 846
 847         va             = page_address(di->page) + wi->offset;
 848         data           = va + rx_headroom;
 849         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 850
 851         dma_sync_single_range_for_cpu(rq->pdev,
 852                                       di->addr + wi->offset,
 853                                       0, frag_size,
 854                                       DMA_FROM_DEVICE);
 855         prefetch(data);
 856         wi->offset += frag_size;
 857
 858         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 859                 rq->stats.wqe_err++;
 860                 return NULL;
 861         }
 862
 863         rcu_read_lock();
 864         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 865         rcu_read_unlock();
 866         if (consumed)
 867                 return NULL; /* page/packet was consumed by XDP */
 868
 869         skb = build_skb(va, frag_size);
 870         if (unlikely(!skb)) {
 871                 rq->stats.buff_alloc_err++;
 872                 return NULL;
 873         }
 874
 875         /* queue up for recycling/reuse */
 876         page_ref_inc(di->page);
 877
 878         skb_reserve(skb, rx_headroom);
 879         skb_put(skb, cqe_bcnt);
 880
 881         return skb;
 882 }
 883
 884 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 885 {
 886         struct mlx5e_wqe_frag_info *wi;
 887         struct mlx5e_rx_wqe *wqe;
 888         __be16 wqe_counter_be;
 889         struct sk_buff *skb;
 890         u16 wqe_counter;
 891         u32 cqe_bcnt;
 892
 893         wqe_counter_be = cqe->wqe_counter;
 894         wqe_counter    = be16_to_cpu(wqe_counter_be);
 895         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 896         wi             = &rq->wqe.frag_info[wqe_counter];
 897         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 898
 899         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 900         if (!skb) {
 901                 /* probably for XDP */
 902                 if (rq->wqe.xdp_xmit) {
 903                         wi->di.page = NULL;
 904                         rq->wqe.xdp_xmit = false;
 905                         /* do not return page to cache, it will be returned on XDP_TX completion */
 906                         goto wq_ll_pop;
 907                 }
 908                 /* probably an XDP_DROP, save the page-reuse checks */
 909                 mlx5e_free_rx_wqe(rq, wi);
 910                 goto wq_ll_pop;
 911         }
 912
 913         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 914         napi_gro_receive(rq->cq.napi, skb);
 915
 916         mlx5e_free_rx_wqe_reuse(rq, wi);
 917 wq_ll_pop:
 918         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 919                        &wqe->next.next_wqe_index);
 920 }
 921
 922 #ifdef CONFIG_MLX5_ESWITCH
 923 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 924 {
 925         struct net_device *netdev = rq->netdev;
 926         struct mlx5e_priv *priv = netdev_priv(netdev);
 927         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
 928         struct mlx5_eswitch_rep *rep = rpriv->rep;
 929         struct mlx5e_wqe_frag_info *wi;
 930         struct mlx5e_rx_wqe *wqe;
 931         struct sk_buff *skb;
 932         __be16 wqe_counter_be;
 933         u16 wqe_counter;
 934         u32 cqe_bcnt;
 935
 936         wqe_counter_be = cqe->wqe_counter;
 937         wqe_counter    = be16_to_cpu(wqe_counter_be);
 938         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 939         wi             = &rq->wqe.frag_info[wqe_counter];
 940         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 941
 942         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 943         if (!skb) {
 944                 if (rq->wqe.xdp_xmit) {
 945                         wi->di.page = NULL;
 946                         rq->wqe.xdp_xmit = false;
 947                         /* do not return page to cache, it will be returned on XDP_TX completion */
 948                         goto wq_ll_pop;
 949                 }
 950                 /* probably an XDP_DROP, save the page-reuse checks */
 951                 mlx5e_free_rx_wqe(rq, wi);
 952                 goto wq_ll_pop;
 953         }
 954
 955         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 956
 957         if (rep->vlan && skb_vlan_tag_present(skb))
 958                 skb_vlan_pop(skb);
 959
 960         napi_gro_receive(rq->cq.napi, skb);
 961
 962         mlx5e_free_rx_wqe_reuse(rq, wi);
 963 wq_ll_pop:
 964         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 965                        &wqe->next.next_wqe_index);
 966 }
 967 #endif
 968
 969 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
 970                                            struct mlx5_cqe64 *cqe,
 971                                            struct mlx5e_mpw_info *wi,
 972                                            u32 cqe_bcnt,
 973                                            struct sk_buff *skb)
 974 {
 975         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
 976         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
 977         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
 978         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
 979         u32 head_page_idx  = page_idx;
 980         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
 981         u32 frag_offset    = head_offset + headlen;
 982         u16 byte_cnt       = cqe_bcnt - headlen;
 983
 984         if (unlikely(frag_offset >= PAGE_SIZE)) {
 985                 page_idx++;
 986                 frag_offset -= PAGE_SIZE;
 987         }
 988
 989         while (byte_cnt) {
 990                 u32 pg_consumed_bytes =
 991                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
 992
 993                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
 994                                          pg_consumed_bytes);
 995                 byte_cnt -= pg_consumed_bytes;
 996                 frag_offset = 0;
 997                 page_idx++;
 998         }
 999         /* copy header */
1000         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
1001                                     head_offset, headlen);
1002         /* skb linear part was allocated with headlen and aligned to long */
1003         skb->tail += headlen;
1004         skb->len  += headlen;
1005 }
1006
1007 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1008 {
1009         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1010         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1011         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1012         struct mlx5e_rx_wqe  *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1013         struct sk_buff *skb;
1014         u16 cqe_bcnt;
1015
1016         wi->consumed_strides += cstrides;
1017
1018         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1019                 rq->stats.wqe_err++;
1020                 goto mpwrq_cqe_out;
1021         }
1022
1023         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1024                 rq->stats.mpwqe_filler++;
1025                 goto mpwrq_cqe_out;
1026         }
1027
1028         skb = napi_alloc_skb(rq->cq.napi,
1029                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
1030                                    sizeof(long)));
1031         if (unlikely(!skb)) {
1032                 rq->stats.buff_alloc_err++;
1033                 goto mpwrq_cqe_out;
1034         }
1035
1036         prefetchw(skb->data);
1037         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1038
1039         mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
1040         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1041         napi_gro_receive(rq->cq.napi, skb);
1042
1043 mpwrq_cqe_out:
1044         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1045                 return;
1046
1047         mlx5e_free_rx_mpwqe(rq, wi);
1048         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1049 }
1050
1051 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1052 {
1053         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1054         struct mlx5e_xdpsq *xdpsq;
1055         struct mlx5_cqe64 *cqe;
1056         int work_done = 0;
1057
1058         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1059                 return 0;
1060
1061         if (cq->decmprs_left)
1062                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1063
1064         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1065         if (!cqe)
1066                 return 0;
1067
1068         xdpsq = &rq->xdpsq;
1069
1070         do {
1071                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1072                         work_done +=
1073                                 mlx5e_decompress_cqes_start(rq, cq,
1074                                                             budget - work_done);
1075                         continue;
1076                 }
1077
1078                 mlx5_cqwq_pop(&cq->wq);
1079
1080                 rq->handle_rx_cqe(rq, cqe);
1081         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1082
1083         if (xdpsq->db.doorbell) {
1084                 mlx5e_xmit_xdp_doorbell(xdpsq);
1085                 xdpsq->db.doorbell = false;
1086         }
1087
1088         mlx5_cqwq_update_db_record(&cq->wq);
1089
1090         /* ensure cq space is freed before enabling more cqes */
1091         wmb();
1092
1093         return work_done;
1094 }
1095
1096 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1097 {
1098         struct mlx5e_xdpsq *sq;
1099         struct mlx5_cqe64 *cqe;
1100         struct mlx5e_rq *rq;
1101         u16 sqcc;
1102         int i;
1103
1104         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1105
1106         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1107                 return false;
1108
1109         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1110         if (!cqe)
1111                 return false;
1112
1113         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1114
1115         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1116          * otherwise a cq overrun may occur
1117          */
1118         sqcc = sq->cc;
1119
1120         i = 0;
1121         do {
1122                 u16 wqe_counter;
1123                 bool last_wqe;
1124
1125                 mlx5_cqwq_pop(&cq->wq);
1126
1127                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1128
1129                 do {
1130                         struct mlx5e_dma_info *di;
1131                         u16 ci;
1132
1133                         last_wqe = (sqcc == wqe_counter);
1134
1135                         ci = sqcc & sq->wq.sz_m1;
1136                         di = &sq->db.di[ci];
1137
1138                         sqcc++;
1139                         /* Recycle RX page */
1140                         mlx5e_page_release(rq, di, true);
1141                 } while (!last_wqe);
1142         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1143
1144         mlx5_cqwq_update_db_record(&cq->wq);
1145
1146         /* ensure cq space is freed before enabling more cqes */
1147         wmb();
1148
1149         sq->cc = sqcc;
1150         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1151 }
1152
1153 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1154 {
1155         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1156         struct mlx5e_dma_info *di;
1157         u16 ci;
1158
1159         while (sq->cc != sq->pc) {
1160                 ci = sq->cc & sq->wq.sz_m1;
1161                 di = &sq->db.di[ci];
1162                 sq->cc++;
1163
1164                 mlx5e_page_release(rq, di, false);
1165         }
1166 }
1167
1168 #ifdef CONFIG_MLX5_CORE_IPOIB
1169
1170 #define MLX5_IB_GRH_DGID_OFFSET 24
1171 #define MLX5_GID_SIZE           16
1172
1173 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1174                                          struct mlx5_cqe64 *cqe,
1175                                          u32 cqe_bcnt,
1176                                          struct sk_buff *skb)
1177 {
1178         struct hwtstamp_config *tstamp;
1179         struct net_device *netdev;
1180         struct mlx5e_priv *priv;
1181         char *pseudo_header;
1182         u32 qpn;
1183         u8 *dgid;
1184         u8 g;
1185
1186         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1187         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1188
1189         /* No mapping present, cannot process SKB. This might happen if a child
1190          * interface is going down while having unprocessed CQEs on parent RQ
1191          */
1192         if (unlikely(!netdev)) {
1193                 /* TODO: add drop counters support */
1194                 skb->dev = NULL;
1195                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1196                 return;
1197         }
1198
1199         priv = mlx5i_epriv(netdev);
1200         tstamp = &priv->tstamp;
1201
1202         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1203         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1204         if ((!g) || dgid[0] != 0xff)
1205                 skb->pkt_type = PACKET_HOST;
1206         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1207                 skb->pkt_type = PACKET_BROADCAST;
1208         else
1209                 skb->pkt_type = PACKET_MULTICAST;
1210
1211         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1212          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1213          */
1214
1215         skb_pull(skb, MLX5_IB_GRH_BYTES);
1216
1217         skb->protocol = *((__be16 *)(skb->data));
1218
1219         skb->ip_summed = CHECKSUM_COMPLETE;
1220         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1221
1222         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1223                 skb_hwtstamps(skb)->hwtstamp =
1224                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1225
1226         skb_record_rx_queue(skb, rq->ix);
1227
1228         if (likely(netdev->features & NETIF_F_RXHASH))
1229                 mlx5e_skb_set_hash(cqe, skb);
1230
1231         /* 20 bytes of ipoib header and 4 for encap existing */
1232         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1233         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1234         skb_reset_mac_header(skb);
1235         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1236
1237         skb->dev = netdev;
1238
1239         rq->stats.csum_complete++;
1240         rq->stats.packets++;
1241         rq->stats.bytes += cqe_bcnt;
1242 }
1243
1244 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1245 {
1246         struct mlx5e_wqe_frag_info *wi;
1247         struct mlx5e_rx_wqe *wqe;
1248         __be16 wqe_counter_be;
1249         struct sk_buff *skb;
1250         u16 wqe_counter;
1251         u32 cqe_bcnt;
1252
1253         wqe_counter_be = cqe->wqe_counter;
1254         wqe_counter    = be16_to_cpu(wqe_counter_be);
1255         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1256         wi             = &rq->wqe.frag_info[wqe_counter];
1257         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1258
1259         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1260         if (!skb)
1261                 goto wq_free_wqe;
1262
1263         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1264         if (unlikely(!skb->dev)) {
1265                 dev_kfree_skb_any(skb);
1266                 goto wq_free_wqe;
1267         }
1268         napi_gro_receive(rq->cq.napi, skb);
1269
1270 wq_free_wqe:
1271         mlx5e_free_rx_wqe_reuse(rq, wi);
1272         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1273                        &wqe->next.next_wqe_index);
1274 }
1275
1276 #endif /* CONFIG_MLX5_CORE_IPOIB */
1277
1278 #ifdef CONFIG_MLX5_EN_IPSEC
1279
1280 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1281 {
1282         struct mlx5e_wqe_frag_info *wi;
1283         struct mlx5e_rx_wqe *wqe;
1284         __be16 wqe_counter_be;
1285         struct sk_buff *skb;
1286         u16 wqe_counter;
1287         u32 cqe_bcnt;
1288
1289         wqe_counter_be = cqe->wqe_counter;
1290         wqe_counter    = be16_to_cpu(wqe_counter_be);
1291         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1292         wi             = &rq->wqe.frag_info[wqe_counter];
1293         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1294
1295         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1296         if (unlikely(!skb)) {
1297                 /* a DROP, save the page-reuse checks */
1298                 mlx5e_free_rx_wqe(rq, wi);
1299                 goto wq_ll_pop;
1300         }
1301         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1302         if (unlikely(!skb)) {
1303                 mlx5e_free_rx_wqe(rq, wi);
1304                 goto wq_ll_pop;
1305         }
1306
1307         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1308         napi_gro_receive(rq->cq.napi, skb);
1309
1310         mlx5e_free_rx_wqe_reuse(rq, wi);
1311 wq_ll_pop:
1312         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1313                        &wqe->next.next_wqe_index);
1314 }
1315
1316 #endif /* CONFIG_MLX5_EN_IPSEC */